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UPA2736GR-E1-AX
Power MOSFET, P Channel, 30 V, 14 A, 7000 µohm, SOP, Surface Mount
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- Manufacturer: RENESAS
- Product type:
- SVHC: No SVHC (25-Jun-2025)
- No. of Pins: 8Pins
- Channel Type: P Channel
- Product Range: uPA2736GR Series
- Qualification: -
- Power Dissipation: 2.5W
- Transistor Mounting: Surface Mount
- Rds(on) Test Voltage: 10V
- Transistor Case Style: SOP
- Drain Source Voltage Vds: 30V
- Operating Temperature Max: 150°C
- Continuous Drain Current Id: 14A
- Drain Source On State Resistance: 7000µohm
- Gate Source Threshold Voltage Max: 2.5V
| Delivery and price | |
|---|---|
| Units per pack | 2500 |
| Price | 0.459 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
Data Sheet ## **PA2736GR** μ ## P-channel MOSFET –30 V, –14 A, 7.0 mΩ R07DS1320EJ0100 Rev.1.00 Jan 25, 2016 ## **Description** The μ PA2736GR is P-channel MOS Field Effect Transistor designed for DC/DC converter and power management applications of portable equipment. ## **Features** - VDSS = − 30 V (TA = 25 ° C) - Low on-state resistance - ⎯ RDS(on) = 7.0 m Ω MAX. (VGS = − 10 V, ID = − 14 A) - 4.5 V Gate-drive available - Small and surface mount package (SOP-8) - Pb-free and Halogen free **==> picture [34 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> SOP-8<br>**----- End of picture text -----**<br> ## **Ordering Information** |**Ordering Information**|||| |---|---|---|---| |**Part No.**|**LEAD PLATING**|**PACKING**|**Package **| |μ PA2736GR-E1-AX|Ni / Pd / Au|Tape 2500 p/reel|Power SOP8<br>0.085 g TYP.| |μPA2736GR-E2-AX|||| ## **Absolute Maximum Ratings (TA = 25** ° **C)** |**Absolute Maximum Ratings (TA = 25A = 25 = 25**|**Absolute Maximum Ratings (TA = 25A = 25 = 25**°**C)**||| |---|---|---|---| |**Item**|**Symbol**|**Ratings **|**Unit**| |Drain to Source Voltage(VGS= 0 V)|VDSS|−30|V| |Gate to Source Voltage(VDS= 0 V)|VGSS|m20|V| |Drain Current(DC)|ID(DC)|m14|A| |Drain Current(pulse) ∗1|ID(pulse)|m140|A| |Total Power Dissipation∗2|PT1|1.1|W| |Total Power Dissipation(PW = 10 sec) ∗2|PT2|2.5|W| |Channel Temperature|Tch|150|°C| |Storage Temperature|Tstg|−55 to+150|°C| |Single Avalanche Current∗3|IAS|14|A| |Single Avalanche Energy ∗3|EAS|19.6|mJ| ## **Thermal Resistance** Channel to Ambient Thermal Resistance[∗2] Rth(ch-A) 114 °C/W Notes:[∗] 1. PW ≤ 10 μs, Duty Cycle ≤ 1% - ∗2. Mounted on a glass epoxy board of 25.4 mm x 25.4 mm x 0.8 mmt - ∗3. Starting Tch = 25°C, VDD = −15 V, RG = 25 Ω, VGS = −20 → 0 V, L = 100 μH R07DS1320EJ0100 Rev.1.00 Jan 25, 2016 Page 1 of 6 μ **PA2736GR** ## **Electrical Characteristics (TA = 25** ° **C)** |**Electrical Characteristics**|**(TA = 2**|**C)**||||| |---|---|---|---|---|---|---| |**Item**|**Symbol**|**MIN.**|**TYP.**|**MAX.**|**Unit**|**Test Conditions**| |Zero Gate Voltage Drain Current|IDSS|||−1|μA|VDS=−30 V, VGS= 0 V| |Gate Leakage Current|IGSS|||m100|nA|VGS=m20 V, VDS= 0 V| |Gate Cut-off Voltage|VGS(off)|−1.0||−2.5|V|VDS=−10 V, ID=−1 mA| |Forward Transfer Admittance∗1|| yfs||6|||S|VDS=−10 V, ID=−7 A| |Drain to Source On-state<br>Resistance∗1|RDS(on)1||5.8|7.0|mΩ|VGS=−10 V, ID=−14 A| ||RDS(on)2||9.2|13.5|mΩ|VGS=−4.5 V, ID=−14 A| |Input Capacitance|Ciss||3400||pF|VDS=−10 V,<br>VGS= 0 V,<br>f = 1 MHz| |Output Capacitance|Coss||1600||pF|| |Reverse Transfer Capacitance|Crss||1450||pF|| |Turn-on DelayTime|td(on)||30||ns|VDD=−15 V, ID=−7 A,<br>VGS=−10 V,<br>RG= 10Ω| |Rise Time|tr||45||ns|| |Turn-off DelayTime|td(off)||100||ns|| |Fall Time|tf||100||ns|| |Total Gate Charge|QG||80||nC|VDD=−24 V,<br>VGS=−10 V,<br>ID=−14 A| |Gate to Source Charge|QGS||5||nC|| |Gate to Drain Charge|QGD||40||nC|| |BodyDiode Forward Voltage∗1|VF(S-D)||0.84||V|IF= 14 A, VGS= 0 V| |Reverse RecoveryTime|trr||55||ns|IF= 14 A, VGS= 0 V,<br>di/dt = 100 A/μs| |Reverse RecoveryCharge|Qrr||70||nC|| Note:[∗] 1. Pulsed ## **TEST CIRCUIT 1 AVALANCHE CAPABILITY** ## **TEST CIRCUIT 2 SWITCHING TIME** **==> picture [163 x 136] intentionally omitted <==** **----- Start of picture text -----**<br> D.U.T.<br>RG = 25 Ω L<br>PG. 50 Ω VDD<br>VGS = − 20 → 0 V<br>− IAS BVDSS<br>VDS<br>ID<br>VDD<br>Starting Tch<br>**----- End of picture text -----**<br> **==> picture [272 x 129] intentionally omitted <==** **----- Start of picture text -----**<br> D.U.T.<br>RL VGS( − )<br>RG Wave FormVGS 0 10% VGS 90%<br>PG. VDD<br>VDS( − )<br>90% 90%<br>VGS( − ) VDS VDS 10% 10%<br>0 Wave Form 0<br>τ td(on) tr td(off) t f<br>ton toff<br>τ = 1 s μ<br>Duty Cycle ≤ 1%<br>**----- End of picture text -----**<br> ## **TEST CIRCUIT 3 GATE CHARGE** **==> picture [134 x 56] intentionally omitted <==** **----- Start of picture text -----**<br> D.U.T.<br>IG = − 2 mA RL<br>PG. 50 Ω VDD<br>**----- End of picture text -----**<br> R07DS1320EJ0100 Rev.1.00 Jan 25, 2016 Page 2 of 6 μ **PA2736GR** ## **TYPICAL CHARACTERISTICS (TA = 25°C)** DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA FORWARD BIAS SAFE OPERATING AREA **==> picture [463 x 401] intentionally omitted <==** **----- Start of picture text -----**<br> 140 -1000<br>120 ID(pulse) = –140 A 100 ms 30 ms<br>-100<br>100 ID(DC) = –14 A<br>-10<br>80<br>60 -1<br>40<br>Single Pulse<br>-0.1 TA = 25°C<br>20 Mounted on glass epoxy board of<br>25.4 mm x 25.4 mm x 0.8 mmt<br>0 -0.01<br>0 25 50 75 100 125 150 175 -0.01 -0.1 -1 -10 -100<br> TA - Ambient Temperature - °C VDS - Drain to Source Voltage – V<br>TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH<br>1000<br>Rth(ch-A) = 114°C/W<br>100<br>10<br>1<br>0.1 Rth(ch-A)：Mounted on glass epoxy board of<br>25.4 mm x 25.4 mm x 0.8 mmt<br>Single pulse<br>0.01<br>100 μ 1 m 10 m 100 m 1 10 100 1000<br> PW - Pulse Width - s<br>Power Dissipation Limited<br>DC<br>10 ms PW = 100 μ s<br>Limited<br>RDS(on)(VGS = –10 V)<br>1ms<br> - Drain Current - A<br>D<br> I<br> dT - Percentage of Rated Power - %<br>C/W<br>°<br> - Transient Thermal Resistance -<br>th(t)<br> r<br>**----- End of picture text -----**<br> DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE **==> picture [212 x 183] intentionally omitted <==** **----- Start of picture text -----**<br> -150<br>VGS = –10 V<br>-100<br>–4.5 V<br>-50<br>Pulsed<br>-0<br>-0 -0.5 -1 -1.5<br> VDS - Drain to Source Voltage - V<br> - Drain Current - A<br>D<br> I<br>**----- End of picture text -----**<br> FORWARD TRANSFER CHARACTERISTICS **==> picture [211 x 182] intentionally omitted <==** **----- Start of picture text -----**<br> -100<br>-10 TA = 150°C<br>75°C<br>25°C<br>-1 –55°C<br>-0.1<br>-0.01<br>Pulsed<br>VDS = –10 V<br>-0.001<br>-0 -1 -2 -3 -4<br> VGS - Gate to Source Voltage - V<br> - Drain Current - A<br>D<br> I<br>**----- End of picture text -----**<br> R07DS1320EJ0100 Rev.1.00 Jan 25, 2016 Page 3 of 6 μ **PA2736GR** GATE TO SOURCE CUT-OFF VOLTAGE vs. CHANNEL TEMPERATURE **==> picture [213 x 188] intentionally omitted <==** **----- Start of picture text -----**<br> -3<br>-2<br>-1<br>Pulsed<br>VDS = –10 V<br>ID = –1 mA<br>-0<br>-50 0 50 100 150<br> Tch - Channel Temperature - °C<br>– Gate to Source Cut-off Voltage - V<br>GS(off)<br> V<br>**----- End of picture text -----**<br> DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT **==> picture [182 x 182] intentionally omitted <==** **----- Start of picture text -----**<br> 20<br>Pulsed<br>16<br>12<br>VGS = –4.5<br>8<br>–10 V<br>4<br>0<br>-1 -10 -100 -1000<br> ID - Drain Current - A<br>**----- End of picture text -----**<br> DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE **==> picture [213 x 185] intentionally omitted <==** **----- Start of picture text -----**<br> 15<br>Pulsed<br>I D = –14 A<br>VGS = –4.5 V<br>10<br>5 V GS = –10 V<br>0<br>-50 0 50 100 150<br> Tch - Channel Temperature - °C<br>Ω<br> - Drain to Source On-state Resistance - m<br>DS(on)<br>R<br>**----- End of picture text -----**<br> FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT **==> picture [209 x 183] intentionally omitted <==** **----- Start of picture text -----**<br> 100<br>T A = 150°C<br>10 75 ° C<br>25°C<br>–55°C<br>1<br>Pulsed<br>V DS = –10 V<br>0.1<br>-0.01 -0.1 -1 -10<br> ID - Drain Current - A<br> | - Forward Transfer Admittance - S<br>fs<br> | y<br>**----- End of picture text -----**<br> DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE **==> picture [213 x 184] intentionally omitted <==** **----- Start of picture text -----**<br> 30<br>Pulsed<br>25 ID = –14 A<br>20<br>15<br>10<br>5<br>0<br>-0 -5 -10 -15 -20<br> VGS - Gate to Source Voltage - V<br>Ω<br> - Drain to Source On-state Resistance - m<br>DS(on)<br>R<br>**----- End of picture text -----**<br> CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE **==> picture [217 x 182] intentionally omitted <==** **----- Start of picture text -----**<br> 10000<br>Ciss<br>C oss<br>1000 Crss<br>V GS = 0 V<br>f = 1 MHz<br>100<br>-0.1 -1 -10 -100<br> VDS - Drain to Source Voltage - V<br> - Capacitance - pF<br>rss<br>, C<br>oss<br>, C<br>iss<br> C<br>**----- End of picture text -----**<br> R07DS1320EJ0100 Rev.1.00 Jan 25, 2016 Page 4 of 6 μ **PA2736GR** DYNAMIC INPUT/OUTPUT CHARACTERISTICS **==> picture [241 x 193] intentionally omitted <==** **----- Start of picture text -----**<br> -25 -10<br>VDS VDD = –24 V<br>–12 V<br>-20 -8<br>–6 V<br>-15 -6<br>VGS<br>-10 -4<br>-5 -2<br>ID = –14 A<br>-0 -0<br>0 20 40 60 80<br> QG - Gate Charge - nC<br> - Drain to Source Voltage - V - Gate to Source Voltage - V<br>DS GS<br> V V<br>**----- End of picture text -----**<br> SOURCE TO DRAIN DIODE FORWARD VOLTAGE **==> picture [215 x 182] intentionally omitted <==** **----- Start of picture text -----**<br> 1000<br>VGS = –10 V<br>100<br>–4.5 V<br>0 V<br>10<br>Pulsed<br>1<br>0 0.2 0.4 0.6 0.8 1 1.2 1.4<br> VF(S-D) - Source to Drain Voltage - V<br> - Diode Forward Current - A<br>F<br> I<br>**----- End of picture text -----**<br> R07DS1320EJ0100 Rev.1.00 Jan 25, 2016 Page 5 of 6 μ **PA2736GR** ## **Package Drawings (Unit: mm)** ## **SOP-8** **==> picture [523 x 319] intentionally omitted <==** **----- Start of picture text -----**<br> Package Name JEITA Package Code RENESAS Code Previous Code MASS[Typ.]<br>SOP-8 P-SOP8-3.95 × 4.9-1.27 PRSP0008DD-D FP-8DAV 0.085g<br>* [1] D<br>8 5 bp<br>Index mark<br>:<br>a<br>1 4 Terminal cross section NOTE)1. DIMENSIONS "*1(Nom)" AND "*2"<br>Z DO NOT INCLUDE MOLD FLASH.<br>* [3] bp x M (Ni/Pd/Au plating) 2. DIMENSION "*3" DOES NOTINCLUDE TRIM OFFSET.<br>e<br>Reference Dimension in Millimeters<br>Symbol Min Nom Max<br>L1 TT DE 4.903.95 5.3<br>A2<br>A1 0.10 0.14 0.25<br>A 1.75<br>bp 0.34 0.40 0.46<br>b1<br>c 0.15 0.20 0.25<br>L c1<br>0° 8°<br>= y HE 5.80 6.10 6.20<br>Detail F e 1.27<br>x 0.25<br>y 0.1<br>Z 0.75<br>L 0.40 0.60 1.27<br>L1 1.08<br>F<br>E E<br>2* H c<br>A<br>A1<br>**----- End of picture text -----**<br> ## **Equivalent Circuit** **==> picture [228 x 88] intentionally omitted <==** **----- Start of picture text -----**<br> Drain<br>Body<br>Gate Diode<br>1, 2, 3 Source<br>4 Gate<br>5, 6, 7, 8 Darin<br>Source<br>**----- End of picture text -----**<br> **Remark** Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. R07DS1320EJ0100 Rev.1.00 Jan 25, 2016 Page 6 of 6 **==> picture [460 x 383] intentionally omitted <==** **----- Start of picture text -----**<br> Notice<br>1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for<br>the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the<br>use of these circuits, software, or information.<br>2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. 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