TVS8501V5MUT5G

TVS8501V5 

## Transient Voltage Suppressors 

## **Features** 

- Protection for the following IEC Standards: 

   - IEC61000−4−2 Level 4: ±30 kV Contact Discharge IEC61000−4−5 (Lightning) 70 A (8/20 s) , 

- These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant 

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1 2 Cathode Anode 

## **MAXIMUM RATINGS** 

~~es~~ **Rating Symbol** ~~es~~ **Value Unit** IEC 61000−4−2 (ESD) Contact ± 30 kV Air ± 30 ~~|~~ Operating Junction and Storage TJ, Tstg −65 to +150 ° C **UDFN2** Temperature Range ~~ee ee| ft~~ , © Maximum Peak Pulse Current IPP 70 A 8/20 s @ TA = 25 ° C A ~~ee~~ 

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MARKING<br>DIAGRAM<br>UDFN2 A M<br>CASE 517CZ<br>© 1<br>A = Specific Device Code<br>M = Date Code<br>**----- End of picture text -----**<br>


Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

## **ORDERING INFORMATION** 

|**Device**|**Package**|**Shipping**†|
|---|---|---|
|TVS8501V5MUT5G|UDFN2<br>(Pb−Free)|8000 / Tape &<br>Reel|



- †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

Publication Order Number: 

**1** 

© Semiconductor Components Industries, LLC, 2014 **November, 2014 − Rev. 1** 

**TVS8501V5/D** 

**TVS8501V5** 

## **ELECTRICAL CHARACTERISTICS** 

## (TA = 25 ° C unless otherwise noted) 

|(TA= 25°C|unless otherwise noted)|
|---|---|
|**Symbol**|**Parameter**|
|IPP|Maximum Reverse Peak Pulse Current|
|VC|Clamping Voltage @ IPP|
|VRWM|Working Peak Reverse Voltage|
|IR|Maximum Reverse Leakage Current @ VRWM|
|VBR|Breakdown Voltage @ IT|
|IT|Test Current|



*See Application Note AND8308/D for detailed explanations of datasheet parameters. 

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I<br>IF<br>VC VBR VRWM<br>V<br>IR VF<br>IT<br>IPP<br>Uni−Directional TVS<br>**----- End of picture text -----**<br>


## **ELECTRICAL CHARACTERISTICS** (TA = 25 ° C unless otherwise specified) 

|**Parameter**|**Symbol**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Reverse Working Voltage|VRWM||||5.0|V|
|Breakdown Voltage (Note 1)|VBR|IT= 1 mA|6.0|7.0|9.0|V|
|Reverse Leakage Current|IR|VRWM= 5 V|||0.1|�A|
|Clamping Voltage (Note 2)|VC|IPP= 1 A, tp= 8 x 20�s|||7.5|V|
|Clamping Voltage (Note 2)|VC|IPP= 35 A, tp= 8 x 20�s|||9.5|V|
|Clamping Voltage (Note 2)|VC|IPP= 70 A, tp= 8 x 20�s|||11.5|V|
|Junction Capacitance|CJ|VR= 0 V, f = 1 MHz|||16|pF|
|Dynamic Resistance|RDYN|TLP Pulse||0.04||�|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

1. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1. 

2. Non−repetitive current pulse at TA = 25 ° C, per IEC61000−4−5 waveform. 

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**2** 

**TVS8501V5** 

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9 14<br>8<br>12<br>7<br>10<br>6<br>5 8<br>4 6<br>3<br>4<br>2<br>2<br>1<br>0 0<br>0 5 10 15 20 25 30 0 10 20 30 40 50 60 70 80<br>Ipk (A) Ipk (A)<br> (V)  (V)<br>pk pk<br>V V<br>**----- End of picture text -----**<br>


**Figure 1. Positive TLP I−V Curve** 

**Figure 2. Clamping Voltage vs. Peak Pulse Current (tp = 8/20 � s)** 

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50<br>45<br>40<br>35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>0 1 2 3 4 5 6<br>VBias (V)<br>C (pF)<br>**----- End of picture text -----**<br>


**Figure 3. CV Characteristics** 

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**TVS8501V5** 

## **Transmission Line Pulse (TLP) Measurement** 

Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 4. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 5 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. For more information on TLP measurements and how to interpret them please refer to AND9007/D. 

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L — | S Attenuator 50  CoaxCable Q<br>SSFee ÷ wy,<br>50  Coax<br>Cable 10 M IM VM<br>Q i<br>DUT<br>VC<br>Oscilloscope<br>**----- End of picture text -----**<br>


**Figure 4. Simplified Schematic of a Typical TLP System** 

**Figure 5. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms** 

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**4** 

**TVS8501V5** 

## **IEC 61000−4−2 Spec.** 

|**Level**|**Test Volt-**<br>**age (kV)**|**First Peak**<br>**Current**<br>**(A)**|**Current at**<br>**30 ns (A)**|**Current at**<br>**60 ns (A)**|
|---|---|---|---|---|
|1|2|7.5|4|2|
|2|4|15|8|4|
|3|6|22.5|12|6|
|4|8|30|16|8|



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IEC61000−4−2 Waveform<br>Ipeak<br>100%<br>90%<br>I @ 30 ns<br>I @ 60 ns<br>10%<br>tP = 0.7 ns to 1 ns<br>**----- End of picture text -----**<br>


**Figure 6. IEC61000−4−2 Spec** 

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ESD Gun Oscilloscope<br>TVS<br>50  �<br>Cable 50  �<br>**----- End of picture text -----**<br>


**Figure 7. Diagram of ESD Test Setup** 

## **ESD Voltage Clamping** 

For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage 

at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. 

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100<br>tr PEAK VALUE IRSM @ 8 �s<br>90<br>80 PULSE WIDTH (tP) IS DEFINED<br>AS THAT POINT WHERE THE<br>70 PEAK CURRENT DECAY = 8 �s<br>60<br>HALF VALUE IRSM/2 @ 20 �s<br>50<br>40<br>30<br>tP<br>20<br>10<br>0<br>0 20 40 60 80<br>t, TIME ( � s)<br>% OF PEAK PULSE CURRENT<br>**----- End of picture text -----**<br>


**Figure 8. 8 X 20 � s Pulse Waveform** 

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**5** 

**TVS8501V5** 

## **PACKAGE DIMENSIONS** 

**UDFN2 1.6x1.0, 1.1P** CASE 517CZ ISSUE A 

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D A NOTES:<br>B 1. DIMENSIONING AND TOLERANCING PER<br>ASME Y14.5M, 1994.<br>Ty 2. CONTROLLING DIMENSION: MILLIMETERS.<br>PIN ONE<br>REFERENCE MILLIMETERS<br>E DIM MIN MAX<br>2X 0.08 C ÉÉÉ A 0.45 0.55<br>A1 −−− 0.05<br>ÉÉÉ b 0.85 0.95<br>2X 0.08 C TOP VIEW D 1.60 BSC<br>E 1.00 BSC<br>e 1.10 BSC<br>ant] # = L 0.35 0.45<br>0.05 C A<br>RECOMMENDED<br>SOLDERING FOOTPRINT*<br>0.05 C<br>SIDE VIEW A1 C [SEATING] PLANE 1.70 1.002X<br>e<br>1<br>e/2<br>0.07 M C A B<br>1<br>b 2X<br>0.58<br>ai e<br>DIMENSIONS: MILLIMETERS<br>2X L<br>0.07 M C A B *For additional information on our Pb−Free strategy and soldering<br>BOTTOM VIEW details, please download the ON Semiconductor Soldering and<br>Mounting Techniques Reference Manual, SOLDERRM/D.<br>**----- End of picture text -----**<br>


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**TVS8501V5/D** 

**6**