TS64GSDXC10M

**4~32GB High Capacity Secure Digital Card** 

## **Rev. 1.0** 

## Description 

Transcend High Capacity SD Card series are specifically designed to meet the High Capacity, High Definition Audio and Video requirement for the latest Digital Cameras, DV Recorders, GPS, etc. The new defined Speed Class 10 enables the host to support AV applications to perform real time recording to the SD memory card. 

## Features 

- RoHS compliant product. 

- Card Lid material: PC + ABS 

- Operating Voltage: 2.7 ~ 3.6V 

- Operating Temperature: -25 ~ 85°C 

- Durability: 10,000 insertion/removal cycles 

- Compatible with SD Specification Ver. 3.0 

- Mechanical Write Protection Switch 

- Supports Speed Class Specification up to Class 10 

## Placement 

- Supports Copy Protection for Recorded Media (CPRM) for SD-Audio 

- Form Factor: 24mm x 32mm x 2.1mm 

Front                        Back 

|Pin No.<br>~~re~~<br>~~a~~|SD Mode<br>~~eS~~<br>~~reee ees~~|SD Mode<br>~~eS~~<br>~~reee ees~~|SD Mode<br>~~eS~~<br>~~reee ees~~|SPI Mode<br>~~eS~~<br>~~eeses~~|SPI Mode<br>~~eS~~<br>~~eeses~~|SPI Mode<br>~~eS~~<br>~~eeses~~|
|---|---|---|---|---|---|---|
||Name<br>~~re~~<br>|Type<br>~~ee ees~~<br>|Description<br>~~ees~~<br>|Name<br>~~ees~~<br>~~ee~~<br>|Type<br>~~es~~<br>~~ee~~<br>|Description<br>|
|1<br>~~re~~<br>~~a~~<br>~~a~~|CD/DAT <br>~~re ~~<br>~~ee~~<br>|I/O/PP3 <br> ~~ee ees~~<br>~~ee~~<br>|Card Detect/Data Line[Bit3]<br>~~ees ~~<br>~~ee~~<br>|CS<br> ~~ees ~~<br>~~ee~~<br>~~ee~~<br>|I<br> ~~es~~<br>~~ee~~<br>~~ee~~<br>|ChipSelect(negtrue)<br>~~ee~~<br>|
|2<br>~~a~~|CMD<br>~~ee~~|PP<br>~~ee~~|Command/Response<br>~~ee~~|DI<br>~~ee ~~<br>~~ee~~|I<br> ~~ee~~<br>~~ee~~|Data In<br>~~ee~~|
|3<br>~~a~~<br>~~a~~|VSS1<br>|S<br>|Supplyvoltageground<br>|VSS<br>|S<br>~~ee ee~~<br>|Supplyvoltageground<br>~~ee~~<br>|
|4<br>~~a ~~<br>~~a~~<br>~~a~~|VDD<br> ~~a~~<br>|S<br>~~ee~~<br>|Supplyvoltage<br>~~ee~~<br>|VDD<br>~~ee~~<br><br>~~ee~~|S<br>~~ee~~<br>~~ee ee~~<br><br>~~ee~~|Supplyvoltage<br>~~ee~~<br>~~ee~~<br>|
|5<br>~~a~~<br>~~a~~|CLK<br>~~ee~~|I<br>~~ee~~|Clock<br>~~ee~~|SCLK<br>~~ee~~<br>~~ee~~|I<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|Clock<br>~~ee~~<br>~~ee~~|
|6<br>~~a~~<br>~~Se~~|VSS2|S|Supplyvoltageground|VSS2<br>~~ee ~~|S<br> ~~ee~~|Supplyvoltageground|
|7<br>~~Se~~<br>~~a~~|DAT0<br>~~a~~|I/O/PP<br>|Data Line[Bit0]|DO<br>~~ee~~|O/PP<br>~~ee~~|Data Out|
|8<br>~~Se~~<br>~~a~~<br>~~a~~|DAT1<br>~~ee~~<br>~~a~~|I/O/PP<br>~~ee~~<br>|Data Line[Bit1]<br>~~ee~~|RSV<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|~~ee~~|
|9<br>~~a~~|DAT2<br>~~a ~~|I/O/PP<br> ~~a~~|Data Line [Bit2]|RSV<br>~~ee ~~|~~ee~~||



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**Rev. 1.0** 

**4~32GB High Capacity Secure Digital Card** 

## Architecture 

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**Rev. 1.0** 

## **4~32GB High Capacity Secure Digital Card** 

## Bus Operating Conditions 

## **• General** 

|Parameter|Symbol|Min.|Max.|Unit|Remark|
|---|---|---|---|---|---|
|Peak voltage on all lines||-0.3|VDD+0.3|V||
|All Inputs||||||
|Input Leakage Current||-10|10|µA||
|All Outputs||||||
|Output Leakage Current||-10|10|µA||



## **• Power Supply Voltage** 

|Parameter|Symbol|Min.|Max.|Unit|Remark|
|---|---|---|---|---|---|
|Supplyvoltage|VDD|2.7|3.6|V||
|Output High Voltage|VOH|0.75* VDD||V|IOH=-100uA@VDD Min.|
|Output Low Voltage|VOL||0.125* VDD|V|IOL=100uA@VDD Min.|
|Input High Voltage|VIH|0.625* VDDV|VDD+0.3|V||
|Input Low Voltage|VIL|VSS-0.3|0.25* VDD|V||
|Power uptime|||250|ms|From 0v to VDD Min.|



## **• Current Consumption** 

The current consumption is measured by averaging over 1 second. 

- Before first command: Maximum 15 mA 

- During initialization: Maximum 100 mA 

- Operation in Default Mode: Maximum 100 mA 

- Operation in High Speed Mode: Maximum 200 mA 

- Operation with other functions: Maximum 500 mA. 

## **• Bus Signal Line Load** 

The total capacitance CL the CLK line of the SD Memory Card bus is the sum of the bus master capacitance CHOST, the bus capacitance CBUS itself and the capacitance CCARD of each card connected to this line: CL = CHOST + CBUS + Ν*CCARD 

Where N is the number of connected cards. 

|Parameter|Symbol|Min.|Max.|Unit|Remark|
|---|---|---|---|---|---|
|Pull-up resistance|RCMD<br>RDAT|10|100|kΩ|To prevent bus floating|
|Bus signal line capacitance|CL||40|pF|1 card<br>CHOST+CBUSshall not exceed<br>30pF|



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## **Rev. 1.0** 

## **4~32GB High Capacity Secure Digital Card** 

|Single card capacitance|CCARD||10|pF||
|---|---|---|---|---|---|
|Maximum signal line inductance|||16|nH|fPP ≤20 MHz|
|Pull-up resistance inside card (pin1)|RDAT3|10|90|kΩ|May be used for card<br>detection|



Note that the total capacitance of CMD and DAT lines will be consist of CHOST, CBUS and one CCARD only because they are connected separately to the SD Memory Card host. 

Host should consider total bus capacitance for each signal as the sum of CHOST, CBUS, and CCARD, these parameters are defined by per signal. The host can determine CHOST and CBUS so that total bus capacitance is less than the card estimated capacitance load (CL=40 pF). The SD Memory Card guarantees its bus timing when total bus capacitance is less than maximum value of CL (40 pF). 

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## **Rev. 1.0** 

## **4~32GB High Capacity Secure Digital Card** 

## **• Bus Signal Levels** 

As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage. 

To meet the requirements of the JEDEC specification JESD8-1A and JESD8-7, the card input and output voltages shall be within the following specified ranges for any VDD of the allowed voltage range: 

|Parameter|Symbol|Min.|Max.|Unit|Remark|
|---|---|---|---|---|---|
|Output HIGH voltage|VOH|0.75*VDD||V|IOH= -100µA@VDDmin|
|Output LOW voltage|VOL||0.125*VDD|V|IOL= -100µA@VDDmin|
|Input HIGH voltage|VIH|0.625*VDD|VDD+ 0.3|V||
|Input LOW voltage|VIL|VSS– 0.3|0.25*VDD|V||



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**Rev. 1.0** 

## **4~32GB High Capacity Secure Digital Card** 

## **• Bus Timing** 

|Parameter<br>~~Pe~~|Symbol<br>~~Pe~~|Min<br>~~Pe~~|Max.<br>~~Pe~~|Unit<br>~~Pe~~|Remark<br>~~Pe~~|
|---|---|---|---|---|---|
|Clock CLK (All values are referred to min (VIH) and max (VIL)<br>~~|~~||||||
|Clock frequency Data Transfer Mode<br>~~ef~~|fPP<br>~~ef~~<br>~~rs~~|0<br>~~ef~~<br>~~rs~~|25<br>~~ef~~<br>~~rs~~|MHz<br>~~ef~~<br>~~rs~~|CCARD ≤10 pF, (1 card)<br>~~ef~~|
|Clock frequency Identification Mode<br>~~rs~~|fOD<br>~~rs~~<br>~~rs~~<br>~~re~~|0(1)/100<br>~~rs~~<br>~~rs~~<br>~~rs~~|400<br>~~rs~~<br>~~rs~~<br>~~rs~~|KHz<br>~~rs~~<br>~~rs~~<br>~~rs~~|CCARD ≤10 pF, (1 card)<br>~~rs~~|
|Clock low time<br>~~rs~~|tWL<br>~~rs ~~<br>~~rs~~<br>~~re~~|(1)<br>10<br> ~~rs ~~<br>~~rs~~<br>~~rs~~|~~rs ~~<br>~~rs~~<br>~~rs~~|ns<br> ~~rs~~<br>~~rs~~<br>~~rs~~|CCARD ≤10 pF, (1 card)<br>~~rs~~|
|Clock high time<br>~~ee~~|tWH<br>~~re~~<br>~~ee~~|10<br>~~rs ~~<br>~~ee~~|~~rs~~<br>~~ee~~|ns<br>~~rs~~<br>~~ee~~|CCARD ≤10 pF, (1 card)<br>~~ee~~|
|Clock rise time<br>~~|~~|tTLH<br>~~|~~|~~|~~|10<br>~~|~~|ns<br>~~|~~|CCARD ≤10 pF, (1 card)<br>~~|~~|
|Clock fall time<br>~~|~~|tTHL<br>~~|~~|~~|~~|10<br>~~|~~|ns<br>~~|~~|CCARD ≤10 pF, (1 card)<br>~~|~~|
|Inputs CMD, DAT (referenced to CLK)<br>~~rsrs~~||||||
|Input set-up time<br>~~rr~~|tISU<br>~~rr~~<br>~~rs~~|5<br>~~rr~~<br>~~rs~~|~~rr~~<br>~~rs~~|ns<br>~~rr~~|CCARD ≤10 pF, (1 card)<br>~~rr~~|
|Input hold time<br>~~|~~|tIH<br>~~rs ~~<br>~~|~~|5<br> ~~rs~~<br>~~|~~|~~rs~~<br>~~|~~|ns<br>~~|~~|CCARD ≤10 pF, (1 card)<br>~~|~~|



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**Rev. 1.0** 

|**SDHC10 Card series**||||||
|---|---|---|---|---|---|
|**SDHC10 Card series**||**4~32GB High Capacity Secure Digital Card**||||
|||||||
|Outputs CMD, DAT (referenced to CLK)||||||
|Output Delay time during Data Transfer Mode|tODLY|0|14|ns|CL ≤40 pF, (1 card)|
|Output Delay time during Identification Mode|tODLY|0|50|ns|CL ≤40 pF, (1 card)|



(1) 0 Hz means to stop the clock. The given minimum frequency range is for cases were continues clock is required 

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**Rev. 1.0** 

## **4~32GB High Capacity Secure Digital Card** 

## **• Bus Timing (High Speed Mode)** 

|Parameter<br>~~Pf~~|Symbol<br>~~Pf~~|Min<br>~~Pf~~|Max.<br>~~Pf~~|Unit<br>~~Pf~~|Remark<br>~~Pf~~|
|---|---|---|---|---|---|
|Clock CLK (All values are referred to min (VIH) and max (VIL)<br>~~Ce~~||||||
|Clock frequency Data Transfer Mode|fPP<br>~~es~~|0<br>~~ss~~|50<br>~~ss~~|MHz<br>~~ss~~|CCARD ≤10 pF, (1 card)|
|Clock low time<br>~~es~~|tWL<br>~~es~~<br>~~es~~<br>~~GG~~|7<br>~~es~~<br>~~ss~~<br>~~GG~~|~~es~~<br>~~ss~~<br>~~GG~~|ns<br>~~es~~<br>~~ss~~|CCARD ≤10 pF, (1 card)<br>~~es~~|
|Clock high time<br>~~en~~|tWH<br>~~es ~~<br>~~en~~<br>~~GG~~|7<br> ~~ss~~<br>~~en~~<br>~~GG~~|~~ss~~<br>~~en~~<br>~~GG~~|ns<br>~~ss~~<br>~~en~~|CCARD ≤10 pF, (1 card)<br>~~en~~|
|Clock rise time<br>~~QQ~~|tTLH<br>~~GG~~<br>~~QQ~~|~~GG~~<br>~~QQ~~|3<br>~~GG~~<br>~~QQ~~|ns<br>~~QQ~~|CCARD ≤10 pF, (1 card)<br>~~QQ~~|
|Clock fall time<br>~~Ce~~|tTHL<br>||3<br>|ns<br>|CCARD ≤10 pF, (1 card)<br>|
|Inputs CMD, DAT (referenced to CLK)<br>~~Ce~~||||||
|Input set-up time<br>~~CeGG~~|tISU<br>~~GG~~<br>~~Gs~~|6<br>~~GG~~<br>~~Gs~~|~~GG~~<br>~~Gs~~|ns<br>~~GG~~|CCARD ≤10 pF, (1 card)<br>~~GG~~|
|Input hold time<br>~~en~~|tIH<br>~~en~~<br>~~Gs~~|2<br>~~en~~<br>~~Gs~~|~~en~~<br>~~Gs~~|ns<br>~~en~~|CCARD ≤10 pF, (1 card)<br>~~en~~|
|Outputs CMD, DAT (referenced to CLK)<br>~~Gs~~<br>~~Pn~~||||||



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**Rev. 1.0** 

## **4~32GB High Capacity Secure Digital Card** 

|Output Delay time during Data Transfer Mode|tODLY||14|ns|CL ≤40 pF, (1 card)|
|---|---|---|---|---|---|
|Output Hold time|tOH|2.5||ns|CL ≤40 pF, (1 card)|
|Total System capacitance for each line1|CL||40|pF|(1 card)|



1) In order to satisfy severe timing, host shall drive only one card. 

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## Reliability and Durability 

|Reliability and Durability|Reliability and Durability|
|---|---|
|Temperature|Operation: -25°C / 85°C<br>Storage: -40°C (168h) / 85°C (500h)<br>Junction temperature: max. 95°C|
|Moisture and corrosion|Operation: 25°C / 95% rel. humidity<br>Storage: 40°C / 93% rel. hum./500h<br>Salt Water Spray: 3% NaCl/35C;24h acc. MIL STD Method 1009|
|Durability|10.000 matingcycles|
|Bending|10N|
|Torque|0.15N.m or +/-2.5 deg|
|Droptest|1.5m free fall|
|Visual inspection<br>Shape and form|No warp page; no mold skin; complete form; no cavities surface smoothness <= -0.1<br>mm/cm² within contour;no cracks;nopollution(fat,oil dust,etc.)|
|Minimum movingforce of WP witch 40|force of WP witch 40gf(Ensures that the WP switch will not slide while it is inserted to the connector.)|
|WP Switch cycles|minimum 1000 Cycles(@Slide force 0.4N to 5N)|



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## **4~32GB High Capacity Secure Digital Card** 

## Register Information 

Within the card interface six registers are defined: OCR, CID, CSD, RCA, DSR and SCR. These can be accessed only by corresponding commands. The OCR, CID, CSD and SCR registers carry the card/content specific information, while the RCA and DSR registers are configuration registers storing actual configuration parameters. 

## **1. OCR register** 

The 32-bit operation conditions register stores the VDD voltage profile of the card. Additionally, this register includes status information bits. One status bit is set if the card power up procedure has been finished. This register includes another status bit indicating the card capacity status after set power up status bit. The OCR register shall be implemented by the cards. The 32-bit operation conditions register stores the VDD voltage profile of the card. Bit 7 of OCR is newly defined for Dual Voltage Card and set to 0 in default. If a Dual Voltage Card does not receive CMD8, OCR bit 7 in the response indicates 0, and the Dual Voltage Card which received CMD8, sets this bit to 1. Additionally, this register includes 2 more status information bits. 

Bit 31 - Card power up status bit, this status bit is set if the card power up procedure has been finished. Bit 30 - Card Capacity Status bit, 0 indicates that the card is SDSC. 1 indicates that the card is SDHC or SDXC. The Card Capacity Status bit is valid after the card power up procedure is completed and the card power up status 

The OCR register shall be implemented by the cards. 

**OCR Register Definition** 

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**4~32GB High Capacity Secure Digital Card** 

- 1) This bit is valid only when the card power up status bit is set. 

2) This bit is set to LOW if the card has not finished the power up routine. 3) Only UHS-I card supports this bit. 

A voltage range is not supported if the corresponding bit value is set to LOW. As long as the card is busy, the corresponding bit (31) is set to LOW. 

## **2. CID Register** 

The Card Identification (CID) register is 128 bits wide. It contains the card identification information used during the card identification phase. Every individual flash card shall have a unique identification number. The structure of the CID register is defined in the following paragraphs: 

|**Name**|**Field**|**Width**|**CID-slice**|
|---|---|---|---|
|Manufacturer ID|MID|8|[127:120]|
|OEM/Application ID|OID|16|[119:104]|
|Product name|PNM|40|[103:64]|
|Product revision|PRV|8|[103:64]<br>[63:56]|
|Product serial number|PSN|32|[55:24]|
|reserved|--|4|[23:20]|
|Manufacturingdate|MDT|12|[19:8]|
|CRC7 checksum|CRC|7|[7:1]|
|not used, always 1|-|1|[0:0]|



**The CID Fields** 

## **• MID** 

An 8-bit binary number that identifies the card manufacturer. The MID number is controlled, defined, and allocated to a SD Memory Card manufacturer by the SD-3C, LLC. This procedure is established to ensure uniqueness of the CID register. 

## **• OID** 

A 2-character ASCII string that identifies the card OEM and/or the card contents (when used as a distribution media either on ROM or FLASH cards). The OID number is controlled, defined, and allocated to a SD Memory Card manufacturer by the SD-3C, LLC. This procedure is established to ensure uniqueness of the CID register. 

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## **Rev. 1.0 4~32GB High Capacity Secure Digital Card** 

Note: SD-3C, LLC licenses companies that wish to manufacture and/or sell SD Memory Cards, including but not limited to flash memory, ROM, OTP, RAM, and SDIO Combo Cards. 

SD-3C, LLC is a limited liability company established by Matsushita Electric Industrial Co. Ltd., SanDisk Corporation and Toshiba Corporation. 

## **• PNM** 

The product name is a string, 5 ASCII characters long. 

## **• PRV** 

The product revision is composed of two Binary Coded Decimal (BCD) digits, four bits each, representing an “n.m” revision number. The “n” is the most significant nibble and “m” is the least significant nibble. As an example, the PRV binary value field for product revision “6.2” will be: 0110 0010b 

## **• PSN** 

The Serial Number is 32 bits of binary number. 

## **• MDT** 

The manufacturing date composed of two hexadecimal digits, one is 8 bit representing the year(y) and the other is four bits representing the month(m). 

The “m” field [11:8] is the month code. 1 = January. The “y” field [19:12] is the year code. 0 = 2000. 

As an example, the binary value of the Date field for production date “April 2001” will be: 00000001 0100. 

## **• CRC** 

CRC7 checksum (7 bits). 

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**4~32GB High Capacity Secure Digital Card** 

## **3. CSD Register** 

The CSD Register shows Definition of the CSD for the High Capacity SD Memory Card and Extended Capacity SD Memory Card (CSD Version 2.0). The following sections describe the CSD fields and the relevant data types for the High Capacity SD Memory Card. 

CSD Version 2.0 is applied to SDHC and SDXC Cards. The field name in parenthesis is set to fixed value and indicates that the host is not necessary to refer these fields. The fixed values enables host, which refers to these fields, to keep compatibility to CSD Version 1.0. The Cell Type field is coded as follows: R = readable, W(1) = writable once, W = multiple writable. 

|**Name**|**Field**|**Width**|**Value**|**Cell Type**|**CSD-slice**|
|---|---|---|---|---|---|
|CSD structure|CSD_STRUCTURE|2|01b|R|[127:126]|
|reserved<br>~~a~~|-<br>~~ee~~|6<br>ee|00 0000b|R|[125:120]|
|data read access-time<br>~~a~~<br>~~a~~|(TAAC)<br>~~a~~<br>~~ee~~<br>~~ee~~|8<br>~~a~~<br>ee<br>~~ee~~|0Eh<br>~~a~~<br>~~ee~~|R<br>~~a~~|[119:112]<br>~~a~~|
|data read access-time in CLK (NSAC)<br>~~a~~|data read access-time in CLK (NSAC)<br>~~ee~~ <br>~~ee~~<br>~~ee~~|8<br> ee<br>~~ee~~<br>~~ee~~|00h<br>~~ee~~<br>~~ee~~|R<br>~~ee~~|[111:104]|
|max. data transfer rate<br>~~a~~|(TRAN_SPEED)<br>~~ee ~~<br>~~a~~<br>~~ee~~<br>~~ee~~|8<br> ~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~|32h, 5Ah, 0Bh or 2Bh <br>~~ee~~<br>~~a~~<br>~~ee~~|R<br>~~a~~<br>~~ee~~|[103:96]<br>~~a~~|
|card command classes<br>~~ae~~|CCC<br>~~ee ~~<br>~~ae~~<br>~~ee~~<br>~~ee~~|12<br> ~~ee~~<br>~~ae~~<br>~~ee~~<br>~~es~~|01x110110101b<br>~~ee~~<br>~~ae~~|R<br>~~ee~~<br>~~ae~~|[95:84]<br>~~ae~~|
|max. read data block length<br>~~a~~|(READ_BL_LEN)<br>~~ee ~~<br>~~a~~<br>~~ee~~|4<br> ~~ee~~<br>~~a~~<br>~~es~~|9<br>~~a~~|R<br>~~a~~|[83:80]<br>~~a~~|
|partial blocks for read allowed <br>~~ee~~|(READ_BL_PARTIAL)<br>~~ee ~~<br>~~ee~~<br>~~ee~~|1<br> ~~es~~<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|R<br>~~ee~~|[79:79]<br>~~ee~~|
|write block misalignment<br>~~ee~~|(WRITE_BLK_MISALIGN) <br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|R<br>~~ee~~|[78:78]<br>~~ee~~|
|read block misalignment<br>~~ee~~|(READ_BLK_MISALIGN)<br>~~ee ~~<br>~~ee~~|1<br> ~~ee~~<br>~~ee~~|0<br>~~ee~~<br>~~ee~~|R<br>~~ee~~|[77:77]<br>~~ee~~|
|DSR implemented|DSR_IMP|1|x|R|[76:76]|
|reserved|-|6|00 0000b|R|[75:70]|
|device size|C_SIZE|22|xxxxxxh|R|[69:48]|
|reserved|-<br>~~ee~~|1<br>~~es~~|0|R|[47:47]|
|erase single block enable<br>~~a~~|(ERASE_BLK_EN)<br>~~a~~<br>~~ee~~<br>~~ee~~|1<br>~~a~~<br>~~es~~<br>~~ee ee~~|1<br>~~a~~<br>~~ee~~|R<br>~~a~~<br>~~ee~~|[46:46]<br>~~a~~|
|erase sector size<br>~~a~~|(SECTOR_SIZE)<br>~~ee ~~<br>~~a~~<br>~~ee~~<br>~~ee~~|7<br> ~~es~~<br>~~a~~<br>~~ee ee~~<br>~~ee~~|7Fh<br>~~a~~<br>~~ee~~|R<br>~~a~~<br>~~ee~~|[45:39]<br>~~a~~|
|write protect group size<br>~~ee~~|(WP_GRP_SIZE)<br>~~ee ~~<br>~~ee~~<br>~~ee~~|7<br> ~~ee ee~~<br>~~ee~~<br>~~ee~~|0000000b<br>~~ee~~<br>~~ee~~|R<br>~~ee~~<br>~~ee~~|[38:32]<br>~~ee~~|
|write protect group enable|(WP_GRP_ENABLE)<br>~~ee ~~|1<br> ~~ee~~|0|R|[31:31]|
|reserved||2|00b|R|[30:29]|



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**4~32GB High Capacity Secure Digital Card** 

## **Rev. 1.0** 

||~~ee~~|~~ee~~||||
|---|---|---|---|---|---|
|write speed factor<br>~~a~~|(R2W_FACTOR)<br>~~a~~<br>~~ee~~<br>~~ee~~|3<br>~~a~~<br>~~ee~~<br>~~ee ee~~|010b<br>~~a~~<br>~~ee~~|R<br>~~a~~|[28:26]<br>~~a~~|
|max. write data block length<br>~~a~~|(WRITE_BL_LEN)<br>~~ee ~~<br>~~a~~<br>~~ee~~|4<br> ~~ee~~<br>~~a~~<br>~~ee ee~~|9<br>~~a~~<br>~~ee~~|R<br>~~a~~|[25:22]<br>~~a~~|
|partial blocks for write allowed|(WRITE_BL_PARTIAL)<br>~~ee ~~|1<br> ~~ee ee~~|0<br>~~ee~~|R|[21:21]|
|reserved|-<br>~~ee~~|5<br>~~ee ee~~|00000b<br>~~ee~~|R<br>~~ee~~|[20:16]|
|File format group<br>~~ee~~|(FILE_FORMAT_GRP)<br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee ee~~|0<br>~~ee~~<br>~~ee~~|R<br>~~ee~~<br>~~ee~~|[15:15]<br>~~ee~~|
|copyflag<br>~~es~~|COPY<br>~~ee~~<br>~~es~~|1<br>~~ee ee~~<br>~~es~~|x<br>~~ee ~~<br>~~es~~|R/W(1)<br> ~~ee~~<br>~~es~~|[14:14]<br>~~es~~|
|permanent writeprotection<br>~~ee~~|PERM_WRITE_PROTECT <br>~~ee~~|1<br>~~ee~~|x<br>~~ee~~|R/W(1)<br>~~ee~~|[13:13]<br>~~ee~~|
|temporary write protection<br>~~ee~~|TMP_WRITE_PROTECT <br>~~ee~~|1<br>~~ee~~|x<br>~~ee~~|R/W<br>~~ee~~|[12:12]<br>~~ee~~|
|File format|(FILE_FORMAT)|2|00b|R|[11:10]|
|reserved<br>~~es~~|-<br>~~es~~|2<br>~~es~~|00b|R|[9:8]|
|CRC<br>~~es~~|CRC<br>~~es~~|7<br>~~es~~|xxxxxxxb|R/W|[7:1]|
|not used, always'1'<br>~~es~~<br>~~ee~~|-<br>~~es~~<br>~~ee~~|1<br>~~es~~<br>~~ee~~|1<br>~~ee~~|-<br>~~ee~~|[0:0]|



**The CSD Register Fields (CSD Version 2.0)** 

The following sections describe the CSD fields and the relevant data types. If not explicitly defined otherwise, all bit strings are interpreted as binary coded numbers starting with the left bit first. 

## **• CSD_STRUCTURE** 

Field structures of the CSD register are different depend on the Physical Specification Version and Card Capacity. The CSD_STRUCTURE field in the CSD register indicates its structure version. The following table shows the version number of the related CSD structure. 

|**CSD_STRUCTURE**|**CSD structure version**|**Card Capacity**|
|---|---|---|
|0|CSD Version 1.0|Standard Capacity|
|1|CSD Version 2.0|Standard Capacity<br>High Capacity and Extended Capacity|
|2-3|reserved|High Capacity and Extended Capacity|



**CSD Register Structure** 

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## **• TAAC** 

This field is fixed to 0Eh, which indicates 1 ms. The host should not use TAAC, NSAC, and R2W_FACTOR to calculate timeout and should uses fixed timeout values for read and write operations. 

|**TAAC bit position**|**code**|
|---|---|
|2:0|time unit<br>0=1ns, 1=10ns, 2=100ns, 3=1µs, 4=10µs,<br>5=100µs, 6=1ms, 7=10ms|
|6:3|time value<br>0=reserved,   1=1.0,   2=1.2,   3=1.3,   4=1.5,<br>5=2.0,<br>6=2.5, 7=3.0, 8=3.5, 9=4.0, A=4.5, B=5.0,<br>C=5.5, D=6.0, E=7.0, F=8.0|
|7|reserved|



## **• NSAC** 

This field is fixed to 00h. NSAC should not be used to calculate time-out values. 

## **• TRAN_SPEED** 

The following table defines the maximum data transfer rate per one data line - TRAN_SPEED: 

|**TRAN SPEED bit**|**code**|
|---|---|
|2:0|transfer rate unit<br>0=100kbit/s, 1=1Mbit/s, 2=10Mbit/s,<br>3=100Mbit/s, 4... 7=reserved|
|6:3|time value<br>0=reserved, 1=1.0, 2=1.2, 3=1.3, 4=1.5,<br>5=2.0, 6=2.5, 7=3.0, 8=3.5, 9=4.0, A=4.5,<br>B=5.0,C=5.5,D=6.0,E=7.0,F=8.0|
|7|reserved|



## **Maximum Data Transfer Rate Definition** 

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Note that for current SD Memory Cards that field must be always 0_0110_010b (032h) which is equal to 25MHz - the mandatory maximum operating frequency of SD Memory Card. 

In High-Speed mode, that field must be always 0_1011_010b (05Ah) which is equal to 50MHz. And when the timing mode returns to the default by CMD6 or CMD0 command, its value will be 032h. 

## **• CCC** 

The SD Memory Card command set is divided into subsets (command classes). The card command class register CCC defines which command classes are supported by this card. A value of ‘1’ in a CCC bit means that the corresponding command class is supported. 

|**CCC bit**|**Supported card command class**|
|---|---|
|0|class 0|
|1|class 1|
|......||
|11|class 11|



## **• READ_BL_LEN** 

This field is fixed to 9h, which indicates READ_BL_LEN=512 Byte. 

## **• READ_BL_PARTIAL** 

This field is fixed to 0, which indicates partial block read is inhibited and only unit of block access is allowed. 

## **• WRITE_BLK_MISALIGN** 

This field is fixed to 0, which indicates that write access crossing physical block boundaries is always disabled in SDHC and SDXC Cards. 

## **• READ_BLK_MISALIGN** 

This field is fixed to 0, which indicates that read access crossing physical block boundaries is always disabled in SDHC and SDXC Cards. 

## **• DSR_IMP** 

Defines if the configurable driver stage is integrated on the card. If set, a driver stage register (DSR) must be implemented also. 

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|**DSR_IMP**|**DSR type**|
|---|---|
|0|no DSR implemented|
|1|DSR implemented|



**DSR Implementation Code Table** 

## **• C_SIZE** 

This field is expanded to 22 bits and can indicate up to 2 TBytes (It is the same as the maximum memory space specified by a 32-bit block address.) This parameter is used to calculate the user data area capacity in the SD memory card (not include the protected area). The user data area capacity is calculated from C_SIZE as follows: 

memory capacity = (C_SIZE+1) * 512K byte 

The Minimum user area size of SDHC Card is 4,211,712 sectors (2GB + 8.5MB). The Minimum value of C_SIZE for SDHC in CSD Version 2.0 is 001010h (4112). 

The maximum user area size of SDHC Card is (32GB - 80MB) The maximum value of C_SIZE for SDHC in CSD Version 2.0 is 00FF5Fh (65375). 

## **• ERASE_BLK_EN** 

This field is fixed to 1, which means the host can erase one or multiple units of 512 bytes. 

## **• SECTOR_SIZE** 

This field is fixed to 7Fh, which indicates 64 KBytes. This value is not related to erase operation. SDHC and SDXC Cards indicate memory boundary by AU size and this field should not be used. 

## **• WP_GRP_SIZE** 

This field is fixed to 00h. SDHC and SDXC Cards do not support write protected groups. 

## **• WP_GRP_ENABLE** 

This field is fixed to 0. SDHC and SDXC Cards do not support write protected groups. 

## **• R2W_FACTOR** 

This field is fixed to 2h, which indicates 4 multiples. Write timeout can be calculated by multiplying the read access time and R2W_FACTOR. However, the host should not use this factor and should use 250 ms for write timeout 

## **• WRITE_BL_LEN** 

This field is fixed to 9h, which indicates WRITE_BL_LEN=512 Byte 

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## **• WRITE_BL_PARTIAL** 

This field is fixed to 0, which indicates partial block read is inhibited and only unit of block access is allowed. 

## **• FILE_FORMAT_GRP** 

This field is set to 0. Host should not use this field. 

## **• COPY** 

Defines whether the contents is original (=0) or has been copied (=1). Setting this bit to 1 indicates that the card content is a copy. The COPY bit is a one time programmable bit except ROM card. 

## **• PERM_WRITE_PROTECT** 

Permanently protects the whole card content against overwriting or erasing (all write and erase commands for this card are permanently disabled). The default value is ‘0’, i.e. not permanently write protected. 

## **• TMP_WRITE_PROTECT** 

Temporarily protects the whole card content from being overwritten or erased (all write and erase commands for this card are temporarily disabled). This bit can be set and reset. The default value is ‘0’, i.e. not write protected. 

## **• FILE_FORMAT** 

This field is set to 0. Host should not use this field. 

## **• CRC** 

The CRC field carries the check sum for the CSD contents. 

The checksum has to be recalculated by the host for any CSD modification. The default corresponds to the initial CSD contents. 

The following table lists the correspondence between the CSD entries and the command classes. A ‘+’ entry indicates that the CSD field affects the commands of the related command class. 

## **4. RCA Register** 

The writable 16-bit relative card address register carries the card address that is published by the card during the card identification. This address is used for the addressed host-card communication after the card identification procedure. The default value of the RCA register is 0x0000. The value0x0000 is reserved to set all cards into the _Stand-by State_ with CMD7. 

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## **5. DSR Register (Optional)** 

The 16-bit driver stage register can be optionally used to improve the bus performance for extended operating conditions (depending on parameters like bus length, transfer rate or number of cards). The CSD register carries the information about the DSR register usage. The default value of the DSR register is 0x404. 

## **6. SCR Register** 

In addition to the CSD register there is another configuration register that named - SD CARD Configuration Register (SCR). SCR provides information on SD Memory Card's special features that were configured into the given card. The size of SCR register is 64 bit. This register shall be set in the factory by the SD Memory Card manufacturer. The following table describes the SCR register content. 

|**Description**|**Field**|**Width**|**Cell**<br>**Type**|**SCR**<br>**Slic**|
|---|---|---|---|---|
|SCR Structure<br>~~ee~~|SCR_STRUCTURE<br>~~ee~~<br>~~ee~~|4<br>~~ee~~<br>~~ee~~|R<br>~~ee~~<br>~~ee~~|[63:60]<br>~~ee~~<br>~~ee~~|
|SD MemoryCard - Spec. Version<br>~~es~~|SD_SPEC<br>~~ee~~<br>~~es~~|4<br>~~ee~~<br>~~es~~|R<br>~~ee~~<br>~~es~~|[59:56]<br>~~ee~~<br>~~es~~|
|data_status_after erases<br>~~ee~~<br>~~ee~~|DATA_STAT_AFTER_ERASE<br>~~ee~~<br>~~ee~~|1<br>~~ee~~<br>~~ee~~|R<br>~~ee~~<br>~~ee~~|[55:55]<br>~~ee~~|
|CPRM SecuritySupport<br>~~ee~~<br>~~ee~~|SD_SECURITY<br>~~ee~~<br>~~ee~~<br>|3<br>~~ee~~<br>~~ee~~<br>|R<br>~~ee~~|[54:52]|
|DAT Bus widths supported<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~a~~|SD_BUS_WIDTHS<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|4<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|R<br>~~ee~~<br>~~ee~~<br>|[51:48]<br>~~ee~~<br>|
|Spec. Version 3.00 or higher<br>~~ee~~<br>~~a~~|SD_SPEC3<br>~~ee~~<br>~~ee~~<br>|1<br>~~ee~~<br>~~ee~~<br>|R<br>|[47]<br>|
|Extended SecuritySupport<br>~~ee ~~<br>~~a ~~<br>~~ee~~<br>~~ee~~|EX_ SECURITY<br>~~ee ~~<br> ~~ee ~~<br> ~~ee~~<br>~~**ee**~~|4<br> ~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~**ee**~~|R<br>~~ee~~|[46:43]<br>~~ee~~|
|Reserved<br> <br>~~ee~~<br>~~ee~~|~~ee~~<br>~~**ee**~~|9<br>~~ee~~<br>~~**ee**~~|R<br>~~ee~~|[42:34]<br>~~ee~~|
|Command Support bits<br> <br>~~ee ~~<br>~~ee~~|CMD_SUPPORT<br> ~~ee~~<br> ~~**ee**~~<br>~~ee~~|14<br>~~ee~~<br>~~**ee**~~<br>~~ee~~|R<br>~~ee~~|[33:32]<br>~~ee~~|
|reserved for manufacturer usage<br> <br>~~ee~~<br>~~ee~~|-<br> ~~**ee** ~~<br>~~ee~~<br>~~ee~~|32<br> ~~**ee**~~<br>~~ee~~<br>~~ee~~|R<br>~~ee~~|[31:0]<br>~~ee~~|



**The SCR Fields** 

## **• SCR_STRUCTURE** 

Version number of the related SCR structure in the SD Memory Card Physical Layer Specification. 

|**SCR STRUCTURE**|**SCR structure version**|**SD Physical Layer Specification Version**|
|---|---|---|
|0|SCR version 1.0|**SD Physical Layer Specification Version**<br>Version 1.01-3.00|
|1-15|reserved||



**SCR Register Structure Version** 

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## **• SD_SPEC** 

Describes the SD Memory Card Physical Layer Specification version supported by this card. 

|**SD_SPEC**|**Physical Layer Specification Version Number**|
|---|---|
|0|Version 1.0-1.01|
|1|Version 1.10|
|2|Version 2.00 or Version 3.00<br>(Referto SD_SPEC3)|
|3-15|reserved|



**Physical Layer Specification Version** 

## **• SD_SPEC3** 

|**SD_SPEC**|**SD_SPEC3**|**Physical Layer Specification Version Number**|
|---|---|---|
|2|0|Version 2.00|
|2|1|Version3.00|



The card manufacturer determines SD_SPEC value by conditions indicated below. All conditions shall be satisfied for each version. The other combination of conditions is not allowed. 

## **• DATA_STAT_AFTER_ERASE** 

Defines the data status after erase, whether it is ‘0’ or ‘1’ (the status is card vendor dependent). 

## **• SD_SECURITY** 

This field indicates CPRM Security Specification Version for each capacity card. The definition of Protected Area is different in each capacity card. 

|**SD_SECURITY**|**CPRM Security Version**|
|---|---|
|0|No Security|
|1|Not Used|
|2|SDSC Card(SecurityVersion 1.01)|
|3|SDHC Card(SecurityVersion 2.00)|
|4|SDXC Card (SecurityVersion 3.xx)|
|5 - 7|Reserved|



**CPRM Security Version** 

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The basic rule of setting this field: 

SDSC Card sets this field to 2 (Version 1.01) SDHC Card sets this field to 3 (Version 2.00). SDXC Card sets this field to 4 (Version 3.xx). 

Note that it is mandatory for a regular writable SD Memory Card to support Security Protocol. 

## **• SD_BUS_WIDTHS** 

Describes all the DAT bus widths that are supported by this card. 

|**SD_BUS_WIDTHS**|**Supported Bus Widths**|
|---|---|
|Bit 0|1 bit(DAT0)|
|Bit 1|reserved|
|Bit 2|4 bit(DAT0-3)|
|Bit 3|reserved|



## **SD Memory Card Supported Bus Widths** 

Since SD Memory Card shall support at least the two bus modes 1bit or 4bit width then any SD Card shall set at least bits 0 and 2 (SD_BUS_WIDTH="0101"). 

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## Mechanical Dimension 

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