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TS555IDTTR
Single CMOS Timer, 2.7 MHz, 2 V to 16 V Supply, SOIC-8
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- Manufacturer: STMICROELECTRONICS
- Product type: Timers, Oscillators & Pulse Generators
| Delivery and price | |
|---|---|
| Units per pack | 100 |
| Price | 1.15 € |
| Current stock | 1000+ |
| Lead time | 7 days |
Datasheet
**TS555** ## Low-power single CMOS timer **Datasheet** - **production data** ## **Description** The TS555 is a single CMOS timer with very low consumption: **SO8** (plastic micropackage) (Icc(TYP) TS555 = 110 µA at VCC = +5 V versus Icc(TYP) NE555[(a)] = 3 mA), and high frequency: ## **Pin connections** (top view) (ff(max.) TS555 = 2.7 MHz versus f(max) NE555[(a)] = 0.1 MHz). Timing remains accurate in both monostable and astable mode. The TS555 provides reduced supply current spikes during output transitions, which enable the use of lower decoupling capacitors compared to those required by bipolar NE555[(a)] . With the high input impedance (10[12] Ω ), timing capacitors can also be minimized. ## **Features** - Very low power consumption: - 110 µA typ at VCC = 5 V - 90 µa typ at VCC = 3 V - High maximum astable frequency of 2.7 MHz - Pin-to-pin functionally-compatible with bipolar NE555[(a)] - Wide voltage range: +2 V to +16 V - Supply current spikes reduced during output transitions - High input impedance: 10[12] Ω - Output compatible with TTL, CMOS and logic MOS a. Terminated product 1/19 June 2015 DocID4077 Rev 4 This is information on a product in full production. _www.st.com_ **Contents** **TS555** ## **Contents** |**1**|**Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 3**| |---|---| |**2**|**Schematic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4**| |**3**|**Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6**| |**4**|**Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13**| ||4.1<br>Monostable operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13| ||4.2<br>Astable operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14| |**5**|**Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15**| ||5.1<br>SO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16| |**6**|**Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17**| |**7**|**Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18**| 2/19 DocID4077 Rev 4 **TS555** **Absolute maximum ratings and operating conditions** ## **1 Absolute maximum ratings and operating conditions** **Table 1. Absolute maximum ratings** |**Symbol**|**Parameter**|**Value**|**Unit**| |---|---|---|---| |VCC|Supply voltage|+18|V| |IOUT|Output current|± 100|mA| |Rthja|Thermal resistance junction to ambient(1)|125|°C/W| |Rthjc|Thermal resistance junction to case(1)|40|| |Tj|Junction temperature|+150|°C| |Tstg|Storage temperature range|-65 to +150|| |ESD|Human body model (HBM)(2)|1500|V| ||Machine model (MM)(3)|200|| ||Charged device model (CDM)(4)|1000|| 1. Short-circuits can cause excessive heating. These values are typical and specified for a four layers PCB. 2. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5k Ω resistor between two pins of the device. This is done for all couples of connected pin combinations while the other pins are floating. 3. Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 Ω ). This is done for all couples of connected pin combinations while the other pins remain floating. 4. Charged device model: all pins plus package are charged together to the specified voltage and then discharged directly to the ground. **Table 2. Operating conditions** |**Symbol**|**Parameter**|**Value**|**Unit**| |---|---|---|---| |VCC|Supply voltage|2 to 16|V| |IOUT|Output sink current<br>Output source current|10<br>50|mA| |Toper|Operating free air temperature range|-40 to +125|°C| 3/19 DocID4077 Rev 4 **Schematic diagrams** **TS555** ## **2 Schematic diagrams** ## **Figure 1. Schematic diagram** 4/19 DocID4077 Rev 4 **TS555** **Schematic diagrams** ## **Figure 2. Block diagram** **Table 3. Functional table** |**Reset**|**Trigger**|**Threshold**|**Output**| |---|---|---|---| |Low|x|x|Low| |High|Low||High| ||High|High|Low| |||Low|Previous state| _Note: Low: level voltage_ ≤ _minimum voltage specified High: level voltage_ ≥ _maximum voltage specified x: irrelevant_ 5/19 DocID4077 Rev 4 **TS555** **Electrical characteristics** ## **3 Electrical characteristics** **Table 4. Static electrical characteristics** **VCC = +2 V, Tamb = +25 °C, reset to VCC (unless otherwise specified)** |**Symbol**|**Parameter**|**Min.**|**Typ.**|**Max.**|**Unit**| |---|---|---|---|---|---| |ICC|Supply current (no load, high and low states)<br>Tmin ≤Tamb ≤Tmax||65|200<br>200|µA| |VCL|Control voltage level<br>Tmin ≤Tamb ≤Tmax|1.2<br>1.1|1.3|1.4<br>1.5|V| |VDIS|Discharge saturation voltage (Idis= 1 mA)<br>Tmin ≤Tamb ≤Tmax||0.05|0.2<br>0.25|| |IDIS|Discharge pin leakage current||1|100|nA| |VOL|Low level output voltage (Isink= 1 mA)<br>Tmin ≤Tamb ≤Tmax||0.1|0.3<br>0.35|V| |VOH|High level output voltage (Isource= -0.3 mA)<br>Tmin ≤Tamb ≤Tmax|1.5<br>1.5|1.9||| |VTRIG|Trigger voltage<br>Tmin ≤Tamb ≤Tmax|0.4<br>0.3|0.67|0.95<br>1.05|| |ITRIG|Trigger current||10||pA| |ITH|Threshold current||10||| |VRESET|Reset voltage<br>Tmin ≤Tamb ≤Tmax|0.4<br>0.3|1.1|1.5<br>2.0|V| |IRESET|Reset current||10||pA| 6/19 DocID4077 Rev 4 **TS555** **Electrical characteristics** **Table 5. Static electrical characteristics VCC = +3 V, Tamb = +25 °C, reset to VCC (unless otherwise specified)** |**Symbol**|**Parameter**|**Min.**|**Typ.**|**Max.**|**Unit**| |---|---|---|---|---|---| |ICC|Supply current (no load, high and low states)<br>Tmin ≤Tamb ≤Tmax||90|230<br>230|µA| |VCL|Control voltage level<br>Tmin ≤Tamb ≤Tmax|1.8<br>1.7|2|2.2<br>2.3|V| |VDIS|Discharge saturation voltage (Idis= 1 mA)<br>Tmin ≤Tamb ≤Tmax||0.05|0.2<br>0.25|| |IDIS|Discharge pin leakage current||1|100|nA| |VOL|Low level output voltage (Isink= 1 mA)<br>Tmin ≤Tamb ≤Tmax||0.1|0.3<br>0.35|V| |VOH|High level output voltage (Isource= -0.3 mA)<br>Tmin ≤Tamb ≤Tmax|2.5<br>2.5|2.9||| |VTRIG|Trigger voltage<br>Tmin ≤Tamb ≤Tmax|0.9<br>0.8|1|1.1<br>1.2|| |ITRIG|Trigger current||10||pA| |ITH|Threshold current||10||| |VRESET|Reset voltage<br>Tmin ≤Tamb ≤Tmax|0.4<br>0.3|1.1|1.5<br>2.0|V| |IRESET|Reset current||10||pA| 7/19 DocID4077 Rev 4 **TS555** **Electrical characteristics** **Table 6. Dynamic electrical characteristics VCC = +3 V, Tamb = +25 °C, reset to VCC (unless otherwise specified)** |**Symbol**|**Parameter**|**Min.**|**Typ.**|**Max.**|**Unit**| |---|---|---|---|---|---| ||Timing accuracy (monostable)(1)<br>R = 10 kΩ, C = 0.1 µF<br>VCC= 2 V<br>VCC= 3 V|—|1<br>1|—|%| ||Timing shift with supply voltage variations<br>(monostable)<br>R = 10 kΩ, C = 0.1 µF, VCC= 3 V ± 0.3 V(1)||0.5||%/V| ||Timing shift with temperature(1)<br>Tmin≤Tamb ≤Tmax||75||ppm/°C| |fmax|Maximum astable frequency(2)<br>RA= 470Ω, RB= 200Ω, C = 200 pF||2||MHz| ||Astable frequency accuracy(2)<br>RA= RB= 1 kΩto 100 kΩ, C = 0.1 µF||5||%| ||Timing shift with supply voltage variations<br>(astable mode)(2)<br>RA= RB= 1 kΩto 100 kΩ, C = 0.1 µF,<br>VCC= 3 to 5 V||0.5||%/V| |tR|Output rise time (Cload= 10 pF)||25||ns| |tF|Output fall time (Cload= 10 pF)||20||| |tPD|Trigger propagation delay||100||| |tRPW|Minimum reset pulse width (Vtrig= 3 V)||350||| 1. See _Figure 4_ 2. See _Figure 6_ 8/19 DocID4077 Rev 4 **TS555** **Electrical characteristics** **Table 7. Static electrical characteristics VCC = +5 V, Tamb = +25 °C, reset to VCC (unless otherwise specified)** |**Symbol**|**Parameter**|**Min.**|**Typ.**|**Max.**|**Unit**| |---|---|---|---|---|---| |ICC|Supply current (no load, high and low states)<br>Tmin ≤Tamb≤Tmax||110|250<br>250|µA| |VCL|Control voltage level<br>Tmin≤Tamb ≤Tmax|2.9<br>2.8|3.3|3.8<br>3.9|V| |VDIS|Discharge saturation voltage (Idis= 10 mA)<br>Tmin ≤Tamb≤Tmax||0.2|0.3<br>0.35|| |IDIS|Discharge pin leakage current||1|100|nA| |VOL|Low level output voltage (Isink= 8 mA)<br>Tmin ≤Tamb ≤Tmax||0.3|0.6<br>0.8|V| |VOH|High level output voltage (Isource= -2 mA)<br>Tmin ≤Tamb ≤Tmax|4.4<br>4.4|4.6||| |VTRIG|Trigger voltage<br>Tmin≤Tamb ≤Tmax|1.36<br>1.26|1.67|1.96<br>2.06|| |ITRIG|Trigger current||10||pA| |ITH|Threshold current||10||| |VRESET|Reset voltage<br>Tmin ≤Tamb ≤Tmax|0.4<br>0.3|1.1|1.5<br>2.0|V| |IRESET|Reset current||10||pA| 9/19 DocID4077 Rev 4 **TS555** **Electrical characteristics** m **Table 8. Dynamic electrical characteristics VCC = +5 V, Tamb = +25 °C, reset to VCC (unless otherwise specified)** |**Symbol**|**Parameter**|**Min.**|**Typ.**|**Max.**|**Unit**| |---|---|---|---|---|---| ||Timing accuracy (monostable)(1)<br>R = 10 kΩ, C = 0.1 µF|—|2|—|%| ||Timing shift with supply voltage variations<br>(monostable)(1)<br>R = 10 kΩ, C = 0.1 µF,VCC= 5 V ± 1 V||0.38||%/V| ||Timing shift with temperature(1)<br>Tmin≤Tamb ≤Tmax5||75||ppm/°C| |fmax|Maximum astable frequency(2)<br>RA= 470Ω, RB= 200Ω, C = 200 pF||2.7||MHz| ||Astable frequency accuracy(2)<br>RA= RB= 1 kΩto 100 kΩ, C = 0.1 µF||3||%| ||Timing shift with supply voltage variations<br>(astable mode)(2)<br>RA= RB= 10 kΩ, C = 0.1 µF, VCC= 5 to 12 V||0.1||%/V| |tR|Output rise time (Cload= 10 pF)||25||ns| |tF|Output fall time (Cload= 10 pF)||20||| |tPD|Trigger propagation delay||100||| |tRPW|Minimum reset pulse width (Vtrig= 5 V)||350||| 1. See _Figure 4_ 2. See _Figure 6_ 10/19 DocID4077 Rev 4 **TS555** **Electrical characteristics** **Table 9. Static electrical characteristics VCC = +12 V, Tamb = +25 °C, reset to VCC (unless otherwise specified)** |**Symbol**|**Parameter**|**Min.**|**Typ.**|**Max.**|**Unit**| |---|---|---|---|---|---| |ICC|Supply current (no load, high and low states)<br>Tmin≤Tamb ≤Tmax||170|400<br>400|µA| |VCL|Control voltage level<br>Tmin≤Tamb ≤Tmax|7.4<br>7.3|8|8.6<br>8.7|V| |VDIS|Discharge saturation voltage (Idis= 80 mA)<br>Tmin≤Tamb ≤Tmax||0.09|1.5<br>2.0|| |IDIS|Discharge pin leakage current||1|100|nA| |VOL|Low level output voltage (Isink= 50 mA)<br>Tmin≤Tamb ≤Tmax||1.2|2<br>2.8|V| |VOH|High level output voltage (Isource= -10 mA)<br>Tmin≤Tamb ≤Tmax|10.5<br>10.5|11||| |VTRIG|Trigger voltage<br>Tmin≤Tamb ≤Tmax|3.2<br>3.1|4|4.8<br>4.9|| |ITRIG|Trigger current||10||pA| |ITH|Threshold current||10||| |VRESET|Reset Voltage<br>Tmin≤Tamb ≤Tmax|0.4<br>0.3|1.1|1.5<br>2.0|V| |IRESET|Reset current||10||pA| 11/19 DocID4077 Rev 4 **TS555** **Electrical characteristics** **Table 10. Dynamic electrical characteristics VCC = +12 V, Tamb = +25 °C, reset to VCC (unless otherwise specified)** |**Symbol**|**Parameter**|**Min.**|**Typ.**|**Max.**|**Unit**| |---|---|---|---|---|---| ||Timing accuracy (monostable)(1)<br>R = 10 kΩ, C = 0.1 µF, VCC= +12 V|—|4|—|%| ||Timing shift with supply voltage variations<br>(monostable)(1)<br>R = 10 kΩ, C = 0.1 µF, VCC= +5 V ±1 V||0.38||%/V| ||Timing shift with temperature<br>Tmin≤Tamb≤Tmax., VCC= +5 V||75||ppm/°C| |fmax|Maximum astable frequency(2)<br>RA= 470Ω, RB= 200Ω, C = 200 pF, VCC= +5 V||2.7||MHz| ||Astable frequency accuracy<br>RA= RB= 1 kΩto 100 kΩ, C = 0.1 µF,<br>VCC= +12 V||3||%| ||Timing shift with supply voltage variations<br>(astable mode)<br>RA= RB= 1 kΩto 100 kΩ, C = 0.1 µF,<br>VCC= 5 to +12 V||0.1||%/V| 1. See _Figure 4_ 2. See _Figure 6_ ## **Figure 3. Supply current (per timer) versus supply voltage** 12/19 DocID4077 Rev 4 **TS555** **Application information** ## **4 Application information** ## **4.1 Monostable operation** In monostable mode, the timer operates like a one-shot generator. The external capacitor is initially held discharged by a transistor inside the timer, as shown in _Figure 4_ . **Figure 4. Application schematic** **==> picture [405 x 132] intentionally omitted <==** **----- Start of picture text -----**<br> ���<br>�����<br>�<br>� �<br>������� � �<br>����� � �<br>��� � �<br>���������������<br>� ���������<br>**----- End of picture text -----**<br> The circuit triggers on a negative-going input signal when the level reaches 1/3 VCC. Once triggered, the circuit remains in this state until the set time has elapsed, even if it is triggered again during this interval. The duration of the output HIGH state is given by _t = 1.1 R x C_ . Since the charge rate and threshold level of the comparator are both directly proportional to the supply voltage, the timing interval is independent of the supply. Applying a negative pulse simultaneously to the reset terminal (pin 4) and the trigger terminal (pin 2) during the timing cycle discharges the external capacitor and causes the cycle to start over. The timing cycle then starts on the positive edge of the reset pulse. While the reset pulse is applied, the output is driven to the LOW state. When a negative trigger pulse is applied to pin 2, the flip-flop is set, releasing the short circuit across the external capacitor and driving the output HIGH. The voltage across the capacitor increases exponentially with the time constant τ _= R x C_ . When the voltage across the capacitor equals 2/3 VCC, the comparator resets the flip-flop which then discharges the capacitor rapidly and drives the output to its LOW state. _Figure 5_ shows the actual waveforms generated in this mode of operation. When reset is not used, it should be tied high to avoid any false triggering. **Figure 5. Timing diagram** **==> picture [405 x 133] intentionally omitted <==** **----- Start of picture text -----**<br> ����������������<br>������������� � �<br>����� � ���������� � ������<br>����������������������������<br>������������������������������������<br>**----- End of picture text -----**<br> 13/19 DocID4077 Rev 4 **Application information** **TS555** ## **4.2 Astable operation** When the circuit is connected as shown in _Figure 6_ (pins 2 and 6 connected) it triggers itself and runs as a multi-vibrator. The external capacitor charges through RA and RB and discharges through RB only. Therefore, the duty cycle may be precisely set by the ratio of these two resistors. In the astable mode of operation, C charges and discharges between 1/3 VCC and 2/3 VCC. As in the triggered mode, the charge and discharge times, and therefore frequency, are independent of the supply voltage. **Figure 6. Application schematic** _Figure 7_ shows actual waveforms generated in this mode of operation. The charge time (output HIGH) is given by: _t1 = 0.693 (RA + RB) C_ The discharge time (output LOW) by: _t2 = 0.693 x RB x C_ Thus the total period T is given by: **==> picture [144 x 11] intentionally omitted <==** The frequency of oscillation is then: **==> picture [79 x 18] intentionally omitted <==** The duty cycle is given by: **==> picture [54 x 16] intentionally omitted <==** ## **Figure 7. Timing diagram** 14/19 DocID4077 Rev 4 **TS555** **Package information** ## **5 Package information** In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _www.st.com_ . ECOPACK[®] is an ST trademark. 15/19 DocID4077 Rev 4 **Package information** **TS555** ## **5.1 SO8 package information** ## **Figure 8. SO8 package outline** **==> picture [264 x 234] intentionally omitted <==** **Table 11. SO8 mechanical data** ||**Table 11. SO8 mechanical data**|**Table 11. SO8 mechanical data**|**Table 11. SO8 mechanical data**|**Table 11. SO8 mechanical data**|**Table 11. SO8 mechanical data**|**Table 11. SO8 mechanical data**| |---|---|---|---|---|---|---| |**Ref.**|**Dimensions**|||||| ||**Millimeters**|||**Inches**||| ||**Min.**|**Typ.**|**Max.**|**Min.**|**Typ.**|**Max.**| |A|||1.75|||0.069| |A1|0.10||0.25|0.004||0.010| |A2|1.25|||0.049||| |b|0.28||0.48|0.011||0.019| |c|0.17||0.23|0.007||0.010| |D|4.80|4.90|5.00|0.189|0.193|0.197| |E|5.80|6.00|6.20|0.228|0.236|0.244| |E1|3.80|3.90|4.00|0.150|0.154|0.157| |e||1.27|||0.050|| |h|0.25||0.50|0.010||0.020| |L|0.40||1.27|0.016||0.050| |L1||1.04|||0.040|| |k|1°||8°|1°||8°| |ccc|||0.10|||0.004| 16/19 DocID4077 Rev 4 **TS555** **Ordering information** ## **6 Ordering information** ## **Table 12. Order code table** |**Order code**|**Temperature range**|**Package**|**Packaging**|**Marking**| |---|---|---|---|---| |TS555IDTTR|-40 °C to 125 °C|SO8|Tape and reel|555I| 17/19 DocID4077 Rev 4 **TS555** **Revision history** ## **7 Revision history** **Table 13. Document revision history** |**Date**|**Revision**|**Changes**| |---|---|---| |01-Feb-2003|1|Initial release.| |03-Nov-2008|2|Document reformatted.<br>Added output current, ESD and thermal resistance values in<br>_Table 1: Absolute maximum ratings_.<br>Added output current values in_Table 2: Operating conditions_.| |29-Aug-2014|3|_Section 5: Package information_: updated corporate text<br>Replaced_Table 15: Ordering information scheme_| |24-Jun-2015|4|_Features_and_Description_: added footnote to NE555 product to<br>explain it is terminated.<br>Removed all references to DIP8 and TSSOP8 packages<br>Removed all temperature ranges except -40 to 125 °C<br>Replaced_Table 15: Ordering information scheme_with_Table 12:_<br>_Order code table_.| 18/19 DocID4077 Rev 4 **TS555** ## **IMPORTANT NOTICE – PLEASE READ CAREFULLY** STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 19/19 DocID4077 Rev 4
Updated at February 9, 2023
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