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SX1502I087TRT
8 CHANNEL LOW VOLTAGE GPIO 23AH8949
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- Manufacturer: SEMTECH
- Product type: I/O Expanders
- No. of Pins: 20Pins
- No. of I/O's: 8I/O's
- Bus Frequency: 400kHz
- IC Interface Type: I2C
- Chip Configuration: 8bit
- Supply Voltage Max: 5.5V
- Supply Voltage Min: 1.2V
- Interface Case Style: TQFN
| Delivery and price | |
|---|---|
| Units per pack | 6000 |
| Price | 0.539 € |
| Current stock | 10+ |
| Lead time | 7 days |
Datasheet
**SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## **WIRELESS & SENSING** ## **SX1501/SX1502/SX1503** ## **4/8/16 Channel Low Voltage GPIO with NINT and NRESET** ## **GENERAL DESCRIPTION** The SX1501, SX1502 and SX1503 are complete ultra low voltage General Purpose parallel Input/Output (GPIO) expanders ideal for low power handheld battery powered equipment. They allow easy serial expansion of I/O through a standard I[2] C interface. GPIO devices can provide additional control and monitoring when the microcontroller or chipset has insufficient I/O ports, or in systems where serial communication and control from a remote location is advantageous. These devices can also act as a level shifter to connect a microcontroller running at one voltage level to a component running at a different voltage level. The core is operating as low as 1.2V while the I/O banks can operate between 1.2V and 5.5V independent of the core voltage and each other. Each GPIO is programmable via 8-bit configuration registers. Data registers, direction registers, pullup/pull-down registers, interrupt mask registers and interrupt registers allow the system master to program and configure 4 or 8 or 16-GPIOs using a standard 400kHz I[2] C interface. The SX1501, SX1502 and SX1503 offer a unique fully programmable logic functions like a PLD to give more flexibility and reduce external logic gates used for standard applications. The SX1501, SX1502 and SX1503 have the ability to generate mask-programmable interrupts based on falling/rising edge of any of its GPIO lines. A dedicated pin indicates to a host controller that a state change occurred in one or more of the GPIO lines. ## **KEY PRODUCT FEATURES** - 4/8/16 channel of I/Os - True bi-directional style I/O - Programmable Pull-up/Pull-down Push/Pull outputs - 1.2V to 5.5V independent operating voltage for all supply rails (VDDM, VCC1, VCC2) - 5.5V compatible I/Os, up to 24mA output sink (no total sink current limit) - Fully programmable logic functions (PLD) - 400kHz 2-wire I[2] C compatible slave interface - Open drain active low interrupt output (NINT) - Bit maskable - Programmable edge sensitivity - Power-On Reset and reset input (NRESET) - Ultra low current consumption of typ. 1uA - -40°C to +85°C operating temperature range - Ultra-Thin 3x3mm QFN-UT-20 package (SX1501/SX1502) - Ultra-Thin 4x4mm QFN-UT-28 package (SX1503) ## **TYPICAL APPLICATIONS** - Cell phones, PDAs, MP3 players - Digital camera - Portable multimedia player - Notebooks - GPS Units - Industrial, ATE - Any battery powered equipment The SX1501, SX1502 and SX1503 each come in a small QFN-UT-20/28 package. All devices are rated from -40°C to +85°C temperature range. |**Part Number **|**I/O Channels**|**Package**| |---|---|---| |SX1501I087TRT|4|QFN-UT-20| |SX1502I087TRT|8|QFN-UT-20| |SX1503I091TRT<br>~~(1)~~|16|QFN-UT-28| |SX1502EVK~~(1)~~<br>~~(1)~~|8<br>|Evaluation Kit<br>| ~~(1)~~ SX1502I087TRT based, unique evaluation kit for the three parts. Rev 11 – 16[th] May 2012 www.semtech.com 1 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** **WIRELESS & SENSING** LC ## **Table of Contents** |**Table of Contents**|**Table of Contents**|**Table of Contents**| |---|---|---| |**GENERALDESCRIPTION..................................................................................................................... 1**||| |**ORDERINGINFORMATION................................................................................................................... 1**||| |**KEYPRODUCTFEATURES.................................................................................................................. 1**||| |**TYPICALAPPLICATIONS ..................................................................................................................... 1**||| |**1**|**PIN DESCRIPTION ...................................................................................................................... 4**|| |**1.1**|**SX1501 4-channel GPIO**|**4**| |**1.2**|**SX1502 8-channel GPIO**|**5**| |**1.3**|**SX1503 16-channel GPIO**|**6**| |**2**|**ELECTRICALCHARACTERISTICS............................................................................................... 7**|| |**2.1**|**Absolute Maximum Ratings**|**7**| |**2.2**|**Electrical Specifications**|**7**| ||2.2.1<br>Increasing I/O Sink and Source Current Capabilities (Boost Mode)|9| |**3**|**TYPICALOPERATINGCHARACTERISTICS ............................................................................... 10**|| |**3.1**|**IDDM vs. VDDM**|**10**| |**3.2**|**VOL vs. IOL**|**10**| |**3.3**|**VOH vs. IOH**|**11**| |**3.4**|**ICC1+ICC2 vs. VCC1,2 when Boost Mode is ON**|**12**| |**4**|**BLOCKDETAILEDDESCRIPTION............................................................................................. 13**|| |**4.1**|**SX1501 4-channel GPIO**|**13**| |**4.2**|**SX1502 8-channel GPIO**|**13**| |**4.3**|**SX1503 16-channel GPIO**|**14**| |**4.4**|**Reset (NRESET)**|**14**| |**4.5**|**2-Wire Interface (I2C)**|**15**| ||4.5.1<br>WRITE|15| ||4.5.2<br>READ|16| ||4.5.3<br>READ - STOP separated format (SX1501 and SX1502 only)|16| |**4.6**|**Interrupt (NINT)**|**17**| |**4.7**|**Programmable Logic Functions (PLD)**|**17**| ||4.7.1<br>SX1501|17| ||4.7.2<br>SX1502|18| ||4.7.3<br>SX1503|18| ||4.7.4<br>Tutorial|19| |**5**|**CONFIGURATIONREGISTERS.................................................................................................. 20**|| |**5.1**|**SX1501 4-channel GPIO**|**20**| |**5.2**|**SX1502 8-channel GPIO**|**21**| |**5.3**|**SX1503 16-channel GPIO**|**23**| |**6**|**APPLICATIONINFORMATION ................................................................................................... 27**|| |**6.1**|**Typical Application Circuit**|**27**| |**6.2**|**Typical LED Operation**|**27**| ||6.2.1<br>LED ON/OFF Control|27| ||6.2.2<br>LED Intensity Control|28| |**6.3**|**Keypad Implementation**|**28**| |**6.4**|**Level Shifter Implementation Hints**|**28**| |Rev 11 – 16thMay 2012||www.semtech.com| **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** |**WIRELESS & SENSING**<br>**7**<br>**PACKAGINGINFORMATION ..................................................................................................... 29**<br>LC|**WIRELESS & SENSING**<br>**7**<br>**PACKAGINGINFORMATION ..................................................................................................... 29**<br>LC|**..................................................................................................... 29**| |---|---|---| |**7.1**|**QFN-UT 20-pin Outline Drawing**|**29**| |**7.2**|**QFN-UT 20-pin Land Pattern**|**29**| |**7.3**|**QFN-UT 28-pin Outline Drawing**|**30**| |**7.4**|**QFN-UT 28-pin Land Pattern**|**30**| |**8**|**SOLDERINGPROFILE .............................................................................................................. 31**|**.............................................................................................................. 31**| Rev 11 – 16[th] May 2012 www.semtech.com 3 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## **WIRELESS & SENSING** ## **1 PIN DESCRIPTION** ## **1.1 SX1501 4-channel GPIO** |**Pin**|**Symbol**|**Type**|**Description**| |---|---|---|---| |1<br>~~a~~|NRESET<br>~~Qe~~|DIO<br>~~Qe~~|Active low reset<br>~~Qe~~| |2<br>~~a~~|SDA<br>~~es~~|DIO<br>~~es~~|I2C serial data line| |3<br>~~a~~<br>~~es~~|NC1<br>~~es~~<br>~~es~~|-<br>~~es~~<br>~~GO~~|Leave open, not connected<br>~~GO~~| |4<br>~~a~~<br>~~es~~<br>~~es~~|SCL<br>~~es~~<br>~~es~~<br>~~es~~|DI<br>~~(*1)~~<br>~~es~~<br>~~GO~~<br>~~Qe~~|I2C serial clock line<br>~~GO~~<br>~~Qe~~| |5<br>~~es~~<br>~~es~~<br>~~es~~|I/O[0]<br>~~es~~<br>~~es~~<br>~~es~~|DIO~~(*1)~~<br>~~(*1)~~<br>~~GO~~<br>~~Qe~~<br>~~GO~~|I/O[0],atpower-on configured as an input<br>~~GO~~<br>~~Qe~~<br>~~GO~~| |6<br>~~es~~<br>~~es~~<br>~~es~~|I/O[1]<br>~~es~~<br>~~es~~<br>~~es~~|DIO~~(*1)~~<br>~~Qe~~<br>~~GO~~<br>~~Qe~~|I/O[1],atpower-on configured as an input<br>~~Qe~~<br>~~GO~~<br>~~Qe~~| |7<br>~~es~~<br>~~es~~|VCC1<br>~~es~~<br>~~es~~|P<br>~~GO~~<br>~~Qe~~|I/O supplyvoltage<br>~~GO~~<br>~~Qe~~| |8<br>~~es~~<br>~~ee~~|GND<br>~~es~~<br>~~ee~~|P<br>~~Qe~~<br>~~ee~~|Ground Pin<br>~~Qe~~<br>~~ee~~| |9<br>~~ee~~|I/O[2]<br>~~ee~~|DIO(*1)<br>~~ee~~|I/O[2], at power-on configured as an input<br>High sink I/O.<br>~~ee~~| |10<br>~~ee~~<br>~~es~~|I/O[3]<br>~~ee~~<br>~~es~~|DIO(*1)<br>~~ee~~<br>~~Qe~~|I/O[3], at power-on configured as an input<br>High sink I/O.<br>~~ee~~<br>~~Qe~~| |11<br>~~es~~<br>~~es~~|NINT<br>~~es~~<br>~~es~~|DO<br>~~Qe~~<br>~~GO~~|Active low interrupt output<br>~~Qe~~<br>~~GO~~| |12<br>~~es~~<br>~~es~~<br>~~es~~|ADDR<br>~~es~~<br>~~es~~<br>~~es~~|DI<br>~~Qe~~<br>~~GO~~<br>~~Qe~~|Address input,connect to VDDM or GND<br>~~Qe~~<br>~~GO~~<br>~~Qe~~| |13<br>~~es~~<br>~~es~~<br>~~es~~|NC2<br>~~es~~<br>~~es~~<br>~~es~~|-<br>~~GO~~<br>~~Qe~~<br>~~GO~~|Leave open,not connected<br>~~GO~~<br>~~Qe~~<br>~~GO~~| |14<br>~~es~~<br>~~es~~<br>~~es~~|VDDM<br>~~es~~<br>~~es~~<br>~~es~~|P<br>~~Qe~~<br>~~GO~~<br>~~Qe~~|Main supplyvoltage<br>~~Qe~~<br>~~GO~~<br>~~Qe~~| |15<br>~~es~~<br>~~es~~<br>~~es~~|NC3<br>~~es~~<br>~~es~~<br>~~es~~|-<br>~~GO~~<br>~~Qe~~<br>~~GO~~|Leave open,not connected<br>~~GO~~<br>~~Qe~~<br>~~GO~~| |16<br>~~es~~<br>~~es~~<br>~~es~~|NC4<br>~~es~~<br>~~es~~<br>~~es~~|-<br>~~Qe~~<br>~~GO~~<br>~~Qe~~|Leave open,not connected<br>~~Qe~~<br>~~GO~~<br>~~Qe~~| |17<br>~~es~~<br>~~es~~<br>~~es~~|NC7<br>~~es~~<br>~~es~~<br>~~es~~|-<br>~~GO~~<br>~~Qe~~<br>~~GO~~|Connect to VCC1<br>~~GO~~<br>~~Qe~~<br>~~GO~~| |18<br>~~es~~<br>~~es~~<br>~~es~~|GND<br>~~es~~<br>~~es~~<br>~~es~~|P<br>~~Qe~~<br>~~GO~~<br>~~Qe~~|Ground Pin<br>~~Qe~~<br>~~GO~~<br>~~Qe~~| |19<br>~~es~~<br>~~es~~|NC5<br>~~es~~<br>~~es~~|-<br>~~GO~~<br>~~Qe~~|Leave open,not connected<br>~~GO~~<br>~~Qe~~| |20<br>~~es~~<br>~~Rs~~|NC6<br>~~es~~<br>~~Rs~~|-<br>~~Qe~~<br>~~GO~~|Leave open,not connected<br>~~Qe~~<br>~~GO~~| A: Analog D: Digital I: Input O: Output P: Power (*1) This pin is programmable through the I[2] C interface _Table 1 – SX1501 Pin Description_ **==> picture [203 x 184] intentionally omitted <==** **----- Start of picture text -----**<br> O Pritt ii etd<br>o) 3) Ge) 7) Bel<br>NRESET “ee NC3<br>SDA Ts]J Hi TOP VIEW ii (a4aaalias VDDM<br>NC1 NC2<br>a) | fae<br>SCL GND ADDR<br>eas | (PAD) _—<br>I/O[0] RY enenee eect NINT<br>fel (7) fel fs) ao<br>NC6 NC5 GND NC7 NC4<br>I/O[1] VCC1 GND I/O[2] I/O[3]<br>**----- End of picture text -----**<br> _Figure 1 – SX1501 QFN-UT-20 Pinout_ Rev 11 – 16[th] May 2012 www.semtech.com 4 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## **WIRELESS & SENSING** ## **1.2 SX1502 8-channel GPIO** |**Pin**<br>~~es~~|**Symbol**<br>~~es~~|**Type**|**Description**| |---|---|---|---| |1<br>~~es~~|NRESET<br>~~es~~|DIO|Active low reset| |2<br>~~es~~<br>~~GO~~<br>~~es~~|SDA<br>~~es~~<br>~~GO~~<br>~~es~~|DIO<br>~~GO~~|I2C serial data line<br>~~GO~~| |3<br>~~es~~|NC1<br>~~es~~|-|Leave open,not connected| |4<br>~~es~~<br>~~GO~~<br>~~es~~|SCL<br>~~es~~<br>~~GO~~<br>~~es~~|DI<br>~~(*1)~~<br>~~GO~~|I2C serial clock line<br>~~GO~~| |5<br>~~es~~|I/O[0]<br>~~es~~|DIO~~(*1)~~<br>~~(*1)~~|I/O[0],atpower-on configured as an input| |6<br>~~es~~<br>~~GO~~<br>~~es~~|I/O[1]<br>~~es~~<br>~~GO~~<br>~~es~~|DIO~~(*1)~~<br>~~GO~~|I/O[1],atpower-on configured as an input<br>~~GO~~| |7<br>~~es~~|VCC1<br>~~es~~|P|Supplyvoltage for Bank A I/O[0-3]| |8<br>~~es~~|GND<br>~~es~~|P|Ground Pin| |9<br>~~a ee~~|I/O[2]<br>~~ee~~|DIO(*1)<br>~~ee~~|I/O[2], at power-on configured as an input<br>High sink I/O.<br>~~ee~~| |10<br>~~es~~|I/O[3]<br>~~es~~|DIO(*1)|I/O[3], at power-on configured as an input<br>High sink I/O.| |11<br>~~es~~|NINT<br>~~es~~|DO|Active low interrupt output| |12<br>~~es~~<br>~~GO~~<br>~~es~~|ADDR<br>~~es~~<br>~~GO~~<br>~~es~~|DI<br>~~GO~~|Address input,connect to VDDM or GND<br>~~GO~~| |13<br>~~es~~|NC2<br>~~es~~|-|Leave open,not connected| |14<br>~~es~~<br>~~GO~~<br>~~es~~|VDDM<br>~~es~~<br>~~GO~~<br>~~es~~|P<br>~~(*1)~~<br>~~GO~~|Main supplyvoltage<br>~~GO~~| |15<br>~~es~~|I/O[4]<br>~~es~~|DIO~~(*1)~~<br>~~(*1)~~|I/O[4],atpower-on configured as an input| |16<br>~~es~~<br>~~GO~~<br>~~es~~|I/O[5]<br>~~es~~<br>~~GO~~<br>~~es~~|DIO~~(*1)~~<br>~~GO~~|I/O[5],atpower-on configured as an input<br>~~GO~~| |17<br>~~es~~|VCC2<br>~~es~~|P|Supplyvoltage for Bank B I/O[4-7]| |18<br>~~es~~<br>~~GO~~<br>~~es~~|GND<br>~~es~~<br>~~GO~~<br>~~es~~|P<br>~~(*1)~~<br>~~GO~~|Ground Pin<br>~~GO~~| |19<br>~~es~~|I/O[6]<br>~~es~~|DIO~~(*1)~~<br>~~(*1)~~|I/O[6],atpower-on configured as an input| |20<br>~~es~~<br>~~GO~~|I/O[7]<br>~~es~~<br>~~GO~~|DIO~~(*1)~~<br>~~GO~~|I/O[7],atpower-on configured as an input<br>~~GO~~| A: Analog D: Digital I: Input O: Output P: Power (*1) This pin is programmable through the I[2] C interface _Table 2 – SX1502 Pin Description_ **==> picture [203 x 188] intentionally omitted <==** **----- Start of picture text -----**<br> Ei bd ba bt at<br>CQ) 7?zo ££&9tf £&esYba”bt &GStf<br>NRESET a) eC I/O[4]<br>SDA Ts] H TOP VIEW i (a4 VDDM<br>—— i i ——<br>NC1 NC2<br>eae | Peart<br>SCL #) | GND ; (aa” ADDR<br>aie | (PAD) BP eecn<br>I/O[0] eS reoi NINT<br>fe) (7) (a) (3) G0<br>I/O[7] I/O[6] GND VCC2 I/O[5]<br>I/O[1] VCC1 GND I/O[2] I/O[3]<br>**----- End of picture text -----**<br> _Figure 2 – SX1502 QFN-UT-20 Pinout_ Rev 11 – 16[th] May 2012 www.semtech.com 5 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## **WIRELESS & SENSING** ## **1.3 SX1503 16-channel GPIO** |**Pin**|**Symbol**|**Type**|**Description**| |---|---|---|---| |1<br>~~a~~|GND<br>~~es~~|P<br>~~(*1)~~<br>~~es~~|Ground Pin| |2|I/O[2]|DIO~~(*1)~~<br>~~(*1)~~|I/O[2],atpower-on configured as an input| |3<br>~~a~~|I/O[3]<br>~~es~~|DIO~~(*1)~~<br>~~es~~|I/O[3],atpower-on configured as an input| |4|VCC1|P<br>~~(*1)~~|I/O supplyvoltage for Bank A I/O[0-7]| |5<br>~~a~~|I/O[4]<br>~~es~~|DIO~~(*1)~~<br>~~(*1)~~<br>~~es~~|I/O[4],atpower-on configured as an input| |6|I/O[5]|DIO~~(*1)~~|I/O[5],atpower-on configured as an input| |7<br>~~a~~|GND<br>~~es~~|P<br>~~es~~|Ground Pin| |8<br>~~ee~~|I/O[6]<br>~~ee~~|DIO(*1)<br>~~ee~~|I/O[6], at power-on configured as an input<br>High sink I/O.<br>~~ee~~| |9<br>~~ee~~|I/O[7]<br>~~ee~~|DIO(*1)<br>~~ee~~|I/O[7], at power-on configured as an input<br>High sink I/O.<br>~~ee~~| |10|NINT|DO|Active low interrupt output| |11<br>~~a~~|NC<br>~~es~~|-<br>~~es~~|Leave open,not connected| |12|VDDM|P<br>~~(*1)~~|Main supplyvoltage| |13<br>~~a~~|I/O[8]<br>~~es~~|DIO~~(*1)~~<br>~~(*1)~~<br>~~es~~|I/O[8],atpower-on configured as an input| |14|I/O[9]|DIO~~(*1)~~|I/O[9],atpower-on configured as an input| |15<br>~~a~~|GND<br>~~es~~|P<br>~~(*1)~~<br>~~es~~|Ground Pin| |16|I/O[10]|DIO~~(*1)~~<br>~~(*1)~~|I/O[10],atpower-on configured as an input| |17<br>~~a~~|I/O[11]<br>~~es~~|DIO~~(*1)~~<br>~~es~~|I/O[11],atpower-on configured as an input| |18|VCC2|P<br>~~(*1)~~|I/O supplyvoltage for Bank B I/O[8-15]| |19<br>~~a~~|I/O[12]<br>~~es~~|DIO~~(*1)~~<br>~~(*1)~~<br>~~es~~|I/O[12],atpower-on configured as an input| |20|I/O[13]|DIO~~(*1)~~|I/O[13],atpower-on configured as an input| |21<br>~~a~~|GND<br>~~es~~|P<br>~~es~~|Ground Pin| |22<br>~~ee~~|I/O[14]<br>~~ee~~|DIO(*1)<br>~~ee~~|I/O[14], at power-on configured as an input<br>High sink I/O.<br>~~ee~~| |23<br>~~ee~~|I/O[15]<br>~~ee~~|DIO(*1)<br>~~ee~~|I/O[15], at power-on configured as an input<br>High sink I/O.<br>~~ee~~| |24|NRESET|DIO|Active low reset| |25<br>~~a~~|SDA<br>~~es~~|DIO<br>~~es~~|I2C serial data line| |26|SCL|DI<br>~~(*1)~~|I2C serial clock line| |27<br>~~a~~|I/O[0]<br>~~es~~|DIO~~(*1)~~<br>~~(*1)~~<br>~~es~~|I/O[0],atpower-on configured as an input| |28|I/O[1]|DIO~~(*1)~~|I/O[1],atpower-on configured as an input| A: Analog D: Digital I: Input O: Output P: Power (*1) This pin is programmable through the I[2] C interface _Table 3 – SX1503 Pin Description_ **==> picture [208 x 215] intentionally omitted <==** **----- Start of picture text -----**<br> GND 1 21 GND<br>I/O[2] 2 20 I/O[13]<br>I/O[3] 3 TOP VIEW 19 I/O[12]<br>VCC1 4 GND 18 VCC2<br>(PAD)<br>I/O[4] 5 17 I/O[11]<br>I/O[5] 6 16 I/O[10]<br>GND<br>GND 7 15<br>I/O[1] I/O[0] SCL SDA NRESET I/O[15] I/O[14]<br>28 27 26 25 24 23 22<br>8 9 10 11 12 13 14<br>I/O[6] I/O[7] NINT NC VDDM I/O[8] I/O[9]<br>**----- End of picture text -----**<br> _Figure 3 – SX1503 QFN-UT-28 Pinout_ Rev 11 – 16[th] May 2012 www.semtech.com 6 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## ~~LO~~ **WIRELESS & SENSING** ~~|~~ **2 ELECTRICAL CHARACTERISTICS** **2.1 Absolute Maximum Ratings** Stress above the limits listed in the following table may cause permanent failure. Exposure to absolute ratings for extended time periods may affect device reliability. The limiting values are in accordance with the Absolute Maximum Rating System (IEC 134). All voltages are referenced to ground (GND). |**Symbol **|**Description **|**Min**|**Max **|**Unit**| |---|---|---|---|---| |VDDMmax|Mainsupplyvoltage|-0.4|6.0|V| |VCC1,2max|I/O banks supplyvoltage|-0.4|6.0|V| |VESD_HBM|ElectrostatichandlingHBM model(1)|-|1500|V| |ESD_HBM<br>VESD_CDM|Electrostatichandling CDM model|-|300|V| |ESD_CDM<br>VESD_MM|ElectrostatichandlingMM model|-|200|V| |ESD_MM<br>TA|OperatingAmbientTemperatureRange|-40|+85|°C| |TC|Junction TemperatureRange|-40|+125|°C| |TSTG|StorageTemperatureRange|-55|+150|°C| |Ilat|Latchup-freeinput pincurrent(2)|+/-100|-|mA| (1) Tested according to JESD22-A114A (2) Static latch-up values are valid at maximum temperature according to JEDEC 78 specification _Table 4 - Absolute Maximum Ratings_ ## **2.2 Electrical Specifications** Table below applies to default registers values (Boost Mode Off), unless otherwise specified. Typical values are given for TA = +25°C, VDDM=VCC1=VCC2=3.3V. |**Symbol **|**Description **|**Conditions**|**Min**|**Typ**|**Max **|**Unit**| |---|---|---|---|---|---|---| |**Supply**<br>~~SSS~~||||||| |VDDM<br>~~SSS~~|Main supply voltage<br>~~SSS~~|-<br>~~SSS~~|1.2<br>~~SSS~~|-<br>~~SSS~~|5.5<br>~~SSS~~|V<br>~~SSS~~| |VCC1,2<br>~~a~~|I/O banks supply voltage<br>~~a~~|-<br>~~a~~|1.2<br>~~a~~|-<br>~~a~~|5.5<br>~~a~~|V<br>~~a~~| |IDDM<br>~~a~~|Main supply current<br>(I2C inactive)<br>~~a~~|-<br>~~a~~|-<br>~~a~~|1<br>~~a~~|5<br>~~a~~|µA<br>~~a~~| |ICC1,2|I/O banks supply current(1)|VCC1,2 >=2V|-|1|2|µA| |||VCC1,2 < 2V|-|0.5|1|| |**I/Os set as Input**||||||| |VIH<br>~~a~~|High level input voltage<br>~~a~~|-<br>~~a~~|0.7*<br>VCC1,2<br>~~a~~|-<br>~~a~~|VCC1,2<br>+0.3<br>~~a~~|V<br>~~a~~| |VIL<br>~~a~~|Low level input voltage<br>~~a~~|-<br>~~a~~|-0.4<br>~~a~~|-<br>~~a~~|0.3*<br>VCC1,2<br>~~a~~|V<br>~~a~~| |VHYS<br>~~a~~|Hysteresis of Schmitt trigger<br>~~a~~|-<br>~~a~~|-<br>~~a~~|0.1*<br>VCC1,2<br>~~a~~|-<br>~~a~~|V<br>~~a~~| |ILEAK<br>~~a~~|Input leakage current<br>~~a~~|Assuming no active<br>pull-up/down<br>~~a~~|-1.5<br>~~a~~|-<br>~~a~~|1.5<br>~~a~~|µA<br>~~a~~| |CI<br>~~Cel~~|Input capacitance<br>~~Cel~~|-<br>~~Cel~~|-<br>~~Cel~~|-<br>~~Cel~~|10<br>~~Cel~~|pF<br>~~Cel~~| |**I/Os set as Output**<br>~~Cel~~||||||| |VOH<br>~~a~~<br>~~ee~~|High level output voltage<br>|-|VCC1,2<br>–0.3|-|VCC1,2|V| |VOL<br>~~ee~~|Low level output voltage<br>|-|-0.4|-|0.3|V| |IOH<br>~~eeee~~|High level output source<br>current<br>~~ee~~|VCC1,2 >=2V|-|-|8<br>~~(2)~~|mA<br>~~eee~~| |||VCC1,2 < 2V<br>~~eee~~|-<br>~~eee~~|-<br>~~eee~~|0.3~~(2)~~<br>~~eee~~|| |IOL<br>~~ee~~|Low level output sink current<br>for the high sink I/Os<br>~~ee~~|VCC1,2 >=2V<br>~~eee~~|-<br>~~eee~~|-<br>~~eee~~|24<br>~~(2)~~<br>~~eee~~|mA<br>~~eee~~<br>~~eee~~| |||VCC1,2 < 2V<br>~~eee~~|-<br>~~eee~~|-<br>~~eee~~<br>~~eee~~|6~~(2)~~<br>~~eee~~<br>~~eee~~|| ||Low level output sink current<br>for the other I/Os.<br>~~ee~~<br>~~es~~|VCC1,2 >=2V<br>~~eee~~<br>~~a~~<br>~~es~~|-<br>~~eee~~<br>~~a~~<br>~~es~~|-<br>~~eee~~<br>~~a~~<br>~~es~~<br>~~eee~~|12<br>~~eee~~<br>~~a~~<br>~~es~~<br>~~eee~~|mA<br>~~eee~~<br>~~es~~<br>~~eee~~| |||VCC1,2 < 2V<br>~~eee~~<br>~~es~~|-<br>~~eee~~<br>~~es~~|-<br>~~eee~~<br>~~es~~<br>~~eee~~|6<br>~~eee~~<br>~~es~~<br>~~eee~~|| |tPV<br>~~ee~~<br>~~Cel~~|Output data valid timing<br>~~ee~~<br>~~Cel~~|Cf. Figure 9<br>~~eee~~<br>~~Cel~~|-<br>~~eee~~<br>~~Cel~~|-<br>~~eee~~<br>~~eee~~<br>~~Cel~~|1.5<br>~~eee~~<br>~~eee~~<br>~~Cel~~|µs<br>~~eee~~<br>~~eee~~<br>~~Cel~~| |**NINT(Output)**<br>~~Cel~~||||||| |VOL<br>~~a a~~|Low level output voltage<br>~~a~~|-<br>~~a~~|-<br>~~a~~|-<br>~~a~~|0.3<br>~~a~~|V<br>~~a~~| |IOLM<br>~~ry}~~|Low level output sink current<br>~~ry}~~|VDDM >=2V<br>~~ry}~~|-<br>~~ry}~~|-<br>~~ry}~~|12<br>~~ry}~~|m~~A~~<br>~~ry}~~| |||VDDM < 2V<br>~~ry}~~|-<br>~~ry}~~|-<br>~~ry}~~|6<br>~~ry}~~|| |tIV<br>~~a~~|Interrupt valid timing<br>~~a~~|From input data change<br>~~a~~|-<br>~~a~~|-<br>~~a~~|1<br>~~a~~|µs<br>~~a~~| Rev 11 – 16[th] May 2012 www.semtech.com 7 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## **WIRELESS & SENSING** |**Symbol **|**Description **|**Conditions**|**Min**|**Typ**|**Max **|**Unit**| |---|---|---|---|---|---|---| |tIR|Interrupt reset timing|From RegInterruptSource<br>clearing|-|-|2|µs| |**NRESET(Input/Output)**<br>~~aaa~~<br>~~es~~||||||| |VOL<br>~~es~~|Low level output voltage|-|-|-|0.3|V| |IOLM<br>~~es~~|Low level output sink current<br>~~a~~|VDDM >=2V<br>~~a~~|-|-|12|mA| |||VDDM < 2V<br>~~a~~|-|-|6|| |VIHMR|High level input voltage<br>~~a~~|-<br>~~a~~|0.7*<br>VDDM|-|5.5|V| |VILM|Low level input voltage|-|-0.4|-|0.3*<br>VDDM|V| |VHYSM<br>~~ee~~|Hysteresis of Schmitt trigger|-|-|0.1*<br>VDDM|-|V| |ILEAK<br>~~ee~~<br>~~ee~~|Input leakage current|-|-1.5|-|1.5|µA| |CI<br>~~ee~~<br>~~ee~~<br>~~ee~~|Input capacitance|-|-|-|10|pF| |VPOR<br>~~ee~~<br>~~ee~~<br>~~ee~~|Power-On-Reset voltage|Cf. Figure 7|0.7|-|0.9|V| |VDROPH <br>~~ee~~<br>~~ee~~<br>~~ee~~|High brown-out voltage|Cf. Figure 7|-|VDDM-1|-|V| |VDROPL <br>~~ee~~<br>~~ee~~<br>~~ee~~|Low brown-out voltage|Cf. Figure 7|-|0.2|-|V| |tRESET<br>~~ee~~<br>~~ee~~<br>~~ee~~|Reset time<br>|Cf. Figure 7<br>|-<br>|-<br>|7<br>|ms<br>| |tPULSE<br>~~ee~~<br>~~ee~~|Reset pulse from host uC<br>|Cf. Figure 7<br>|300<br>|-<br>|-<br>|ns<br>| |**ADDR(Input)**<br>~~eeaaa~~||||||| |VIHMA|High level input voltage|-|0.7*<br>VDDM|-|VDDM<br>+0.3|V| |VILM|Low level input voltage|-|-0.4|-|0.3*<br>VDDM|V| |VHYSM<br>~~ee~~|Hysteresis of Schmitt trigger|-|-|0.1*<br>VDDM|-|V| |ILEAK<br>~~ee~~<br>~~ee~~|Input leakage current<br>|-<br>|-1.5<br>|-<br>|1.5<br>|µA<br>| |CI<br><br>~~ee~~<br>~~ee~~|Input capacitance<br>~~**(3)**~~<br>|-<br>|-<br>|-<br>|10<br>|pF<br>| |**SCL (Input) and SDA(Input/Output) **~~**(3)**~~<br>~~22~~<br>~~eeaaa~~||||||| |Interface complies with slave F/S mode I~~2~~C interface as described by Philips I~~2~~C specification version 2.1<br>dated January, 2000. Please refer to that document for more detailed I2C specifications.<br>C4<br>a<br>__<br>ro<br>co<br>|<br>ail<br>--<br>|<br>|<br>tr r<br>tlow><br>pt<br>| tsu;pat 7]<br>[7<br>|<br>|<br>tHD:STA<br>Hour<br>7<br>|<br>i<br>|i<br>i}<br>|<br>i]<br>|<br>i<br>|<br>i<br>||<br>--<br>i}<br>|<br>--<br>i]<br>|<br>i<br>|<br>|=!<br>|<br>tHp:sTa<br>'<br>tsu;stae<br>|<br>|<br>tsu:sto™<br>|<br>|<br>t<br>|<br>\s|<br>HD:DAT<br>‘HIGH<br>| sr |<br>|P|<br>Is |<br>~~ee~~||||||| |VOL<br>~~ee~~|Low level output voltage|-|-|-|0.3|V| |IOLM<br>~~ee~~|Low level output sink current<br>~~a~~|VDDM >=2V<br>~~a~~|-|-|12|mA| |||VDDM < 2V<br>~~a~~|-|-|6|| |VIHMR|High level input voltage<br>~~a~~|-<br>~~a~~|0.7*<br>VDDM|-|5.5|V| |VILM<br>~~ee~~|Low level input voltage|-|-0.4|-|0.3*<br>VDDM|V| |fSCL<br>~~ee~~|SCL clock frequency|-|0|-|400|kHz| |tHD;STA<br>~~ee~~<br>~~ee~~|Hold time (repeated) START<br>condition|-|0.6|-|-|µs| |tLOW<br>~~ee~~|LOW period of the SCL clock|-|1.3|-|-|µs| |tHIGH<br>~~ee~~|HIGH period of the SCL clock<br>~~a~~|VDDM >=1.3V<br>~~a~~|0.6|-|-|µs| |||VDDM < 1.3V<br>~~a~~|1|-|-|| |tSU;STA<br>~~ee~~|Set-up time for a repeated<br>START condition<br>~~a~~|-<br>~~a~~|0.6<br>~~(4)~~|-|-<br>~~(5)~~|µs| |tHD;DAT<br>~~ee~~<br>~~ee~~|Data hold time|-|0~~(4)~~<br>~~(6)~~|-|0.9~~(5)~~|µs| |HD;DAT<br>tSU;DAT<br>~~ee~~<br>~~ee~~|Data set-up time|-|100~~(6)~~|-|-|| |SU;DAT<br>tr<br>~~ee~~|Rise time of both SDA and<br>SCL signals|-|20+0.1Cb<br>(7)|-|300|ns| Rev 11 – 16[th] May 2012 www.semtech.com 8 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## ~~LT~~ **WIRELESS & SENSING** |**Symbol **|**Description **|**Conditions**|**Min**|**Typ**|**Max **|**Unit**| |---|---|---|---|---|---|---| |tf<br>~~a~~|Fall time of both SDA and<br>SCL signals<br>~~a~~|-<br>~~a~~|20+0.1Cb<br>(7)<br>~~a~~|-<br>~~a~~|300<br>~~a~~|ns<br>~~a~~| |tSU;STO<br>~~a~~|Set-up time for STOP<br>condition<br>~~a~~|-<br>~~a~~|0.6<br>~~a~~|-<br>~~a~~|-<br>~~a~~|µs<br>~~a~~| |tBUF<br>~~a~~|Bus free time between a<br>STOP and START condition<br>~~a~~|-<br>~~a~~|1.3<br>~~a~~|-<br>~~a~~|-<br>~~a~~|µs<br>~~a~~| |Cb<br>~~a~~|Capacitive load for each bus<br>line<br>~~a~~|-<br>~~a~~|-<br>~~a~~|-<br>~~a~~|400<br>~~a~~|pF<br>~~a~~| |VnL<br>~~a~~|Noise margin at the LOW<br>level for each connected<br>device (including hysteresis)<br>~~a~~|-<br>~~a~~<br>~~a~~|0.1*VDDM<br>~~a~~|-<br>~~a~~<br>~~ee~~|-<br>~~a~~<br>~~ee~~|V<br>~~a~~<br>~~ee~~| |VnH<br>~~rr~~|Noise margin at the HIGH<br>level for each connected<br>device (including hysteresis)<br>~~rr~~|-<br>~~rr~~<br>~~a~~|0.2*VDDM<br>~~rr~~|-<br>~~rr~~<br>~~ee~~|-<br>~~rr~~<br>~~ee~~|V<br>~~rr~~<br>~~ee~~| |**Miscellaneous**<br>~~rr~~<br>~~a~~<br>~~ee~~||||||| |RPULL<br>~~a~~|Programmable pull-up/down<br>resistors for IO[0-7]<br>~~a~~|-<br>~~a~~<br>~~a~~|-<br>~~a~~|60<br>~~ee~~<br>~~a~~|-<br>~~ee~~<br>~~a~~|kΩ<br>~~ee~~<br>~~a~~| |tPLD|PLD propagation delay|VCC1,2 & VDDM=5V|-|-|25|ns| |||VCC1,2 & VDDM=1.2V|-|-|500|| (1) Assuming no load connected to outputs and inputs fixed to VCC1,2 or GND. (2) Can be increased in RegAdvanced register. Please refer to §2.2.1 for more details. (3) All values referred to VIHMR min and VILM max levels. (4) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to VIHMR min) to bridge the undefined region of the falling edge of SCL. (5) The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. (6) A Fast-mode I[2] C-bus device can be used in a Standard-mode I[2] C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max+ tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. (7) Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times are allowed. _Table 5 – Electrical Specifications_ ## 2.2.1 Increasing I/O Sink and Source Current Capabilities (Boost Mode) When bit 1 of RegAdvanced register is set, max IOH and IOL spec **when VCC1,2 is below VBOOST** can be increased together with IDDM and ICC1,2 figures as described below. |**Symbol **|**Description **|**Conditions**|**Conditions**|**Min**|**Typ**|**Max **|**Unit**| |---|---|---|---|---|---|---|---| |**Supply**<br>~~a~~|||||||| |VBOOST <br>~~a~~|Low voltage boost threshold<br>~~a~~|-<br>~~a~~||2.0<br>~~a~~|2.6<br>~~a~~|-<br>~~a~~|V<br>~~a~~| |IDDM<br>~~a~~|Main supply current<br>(I2C inactive)<br>~~a~~|VDDM=5.5V (VCC1,2 < 2V)<br>~~a~~<br>~~———=——)~~||-<br>~~a~~<br>~~———=——)~~|150<br>~~a~~<br>~~———=——)~~|250<br>~~a~~<br>~~———=——)~~|µA<br>~~a~~<br>~~———=——)~~| |||VDDM=1.2V (VCC1,2 < 2V)<br>~~———=——)~~||-<br>~~———=——)~~|25<br>~~———=——)~~|50<br>~~———=——)~~|uA<br>~~———=——)~~| |ICC1<br>~~a~~|I/O bank A supply current<br>~~a~~|SX1501/2<br>~~a~~<br>~~———=——)~~<br>~~ee~~|VCC1=2V<br>~~a~~<br>~~———=——)~~|-<br>~~a~~<br>~~———=——)~~|250<br>~~a~~<br>~~———=——)~~|550<br>~~a~~<br>~~———=——)~~|µA<br>~~a~~<br>~~———=——)~~| ||||VCC1=1.2V<br>~~a~~<br>~~———=——)~~<br>~~ee~~|-<br>~~a~~<br>~~———=——)~~<br>~~eee~~|100<br>~~a~~<br>~~———=——)~~<br>~~ee~~|200<br>~~a~~<br>~~———=——)~~<br>~~ee~~|| |||SX1503<br>~~a~~<br>~~———=——)~~<br>~~ee~~|VCC1=2V<br>~~a~~<br>~~———=——)~~<br>~~ee~~|-<br>~~a~~<br>~~———=——)~~<br>~~eee~~|250<br>~~a~~<br>~~———=——)~~<br>~~ee~~|550<br>~~a~~<br>~~———=——)~~<br>~~ee~~|| ||||VCC1=1.2V<br>~~a~~<br>~~———=——)~~<br>~~ee~~|-<br>~~a~~<br>~~———=——)~~<br>~~eee~~|100<br>~~a~~<br>~~———=——)~~<br>~~ee~~|200<br>~~a~~<br>~~———=——)~~<br>~~ee~~|| |ICC2<br>~~i~~|I/O bank B supply current<br>~~i~~|SX1502<br>~~———=——)~~<br>~~ee~~<br>~~ee~~|VCC2=2V<br>~~———=——)~~<br>~~ee ~~<br>~~ee~~<br>~~===)~~|-<br>~~———=——)~~<br> ~~eee ~~<br>~~ee~~<br>~~===)~~|150<br>~~———=——)~~<br> ~~ee ~~<br>~~ee~~<br>~~===)~~|250<br>~~———=——)~~<br> ~~ee~~<br>~~ee~~<br>~~===)~~|µA<br>~~———=——)~~<br>~~===)~~| ||||VCC2=1.2V<br>~~———=——)~~<br>~~ee~~<br>~~===)~~|-<br>~~———=——)~~<br>~~ee~~<br>~~===)~~|50<br>~~———=——)~~<br>~~ee~~<br>~~===)~~|150<br>~~———=——)~~<br>~~ee~~<br>~~===)~~|| |||SX1503<br>~~———=——)~~<br>~~ee~~|VCC2=2V<br>~~———=——)~~<br>~~ee~~<br>~~===)~~|-<br>~~———=——)~~<br>~~ee~~<br>~~===)~~|250<br>~~———=——)~~<br>~~ee~~<br>~~===)~~|450<br>~~———=——)~~<br>~~ee~~<br>~~===)~~|| ||||VCC2=1.2V<br>~~ee~~<br>~~===)~~<br>~~po~~|-<br>~~ee~~<br>~~===)~~<br>~~po~~|100<br>~~ee~~<br>~~===)~~<br>~~po~~|200<br>~~ee~~<br>~~===)~~<br>~~po~~|| |**I/Os set as Output**|||||||| |IOH<br>~~————————~~|High level output source<br>current for all I/Os<br>~~————————~~|VCC1,2 >=VBOOST<br>~~————————~~||-<br>~~————————~~|-<br>~~————————~~|8<br>~~————————~~|mA<br>~~————————~~| |||VCC1,2 < VBOOST<br>~~————————~~||-<br>~~————————~~|-<br>~~————————~~|**4**<br>~~————————~~|| |IOL|Low level output sink current<br>for the high sink I/Os|VCC1,2 >=VBOOST<br>~~a~~||-<br>~~a~~|-<br>~~a~~|24<br>~~a~~|mA<br>~~a~~| |||VCC1,2 < VBOOST||-|-|**12**|| ||Low level output sink current<br>for the other I/Os<br>~~5~~|VCC1,2 >=VBOOST<br>~~5~~||-<br>~~5~~|-<br>~~5~~|12<br>~~5~~|mA<br> || |||VCC1,2 < VBOOST<br>~~5~~||-<br>~~5~~|-<br>~~5~~|6<br>~~5 ~~|| |**NINT, NRESET**<br>~~ie~~|||||||| |IOLM<br>~~ie~~|Low level output sink current<br>for NINT,NRESET<br>~~ie~~|VDDM >=VBOOST<br>~~ie~~||-<br>~~ie~~|-<br>~~ie~~|12<br>~~ie~~|mA<br>~~ie~~| |||VDDM < VBOOST<br>~~ie~~||-<br>~~ie~~|-<br>~~ie~~|6<br>~~ie~~|| www.semtech.com 9 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## **WIRELESS & SENSING** ## —————zZ—a>—X—LXzz&&C—&——GC—E— **3 TYPICAL OPERATING CHARACTERISTICS** Figures below apply to default registers values (Boost Mode Off), Tamb, unless otherwise specified. ## **3.1 IDDM vs. VDDM** **==> picture [308 x 201] intentionally omitted <==** **----- Start of picture text -----**<br> IDDM vs VDDM<br>3.5<br>3<br>2.5<br>IDDM (uA) 2 90°C<br>-40°C<br>1.5<br>1<br>0.5<br>0<br>0 1 2 3 4 5 6<br>VDDM (V)<br>**----- End of picture text -----**<br> ## **3.2 VOL vs. IOL** **==> picture [303 x 199] intentionally omitted <==** **----- Start of picture text -----**<br> VOL vs IOL (VCC1,2=1.2V, all IOs)<br>0.15<br>0.1<br>VOL (V) Tamb [*]<br>0.05<br>0<br>0 1.5 3 4.5 6 7.5 9<br>*<br>Doesn’t vary significantly with temperature IOL (mA)<br>**----- End of picture text -----**<br> Rev 11 – 16[th] May 2012 www.semtech.com 10 **==> picture [500 x 789] intentionally omitted <==** **----- Start of picture text -----**<br> SX1501/SX1502/SX1503<br> 4/8/16 Channel Low Voltage GPIO<br>WIRELESS & SENSING<br>VOL vs IOL (VCC1,2=5.5V, High Sink IOs)<br>0.15<br>0.1<br>VOL (V)<br>Tamb [*]<br>0.05<br>0<br>0 5 10 15 20 25 30<br>*<br>Doesn’t vary significantly with temperature IOL (mA)<br>=<br>3.3 VOH vs. IOH<br>VOH vs IOH (VCC1,2=1.2V)<br>1.2<br>1.18<br>1.16<br>VOH (V)<br>Tamb [*]<br>1.14<br>1.12<br>1.1<br>0 0.2 0.4 0.6 0.8 1<br>*<br>Doesn’t vary significantly with temperature IOH (mA)<br>La!<br>VOH vs IOH (VCC1,2=5.5V)<br>5.5<br>5.4<br>VOH (V) 5.3<br>Tamb [*]<br>5.2<br>5.1<br>5<br>0 10 20<br>*<br>Doesn’t vary significantly with temperature IOH (mA)<br>Ls<br>Rev 11 – 16 [th] May 2012 www.semtech.com<br>11<br>**----- End of picture text -----**<br> **SX1501/SX1502/SX1503** **4/8/16 Channel Low Voltage GPIO** ~~[~~ **WIRELESS & SENSING** ## **3.4 ICC1+ICC2 vs. VCC1,2 when Boost Mode is ON** **==> picture [375 x 199] intentionally omitted <==** **----- Start of picture text -----**<br> ICC1+ICC2 vs VCC1,2 (VDDM = 1.2V)<br>700<br>600<br>500<br>Tamb<br>400<br>ICC (uA) Boost Mode ON -40°C<br>300<br>90°C<br>200<br>100<br>0<br>0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2<br>VCC1,2 (V)<br>**----- End of picture text -----**<br> **==> picture [375 x 194] intentionally omitted <==** **----- Start of picture text -----**<br> ICC1+ICC2 vs VCC1,2 (VDDM = 5.5V)<br>500<br>400 Tamb<br>ICC (uA) Boost Mode ON<br>300<br>-40°C<br>200 90°C<br>100<br>0<br>0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2<br>VCC1,2 (V)<br>**----- End of picture text -----**<br> Rev 11 – 16[th] May 2012 www.semtech.com 12 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## **WIRELESS & SENSING** ## **4 BLOCK DETAILED DESCRIPTION** ## **4.1 SX1501 4-channel GPIO** **==> picture [432 x 524] intentionally omitted <==** **----- Start of picture text -----**<br> VDDM<br>Reset<br>NRESET SZ Dx] VCC1<br>. = I [2] C Bus 4-Bit on I/O[0]<br>R/W I/O Bank A x] I/O[1]<br>Control I/O[2]<br>SCL Input I/O[3]<br>aN Filter x]<br>SDA<br>Interrupt a NINT<br>ADDR x ]<br>SX1501<br>Xx]<br>GND<br>Figure 4 – 4-channel Low Voltage GPIO<br>SX1502 8-channel GPIO<br>VCC1<br>VDDM ms Xx] I/O[0]<br>Reset I/O Bank A 5 I/O[1]<br>NRESET Dd | <p“be I/O[2]<br>I [2] C Bus 8-Bit I/O[3]<br>Control <__» R/W vs<br>I Lx] VCC2<br>SCL<br>Input<br>I/O[4]<br>Xx <Po<br>Filter I/O Bank B x] I/O[5]<br>SDA I/O[6]<br>x] I/O[7]<br>ADDR<br>SX1502<br>Interrupt x] NINT<br>Xx]<br>GND<br>**----- End of picture text -----**<br> ## **4.2 SX1502 8-channel GPIO** _Figure 5 – 8-channel Low Voltage GPIO_ Rev 11 – 16[th] May 2012 www.semtech.com 13 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## ~~Lo~~ **WIRELESS & SENSING** ## **4.3 SX1503 16-channel GPIO** **==> picture [433 x 263] intentionally omitted <==** **----- Start of picture text -----**<br> VCC1<br>I/O[0]<br>I/O[1]<br>I/O[2]<br>I/O Bank A I/O[3]<br>VDDM 8-Bit I/O[4]<br>Reset I/O[5]<br>NRESET R/W I/O[6]<br>I [2] C Bus I/O[7]<br>Control VCC2<br>SCL Input 8-Bit I/O[8]<br>I/O[9]<br>Filter R/W<br>SDA I/O[10]<br>I/O Bank B I/O[11]<br>I/O[12]<br>I/O[13]<br>I/O[14]<br>SX1503 I/O[15]<br>Interrupt NINT<br>**----- End of picture text -----**<br> ## GND _Figure 6 – 16-channel Low Voltage GPIO_ ## **4.4 Reset (NRESET)** **==> picture [500 x 205] intentionally omitted <==** **----- Start of picture text -----**<br> The SX1501, SX1502 and SX1503 generate their own power on reset signal after a power supply is connected<br>to the VDDM pin. The reset signal is made available for the user at the pin NRESET. The rising edge of the<br>NRESET indicates that the startup sequence of the SX1501, SX1502 or SX1503 has finished. NRESET must be<br>connected to VDDM (or greater) either directly, or via a resistor.<br>1 2 3 4 5 6 1 2<br>VDROPH<br>VPOR<br>VDROPL<br>VDDM epee dict<br>4 !<br>Undefined Undefined Undefined<br>NRESET<br>ao tRESET tPULSE Be tRESET<br>**----- End of picture text -----**<br> _Figure 7 – Power-On / Brown-out Reset Conditions_ 1. Device behavior is undefined until VDDM rises above VPOR, at which point NRESET is driven to GND by the SX1501, SX1502 or SX1503. 2. After tRESET, NRESET is released (high-impedance) by the SX1501, SX1502 or SX1503 to allow it to be pulled high by an external resistor. 3. In operation, the SX1501, SX1502 and SX1503 may be reset at anytime by an external device driving NRESET low during tPULSE. Chip can be accessed normally again after NRESET rising edge. Rev 11 – 16[th] May 2012 www.semtech.com 14 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## ~~LO~~ **WIRELESS & SENSING** 4. During a brown-out event, if VDDM drops above VDROPH a reset will not occur. 5. During a brown-out event, if VDDM drops between VDROPH and VDROPL a reset may occur. 6. During a brown-out event, if VDDM drops below VDROPL a reset will occur next time VPOR is crossed. Please note that a brown-out event is defined as a transient event on VDDM. If VDDM is attached to a battery, then the gradual decay of the battery voltage will not be interpreted as a brown-out event. Please also note that a sharp rise in VDDM (> 1V/us) may induce a circuit reset. ## **4.5 2-Wire Interface (I[2] C)** The SX1501, SX1502 and SX1503 2-wire interface (I[2] C compliant) operates only in slave mode. In this configuration, the device has one or two device addresses defined by ADDR pin. |**Device**|**ADDR Pin**|**I**~~**2**~~**C Address**|**Description**| |---|---|---|---| |SX1501 &<br>SX1502|**0**|0x2**0** (010000**0**)|First address of the 2-wire interface| ||**1**|0x2**1** (010000**1**)|Second address of the 2-wire interface| |SX1503||0x20 (0100000)|Fixed address ofthe2-wireinterface| 2 lines are used to exchange data between an external master host and the slave device: - **SCL** : **S** erial **CL** ock - **SDA** : **S** erial **DA** ta The SX1501, SX1502 and SX1503 are read-write slave-mode I[2] C devices and comply with the Philips I[2] C standard Version 2.1 dated January, 2000. The SX1501, SX1502 and SX1503 have respectively 12, 16, and 31 user-accessible internal 8-bit registers. The I[2] C interface has been designed for program flexibility, in that once the slave address has been sent to the SX1501, SX1502 or SX1503 enabling it to be a slave transmitter/receiver, any register can be written or read independently of each other. While there is no auto increment/decrement capability in the SX1501 and SX1502 I[2] C logic, a tight software loop can be designed to access the next register independent of which register you begin accessing. SX1503 implements auto increment capability. The start and stop commands frame the data-packet and the repeat start condition is allowed if necessary. Seven bit addressing is used and ten bit addressing is not allowed. Any general call address will be ignored by the SX1501, SX1502 and SX1503. The SX1501, SX1502 and SX1503 are not CBUS compatible and can operate in standard mode (100kbit/s) or fast mode (400kbit/s). ## 4.5.1 WRITE The simplest format for an I[2] C write is given below. After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The I[2] C then acknowledges that it is being addressed, and the master responds with an 8 bit data byte consisting of the register address. The slave acknowledges and the master sends the appropriate 8 bit data byte. Once again the slave acknowledges and the master terminates the transfer with the stop condition [P]. Master operations SX1501, SX1502 or SX1503 operations (Slave) S: Start Condition Slave Address: 7 bit W: Write = ‘0’ Register Address: 8 bit A: Acknowledge (sent by slave) Data: 8 bit P: Stop condition _Figure 8 - 2-Wire Serial Interface, Write Register Operation_ Rev 11 – 16[th] May 2012 www.semtech.com 15 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## **WIRELESS & SENSING** ## _Figure 9 – Write RegData Register_ Please note that SX1503 implements register address auto-increment i.e. after the Data ACK from Slave the master can write further bytes and the interface will handle the register address increment automatically. Finally the master terminates the transfer normally the stop condition [P]. ## 4.5.2 READ After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The I[2] C then acknowledges that it is being addressed, and the master responds with an 8 bit data byte consisting of the register address. The slave acknowledges and the master sends the repeated start condition [Sr]. Once again, the slave address is sent, followed by an eighth bit indicating a read. The slave responds with an acknowledge and the previously addressed 8 bit data byte; the master then sends a non-acknowledge (NACK). Finally, the master terminates the transfer with the stop condition [P]. Master operations SX1501, SX1502 or SX1503 operations (Slave) S: Start Condition Slave Address: 7 bit W: Write = ‘0’ Register Address: 8 bit R: Read = ‘1’ Data: 8 bit A: Acknowledge (sent by slave) NACK: Non-Acknowledge (sent by master) Sr: Repeated Start Condition P: Stop condition ## _Figure 10 - 2-Wire Serial Interface, Read Register Operation_ Please note that SX1503 implements register address auto-increment i.e. after the Data byte from Slave the master can acknowledge (ACK) to indicate that it wants to read the next byte and the interface will handle the register address increment automatically. Finally the master terminates the transfer normally with a NACK followed by the stop condition [P]. ## 4.5.3 READ - STOP separated format (SX1501 and SX1502 only) When operating SX1501 or SX1502, stop-separated reads can also be used. This format allows a master to set up the register address pointer for a read and return to that slave at a later time to read the data. In this format the slave address followed by a write command are sent after a start [S] condition. The slave then acknowledges it is being addressed, and the master responds with the 8-bit register address. The master sends a Stop or Restart condition and may then address another slave. After performing other tasks, the master can send a start or restart condition to the slave with a read command. The slave acknowledges this request and returns the data from the register location that had previously been set up. Rev 11 – 16[th] May 2012 www.semtech.com 16 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## **WIRELESS & SENSING** Master operations SX1501, SX1502 or SX1503 operations (Slave) S: Start Condition Slave Address: 7 bit W: Write = ‘0’ Register Address: 8 bit R: Read = ‘1’ Data: 8 bit A: Acknowledge (sent by slave) NACK: Non-Acknowledge (sent by master) Sr: Repeated Start Condition P: Stop condition _Figure 11 - 2-Wire Serial Interface, Read – Stop Separated Mode Operation_ ## **4.6 Interrupt (NINT)** At start-up, the transition detection logic is reset, and NINT is released to a high-impedance state. The interrupt mask register is set to 0xFF, disabling the interrupt output for transitions on all I/O ports. The transition flags are cleared to indicate no data changes. An interrupt NINT can be generated on any programmed combination of I/Os rising and/or falling edges through the RegInterruptMask and RegSense registers. If needed, the I/Os which triggered the interrupt can then be identified by reading RegInterruptSource register. When NINT is low (i.e. interrupt occurred), it can be reset back high (i.e. cleared) by writing 0xFF in RegInterruptSource (this will also clear corresponding bits in RegEventStatus register). SX1503 also allows the interrupt to be cleared automatically when reading RegData register (Cf. RegAdvanced) _Example: We want to detect rising edge of I/O[1] on SX1502 (NINT will go low)._ _1. We enable interrupt on I/O[1] in RegInterruptMask_ - _RegInterruptMask =“XXXXXX_ _**0** X”_ _2. We set edge sense for I/O[1] in RegSense_ > _RegSenseLow =“XXXX_ _**01** XX”_ ## **4.7 Programmable Logic Functions (PLD)** The SX1501, SX1502 and SX1503 offer a unique fully programmable logic functions like a PLD to give more flexibility and reduce external logic gates used for standard applications. Since the whole truth table is fully programmable, the SX1501, SX1502, and SX1503 can implement combinatory functions ranging from the basic AND/OR gates to the most complicated ones with up to four 3-to1 PLDs or two 3-to-2 PLDs which can also be externally cascaded if needed. In all cases, any IO not configured for PLD functionality retains its GPIO functionality while I/Os used by the PLD have their direction automatically set accordingly. Please note that while RegDir corresponding bits are ignored for PLD operation they may still be set to input to access unused PLD inputs as normal GPI (PLD truth table can define some inputs to have no effect on PLD output) and/or generate interrupt based on any of the PLD inputs or outputs bits. ## 4.7.1 SX1501 The SX1501 I/Os can be configured to provide any combinational 2-to-1 logic function using I/O[0-2] whilst retaining GPIO capability on I/O[3] OR provide a combinational 3-to-1 decode function using all 4 I/O ports. |**RegPLDMode**|**SX1501 I/Os**|**SX1501 I/Os**|**SX1501 I/Os**|**SX1501 I/Os**| |---|---|---|---|---| |**1:0**|**3**|**2**|**1**|**0**| |00|GPIO|GPIO|GPIO|GPIO| |01|GPIO|PLD OUT|PLD IN|PLD IN| |10|PLD OUT|PLD IN|PLD IN|PLD IN| _Table 8 – SX1501 PLD Modes Settings_ Rev 11 – 16[th] May 2012 www.semtech.com 17 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## **WIRELESS & SENSING** ## 4.7.2 SX1502 The SX1502 I/Os can be configured as per the SX1501, and can additionally be configured to provide a 2-to-1 logic function on I/O[4-6], 3-to-1 logic function on I/O[4-7], or 3-to-2 logic decode on I/O[0-4]. |**RegPLDMode**|**RegPLDMode**|**SX1502 I/Os**|**SX1502 I/Os**|**SX1502 I/Os**|**SX1502 I/Os**|**SX1502 I/Os**|**SX1502 I/Os**|**SX1502 I/Os**|**SX1502 I/Os**| |---|---|---|---|---|---|---|---|---|---| |**5:4**|**1:0**|**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**| |00<br>~~a~~<br>~~ee~~|00<br>~~a~~<br>~~es~~|GPIO<br>~~QO~~|GPIO<br>~~Ga~~|GPIO|GPIO<br>~~GG~~|GPIO<br>~~GG~~|GPIO<br>~~GG~~|GPIO<br>~~CO~~|GPIO<br>~~CO~~| |00<br>~~ee~~|01<br>~~es~~|GPIO<br>~~QO~~|GPIO<br>~~Ga~~|GPIO|GPIO<br>~~GG~~|GPIO<br>~~GG~~|PLD OUT<br>~~GG~~|PLD IN<br>~~CO~~|PLD IN<br>~~CO~~| |00<br>~~ee ~~<br>~~po~~|10<br> ~~es~~<br>~~po~~|GPIO<br>~~QO~~|GPIO<br>~~Ga~~|GPIO|GPIO<br>~~GG~~|PLD OUT<br>~~GG~~|PLD IN<br>~~GG~~|PLD IN<br>~~CO~~|PLD IN<br>~~CO~~| |00<br>~~po~~|11<br>~~po~~|GPIO|GPIO|GPIO|PLD OUT|PLD OUT|PLD IN|PLD IN|PLD IN| |01<br>~~po~~|00<br>~~po~~|GPIO|PLD OUT|PLD IN|PLD IN|GPIO|GPIO|GPIO|GPIO| |01<br>~~po~~|01<br>~~po~~|GPIO|PLD OUT|PLD IN|PLD IN|GPIO|PLD OUT|PLD IN|PLD IN| |01<br>~~po~~|10<br>~~po~~|GPIO|PLD OUT|PLD IN|PLD IN|PLD OUT|PLD IN|PLD IN|PLD IN| |01<br>~~po~~|11<br>~~po~~|GPIO|GPIO|GPIO|PLD OUT|PLD OUT|PLD IN|PLD IN|PLD IN| |10<br>~~Po~~|00<br>~~Po~~|PLD OUT|PLD IN|PLD IN|PLD IN|GPIO|GPIO|GPIO|GPIO| |10<br>~~po~~<br>~~a~~|01<br>~~po~~<br>~~ee~~|PLD OUT<br>~~QO~~|PLD IN<br>~~(n(n~~|PLD IN<br>~~(n(n~~|PLD IN<br>~~GG~~|GPIO<br>~~GG~~|PLD OUT<br>~~GG~~|PLD IN<br>~~CO~~|PLD IN<br>~~CO~~| |10<br>~~a~~|10<br>~~ee~~|PLD OUT<br>~~QO~~|PLD IN<br>~~(n(n~~|PLD IN<br>~~(n(n~~|PLD IN<br>~~GG~~|PLD OUT<br>~~GG~~|PLD IN<br>~~GG~~|PLD IN<br>~~CO~~|PLD IN<br>~~CO~~| |10<br>~~a~~<br>~~po~~|11<br>~~ee~~<br>~~po~~|GPIO<br>~~QO~~|GPIO<br>~~(n(n~~|GPIO<br>~~(n(n~~|PLD OUT<br>~~GG~~|PLD OUT<br>~~GG~~|PLD IN<br>~~GG~~|PLD IN<br>~~CO~~|PLD IN<br>~~CO~~| _Table 9 – SX1502 PLD Modes Settings_ ## 4.7.3 SX1503 Each of the two I/O banks of the SX1503 I/Os can be configured as per the SX1502. |**RegPLDModeB**|**RegPLDModeB**|**SX1503 I/Os**|**SX1503 I/Os**|**SX1503 I/Os**|**SX1503 I/Os**|**SX1503 I/Os**|**SX1503 I/Os**|**SX1503 I/Os**|**SX1503 I/Os**| |---|---|---|---|---|---|---|---|---|---| |**5:4**|**1:0**|**15**|**14**|**13**|**12**|**11**|**10**|**9**|**8**| |00<br>~~a~~<br>~~ee~~|00<br>~~a~~<br>~~es~~|GPIO<br>~~QO~~|GPIO<br>~~Ga~~|GPIO|GPIO<br>~~GG~~|GPIO<br>~~GG~~|GPIO<br>~~GG~~|GPIO<br>~~CO~~|GPIO<br>~~CO~~| |00<br>~~ee~~|01<br>~~es~~|GPIO<br>~~QO~~|GPIO<br>~~Ga~~|GPIO|GPIO<br>~~GG~~|GPIO<br>~~GG~~|PLD OUT<br>~~GG~~|PLD IN<br>~~CO~~|PLD IN<br>~~CO~~| |00<br>~~ee ~~<br>~~po~~|10<br> ~~es~~<br>~~po~~|GPIO<br>~~QO~~|GPIO<br>~~Ga~~|GPIO|GPIO<br>~~GG~~|PLD OUT<br>~~GG~~|PLD IN<br>~~GG~~|PLD IN<br>~~CO~~|PLD IN<br>~~CO~~| |00<br>~~po~~|11<br>~~po~~|GPIO|GPIO|GPIO|PLD OUT|PLD OUT|PLD IN|PLD IN|PLD IN| |01<br>~~po~~|00<br>~~po~~|GPIO|PLD OUT|PLD IN|PLD IN|GPIO|GPIO|GPIO|GPIO| |01<br>~~po~~|01<br>~~po~~|GPIO|PLD OUT|PLD IN|PLD IN|GPIO|PLD OUT|PLD IN|PLD IN| |01<br>~~po~~|10<br>~~po~~|GPIO|PLD OUT|PLD IN|PLD IN|PLD OUT|PLD IN|PLD IN|PLD IN| |01<br>~~po~~|11<br>~~po~~|GPIO|GPIO|GPIO|PLD OUT|PLD OUT|PLD IN|PLD IN|PLD IN| |10<br>~~Po~~|00<br>~~Po~~|PLD OUT|PLD IN|PLD IN|PLD IN|GPIO|GPIO|GPIO|GPIO| |10<br>~~po~~<br>~~a~~|01<br>~~po~~<br>~~ee~~|PLD OUT<br>~~QO~~|PLD IN<br>~~(n(n~~|PLD IN<br>~~(n(n~~|PLD IN<br>~~GG~~|GPIO<br>~~GG~~|PLD OUT<br>~~GG~~|PLD IN<br>~~CO~~|PLD IN<br>~~CO~~| |10<br>~~a~~|10<br>~~ee~~|PLD OUT<br>~~QO~~|PLD IN<br>~~(n(n~~|PLD IN<br>~~(n(n~~|PLD IN<br>~~GG~~|PLD OUT<br>~~GG~~|PLD IN<br>~~GG~~|PLD IN<br>~~CO~~|PLD IN<br>~~CO~~| |10<br>~~a~~<br>~~po~~|11<br>~~ee~~<br>~~po~~|GPIO<br>~~QO~~|GPIO<br>~~(n(n~~|GPIO<br>~~(n(n~~|PLD OUT<br>~~GG~~|PLD OUT<br>~~GG~~|PLD IN<br>~~GG~~|PLD IN<br>~~CO~~|PLD IN<br>~~CO~~| _Table 10 – SX1503 PLD Modes Settings (Bank B)_ |**RegPLDModeA**|**RegPLDModeA**|**SX1503 I/Os**|**SX1503 I/Os**|**SX1503 I/Os**|**SX1503 I/Os**|**SX1503 I/Os**|**SX1503 I/Os**|**SX1503 I/Os**|**SX1503 I/Os**| |---|---|---|---|---|---|---|---|---|---| |**5:4**<br>~~a~~|**1:0**<br>~~a~~|**7**|**6**|**5**|**4**|**3**|**2**<br>~~C~~|**1**|**0**| |00<br>~~a~~|00<br>~~a~~|GPIO|GPIO|GPIO|GPIO|GPIO|GPIO<br>~~C~~|GPIO|GPIO| |00<br>~~a~~<br>~~po~~|01<br>~~a~~<br>~~po~~|GPIO|GPIO|GPIO|GPIO|GPIO|PLD OUT<br>~~C~~|PLD IN|PLD IN| |00<br>~~po~~|10<br>~~po~~|GPIO|GPIO|GPIO|GPIO|PLD OUT|PLD IN|PLD IN|PLD IN| |00<br>~~po~~|11<br>~~po~~|GPIO|GPIO|GPIO|PLD OUT|PLD OUT|PLD IN|PLD IN|PLD IN| |01<br>~~po~~|00<br>~~po~~|GPIO|PLD OUT|PLD IN|PLD IN|GPIO|GPIO|GPIO|GPIO| |01<br>~~po~~<br>~~I~~<br>~~po~~|01<br>~~po~~<br>~~ee~~<br>~~po~~|GPIO<br>~~fe~~|PLD OUT<br>~~fe~~|PLD IN<br>~~(GO~~|PLD IN<br>~~(GO~~|GPIO<br>~~(GO~~|PLD OUT<br>~~(GO~~|PLD IN<br>~~(GO~~<br>~~CO~~|PLD IN<br>~~(GO~~<br>~~CO~~| |01<br>~~I~~<br>~~po~~|10<br>~~ee~~<br>~~po~~|GPIO<br>~~fe~~|PLD OUT<br>~~fe~~|PLD IN<br>~~(GO~~|PLD IN<br>~~(GO~~|PLD OUT<br>~~(GO~~|PLD IN<br>~~(GO~~|PLD IN<br>~~(GO~~<br>~~CO~~|PLD IN<br>~~(GO~~<br>~~CO~~| |01<br>~~I~~<br>~~po~~<br>~~I~~|11<br>~~ee~~<br>~~po~~|GPIO<br>~~fe~~|GPIO<br>~~fe ~~|GPIO<br> ~~(GO~~|PLD OUT<br>~~(GO~~|PLD OUT<br>~~(GO~~|PLD IN<br>~~(GO~~|PLD IN<br>~~(GO~~<br>~~CO~~<br>~~CO~~|PLD IN<br>~~(GO~~<br>~~CO~~<br>~~CO~~| |10<br>~~a~~<br>~~I~~<br>~~po~~|00<br>~~a~~<br>~~es~~<br>~~po~~|PLD OUT<br>~~ss~~<br>~~es~~|PLD IN<br>~~ss~~<br>~~Qe~~|PLD IN<br>~~GG~~<br>~~GG~~|PLD IN<br>~~GG~~<br>~~GG~~|GPIO<br>~~GG~~<br>~~GG~~|GPIO<br>~~GG~~<br>~~GG~~|GPIO<br>~~GG~~<br>~~CO~~<br>~~GG~~<br>~~CO~~|GPIO<br>~~GG~~<br>~~CO~~<br>~~GG~~<br>~~CO~~| |10<br>~~I~~<br>~~po~~|01<br>~~es~~<br>~~po~~|PLD OUT<br>~~es~~|PLD IN<br>~~Qe~~|PLD IN<br>~~GG~~|PLD IN<br>~~GG~~|GPIO<br>~~GG~~|PLD OUT<br>~~GG~~|PLD IN<br>~~CO~~<br>~~GG~~<br>~~CO~~|PLD IN<br>~~CO~~<br>~~GG~~<br>~~CO~~| |10<br>~~po~~|10<br>~~es~~<br>~~po~~|PLD OUT<br>~~es~~|PLD IN<br>~~Qe ~~|PLD IN<br> ~~GG~~|PLD IN<br>~~GG~~|PLD OUT<br>~~GG~~|PLD IN<br>~~GG~~|PLD IN<br>~~GG~~<br>~~CO~~|PLD IN<br>~~GG~~<br>~~CO~~| |10<br>~~po~~|11<br>~~po~~|GPIO|GPIO|GPIO|PLD OUT|PLD OUT|PLD IN|PLD IN|PLD IN| _Table 11 – SX1503 PLD Modes Settings (Bank B)_ Rev 11 – 16[th] May 2012 www.semtech.com 18 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ~~LT~~ **WIRELESS & SENSING** ## 4.7.4 Tutorial The generic method described in this paragraph can be applied to any of the SX1501, SX1502 or SX1503. _Example: We want to implement an AND gate between I/O[0] and IO[1] on SX1502_ 1. Identify in the tables above the RegPLDMode setting to be programmed. _What we need corresponds to the second line of the SX1502 PLD Table => RegPLDMode = “xx00xx_ _**01** ”_ 2. Fill corresponding RegPLDTableX with the wanted truth table. - _As mentioned in RegPLDMode description, using PLD 2-to-1 mode on I/0[0-2] implies to fill the truth table located in RegPLDTable0(3:0)_ **==> picture [290 x 65] intentionally omitted <==** **----- Start of picture text -----**<br> I/O[1] I/O[0] I/O[2]<br>0 0 0<br>0 1 0 => RegPLDTable0 = “xxxx 1000 ”<br>1 0 0<br>1 1 1<br>= f<br>**----- End of picture text -----**<br> Rev 11 – 16[th] May 2012 www.semtech.com 19 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ~~LT~~ **WIRELESS & SENSING** ## ~~LT~~ **5 CONFIGURATION REGISTERS** ## **5.1 SX1501 4-channel GPIO** |**Address**|**Name**|**Description**|**Default**<br>*| |---|---|---|---| |0x00|**RegData**|Data register|1111 1111*| |0x01<br>~~Ss~~|**RegDir**<br>~~Ss~~|Direction register|1111 1111| |0x02<br>~~Ss~~|**RegPullUp**<br>~~Ss~~<br>~~_SS.f]1[1]>>}}JS|T—72—}~~|Pull-upregister<br>~~_SS.f]1[1]>>}}JS|T—72—}~~|0000 0000<br>~~_SS.f]1[1]>>}}JS|T—72—}~~| |0x03<br>~~Ss~~<br>~~Ss~~|**RegPullDown**<br>~~Ss~~<br>~~_SS.f]1[1]>>}}JS|T—72—}~~<br>~~Ss~~|Pull-down register<br>~~_SS.f]1[1]>>}}JS|T—72—}~~|0000 0000<br>~~_SS.f]1[1]>>}}JS|T—72—}~~| |0x04<br>~~Ss~~<br>~~Ss~~|**Reserved**<br>~~Ss~~<br>~~Ss~~<br>~~_SS.f]1[1]>>}}JS|T—72—}~~|Unused<br>~~_SS.f]1[1]>>}}JS|T—72—}~~|XXXX XXXX<br>~~_SS.f]1[1]>>}}JS|T—72—}~~| |0x05<br>~~Ss~~<br>~~Ss~~|**RegInterruptMask**<br>~~Ss~~<br>~~_SS.f]1[1]>>}}JS|T—72—}~~<br>~~Ss~~|Interrupt mask register<br>~~_SS.f]1[1]>>}}JS|T—72—}~~|1111 1111<br>~~_SS.f]1[1]>>}}JS|T—72—}~~| |0x06<br>~~Ss~~<br>~~Ss~~|**RegSenseHigh **<br>~~Ss~~<br>~~Ss~~<br>~~_SS.f]1[1]>>}}JS|T—72—}~~|Unused<br>~~_SS.f]1[1]>>}}JS|T—72—}~~|XXXX XXXX<br>~~_SS.f]1[1]>>}}JS|T—72—}~~| |0x07<br>~~Ss~~<br>~~Ss~~|**RegSenseLow**<br>~~Ss~~<br>~~_SS.f]1[1]>>}}JS|T—72—}~~<br>~~Ss~~|Sense register<br>~~_SS.f]1[1]>>}}JS|T—72—}~~|0000 0000<br>~~_SS.f]1[1]>>}}JS|T—72—}~~| |0x08<br>~~Ss~~<br>~~Ss~~|**RegInterruptSource**<br>~~Ss~~<br>~~Ss~~<br>~~_SS.f]1[1]>>}}JS|T—72—}~~|Interrupt source register<br>~~_SS.f]1[1]>>}}JS|T—72—}~~|0000 0000<br>~~_SS.f]1[1]>>}}JS|T—72—}~~| |0x09<br>~~Ss~~|**RegEventStatus**<br>~~Ss~~<br>~~_SS.f]1[1]>>}}JS|T—72—}~~|Event status register<br>~~_SS.f]1[1]>>}}JS|T—72—}~~|0000 0000<br>~~_SS.f]1[1]>>}}JS|T—72—}~~| |0x10<br>~~Ss~~<br>~~————~~|**RegPLDMode**<br>~~Ss~~<br>~~————~~|PLD mode register<br>~~————~~|0000 0000<br>~~————~~| |0x11<br>~~————~~|**RegPLDTable0**<br>~~————~~|PLD truth table 0<br>~~————~~|0000 0000<br>~~————~~| |0x12<br>~~————~~<br>~~Ss~~|**RegPLDTable1**<br>~~————~~<br>~~Ss~~|Unused<br>~~————~~|XXXX XXXX<br>~~————~~| |0x13<br>~~Ss~~|**RegPLDTable2**<br>~~Ss~~<br>~~_SS.f]1[1]>>}}JS|T—72—}~~|PLD truth table 2<br>~~_SS.f]1[1]>>}}JS|T—72—}~~|0000 0000<br>~~_SS.f]1[1]>>}}JS|T—72—}~~| |0x14<br>~~Ss~~|**RegPLDTable3**<br>~~Ss~~<br>~~_SS.f]1[1]>>}}JS|T—72—}~~|Unused<br>~~_SS.f]1[1]>>}}JS|T—72—}~~|XXXX XXXX<br>~~_SS.f]1[1]>>}}JS|T—72—}~~| |0x15<br>~~Ss~~<br>~~=~~|**RegPLDTable4**<br>~~Ss~~<br>~~pSTY}>})™>N——~~|Unused<br>~~pSTY}>})™>N——~~|XXXX XXXX<br>~~pSTY}>})™>N——~~| |0xAB<br>*Bits set as output take “1” as default value.<br>~~=~~|**RegAdvanced**<br>*Bits set as output take “1” as default value.<br>~~pSTY}>})™>N——~~|Advanced settings register<br>~~pSTY}>})™>N——~~|0000 0000<br>~~pSTY}>})™>N——~~| _Table 12 – SX1501 Configuration Registers Overview_ |**Addr**<br>~~pp~~|**Name**<br>~~pp~~|**Default**<br>~~pp~~|**Bits**<br>~~pp~~|**Description**<br>~~pp~~|**Description**<br>~~pp~~| |---|---|---|---|---|---| |0x00<br>~~pp~~<br>~~ee~~|**RegData**<br>~~pp~~<br>~~ee~~|0xFF<br>~~pp~~|7:4<br>~~pp~~|Reserved. Must be set to1(defaultvalue)<br>~~pp~~|| ||||3:0|Write: Data to be output to the output-configured IOs<br>Read: Data seen at the IOs,independent of the direction configured.|| |0x01<br>~~a~~|**RegDir**<br>~~a~~|0xFF|7:4|Reserved. Must be set to1(defaultvalue)|| ||||3:0|Configures direction for each IO.<br>0 : IO is configured as an output<br>1 : IO is configured as an input|| |0x02<br>~~a~~|**RegPullUp**<br>~~a~~|0x00|7:4|Reserved. Must be set to 0 (defaultvalue)|| ||||3:0|Enables the pull-up for each IO<br>0 : Pull-up is disabled<br>1 : Pull-upis enabled|| |0x03<br>~~2~~|**RegPullDown**<br>~~2~~|0x00|7:4|Reserved. Must be set to 0 (defaultvalue)|| ||||3:0|Enables the pull-down for each IO<br>0 : Pull-down is disabled<br>1 : Pull-down is enabled|| |0x04<br>~~2~~|**Reserved**<br>~~2~~|0xXX|7:0|Unused|| |0x05<br>~~2~~|**RegInterruptMask**<br>~~2~~|0xFF<br>~~2~~|7:4<br>~~a~~<br>~~2~~|Reserved. Must be set to1(defaultvalue)<br>~~a~~|| ||||3:0<br>~~2~~|Configures which [input-configured] IO will trigger an interrupt on NINT pin<br>0 : An event on this IO will trigger an interrupt<br>1 : An event on this IO will NOT trigger an interrupt|| |0x06<br>~~2~~|**RegSenseHigh **<br>~~2~~|0xXX<br>~~2~~|7:0<br>~~2~~|Unused|| |0x07<br>~~a~~|**RegSenseLow**<br>~~a~~|0x00<br>~~aSSS~~|7:6<br>~~aSSS~~|Edge sensitivity of I/O[3]<br>~~SSS~~|00 : None<br>01 : Rising<br>10 : Falling<br>11 : Both<br>~~SSS~~<br>~~————~~| ||||5:4<br>~~aSSS~~|Edge sensitivity of I/O[2]<br>~~SSS~~|| ||||3:2<br>~~aSSS~~<br>~~————~~|Edge sensitivity of I/O[1]<br>~~SSS~~<br>~~————~~|| ||||1:0<br>~~aSSS~~<br>~~————~~|Edge sensitivityof I/O[0]<br>~~SSS~~<br>~~————~~|| |0x08<br>~~pp~~|**RegInterruptSource**<br>~~pp~~|0x00<br>~~pp~~|7:4<br>~~————~~<br>~~pp~~|Reserved. Must be set to 0 (defaultvalue)<br>~~————~~<br>~~pp~~|| ||||3:0<br>~~pp~~|Interrupt source (from IOs set in RegInterruptMask)<br>0 : No interrupt has been triggered by this IO<br>1 : An interrupt has been triggered by this IO (an event as configured in relevant<br>RegSense register occured).<br>Writing '1' clears the bit in RegInterruptSource and in RegEventStatus.<br>When all bits are cleared,NINT signalgoes back high.<br>~~pp~~|| |0x09<br>~~pp~~|~~pp~~|0x00<br>~~pp~~|7:4<br>~~pp~~|Reserved. Must be set to 0 (defaultvalue)<br>~~pp~~|| Rev 11 – 16[th] May 2012 www.semtech.com 20 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## ~~Ld~~ **WIRELESS & SENSING** |**Addr**<br>~~||~~|**Name**<br>~~||~~|**Default**<br>~~||~~|**Bits**<br>~~||~~|**Description**<br>~~||~~|**Description**<br>~~||~~| |---|---|---|---|---|---| ||**RegEventStatus**||3:0|Event status of all IOs.<br>0 : No event has occured on this IO<br>1 : An event has occured on this IO (an edge as configured in relevant RegSense<br>register occured).<br>Writing '1' clears the bit in RegEventStatus and in RegInterruptSource if relevant.<br>If the edge sensitivityof the IO is changed,the bit(s)will be cleared automatically|| |0x10|**RegPLDMode**|0x00|7:2|Reserved. Must be set to 0(default value)|| ||||1:0|PLDMode<br>00 : PLD disabled – Normal GPIO mode for I/O[3:0]<br>01 : PLD 2-to-1 mode – I/O[2] is a decode of I/O[1:0] as defined in RegPLDTable0<br>10 : PLD 3-to-1 mode – I/O[3] is a decode of I/O[2:0] as defined in RegPLDTable2<br>11 : Not used|| |0x11<br>~~SSS~~<br>~~a~~|**RegPLDTable0**<br>~~SSS~~<br>~~a Re~~|0x00<br>~~SSS~~<br>~~Re~~|7:4<br>~~a~~<br>~~SSS~~|Reserved. Must be set to 0 (defaultvalue)<br>~~a~~<br>~~SSS~~|| ||||3<br>~~SSS~~|Value to be output on I/O[2]when I/O[1:0]= 11<br>~~SSS~~|Applies only when PLDMode is<br>set to PLD 2-to-1 mode<br>~~SSS~~| ||||2<br>~~SSS~~|Value to be output on I/O[2]when I/O[1:0]= 10<br>~~SSS~~|| ||||1<br>~~SSS~~|Value to be output on I/O[2]when I/O[1:0]=01<br>~~SSS~~|| ||||0<br>~~SSS~~<br>~~es~~|Value to be output on I/O[2]when I/O[1:0]= 00<br>~~SSS~~|| |0x12<br>~~a~~|**RegPLDTable1**<br>~~a Re~~|0xXX<br>~~Re~~|7:0<br>~~es~~|Unused|| |0x13<br>~~a~~|**RegPLDTable2**<br>~~a Re~~|0x00<br>~~Re~~|7<br>~~es~~<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 111|Applies only when PLDMode is<br>set to PLD 3-to-1 mode| ||||6<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 110|| ||||5|Value to be output on I/O[3]when I/O[2:0]= 101|| ||||4<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 100|| ||||3|Value to be output on I/O[3]when I/O[2:0]=011|| ||||2|Value to be output on I/O[3]when I/O[2:0]=010|| ||||1<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]=001|| ||||0<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 000|| |0x14|**RegPLDTable3**|0xXX|7:0|Unused|| |0x15<br>~~Rs~~|**RegPLDTable4**<br>~~Rs~~|0xXX<br>~~Rs~~|7:0<br>~~Rs~~|Unused<br>~~Rs~~|| |0xAB<br>~~0~~|**RegAdvanced**<br>~~ee~~|0x00<br>~~ee~~|7.2<br>~~a~~<br>~~ee~~|Reserved. Must be set to 0(default value)<br>~~ee~~|| ||||1<br>~~a~~<br>~~ee~~|Boost Mode (Cf. § 2.2.1)<br>0: OFF<br>1: ON<br>~~ee~~|| ||||0<br>~~a~~<br>~~ee~~|Reserved. Must be set to 0(default value)<br>~~ee~~|| _Table 13 – SX1501 Configuration Register_ s _Description_ |**Address**<br>~~0~~|**Name**<br>~~0~~<br>~~es~~|**Description**<br>~~0~~<br>~~|~~|**Default**<br>*<br>~~|~~| |---|---|---|---| |0x00<br>~~a~~|**RegData**<br>~~a~~<br>~~es~~|Data register<br>~~a~~|1111 1111*| |0x01<br>~~a~~|**RegDir**<br>~~es~~<br>~~es~~|Direction register|1111 1111| |0x02<br>~~a~~<br>~~a~~|**RegPullUp**<br>~~es~~<br>~~es~~|Pull-upregister|0000 0000| |0x03<br>~~a~~<br>~~a~~<br>~~a~~|**RegPullDown**<br>~~es~~<br>~~es~~<br>~~es~~|Pull-down register|0000 0000| |0x04<br>~~a~~<br>~~a~~<br>~~a~~|**Reserved**<br>~~es~~<br>~~es~~<br>~~es~~|Unused|XXXX XXXX| |0x05<br>~~a~~<br>~~a~~<br>~~a~~|**RegInterruptMask**<br>~~es~~<br>~~es~~<br>~~es~~|Interrupt mask register|1111 1111| |0x06<br>~~a~~<br>~~a~~<br>~~a~~|**RegSenseHigh **<br>~~es~~<br>~~es~~<br>~~es~~|Sense register for I/O[7:4]|0000 0000| |0x07<br>~~a~~<br>~~a~~<br>~~a~~|**RegSenseLow**<br>~~es~~<br>~~es~~<br>~~es~~|Sense register for I/O[3:0]|0000 0000| |0x08<br>~~a~~<br>~~a~~<br>~~a~~|**RegInterruptSource**<br>~~es~~<br>~~es~~<br>~~es~~|Interrupt source register|0000 0000| |0x09<br>~~a~~<br>~~a~~<br>~~a~~|**RegEventStatus**<br>~~es~~<br>~~es~~<br>~~es~~|Event status register|0000 0000| |0x10<br>~~a~~<br>~~a~~<br>~~a~~|**RegPLDMode**<br>~~es~~<br>~~es~~<br>~~es~~|PLD mode register|0000 0000| |0x11<br>~~a~~<br>~~a~~<br>~~a~~|**RegPLDTable0**<br>~~es~~<br>~~es~~<br>~~es~~|PLD truth table 0|0000 0000| |0x12<br>~~a~~<br>~~a~~<br>~~a~~|**RegPLDTable1**<br>~~es~~<br>~~es~~<br>~~es~~|PLD truth table 1|0000 0000| |0x13<br>~~a~~<br>~~a~~|**RegPLDTable2**<br>~~es~~<br>~~es~~|PLD truth table 2|0000 0000| |0x14<br>~~a~~<br>~~a~~|**RegPLDTable3**<br>~~es~~<br>~~es~~|PLD truth table 3|0000 0000| |0x15<br>~~a~~<br>~~a~~|**RegPLDTable4**<br>~~es~~<br>~~es~~|PLD truth table 4|0000 0000| |0xAB<br>*Bits set as output take “1” as default value.<br>~~a~~<br>~~a~~|**RegAdvanced**<br>*Bits set as output take “1” as default value.<br>~~es~~<br>~~es~~|Advanced settings register|0000 0000| _Table 14 – SX1502 Configuration Registers Overview_ |**Addr**|**Name**|**Default**|**Bits**|**Description**| |---|---|---|---|---| |0x00|**RegData**|0xFF|7:0|Write: Data to be output to the output-configured IOs<br>Read: Data seen at the IOs,independent of the direction configured.| |0x01|**RegDir**|0xFF|7:0|Configures direction for each IO.<br>0 : IO is configured as an output<br>1 : IO is configured as an input| Rev 11 – 16[th] May 2012 www.semtech.com 21 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## **WIRELESS & SENSING** |**Addr**<br>~~|~~|**Name**<br>~~|~~|**Default**<br>~~|~~|**Bits**<br>~~|~~|**Description**<br>~~|~~|**Description**<br>~~|~~| |---|---|---|---|---|---| |0x02<br>~~1~~<br>~~re~~|**RegPullUp**<br>~~1~~<br>~~re~~|0x00<br>~~1~~<br>~~ee~~|7:0<br>~~1~~<br>~~ee~~|Enables the pull-up for each IO<br>0 : Pull-up is disabled<br>1 : Pull-upis enabled<br>~~1~~<br>~~eee~~|| |0x03<br>~~re~~|**RegPullDown**<br>~~re~~|0x00<br>~~ee~~|7:0<br>~~ee~~|Enables the pull-down for each IO<br>0 : Pull-down is disabled<br>1 : Pull-down is enabled<br>~~eee~~|| |0x04<br>~~re~~|**Reserved**<br>~~re ~~|0xXX<br> ~~ee~~|7:0<br>~~ee~~|Unused<br>~~eee~~|| |0x05<br>~~2~~|**RegInterruptMask**|0xFF|7:0|Configures which [input-configured] IO will trigger an interrupt on NINT pin<br>0 : An event on this IO will trigger an interrupt<br>1 : An event on this IO will NOT trigger an interrupt|| |0x06|**RegSenseHigh**|0x00|7:6|Edge sensitivity of I/O[7]|00 : None<br>01 : Rising<br>10 : Falling<br>11 : Both<br>~~Pd~~| ||||5:4<br>~~a~~|Edge sensitivity of I/O[6]|| ||||3:2<br>~~a~~|Edge sensitivity of I/O[5]<br>|| ||||1:0<br>~~Pd~~|Edge sensitivityof I/O[4]<br>~~Pd~~|| |0x07|**RegSenseLow**|0x00|7:6<br>~~a~~|Edge sensitivity of I/O[3]|00 : None<br>01 : Rising<br>10 : Falling<br>11 : Both| ||||5:4<br>~~a~~|Edge sensitivity of I/O[2]|| ||||3:2<br>~~a~~|Edge sensitivity of I/O[1]|| ||||1:0|Edge sensitivityof I/O[0]|| |0x08|**RegInterruptSource**|0x00|7:0|Interrupt source (from IOs set in RegInterruptMask)<br>0 : No interrupt has been triggered by this IO<br>1 : An interrupt has been triggered by this IO (an event as configured in relevant<br>RegSense register occured).<br>Writing '1' clears the bit in RegInterruptSource and in RegEventStatus<br>When all bits are cleared,NINT signalgoes back high.|| |0x09|**RegEventStatus**|0x00|7:0|Event status of all IOs.<br>0 : No event has occured on this IO<br>1 : An event has occured on this IO (an edge as configured in relevant RegSense<br>register occured).<br>Writing '1' clears the bit in RegEventStatus and in RegInterruptSource if relevant.<br>If the edge sensitivityof the IO is changed,the bit(s)will be cleared automatically|| |0x10|**RegPLDMode**|0x00|7:6|Reserved. Must be set to 0(default value)|| ||||5:4<br>~~PP~~|PLDModeHigh (applies to I/O[7:4])<br>00 : PLD disabled – Normal GPIO mode for I/O[7:4]<br>01 : PLD 2-to-1 mode – I/O[6] is a decode of I/O[5:4] as defined in RegPLDTable0<br>10 : PLD 3-to-1 mode – I/O[7] is a decode of I/O[6:4] as defined in RegPLDTable1<br>11 : Reserved<br>~~PP~~|| ||||3:2|Reserved. Must be set to 0(default value)|| ||||1:0<br>~~PP~~|PLDModeLow (applies to I/O[3:0])<br>00 : PLD disabled – Normal GPIO mode for I/O[3:0]<br>01 : PLD 2-to-1 mode – I/O[2] is a decode of I/O[1:0] as defined in RegPLDTable0<br>10 : PLD 3-to-1 mode – I/O[3] is a decode of I/O[2:0] as defined in RegPLDTable2<br>11 : PLD 3-to-2 mode – I/O[4:3] are decodes of I/O[2:0] as defined in RegPLDTable3<br>and RegPLDTable4<br>~~PP~~|| |0x11|**RegPLDTable0**|0x00|7<br>~~a~~|Value to be output on I/O[6]when I/O[5:4]= 11|Applies only when<br>PLDModeHigh is set to PLD 2-<br>to-1 mode| ||||6<br>~~a ee~~|Value to be output on I/O[6]when I/O[5:4]= 10<br>~~ee~~|| ||||5<br>~~a~~|Value to be output on I/O[6]when I/O[5:4]= 01|| ||||4<br>~~a~~|Value to be output on I/O[6]when I/O[5:4]= 00<br>~~ee~~|| ||||3<br>~~a~~|Value to be output on I/O[2]when I/O[1:0]= 11|Applies only when<br>PLDModeLow is set to PLD 2-<br>to-1 mode| ||||2<br>~~a~~|Value to be output on I/O[2]when I/O[1:0]= 10<br>~~ee~~|| ||||1<br>~~a~~|Value to be output on I/O[2]when I/O[1:0]= 01|| ||||0<br>~~a~~|Value to be output on I/O[2]when I/O[1:0]= 00|| |0x12|**RegPLDTable1**|0x00|7<br>~~a~~|Value to be output on I/O[7]when I/O[6:4]= 111|Applies only when<br>PLDModeHigh is set to PLD 3-<br>to-1 mode| ||||6<br>~~a~~|Value to be output on I/O[7]when I/O[6:4]= 110<br>~~ee~~|| ||||5<br>~~a~~|Value to be output on I/O[7]when I/O[6:4]= 101|| ||||4<br>~~a~~|Value to be output on I/O[7]when I/O[6:4]= 100<br>~~ee~~|| ||||3<br>~~a~~|Value to be output on I/O[7]when I/O[6:4]= 011|| ||||2<br>~~a~~|Value to be output on I/O[7]when I/O[6:4]= 010<br>~~ee~~|| ||||1<br>~~a~~|Value to be output on I/O[7]when I/O[6:4]= 001|| ||||0<br>~~a~~|Value to be output on I/O[7]when I/O[6:4]= 000|| |0x13|**RegPLDTable2**|0x00|7<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 111|Applies only when<br>PLDModeLow is set to PLD 3-<br>to-1 mode| ||||6<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 110<br>~~ee~~|| ||||5<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 101|| ||||4<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 100<br>~~ee~~|| ||||3<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 011|| ||||2<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 010<br>~~ee~~|| ||||1<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 001|| Rev 11 – 16[th] May 2012 www.semtech.com 22 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## **WIRELESS & SENSING** **==> picture [531 x 245] intentionally omitted <==** **----- Start of picture text -----**<br> |||||||| |---|---|---|---|---|---|---| |a|Addr|Name|Default|Bits|Description| |0|Value to be output on I/O[3] when I/O[2:0] = 000| |||7|PO|Value to be output on I/O[4] when I/O[2:0] = 111| |a|6|Value to be output on I/O[4] when I/O[2:0] = 110| |a|5|Value to be output on I/O[4] when I/O[2:0] = 101| |0x14|RegPLDTable3|0x00|a|4|Value to be output on I/O[4] when I/O[2:0] = 100|Applies only when PLDModeLow is set to PLD 3-| |a|3|Value to be output on I/O[4] when I/O[2:0] = 011|to-2 mode| |a|2|Value to be output on I/O[4] when I/O[2:0] = 010| |a|1|Value to be output on I/O[4] when I/O[2:0] = 001| |a|0|ee|Value to be output on I/O[4] when I/O[2:0] = 000| |a|7|Value to be output on I/O[3] when I/O[2:0] = 111| |a|6|Value to be output on I/O[3] when I/O[2:0] = 110| |a|5|Value to be output on I/O[3] when I/O[2:0] = 101| |0x15|RegPLDTable4|0x00|a|4|Value to be output on I/O[3] when I/O[2:0] = 100|Applies only when PLDModeLow is set to PLD 3-| |a|3|Value to be output on I/O[3] when I/O[2:0] = 011|to-2 mode| |a|2|Value to be output on I/O[3] when I/O[2:0] = 010| |a|1|Value to be output on I/O[3] when I/O[2:0] = 001| |a|0|ee|Value to be output on I/O[3] when I/O[2:0] = 000| |7:2|Reserved. Must be set to 0 (default value)| |Boost Mode (Cf. §2.2.1)| |0xAB|RegAdvanced|0x00|1|0: OFF| |1: ON| |Pe|0|Reserved. Must be set to 0 (default value)| **----- End of picture text -----**<br> _Table 15 – SX1502 Configuration Registers Description_ **==> picture [483 x 375] intentionally omitted <==** **----- Start of picture text -----**<br> |||||| |---|---|---|---|---| |5.3|SX1503 16-channel GPIO| |Address|Name|Description|Default| |||||| |0x00|RegDataB|Data register for Bank B I/O[15:8]|1111 1111|[* ]| |a|es| |0x01|RegDataA|Data register for Bank A I/O[7:0]|1111 1111|[*]| |a|es| |0x02|RegDirB|Direction register for Bank B I/O[15:8]|1111 1111| |a|es| |0x03|RegDirA|Direction register for Bank A I/O[7:0]|1111 1111| |a|es| |0x04|RegPullUpB|Pull-up register for Bank B I/O[15:8]|0000 0000| |a|es| |0x05|RegPullUpA|Pull-up register for Bank A I/O[7:0]|0000 0000| |a|es| |0x06|RegPullDownB|Pull-down register for Bank B I/O[15:8]|0000 0000| |a|es| |0x07|RegPullDownA|Pull-down register for Bank A I/O[7:0]|0000 0000| |a|es| |0x08|RegInterruptMaskB|Interrupt mask register for Bank B I/O[15:8]|1111 1111| |a|es| |0x09|RegInterruptMaskA|Interrupt mask register for Bank A I/O[7:0]|1111 1111| |a|es| |0x0A|RegSenseHighB|Sense register for I/O[15:12]|0000 0000| |a|es| |0x0B|RegSenseHighA|Sense register for I/O[7:4]|0000 0000| |a|es| |0x0C|RegSenseLowB|Sense register for I/O[11:8]|0000 0000| |a|es| |0x0D|RegSenseLowA|Sense register for I/O[3:0]|0000 0000| |a|es| |0x0E|RegInterruptSourceB|Interrupt source register for Bank B I/O[15:8]|0000 0000| |a|es| |0x0F|RegInterruptSourceA|Interrupt source register for Bank A I/O[7:0]|0000 0000| |a|es| |0x10|RegEventStatusB|Event status register for Bank B I/O[15:8]|0000 0000| |a|es| |0x11|RegEventStatusA|Event status register for Bank A I/O[7:0]|0000 0000| |a|es| |0x20|RegPLDModeB|PLD mode register for Bank B I/O[15:8]|0000 0000| |a|es| |0x21|RegPLDModeA|PLD mode register for Bank A I/O[7:0]|0000 0000| |a|es| |0x22|RegPLDTable0B|PLD truth table 0 for Bank B I/O[15:8]|0000 0000| |a|es| |0x23|RegPLDTable0A|PLD truth table 0 for Bank A I/O[7:0]|0000 0000| |a|es| |0x24|RegPLDTable1B|PLD truth table 1 for Bank B I/O[15:8]|0000 0000| |a|es| |0x25|RegPLDTable1A|PLD truth table 1 for Bank A I/O[7:0]|0000 0000| |a|es| |0x26|RegPLDTable2B|PLD truth table 2 for Bank B I/O[15:8]|0000 0000| |a|es| |0x27|RegPLDTable2A|PLD truth table 2 for Bank A I/O[7:0]|0000 0000| |a|es| |0x28|RegPLDTable3B|PLD truth table 3 for Bank B I/O[15:8]|0000 0000| |a|es| |0x29|RegPLDTable3A|PLD truth table 3 for Bank A I/O[7:0]|0000 0000| |a|es| |0x2A|RegPLDTable4B|PLD truth table 4 for Bank B I/O[15:8]|0000 0000| |a|es| |0x2B|RegPLDTable4A|PLD truth table 4 for Bank A I/O[7:0]|0000 0000| |a|es| |0xAD|RegAdvanced|Advanced settings register|0000 0000| |*Bits set as output take “1” as default value.|a|es| **----- End of picture text -----**<br> _Table 16 – SX1503 Configuration Registers Overview_ **Addr Name Default Bits Description** Rev 11 – 16[th] May 2012 www.semtech.com 23 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## ~~Ce~~ **WIRELESS & SENSING** |**Addr**<br>~~TTT~~<br>~~a~~|**Name**<br>~~TTT~~<br>~~a~~|**Default**<br>~~TTT~~<br>~~ae~~|**Bits**<br>~~TTT~~<br>~~ee~~|**Description**<br>~~TTT~~|**Description**<br>~~TTT~~| |---|---|---|---|---|---| |0x00<br>~~a~~<br>~~a~~|**RegDataB**<br>~~a~~<br>~~ee~~|0xFF<br>~~ae~~<br>~~ee~~|7:0<br>~~ee~~<br>~~ee~~|Write: Data to be output to the output-configured IOs<br>Read: Data seen at the IOs,independent of the direction configured.|| |0x01<br>~~a~~<br>~~a~~<br>~~|~~|**RegDataA**<br>~~a~~<br>~~ee~~|0xFF<br>~~ae ~~<br>~~ee~~<br>~~EI~~|7:0<br> ~~ee~~<br>~~ee~~|Write: Data to be output to the output-configured IOs<br>Read: Data seen at the IOs,independent of the direction configured.|| |0x02<br>~~a~~<br>~~|~~|**RegDirB**<br>~~ee~~|0xFF<br>~~ee ~~<br>~~EI~~|7:0<br> ~~ee~~|Configures direction for each IO.<br>0 : IO is configured as an output<br>1 : IO is configured as an input|| |0x03<br>~~|~~<br>~~|~~|**RegDirA**<br>i|0xFF<br>~~EI~~<br>~~EDTA~~<br>~~EI~~|7:0<br>~~EDTA~~|Configures direction for each IO.<br>0 : IO is configured as an output<br>1 : IO is configured as an input<br>~~EDTA~~|| |0x04<br>~~|~~|**RegPullUpB**|0x00<br>~~EI~~|7:0|Enables the pull-up for each IO<br>0 : Pull-up is disabled<br>1 : Pull-upis enabled|| |0x05<br>~~|~~<br>~~|~~|**RegPullUpA**<br>i|0x00<br>~~EI~~<br>~~EDTA~~<br>~~EI~~|7:0<br>~~EDTA~~|Enables the pull-up for each IO<br>0 : Pull-up is disabled<br>1 : Pull-upis enabled<br>~~EDTA~~|| |0x06<br>~~|~~|**RegPullDownB**|0x00<br>~~EI~~|7:0|Enables the pull-down for each IO<br>0 : Pull-down is disabled<br>1 : Pull-down is enabled|| |0x07<br>~~|~~<br>~~pf~~|**RegPullDownA**<br>i<br>~~pf~~|0x00<br>~~EI~~<br>~~EDTA~~<br>~~EI~~<br>|7:0<br>~~EDTA~~<br>|Enables the pull-down for each IO<br>0 : Pull-down is disabled<br>1 : Pull-down is enabled<br>~~EDTA~~<br>|| |0x08<br>~~pf~~|**RegInterruptMaskB**<br>~~pf~~|0xFF<br>~~EI~~<br>|7:0<br>|Configures which [input-configured] IO will trigger an interrupt on NINT pin<br>0 : An event on this IO will trigger an interrupt<br>1 : An event on this IO will NOT trigger an interrupt<br>|| |0x09<br>~~pf~~|**RegInterruptMaskA**<br>~~pf~~|0xFF<br>~~EI~~<br>|7:0<br>|Configures which [input-configured] IO will trigger an interrupt on NINT pin<br>0 : An event on this IO will trigger an interrupt<br>1 : An event on this IO will NOT trigger an interrupt<br>|| |0x0A<br>|**RegSenseHighB**<br>|0x00<br>|7:6<br>|Edge sensitivityof I/O[15]<br>|00 : None<br>01 : Rising<br>10 : Falling<br>11 : Both<br>| ||||5:4<br>|Edge sensitivityof I/O[14]<br>|| ||||3:2<br>|Edge sensitivityof I/O[13]<br>|| ||||1:0<br>|Edge sensitivityof I/O[12]<br>|| |0x0B<br>~~Zee~~|**RegSenseHighA**<br>~~Zee~~|0x00<br>~~Zee~~|7:6<br>~~Zee~~|Edge sensitivityof I/O[7]<br>~~Zee~~|00 : None<br>01 : Rising<br>10 : Falling<br>11 : Both<br>~~Zee~~| ||||5:4<br>~~Zee~~|Edge sensitivityof I/O[6]<br>~~Zee~~|| ||||3:2<br>~~Zee~~<br>~~——_—_—_———~~|Edge sensitivityof I/O[5]<br>~~Zee~~<br>~~——_—_—_———~~|| ||||1:0<br>~~Zee~~<br>~~——_—_—_———~~|Edge sensitivityof I/O[4]<br>~~Zee~~<br>~~——_—_—_———~~|| |0x0C|**RegSenseLowB**|0x00|7:6<br>~~——_—_—_———~~|Edge sensitivityof I/O[11]<br>~~——_—_—_———~~|00 : None<br>01 : Rising<br>10 : Falling<br>11 : Both| ||||5:4|Edge sensitivityof I/O[10]|| ||||3:2|Edge sensitivityof I/O[9]|| ||||1:0|Edge sensitivityof I/O[8]|| |0x0D<br>~~i=~~<br>~~Th.~~|**RegSenseLowA**<br>~~i=~~<br>~~Th.~~|0x00<br>~~i=~~<br>~~Th.~~|7:6<br>~~i=~~|Edge sensitivityof I/O[3]<br>~~i=~~|00 : None<br>01 : Rising<br>10 : Falling<br>11 : Both<br>~~i=~~<br>~~Th.~~| ||||5:4<br>~~i=~~|Edge sensitivityof I/O[2]<br>~~i=~~|| ||||3:2<br>~~i=~~<br>~~Th.~~|Edge sensitivityof I/O[1]<br>~~i=~~<br>~~Th.~~|| ||||1:0<br>~~i=~~<br>~~Th.~~|Edge sensitivityof I/O[0]<br>~~i=~~<br>~~Th.~~|| |0x0E<br>~~Th.~~|**RegInterruptSourceB**<br>~~Th.~~|0x00<br>~~Th.~~|7:0<br>~~Th.~~|Interrupt source (from IOs set in RegInterruptMaskB)<br>0 : No interrupt has been triggered by this IO<br>1 : An interrupt has been triggered by this IO (an event as configured in relevant<br>RegSense register occured).<br>Writing '1' clears the bit in RegInterruptSourceB and in RegEventStatusB<br>When all bits of both RegInterruptSourceA/B are cleared,NINT signalgoes back high.<br>~~Th.~~|| |0x0F|**RegInterruptSourceA**|0x00|7:0|Interrupt source (from IOs set in RegInterruptMaskA)<br>0 : No interrupt has been triggered by this IO<br>1 : An interrupt has been triggered by this IO (an event as configured in relevant<br>RegSense register occured).<br>Writing '1' clears the bit in RegInterruptSourceA and in RegEventStatusA<br>When all bits of both RegInterruptSourceA/B are cleared,NINT signalgoes back high.|| |0x10|**RegEventStatusB**|0x00|7:0|Event status of all IOs.<br>0 : No event has occured on this IO<br>1 : An event has occured on this IO (an edge as configured in relevant RegSense<br>register occured).<br>Writing '1' clears the bit in RegEventStatusB and in RegInterruptSourceB if relevant.<br>If the edge sensitivityof the IO is changed,the bit(s)will be cleared automatically|| Rev 11 – 16[th] May 2012 www.semtech.com 24 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## **WIRELESS & SENSING** |**Addr**|**Name**|**Default**|**Bits**|**Description**|**Description**| |---|---|---|---|---|---| |0x11|**RegEventStatusA**|0x00|7:0|Event status of all IOs.<br>0 : No event has occured on this IO<br>1 : An event has occured on this IO (an edge as configured in relevant RegSense<br>register occured).<br>Writing '1' clears the bit in RegEventStatusA and in RegInterruptSourceA if relevant.<br>If the edge sensitivityof the IO is changed,the bit(s)will be cleared automatically|| |0x20|**RegPLDModeB**|0x00|7:6|Reserved. Must be set to 0(default value)|| ||||5:4<br>~~PP~~|PLDModeHighB (applies to I/O[15:12])<br>00 : PLD disabled – Normal GPIO mode for I/O[15:12]<br>01 : PLD 2-to-1 mode – I/O[14] is a decode of I/O[13:12] as defined in RegPLDTable0B<br>10 : PLD 3-to-1 mode – I/O[15] is a decode of I/O[14:12] as defined in RegPLDTable1B<br>11 : Reserved<br>~~PP~~|| ||||3:2|Reserved. Must be set to 0(default value)|| ||||1:0<br>~~PP~~|PLDModeLowB (applies to I/O[11:8])<br>00 : PLD disabled – Normal GPIO mode for I/O[11:8]<br>01 : PLD 2-to-1 mode – I/O[10] is a decode of I/O[9:8] as defined in RegPLDTable0B<br>10 : PLD 3-to-1 mode – I/O[11] is a decode of I/O[10:8] as defined in RegPLDTable2B<br>11 : PLD 3-to-2 mode – I/O[12:11] are decodes of I/O[10:8] as defined in<br>RegPLDTable3B and RegPLDTable4B<br>~~PP~~|| |0x21|**RegPLDModeA**|0x00|7:6|Reserved. Must be set to 0(default value)|| ||||5:4<br>~~PP~~|PLDModeHighA (applies to I/O[7:4])<br>00 : PLD disabled – Normal GPIO mode for I/O[7:4]<br>01 : PLD 2-to-1 mode – I/O[6] is a decode of I/O[5:4] as defined in RegPLDTable0A<br>10 : PLD 3-to-1 mode – I/O[7] is a decode of I/O[6:4] as defined in RegPLDTable1A<br>11 : Reserved<br>~~PP~~|| ||||3:2|Reserved. Must be set to 0(default value)|| ||||1:0<br>~~PP~~|PLDModeLowA (applies to I/O[3:0])<br>00 : PLD disabled – Normal GPIO mode for I/O[3:0]<br>01 : PLD 2-to-1 mode – I/O[2] is a decode of I/O[1:0] as defined in RegPLDTable0A<br>10 : PLD 3-to-1 mode – I/O[3] is a decode of I/O[2:0] as defined in RegPLDTable2A<br>11 : PLD 3-to-2 mode – I/O[4:3] are decodes of I/O[2:0] as defined in RegPLDTable3A<br>and RegPLDTable4A<br>~~PP~~|| |0x22|**RegPLDTable0B**|0x00|7<br>~~a~~|Value to be output on I/O[14]when I/O[13:12]= 11|Applies only when<br>PLDModeHighB is set to PLD<br>2-to-1 mode| ||||6<br>~~a~~|Value to be output on I/O[14]when I/O[13:12]= 10|| ||||5<br>~~a~~|Value to be output on I/O[14]when I/O[13:12]= 01<br>~~ee~~|| ||||4<br>~~a~~|Value to be output on I/O[14]when I/O[13:12]= 00|| ||||3<br>~~a ee~~|Value to be output on I/O[10]when I/O[9:8]= 11<br>~~ee~~|Applies only when<br>PLDModeLowB is set to PLD<br>2-to-1 mode| ||||2<br>~~a~~|Value to be output on I/O[10]when I/O[9:8]= 10|| ||||1<br>~~a~~|Value to be output on I/O[10]when I/O[9:8]= 01<br>~~ee~~|| ||||0<br>~~a ee~~|Value to be output on I/O[10]when I/O[9:8]= 00<br>~~ee~~|| |0x23|**RegPLDTable0A**|0x00|7<br>~~a~~|Value to be output on I/O[6]when I/O[5:4]= 11|Applies only when<br>PLDModeHighA is set to PLD<br>2-to-1 mode| ||||6<br>~~a~~|Value to be output on I/O[6]when I/O[5:4]= 10|| ||||5<br>~~a~~|Value to be output on I/O[6]when I/O[5:4]= 01<br>~~ee~~|| ||||4<br>~~a~~|Value to be output on I/O[6]when I/O[5:4]= 00|| ||||3<br>~~a ee~~|Value to be output on I/O[2]when I/O[1:0]= 11<br>~~ee~~|Applies only when<br>PLDModeLowA is set to PLD<br>2-to-1 mode| ||||2<br>~~a~~|Value to be output on I/O[2]when I/O[1:0]= 10|| ||||1<br>~~a~~|Value to be output on I/O[2]when I/O[1:0]= 01<br>~~ee~~|| ||||0<br>~~a ee~~|Value to be output on I/O[2]when I/O[1:0]= 00<br>~~ee~~|| |0x24|**RegPLDTable1B**|0x00|7<br>~~a~~|Value to be output on I/O[15]when I/O[14:12]= 111|Applies only when<br>PLDModeHighB is set to PLD<br>3-to-1 mode| ||||6<br>~~a~~|Value to be output on I/O[15]when I/O[14:12]= 110|| ||||5<br>~~a~~|Value to be output on I/O[15]when I/O[14:12]= 101<br>~~ee~~|| ||||4<br>~~a~~|Value to be output on I/O[15]when I/O[14:12]= 100|| ||||3<br>~~a~~|Value to be output on I/O[15]when I/O[14:12]= 011<br>~~ee~~|| ||||2<br>~~a~~|Value to be output on I/O[15]when I/O[14:12]= 010|| ||||1<br>~~a~~|Value to be output on I/O[15]when I/O[14:12]= 001<br>~~ee~~|| ||||0<br>~~a ee~~|Value to be output on I/O[15]when I/O[14:12]= 000<br>~~ee~~|| |0x25|**RegPLDTable1A**|0x00|7<br>~~a~~|Value to be output on I/O[7]when I/O[6:4]= 111|Applies only when<br>PLDModeHighA is set to PLD<br>3-to-1 mode| ||||6<br>~~a~~|Value to be output on I/O[7]when I/O[6:4]= 110|| ||||5<br>~~a~~|Value to be output on I/O[7]when I/O[6:4]= 101<br>~~ee~~|| ||||4<br>~~a~~|Value to be output on I/O[7]when I/O[6:4]= 100|| ||||3<br>~~a~~|Value to be output on I/O[7]when I/O[6:4]= 011<br>~~ee~~|| ||||2<br>~~a~~|Value to be output on I/O[7]when I/O[6:4]= 010|| ||||1<br>~~a~~|Value to be output on I/O[7]when I/O[6:4]= 001<br>~~ee~~|| ||||0|Value to be output on I/O[7]when I/O[6:4]= 000|| |0x26|**RegPLDTable2B**|0x00|7<br>~~a~~|Value to be output on I/O[11]when I/O[10:8]= 111|Applies only when<br>PLDModeLowB is set to PLD| ||||6<br>~~a~~|Value to be output on I/O[11]when I/O[10:8]= 110|| Rev 11 – 16[th] May 2012 www.semtech.com 25 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## **WIRELESS & SENSING** |**Addr**<br>~~A~~|**Name**<br>~~a~~<br>~~0~~|**Default**<br>~~8~~|**Bits**<br>~~8~~|**Description**|**Description**| |---|---|---|---|---|---| |~~A ~~|~~a~~<br>~~0 ~~|~~8~~|5<br>~~8a~~|Value to be output on I/O[11]when I/O[10:8]= 101|3-to-1 mode| ||||4<br>~~a~~|Value to be output on I/O[11]when I/O[10:8]= 100<br>~~ee~~|| ||||3<br>~~a~~|Value to be output on I/O[11]when I/O[10:8]= 011|| ||||2<br>~~a~~|Value to be output on I/O[11]when I/O[10:8]= 010<br>~~ee~~|| ||||1<br>~~a~~|Value to be output on I/O[11]when I/O[10:8]= 001|| ||||0<br>~~a~~|Value to be output on I/O[11]when I/O[10:8]= 000|| |0x27|**RegPLDTable2A**|0x00|7<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 111|Applies only when<br>PLDModeLowA is set to PLD<br>3-to-1 mode| ||||6<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 110<br>~~ee~~|| ||||5<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 101|| ||||4<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 100<br>~~ee~~|| ||||3<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 011|| ||||2<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 010<br>~~ee~~|| ||||1<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 001|| ||||0<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 000|| |0x28|**RegPLDTable3B**|0x00|7<br>~~a~~|Value to be output on I/O[11]when I/O[10:8]= 111|Applies only when<br>PLDModeLowB is set to PLD<br>3-to-2 mode| ||||6<br>~~a~~|Value to be output on I/O[11]when I/O[10:8]= 110<br>~~ee~~|| ||||5<br>~~a~~|Value to be output on I/O[11]when I/O[10:8]= 101|| ||||4<br>~~a~~|Value to be output on I/O[11]when I/O[10:8]= 100<br>~~ee~~|| ||||3<br>~~a~~|Value to be output on I/O[11]when I/O[10:8]= 011|| ||||2<br>~~a~~|Value to be output on I/O[11]when I/O[10:8]= 010<br>~~ee~~|| ||||1<br>~~a~~|Value to be output on I/O[11]when I/O[10:8]= 001|| ||||0<br>~~a~~|Value to be output on I/O[11]when I/O[10:8]= 000|| |0x29|**RegPLDTable3A**|0x00|7<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 111|Applies only when<br>PLDModeLowA is set to PLD<br>3-to-2 mode| ||||6<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 110<br>~~ee~~|| ||||5<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 101|| ||||4<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 100<br>~~ee~~|| ||||3<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 011|| ||||2<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 010<br>~~ee~~|| ||||1<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 001|| ||||0<br>~~a~~|Value to be output on I/O[3]when I/O[2:0]= 000|| |0x2A|**RegPLDTable4B**|0x00|7<br>~~a~~|Value to be output on I/O[12]when I/O[10:8]= 111|Applies only when<br>PLDModeLowB is set to PLD<br>3-to-2 mode| ||||6<br>~~a~~|Value to be output on I/O[12]when I/O[10:8]= 110<br>~~ee~~|| ||||5<br>~~a~~|Value to be output on I/O[12]when I/O[10:8]= 101|| ||||4<br>~~a~~|Value to be output on I/O[12]when I/O[10:8]= 100<br>~~ee~~|| ||||3<br>~~a~~|Value to be output on I/O[12]when I/O[10:8]= 011|| ||||2<br>~~a~~|Value to be output on I/O[12]when I/O[10:8]= 010<br>~~ee~~|| ||||1<br>~~a~~|Value to be output on I/O[12]when I/O[10:8]= 001|| ||||0<br>~~a~~|Value to be output on I/O[12]when I/O[10:8]= 000|| |0x2B|**RegPLDTable4A**|0x00|7<br>~~a~~|Value to be output on I/O[4]when I/O[2:0]= 111|Applies only when<br>PLDModeLowA is set to PLD<br>3-to-2 mode| ||||6<br>~~a~~|Value to be output on I/O[4]when I/O[2:0]= 110<br>~~ee~~|| ||||5<br>~~a~~|Value to be output on I/O[4]when I/O[2:0]= 101|| ||||4<br>~~a~~|Value to be output on I/O[4]when I/O[2:0]= 100<br>~~ee~~|| ||||3<br>~~a~~|Value to be output on I/O[4]when I/O[2:0]= 011|| ||||2<br>~~a~~|Value to be output on I/O[4]when I/O[2:0]= 010<br>~~ee~~|| ||||1<br>~~a~~|Value to be output on I/O[4]when I/O[2:0]= 001|| ||||0<br>~~a~~|Value to be output on I/O[4]when I/O[2:0]= 000|| |0xAD|**RegAdvanced**|0x00|7:3|Reserved. Must be set to 0(default value)|| ||||2|Autoclear NINT on RegData read (Cf. § 4.6)<br>0: OFF.RegInterruptSource must be manually cleared directly or via RegEventStatus<br>1: ON.RegInterruptSource is automaticallycleared when RegDataB or RegDataA is read|| ||||1|Boost Mode (Cf. § 2.2.1)<br>0: OFF<br>1: ON|| ||||0<br>~~a~~|Reserved. Must be set to 0(default value)|| _Table 17 – SX1503 Configuration Registers Description_ Rev 11 – 16[th] May 2012 www.semtech.com 26 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## **WIRELESS & SENSING** ## **6 APPLICATION INFORMATION** ## **6.1 Typical Application Circuit** **==> picture [351 x 260] intentionally omitted <==** **----- Start of picture text -----**<br> 3.3V SX1502 2.5V<br>Dx] VDDM VCC1 Lx] 5V 5V<br>I/O[0]<br>I/O[1]<br>Host<br>UL I/O[2] a Xx}<—_> A W<br>controller<br>I/O i NRESET I/O[3] RZ i<br>1.2V<br>VCC2 r<br>- bd a<br>SCL i bd SCL I/O[4] i —_<br>I/O[5] i<br>I/O[6] im<br>SDA j<—! i SDA I/O[7] —<br>!<br>!<br>I/O XI¢+--@ D X ADDR<br>1<br>1<br>NINT<br>' GND 1<br>' xX] '<br>' ' '<br>- Optional (depends on the application) '' 1 'Me e— e1111<br>**----- End of picture text -----**<br> _Figure 12 - Typical Application Schematic_ ## **6.2 Typical LED Operation** Typical LED operation is described below. The LED is usually connected to a high voltage (VBAT) to take advantage of the high sink current of the I/O and to accommodate high LED threshold voltages (VLED). **==> picture [161 x 88] intentionally omitted <==** **----- Start of picture text -----**<br> VCCx VBAT<br>VCCx<br>VLED [*]<br>SX1501/2/3<br>R<br>IOx<br>IOL<br>| 4<br>*LED colour/technology dependent<br>**----- End of picture text -----**<br> _Figure 13 – Typical LED Operation_ ## **Important:** VCCx must exceed VBAT-VLED (VCCx = VBAT is recommended) else the LED will never be completely OFF R must be calculated for IOL not to exceed its max spec (Cf. Table 5) ## 6.2.1 LED ON/OFF Control ||||RegDir[x]|**RegData[x]**| |---|---|---|---|---| |LED**ON**<br>LED**OFF**|||“0” (Output)|“**0**”<br>“**1**”| ||_Table 18 – LED ON/OFF Control_|_Table 18 – LED ON/OFF Control_|_Table 18 – LED ON/OFF Control_|| Rev 11 – 16[th] May 2012 www.semtech.com 27 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## ~~E~~ **WIRELESS & SENSING** ~~S~~ ## 6.2.2 LED Intensity Control When the max IOL spec is not enough it is possible to drive simultaneously multiple I/Os connected together hence increasing the total sink capability. _Example: on an SX1502, by driving an LED with both IO[2] and IO[3] one can sink up to 24+24 =48mA._ Driving an LED with multiple I/Os can also be used to implement more intensity steps for the LED. _Example: with two I/Os capable of sinking each 24mA the LED can sink a total of 0mA (no I/O set to “0”), 24mA (one I/O set to “0”) or 48mA (both I/Os set to “0”) => 3 LED intensity steps ( 4 steps with 3 I/Os, 5 steps with 4 I/Os, etc)_ ## **6.3 Keypad Implementation** SX1501, SX1502, and SX1503 can be used to implement keypad applications up to 8x8 matrix (i.e. 64 keys) _Example: We want to implement a 4x4matrix keypad on SX1502_ **==> picture [106 x 167] intentionally omitted <==** **----- Start of picture text -----**<br> SX1502 IO7 c d<br>IO6IO5 a<br>IO4<br>IO3<br>IO2<br>IO1<br>IO0<br>IO[7-0] as inputs with internal pull-ups enabled<br>**----- End of picture text -----**<br> _Figure 14 – 4x4 keypad connection to SX1502_ _1. Set all I/Os as inputs with internal pull-up (RegDir = 0xFF, RegPullUp = 0xFF)_ _2. Set NINT to be triggered on any IO’s falling edge (RegInterruptMask = 0x00, RegSenseHigh = 0xAA, RegSenseLow = 0xAA)_ _3. When NINT goes low read RegData (or RegInterruptSource) to know the X:Y coordinates of the button which has been pressed._ _4. Clear NINT (RegInterruptSource = 0xFF, can be done automatically on SX1503 depending on RegAdvanced setting)_ _5. Restart from point 3_ ## **6.4 Level Shifter Implementation Hints** Because of their I/O banks with independent supply voltages between 1.2V and 5.5V, the SX1502 and SX1503 can be easily used to perform level shifting of signals from one I/O bank to an other (uC reads I/O from one I/O bank and sends it back to the other I/O bank) This can save significant BOM cost in a final application where only a few slow signals need to be level-shifted. Rev 11 – 16[th] May 2012 www.semtech.com 28 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## **WIRELESS & SENSING** ## **7 PACKAGING INFORMATION** ## **7.1 QFN-UT 20-pin Outline Drawing** QFN-UT 20-pin, 3 x 3 mm, 0.4 mm pitch pp _Figure 15 - Packaging Information – QFN-UT 20-pin Outline Drawing_ ## **7.2 QFN-UT 20-pin Land Pattern** _Figure 16 - Packaging Information – QFN-UT 20-pin Land Pattern_ Rev 11 – 16[th] May 2012 www.semtech.com 29 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## **WIRELESS & SENSING** ## **7.3 QFN-UT 28-pin Outline Drawing** QFN-UT 28-pin, 4 x 4 mm, 0.4 mm pitch _Figure 17 - Packaging Information – QFN-UT 28-pin Outline Drawing_ ## **7.4 QFN-UT 28-pin Land Pattern** _Figure 18 - Packaging Information – QFN-UT 28-pin Land Pattern_ Rev 11 – 16[th] May 2012 www.semtech.com 30 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ## **WIRELESS & SENSING** ## **8 SOLDERING PROFILE** The soldering reflow profile for the SX1501, SX1502 and SX1503 is described in the standard IPC/JEDEC J- STD-020C. For detailed information please go to http://www.jedec.org/download/search/jstd020c.pdf _Figure 19 - Classification Reflow Profile (IPC/JEDEC J-STD-020C)_ Rev 11 – 16[th] May 2012 www.semtech.com 31 **SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO** ~~LO~~ **WIRELESS & SENSING** © Semtech 2012 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. ## ~~|~~ **Contact Information** ## Semtech Corporation Wireless and Sensing Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 Rev 11 – 16[th] May 2012 www.semtech.com 32
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When a component is unavailable, discontinued or has an unacceptable lead time, we tap into our network of vetted European and Asian distributors to source what you need — without compromising on quality or traceability.
Request a quote →Compliant Alternatives
We identify pin-to-pin, electrically equivalent substitutes that meet the same certifications (RoHS, AEC-Q100, REACH) as your original specification — validated against datasheets, not just part numbers. Often at a lower cost.
BOM Analysis service →