SVD2955T4G

NTD2955, NVD2955 

## MOSFET – Power, P-Channel, DPAK 

## -60 V, -12 A 

This Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. Designed for low−voltage, high− speed switching applications in power supplies, converters, and power motor controls. These devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer an additional safety margin against unexpected voltage transients. 

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www.onsemi.com<br>V(BR)DSS RDS(on) TYP ID MAX<br>−60 V 155 m  @ −10 V, 6 A −12 A<br>D<br>P−Channel<br>G<br>S<br>**----- End of picture text -----**<br>


## **Features** 

- Avalanche Energy Specified 

- IDSS and VDS(on) Specified at Elevated Temperature 

- Designed for Low−Voltage, High−Speed Switching Applications and to Withstand High Energy in the Avalanche and Commutation Modes 

• NVD and SVD Prefix for Automotive and Other Applications 4 Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable 4 • These Devices are Pb−Free and are RoHS Compliant 1 1[2] * **MAXIMUM RATINGS** (TJ = 25 ° C unless otherwise noted) 3 2 3 **Rating Symbol Value Unit DPAK IPAK CASE 369C CASE 369D** ~~oF~~ Drain−to−Source Voltage VDSS −60 Vdc **STYLE 2 STYLE 2** Gate−to−Source Voltage − Continuous VGS ± 20 Vdc **MARKING DIAGRAMS** − Non−repetitive (tp ≤ 10 ms) VGSM ± 25 Vpk **& PIN ASSIGNMENTS** ~~ee~~ Drain Current ~~ee~~ 4 4 Dr− Continuous @ Ta =  25 ° C ID −12 Adc Drain Drain Dr− Single Pulse (tp ≤ 10 ms) IDM −18 Apk ~~{|~~ Total Power Dissipation @ Ta =  25 ° C PD 55 W Operating and Storage Temperature TJ, Tstg ~~|~~ −55 to ~~|~~ ° C Range 175 Single Pulse Drain−to−Source Avalanche EAS 216 mJ 2 Energy − Starting TJ = 25 ° C 1 Drain 3 (VDD = 25 Vdc, VGS = 10 Vdc, Peak Gate Source 1 2 3 IL = 12 Apk, L = 3.0 mH, RG = 25 ) Gate Drain Source ~~Oe~~ Thermal Resistance a − Junction−to−Case R JC 2.73 ° C/W A = Assembly Location* − Junction−to−Ambient (Note 1) R JA 71.4 NT2955/NV2955 = Specific Device Code (DPAK) − Junction−to−Ambient (Note 2) R JA 100 NT2955 = Specific Device Code (IPAK) Y = Year Maximum Lead Temperature for Soldering TL 260 ° C WW = Work Week Purposes, 1/8 in. from case for G = Pb−Free Package 

|**Rating**<br>~~oF~~|**Symbol**<br>~~oF~~|**Value**<br>~~oF~~|**Unit**<br>~~oF~~|
|---|---|---|---|
|Drain−to−Source Voltage<br>~~oF~~<br>~~ee~~|VDSSDSS<br>~~oF~~<br>~~ee~~|−60<br>~~oF~~<br>~~ee~~|Vdc<br>~~oF~~<br>~~ee~~|
|Gate−to−Source Voltage<br>− Continuous<br>− Non−repetitive (tpp ≤10 ms)<br>~~ee~~|VGSGS<br>VGSMGSM<br>~~ee~~<br>~~|~~|±20<br>±25<br>~~ee~~<br>~~| |~~|Vdc<br>Vpk<br>~~ee~~<br>~~|~~|
|Drain Current<br>Dr− Continuous @ Ta =  25− Continuous @ Ta =  25a =  25=  25°C<br>Dr− Single Pulse (tp− Single Pulse (tpp ≤10 ms)<br>~~ee ~~<br>~~{|~~|IDD<br>IDMDM<br> ~~ee~~<br>~~{|~~<br>~~|~~|−12<br>−18<br>~~ee~~<br>~~{|~~<br>~~| |~~|Adc<br>Apk<br>~~ee~~<br>~~{|~~<br>~~|~~|
|Total Power Dissipation @ Ta =  25a =  25=  25°C<br>~~{|~~|PDD<br>~~{|~~<br>~~|~~|55<br>~~{|~~<br>~~| |~~|W<br>~~{|~~<br>~~|~~|
|Operating and Storage Temperature<br>Range<br>~~Oe~~|TJ, TstgJ, Tstg, Tstgstg<br>~~|~~|−55 to<br>175<br>~~| |~~|°C<br>~~|~~|
|Single Pulse Drain−to−Source Avalanche<br>Energy − Starting TJ = 25J = 25= 25°C<br>(VDD = 25 Vdc, VGS = 10 Vdc, PeakDD = 25 Vdc, VGS = 10 Vdc, Peak= 25 Vdc, VGS = 10 Vdc, PeakGS = 10 Vdc, Peak= 10 Vdc, Peak<br>IL = 12 Apk, L = 3.0 mH, RG = 25 )L = 12 Apk, L = 3.0 mH, RG = 25 )= 12 Apk, L = 3.0 mH, RG = 25 )G = 25 )= 25 )<br>~~Oe~~|EASAS|216|mJ|
|Thermal Resistance<br>− Junction−to−Case<br>− Junction−to−Ambient (Note 1)<br>− Junction−to−Ambient (Note 2)<br>~~Oe~~|R JC<br>R JA<br>R JA|2.73<br>71.4<br>100|°C/W|
|Maximum Lead Temperature for Soldering<br>Purposes, 1/8 in. from case for<br>10 seconds<br>~~pf~~|TLL<br>~~pf~~|260<br>~~pf~~|°C<br>~~pf~~|



* The Assembly Location code (A) is front side optional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank. 

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

1. When surface mounted to an FR4 board using 1 in pad size (Cu area = 1.127 in[2] ). 

2. When surface mounted to an FR4 board using the minimum recommended pad size (Cu area =  0.412 in[2] ). 

## **ORDERING INFORMATION** 

See detailed ordering and shipping information on page 5 of this data sheet. 

Publication Order Number: **NTD2955/D** 

**1** 

© Semiconductor Components Industries, LLC, 2017 **May, 2019 − Rev. 16** 

**NTD2955, NVD2955** 

## **ELECTRICAL CHARACTERISTICS** (TJ = 25 ° C unless otherwise noted) 

|**ELECTRICAL CHARACTERISTICS **(TJ= 25°C unless otherwise noted)|**ELECTRICAL CHARACTERISTICS **(TJ= 25°C unless otherwise noted)||||||
|---|---|---|---|---|---|---|
|**Characteristic**||**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**|||||||
|Drain−to−Source Breakdown Voltage (Note 3)<br>(VGS= 0 Vdc, ID= −0.25 mA)<br>(Positive Temperature Coefficient)||V(BR)DSS|−60<br>−|−<br>67|−<br>−|Vdc<br>mV/°C|
|Zero Gate Voltage Drain Current<br>(VGS= 0 Vdc, VDS= −60 Vdc, TJ= 25°C)<br>(VGS= 0 Vdc, VDS= −60 Vdc, TJ= 150°C)||IDSS|−<br>−|−<br>−|−10<br>−100|�Adc|
|Gate−Body Leakage Current (VGS=±20 Vdc, VDS= 0 Vdc)||IGSS|−|−|−100|nAdc|
|**ON CHARACTERISTICS**(Note 3)|||||||
|Gate Threshold Voltage<br>(VDS= VGS, ID= −250�Adc)<br>(Negative Temperature Coefficient)||VGS(th)|−2.0<br>−|−2.8<br>4.5|−4.0<br>−|Vdc<br>mV/°C|
|Static Drain−Source On−State Resistance<br>(VGS= −10 Vdc, ID= −6.0 Adc)||RDS(on)|−|0.155|0.180|�|
|Drain−to−Source On−Voltage<br>(VGS= −10 Vdc, ID= −12 Adc)<br>(VGS= −10 Vdc, ID= −6.0 Adc,|TJ= 150°C)|VDS(on)||−1.86<br>−|−2.6<br>−2.0|Vdc|
|Forward Transconductance (VDS|= 10 Vdc, ID= 6.0 Adc)|gFS||8.0|−|Mhos|
|**DYNAMIC CHARACTERISTICS**|||||||
|Input Capacitance|(VDS= −25 Vdc, VGS= 0 Vdc,<br>F = 1.0 MHz)|Ciss|−|500|750|pF|
|Output Capacitance||Coss|−|150|250||
|Reverse Transfer Capacitance||Crss|−|50|100||
|**SWITCHING CHARACTERISTICS**(Notes 3 and 4)|||||||
|Turn−On Delay Time|(VDD= −30 Vdc, ID= −12 A,<br>VGS= −10 V, RG= 9.1�)|td(on)|−|10|20|ns|
|Rise Time||tr|−|45|85||
|Turn−Off Delay Time||td(off)|−|26|40||
|Fall Time||tf|−|48|90||
|Gate Charge|(VDS= −48 Vdc, VGS= −10 Vdc,<br>ID= −12 A)|QT|−|15|30|nC|
|||QGS|−|4.0|−||
|||QGD|−|7.0|−||
|**DRAIN−SOURCE DIODE CHARACTERISTICS**(Note 3)|||||||
|Diode Forward On−Voltage<br>(IS= 12 Adc, VGS= 0 V)<br>(IS= 12 Adc, VGS= 0 V, TJ= 150°C)||VSD|−<br>−|−1.6<br>−1.3|−2.5<br>−|Vdc|
|Reverse Recovery Time<br>(IS= 12 A, dIS/dt = 100 A/�s ,VGS= 0 V)||trr|−|50||ns|
|||ta|−|40|−||
|||tb|−|10|−||
|Reverse Recovery Stored Charge||QRR|−|0.10|−|�C|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

3. Indicates Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2%. 

4. Switching characteristics are independent of operating junction temperature. 

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**2** 

**NTD2955, NVD2955** 

## **TYPICAL PERFORMANCE CURVES** (TJ = 25 ° C unless otherwise noted) 

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25<br>TJ = 25° C VGS = -10 V -9 V<br>-8 V<br>-9.5 V<br>20<br>-7 V<br>15 -6.5 V<br>-6 V<br>10<br>-5.5 V<br>-5 V<br>5<br>0<br>0 1 2 3 4 5 6 7 8 9 10<br>−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br> DRAIN CURRENT (A)<br>D,<br>−I<br>**----- End of picture text -----**<br>


**Figure 1. On−Region Characteristics** 

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0.50<br>0.45 V GS  = −10 V<br>0.40<br>0.35<br>0.30 TJ = 125° C<br>0.25<br>0.20 25 ° C<br>0.15<br>-�55° C<br>0.10<br>0.05<br>0<br>0 3 6 9 12 15 18 21 24<br>−ID, DRAIN CURRENT (AMPS)<br>) Ω<br> DRAIN−TO−SOURCE RESISTANCE (<br>DS(on),<br>R<br>**----- End of picture text -----**<br>


**Figure 3. On−Resistance versus Drain Current and Temperature** 

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2.0<br>1.8 VGS = −10 V<br>ID = −6 A<br>1.6<br>1.4<br>1.2<br>1.0<br>0.8<br>0.6<br>0.4<br>0.2<br>0<br>-�50 -�25 0 25 50 75 100 125 150 175<br>TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 5. On−Resistance Variation with<br> DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)<br>DS(on),<br>R<br>**----- End of picture text -----**<br>


**Figure 5. On−Resistance Variation with Temperature** 

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24<br>22 VDS ≥  −10 V TJ = -�55° C<br>20 25° C 125° C<br>18<br>16<br>14<br>12<br>10<br>8<br>6<br>4<br>2<br>0<br>2 3 4 5 6 7 8 9 10<br>−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)<br>Figure 2. Transfer Characteristics<br>0.250<br>TJ = 25° C<br>0.225<br>0.200<br>0.175 V GS  = −10 V<br>0.150<br>- 15 V<br>0.125<br>0.100<br>0.075<br>0.050<br>0 3 6 9 12 15 18 21 24<br>- ID, DRAIN CURRENT (AMPS)<br> DRAIN CURRENT (A)<br>D,<br>−I<br>) Ω<br> DRAIN−TO−SOURCE RESISTANCE (<br>DS(on),<br>R<br>**----- End of picture text -----**<br>


**Figure 4. On−Resistance versus Drain Current and Gate Voltage** 

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1000<br>VGS = 0 V<br>100<br>TJ = 125° C<br>10<br>100° C<br>1<br>5 10 15 20 25 30 35 40 45 50 55 60<br>−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)<br>, LEAKAGE (nA)<br>DSS<br>−I<br>**----- End of picture text -----**<br>


**Figure 6. Drain−To−Source Leakage Current versus Voltage** 

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**3** 

**NTD2955, NVD2955** 

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1200 15 60<br>VDS = 0 V VGS = 0 V T J  = 25° C ID = 12 A<br>1000 Ciss 12.5 V DS TJ = 25°C 50<br>800 Crss 10 QT 40<br>VGS<br>600 7.5 30<br>Ciss QGS QGD<br>400 5 20<br>200 C oss 2.5 10<br>C rss<br>0 0 0<br>10 5 0 5 10 15 20 25 0 2 4 6 8 10 12 14 16<br>-VGS -VDS QT, TOTAL GATE CHARGE (nC)<br>GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)<br>Figure 7. Capacitance Variation Figure 8. Gate−To−Source and Drain−To−Source<br>Voltage versus Total Charge<br>1000 15<br>VIVDDD GS  = −12 A = −10 V= −30 V VTJGS = 25 = 0 V ° C<br>T J  = 25 ° C<br>100 10<br>tf<br>tr<br>td(off)<br>10 td(on) 5<br>1<br>0<br>1 10 100<br>0 0.25 0.5 0.75 1 1.25 1.5 1.75<br>RG, GATE RESISTANCE ( � ) −VSD, SOURCE−TO−DRAIN VOLTAGE (V)<br>Figure 9. Resistive Switching Time Figure 10. Diode Forward Voltage versus Current<br>Variation versus Gate Resistance<br>100<br>VGS = −15 V<br>SINGLE PULSE<br>TC = 25 ° C<br>10<br>di/dt<br>100 �s<br>IS<br>1 ms<br>1 10 ms t rr<br>dc<br>ta t b<br>RDS(on) LIMIT TIME<br>THERMAL LIMIT<br>PACKAGE LIMIT t p 0.25 IS<br>0.1<br>0.1 1 10 100 IS<br>−VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>−V<br>DS<br>C, CAPACITANCE (pF)<br>, GATE−TO−SOURCE VOLTAGE (V)<br>GS<br>−V<br>, DRAIN−TO−SOURCE VOLTAGE (V)<br>t, TIME (ns)<br>, SOURCE CURRENT (AMPS)<br>S<br>−I<br>, DRAIN CURRENT (AMPS)<br>ID<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Rated Forward Biased Safe Operating Area** 

**Figure 12. Diode Reverse Recovery Waveform** 

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**4** 

**NTD2955, NVD2955** 

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1.0<br>D = 0.5<br>0.2<br>0.1<br>0.1 0.05 P(pk)<br>R�JC(t) = r(t) R�JC<br>D CURVES APPLY FOR POWER<br>0.02 PULSE TRAIN SHOWN<br>0.01 t1 READ TIME AT t 1<br>t 2 TJ(pk) - TC = P(pk) R�JC(t)<br>SINGLE PULSE<br>DUTY CYCLE, D = t1/t2<br>0.01<br>1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01<br>t, TIME (s)<br>r(t), NORMALIZED EFFECTIVE<br>TRANSIENT THERMAL RESISTANCE<br>**----- End of picture text -----**<br>


**Figure 13. Thermal Response** 

## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**|||
|---|---|---|
|**Device**|**Package**|**Shipping**†|
|NTD2955G|DPAK<br>(Pb−Free)|75 Units / Rail|
|NTD2955−1G|IPAK<br>(Pb−Free)|75 Units / Rail|
|NTD2955T4G|DPAK<br>(Pb−Free)|2500 / Tape & Reel|
|NVD2955T4G*|DPAK<br>(Pb−Free)|2500 / Tape & Reel|
|SVD2955T4G*|DPAK<br>(Pb−Free)|2500 / Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

*NVD and SVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable. 

**www.onsemi.com** 

**5** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

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IPAK<br>CASE 369D−01<br>ISSUE C<br>,<br>B C NOTES:<br>SCALE 1:1 1. DIMENSIONING AND TOLERANCING PER<br>V R E ANSI Y14.5M, 1982.<br>2. CONTROLLING DIMENSION: INCH.<br>INCHES MILLIMETERS<br>4 Z DIM MIN MAX MIN MAX<br>A 0.235 0.245 5.97 6.35<br>S i s A q leo B 0.250 0.265 6.35 6.73<br>1 2 3 C 0.086 0.094 2.19 2.38<br>D 0.027 0.035 0.69 0.88<br>E 0.018 0.023 0.46 0.58<br>−T− F 0.037 0.045 0.94 1.14<br>SEATING G 0.090 BSC 2.29 BSC<br>PLANE K H 0.034 0.040 0.87 1.01<br>J 0.018 0.023 0.46 0.58<br>K 0.350 0.380 8.89 9.65<br>R 0.180 0.215 4.45 5.45<br>J S 0.025 0.040 0.63 1.01<br>F<br>H V 0.035 0.050 0.89 1.27<br>Z 0.155 −−− 3.93 −−−<br>D 3 PL<br>aE G 0.13 (0.005) M 1 T<br>MARKING<br>DIAGRAMS<br>STYLE 1:PIN 1. BASE STYLE 2:PIN 1. GATE STYLE 3:PIN 1. ANODE STYLE 4:PIN 1. CATHODE Integrated<br>2. COLLECTOR 2. DRAIN 2. CATHODE 2. ANODE Discrete Circuits<br>3. EMITTER 3. SOURCE 3. ANODE 3. GATE<br>4. COLLECTOR 4. DRAIN 4. CATHODE 4. ANODE<br>YWW xxxxx<br>STYLE 5: STYLE 6: STYLE 7: xxxxxxxx ALYWW<br>PIN 1. GATE PIN 1. MT1 PIN 1. GATE<br>2. ANODE 2. MT2 2. COLLECTOR x<br>3. CATHODE 3. GATE 3. EMITTER<br>4. ANODE 4. MT2 4. COLLECTOR<br>4 00<br>xxxxxxxxx = Device Code<br>A = Assembly Location<br>lL = Wafer Lot<br>Y =  Year<br>WW = Work Week<br>**----- End of picture text -----**<br>


DATE 15 DEC 2010 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON10528D** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: IPAK (DPAK INSERTION MOUNT) PAGE 1 OF 1** ~~—~~ ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ~~ee~~ ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2019 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**==> picture [486 x 546] intentionally omitted <==**

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4 DPAK (SINGLE GAUGE)<br>CASE 369C<br>ISSUE F<br>1 ® [2]<br>DATE 21 JUL 2015<br>3<br>SCALE 1:1<br>NOTES:<br>A 1. DIMENSIONING AND TOLERANCING PER ASME<br>Y14.5M, 1994.<br>E C 2. CONTROLLING DIMENSION: INCHES.<br>A 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-<br>b3 B c2 4. DIMENSIONS D AND E DO NOT INCLUDE MOLDMENSIONS b3, L3 and Z.<br>FLASH, PROTRUSIONS, OR BURRS. MOLD<br>FLASH, PROTRUSIONS, OR GATE BURRS SHALL<br>4 NOT EXCEED 0.006 INCHES PER SIDE.<br>L3 Ele 4| Of Z 5. DIMENSIONS D AND E ARE DETERMINED AT THE<br>D DETAIL A H OUTERMOST EXTREMES OF THE PLASTIC BODY.<br>6. DATUMS A AND B ARE DETERMINED AT DATUM<br>1 2 3 PLANE H.<br>7. OPTIONAL MOLD FEATURE.<br>L4 NOTE 7 DIM MININCHESMAX MILLIMETERSMIN MAX<br>b2 c BOTTOM VIEW A 0.086 0.094 2.18 2.38<br>e SIDE VIEW A1 0.000 0.005 0.00 0.13<br>b b 0.025 0.035 0.63 0.89<br>TOP VIEW 0.005 (0.13) M C b2b3 0.0280.180 0.0450.215 0.724.57 1.145.46<br>c 0.018 0.024 0.46 0.61<br>c2 0.018 0.024 0.46 0.61<br>H Z Z D 0.235 0.245 5.97 6.22<br>E 0.250 0.265 6.35 6.73<br>e 0.090 BSC 2.29 BSC<br>L2 [GAUGE] PLANE C SEATINGPLANE H 0.370 0.410 9.40 10.41<br>L 0.055 0.070 1.40 1.78<br>L1 0.114 REF 2.90 REF<br>L2 0.020 BSC 0.51 BSC<br>L L3 0.035 0.050 0.89 1.27<br>A1 BOTTOM VIEW L4 −−− 0.040 −−− 1.01<br>wat L1 h GF CONSTRUCTIONSALTERNATE Z 0.155 −−− 3.93 −−−<br>DETAIL A<br>ROTATED 9  CW GENERIC<br>MARKING DIAGRAM*<br>STYLE 1: STYLE 2: STYLE 3: STYLE 4: STYLE 5:<br>PIN 1. BASE PIN 1. GATE PIN 1. ANODE PIN 1. CATHODE PIN 1. GATE<br>2. COLLECTOR 2. DRAIN 2. CATHODE 2. ANODE 2. ANODE<br>3. EMITTER 3. SOURCE 3. ANODE 3. GATE 3. CATHODE<br>4. COLLECTOR 4. DRAIN 4. CATHODE 4. ANODE 4. ANODE XXXXXXG AYWW<br>ALYWW XXX<br>STYLE 6: STYLE 7: STYLE 8: STYLE 9: STYLE 10: XXXXXG<br>PIN 1. MT1 PIN 1. GATE PIN 1. N/C PIN 1. ANODE PIN 1. CATHODE<br>2. MT2 2. COLLECTOR 2. CATHODE 2. CATHODE 2. ANODE<br>3. GATE 3. EMITTER 3. ANODE 3. RESISTOR ADJUST 3. CATHODE a d<br>4. MT2 4. COLLECTOR 4. CATHODE 4. CATHODE 4. ANODE<br>IC Discrete<br>SOLDERING FOOTPRINT* XXXXXX = Device Code<br>A = Assembly Location<br>6.20 3.00<br>L = Wafer Lot<br>0.244 0.118<br>2.58 Y =  Year<br>0.102 WW = Work Week<br>G = Pb−Free Package<br>5.80 *This information is generic. Please refer<br>0.228 1.60 6.17 to device data sheet for actual part<br>0.063 0.243 marking.<br>Ts.<br>SCALE 3:1 mm<br>inches<br>**----- End of picture text -----**<br>


*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON10527D** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: DPAK (SINGLE GAUGE) PAGE 1 OF 1** ~~ee~~ ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

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© Semiconductor Components Industries, LLC, 2018 

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