STK554U362A-E

## **STK554U362A-E** 

## **Intelligent Power Module (IPM) 600 V, 10 A** 

## **Overview** 

This “Inverter IPM” is highly integrated device containing all High Voltage (HV) control from HV-DC to 3-phase outputs in a single small SIP module. Output stage uses IGBT/FRD technology and implements Under Voltage Protection (UVP) and Over Current Protection (OCP) with a Fault Detection output flag. Internal Boost diodes are provided for high side gate boost drive. 

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## **PACKAGE PICTURE** 

## **Function** 

- Single control power supply due to Internal bootstrap circuit for high side pre-driver circuit 

- All control inputs and status outputs are at low voltage levels directly compatible with microcontrollers. 

- A single power supply drive is enabled through the use of bootstrap circuits for upper power supplies 

- Built-in dead-time for shoot-thru protection 

- Having open emitter output for low side IGBTs ; individual shunt resistor per phase for OCP 

- Externally accessible embedded thermistor for substrate temperature measurement 

SIP29 56x21.8 

## **MARKING DIAGRAM** 

- Shutdown function ‘ITRIP’ to disable all operations of the 6 phase output stage by external input 

## **Certification** 

- UL1557 (File number : E339285) 

## **Typical Applications** 

- Industrial Pumps 

- Industrial Fans 

- Industrial Automation 

- Home Appliances 

STK554U362A = Specific Device Code A = Year B = Month C = Production Site DD = Factory Lot Code Device marking is on package underside | 2D Code Format: DMX code (22X22) Content of the code    Digit Model Lot code             1 – 5 Module parts number   7-19 

## **ORDERING INFORMATION** 

See detailed ordering and shipping information on page 15 of this data sheet. 

**1** 

Publication Order Number : **STK554U362A-E/D** 

© Semiconductor Components Industries, LLC, 2016 **December 2016 - Rev. 3** 

**STK554U362A-E** 

## **Specifications** 

## **Absolute Maximum Ratings** at Tc = 25C 

|<br>Parameter|<br>Symbol|Remarks|Ratings|Unit|
|---|---|---|---|---|
|Supplyvoltage|VCC|V+ to U-,V-,W-,surge < 500 V   *1|450|V|
|Collector-emitter voltage|VCE|V+ to U,V,W  or U,V,W,to U-,V-,W-|600|V|
|Output current|Io|V+,U-,V-,W-,U,V,W terminal current|±10|A|
|||V+,U-,V-,W-,U,V,W terminal current,Tc = 100C|±7|A|
|Outputpeak current|Iop|V+,U-,V-,W-,U,V,W terminal current,P.W. = 1 ms|±20|A|
|Pre-driver voltage|VD1,2,3,4|VB1 to U, VB2 to V, VB3 to W, VDD to VSS   *2|20|V|
|Input signal voltage|VIN|HIN1, 2, 3, LIN1, 2, 3|0.3 to VDD|V|
|FLTEN terminal voltage|VFLTEN|FLTEN terminal|0.3 to VDD|V|
|Maximumpower dissipation|Pd|IGBTper 1 channel|30|W|
|Junction temperature|Tj|IGBT,FRD,Pre-Driver IC|150|C|
|Storage temperature|Tstg||40 to +125|C|
|Operating case<br>temperature|Tc|IPM case|40 to +100|C|
|Tighteningtorque||A screwpart    *3|0.9|Nm|
|Withstand voltage|Vis|50 Hz sine wave AC 1 minute   *4|2000|VRMS|



Reference voltage is “VSS” terminal voltage unless otherwise specified. 

*1 : Surge voltage developed by the switching operation due to the wiring inductance between V+ and U-(V-, W-) terminal. 

- *2 : VD1 = VB1 to U, VD2 = VB2 to V, VD3 = VB3 to W, VD4 = VDD to VSS terminal voltage. 

- *3 : Flatness of the heat-sink should be less than 50 m to +100 m. 

- *4 : Test conditions : AC 2500 V, 1 second. 

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

**Electrical Characteristics** at Tc = 25C, VD1, VD2, VD3, VD4 = 15 V 

|**Electrical Characteristics **at Tc = 25|C,VD1,V|D2,VD3,VD4 = 15 V||||||
|---|---|---|---|---|---|---|---|
|Parameter|Symbol|Conditions|Test<br>circuit|Min|Typ|Max|Unit|
|**Power output section**||||||||
|Collector-emitter cut-off current|ICE|VCE = 600 V|Fig.1|||100|μA|
|Bootstrapdiode reverse current|IR(DB)|VR(DB)= 600 V||||100|μA|
|Collector to emitter saturation voltage|VCE(sat)|Ic = 10 A,Tj= 25C|Fig.2||1.6|2.2|V|
|||Ic = 5 A,Tj= 100C|||1.35|||
|Diode forward voltage|VF|IF = 10 A,Tj= 25C|Fig.3||1.6|2.1|V|
|||IF = 5 A,Tj= 100C|||1.3|||
|Junction to case thermal resistance|θj-c(T)|IGBT||||4|C/W|
||θj-c(D)|FWD||||5||
|**Control(Pre-driver) section**||||||||
|Pre-driver power dissipation|ID|VD1,2,3 = 15 V|Fig.4||0.08|0.4|mA|
|||VD4 = 15 V|||1.6|4||
|High level Input voltage|Vin H|HIN1, HIN2, HIN3,<br>LIN1, LIN2, LIN3 to VSS||2.5|||V|
|Low level Input voltage|Vin L|||||0.8|V|
|Logic 1 input leakage current|IIN+|VIN = +3.3 V|||100|143|μA|
|Logic 0 input leakage current|IIN-|VIN = 0 V||||2|μA|
|FLTEN terminal sink current|IoSD|FAULT : ON / VFLTEN = 0.1 V|||2||mA|
|FLTEN clearance delaytime|FLTCLR|From time fault condition clear||1.3|1.65|2|ms|
|FLTEN Threshold|VEN+|VEN rising||||2.5|V|
||VEN-|VEN falling||0.8|||V|
|ITRIP threshold voltage|VITRIP|ITRIP(16) to VSS(29)||0.44|0.49|0.54|V|
|ITRIP to shutdownpropagation delay|tITRIP|||340|550|800|ns|
|ITRIP blankingtime|tITRIPBL|||250|350||ns|
|VCC and VBS supply undervoltage<br>protection reset|VCCUV+<br>VBSUV+|||10.5|11.1|11.7|V|
|VCC and VBS supply undervoltage<br>protectionset|VCCUV-<br>VBSUV-|||10.3|10.9|11.5|V|
|VCC and VBS supply undervoltage<br>hysteresis|VCCUVH<br>VBSUVH|||0.14|0.2||V|
|Thermistor for substrate temperature<br>Monitor|Rt|Resistance between<br>TH(27) and VSS(29)||42.3|47|51.7|kΩ|



Reference voltage is “VSS” terminal voltage unless otherwise specified. 

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**STK554U362A-E** 

|Parameter|Symbol|Conditions|Test<br>circuit|Min|Typ|Max|Unit|
|---|---|---|---|---|---|---|---|
|**Switching Character**||||||||
|Switching time|t ON|Io = 10 A<br>Inductive load|Fig.5||0.4||μs|
||t OFF||||0.65|||
|Turn-on switching loss|Eon|Io = 5 A,V<br>+= 300 V,<br>VDD = 15 V, L = 650H<br>Tc = 25C|||130||μJ|
|Turn-off switching loss|Eoff||||122||μJ|
|Total switching loss|Etot||||252||μJ|
|Turn-on switching loss|Eon|Io = 5 A, V<br>+= 300 V,<br>VDD = 15 V, L = 650H<br>Tc = 100C|||156||μJ|
|Turn-off switching loss|Eoff||||154||μJ|
|Total switching loss|Etot||||310||μJ|
|Diode reverse recovery energy|Erec|I0= 5 A, V<br>+= 400 V, VDD = 15 V,<br>L = 650H, Tc = 100C|<br>||6.9||μJ|
|Diode reverse recovery time|trr||||57||ns|
|Reverse bias safe operating area|RBSOA|Io = 20 A, VCE = 450 V|||Full square|||
|Short circuit safe operating area|SCSOA|VCE = 400 V, Tc = 100C||4|||μs|
|Allowable offset voltage slew rate|dv/dt|Between U(V,W) to U-(V-,W-)||50||50|V/ns|
|Reference voltage is “VSS” terminal voltage unless otherwise specified.||||||||



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

## Notes 

1. The pre-drive power supply low voltage protection has approximately 200 mV of hysteresis and operates as follows. 

   - Upper side : The gate is turned off and will return to regular operation when recovering to the normal voltage, but the latch will continue till the input signal will turn ‘low’. 

   - Lower side  :  The gate is turned off and will automatically reset when recovering to normal voltage. It does not depend on input signal voltage. 

2. When assembling the IPM on the heat sink the tightening torque range is 0.6 Nm to 0.9 Nm. 

3. The pre-drive low voltage protection protects the device when the pre-drive supply voltage falls due to an operating malfunction. 

4. When use the over-current protection with external shunt resistor, please set the current protection level to be equal to or less than the rating of output peak current (Iop). 

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**STK554U362A-E** 

## **Module Pin-Out Description** 

|Pin|Name|Description|
|---|---|---|
|1|VB3|HighSideFloating SupplyVoltage 3|
|2|W, VS3|Output 3- HighSideFloating Supply OffsetVoltage|
|3|-|Without pin|
|4|-|Without pin|
|5|VB2|HighSideFloating Supplyvoltage2|
|6|V,VS2|Output2 - HighSideFloating Supply OffsetVoltage|
|7|-|Without pin|
|8|-|Without pin|
|9|VB1|HighSideFloating Supplyvoltage1|
|10|U,VS1|Output1 - HighSideFloating Supply OffsetVoltage|
|11|-|Without pin|
|12|-|Without pin|
|13|V+|Positive Bus Input Voltage|
|14|-|Withoutpin|
|15|-|Withoutpin|
|16|ITRIP|Currentprotectionpin|
|17|U-|Low Side Emitter Connection - Phase U|
|18|FLTEN|Enable input / Fault output|
|19|V-|Low Side Emitter Connection - Phase V|
|20|HIN1|Logic Input High Side Gate Driver - Phase U|
|21|W-|Low Side Emitter Connection - Phase W|
|22|HIN2|Logic Input High Side Gate Driver - Phase V|
|23|HIN3|Logic Input High Side Gate Driver - Phase W|
|24|LIN1|Logic Input Low Side Gate Driver - Phase U|
|25|LIN2|Logic Input Low Side Gate Driver - Phase V|
|26|LIN3|Logic Input Low Side Gate Driver - Phase W|
|27|TH|Thermistor output|
|28|VDD|+15 V Main Supply|
|29|VSS|Negative Main Supply|



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**STK554U362A-E** 

## **Equivalent Block Diagram** 

**==> picture [454 x 586] intentionally omitted <==**

**----- Start of picture text -----**<br>
VB3( 1)<br>W,VS3( 2)<br>VB2( 5)<br>V,VS2( 6)<br>VB1( 9)<br>U,VS1(10)<br>V+ (13)<br>DB DB DB U.V. U.V. U.V.<br>U- (17)<br>V- (19)<br>W- (21)<br>Level  Level  Level<br>Shifter  Shifter  Shifter<br>HIN1(20)<br>HIN2(22)<br>HIN3(23) Logic  Logic<br>Logic<br>LIN1(24)<br>LIN2(25)<br>LIN3(26)<br>Thermistor<br>TH(27)<br>Shutdown<br>ITRIP(16)<br>VDD(28)<br>Under voltage  +  S    Q<br>VSS(29) Detect  -<br>Timer<br>Enable/Disable  R<br>Vref<br>Latch time about 1.65ms<br>FLTEN(18)<br>**----- End of picture text -----**<br>


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**STK554U362A-E** 

## **Test Circuit** 

The tested phase : U+ shows the upper side of the U phase and U- shows the lower side of the U phase. 

##  ICE / IR(BD) 

||U+||V+|W+|W+|U-|V-|W-|
|---|---|---|---|---|---|---|---|---|
|M|13||13|13||10|6|2|
|N|10||6|2||17|19|21|
||||||||||
||U(DB)||V(DB)|||W(DB)|||
|M|9||5|||1|||
|N|29||29|||29|||



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**----- Start of picture text -----**<br>
ICE<br>9                    M               A<br>VD1=15V<br>10<br>5<br>VD2=15V<br>6                                                         VCE<br>1<br>VD3=15V<br>2<br>28<br>VD4=15V<br>29                  N<br>**----- End of picture text -----**<br>


## Fig.1 

##  VCE(sat)   (Test by pulse) 

||U+|V+|W+|U-|V-|W-|
|---|---|---|---|---|---|---|
|M|13|13|13|10|6|2|
|N|10|6|2|17|19|21|
|m|20|22|23|24|25|26|



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**----- Start of picture text -----**<br>
9                   M<br>VD1=15V<br>10<br>5<br>VD2=15V<br>6<br>V                            Ic<br>1<br>VD3=15V                                                         VCE(sat)<br>2<br>28<br>VD4=15V<br>5V      m                   N<br>29<br>16<br>**----- End of picture text -----**<br>


##  VF  (Test by pulse) 

||U+|V+|W+|U-|V-|W-|
|---|---|---|---|---|---|---|
|M|13|13|13|10|6|2|
|N|10|6|2|17|19|21|



## Fig.2 

**==> picture [132 x 106] intentionally omitted <==**

**----- Start of picture text -----**<br>
M<br>V      VF              IF<br>N<br>Fig.3<br>**----- End of picture text -----**<br>


##  ID 

|M<br>N|VD1<br>9<br>10|VD2<br>5<br>6|VD3<br>1<br>2|VD4<br>28<br>29|VD*|ID<br>A|M|
|---|---|---|---|---|---|---|---|
||||||||N|
|||||||Fig.4||



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**STK554U362A-E** 

 Switching time (The circuit is a representative example of the lower side U phase.) 

**==> picture [451 x 151] intentionally omitted <==**

**----- Start of picture text -----**<br>
9 13<br>Input signal  VD1=15V<br>(0 to 5 V) 10<br>5<br>VD2=15V<br>90% 6 10                                                Vcc<br>Io 1 CS<br>VD3=15V<br>10% 2<br>28<br>VD4=15V Io<br>tON tOFF<br>Input signal 24 17<br>29<br>16<br>**----- End of picture text -----**<br>


Fig.5 

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**STK554U362A-E** 

**Input  / Output Timing Chart** 

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**----- Start of picture text -----**<br>
VBS undervoltage protection reset signal<br>ON<br>HIN1,2,3<br>OFF<br>LIN1,2,3<br>VDD undervoltage protection reset voltage<br>*2<br>VDD<br>VBS undervoltage protection reset voltage<br>*3<br>VB1,2,3<br>VIT≥0.54V<br>*4<br>ITRIP terminal<br>Voltage  VIT<0.44V<br>FLTEN<br>ON<br>*1<br>Upper<br>U, V, W<br>OFF<br>*1<br>Lower<br>U ,V, W<br>Automatically reset after protection<br>(typ.1.65ms)<br>**----- End of picture text -----**<br>


Fig. 6 

## Notes 

- *1 : Shows the prevention of shoot-thru via control logic, however, more dead time must be added to account for switching delay externally. 

- *2 : When VDD decreases all gate output signals will go low and cut off all 6 IGBT outputs. When VDD rises the operation will resume immediately. 

- *3 : When the upper side voltage at VB1, VB2 and VB3 drops only the corresponding upper side output is turned off. The outputs return to normal operation immediately after the upper side gate voltage rises. 

- *4 : When VITRIP exceeds threshold all IGBT’s are turned off and normal operation resumes 2 ms (typ) after over current condition is removed. 

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**STK554U362A-E** 

## **Logic level table** 

## V+ 

**==> picture [226 x 167] intentionally omitted <==**

**----- Start of picture text -----**<br>
Ho<br>HIN1,2,3<br>(20,22,23)<br>IC  U,V,W<br>Driver  (10,6,2)<br>LIN1,2,3<br>(24,25,26)<br>Lo<br>**----- End of picture text -----**<br>


|FLTEN|Itrip|HIN1,2,3|LIN1,2,3|U,V,W|
|---|---|---|---|---|
|1|0|1|0|Vbus|
|1|0|0|1|0|
|1|0|0|0|Off|
|<br>1|0|1|1|<br>Off|
|1|1|X|X|Off|
|0|X|X|X|Off|



Fig. 7 

## **Sample Application Circuit** 

## STK554U362A-E 

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**----- Start of picture text -----**<br>
VB1: 9<br>CB1<br>U,VS1:10<br>V+:3<br>CI  CS<br>Vcc  VB2: 5<br>CB2<br>V,VS2: 6<br>U-:7<br>RSU<br>VB3: 1<br>V-:19<br>CB3<br>RSV  W,VS3: 2<br>W-:21<br>RSW<br>Op-Amp,<br>Controller<br>U,VS1:10  HIN1:20<br>HIN2:22<br>HIN3:23  Control<br>LIN1:24  Circuit<br>LIN2:25<br>(5V)<br>LIN3:26<br>V,VS2: 6<br>TH:27<br>FLTEN:18<br>RS,<br>ITRIP:16  Controller  RP  RTH<br>VDD:28<br>CD4<br>W,VS3: 2  VSS:29<br>VD4=15V<br>**----- End of picture text -----**<br>


Fig.8 

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**STK554U362A-E** 

## **Recommended Operating Condition** 

|Item|Symbol|Conditions|Min.|Typ.|Max.|Unit|
|---|---|---|---|---|---|---|
|Supplyvoltage|VCC|V+ to U-(V-,W-)|0|280|450|V|
|Pre-driver supply voltage|VD1, 2, 3|VB1 to U, VB2 to V, VB3 to W|12.5|15|17.5|V|
||VD4|VDD to VSS    *1|13.5|15|16.5||
|ON-state input voltage|VIN(ON)|HIN1, HIN2, HIN3,<br>LIN1, LIN2, LIN3|3.0||5.0|V|
|OFF-state input voltage|VIN(OFF)||0||0.3||
|PWM frequency|fPWM||1||20|kHz|
|Dead time|DT|Turn-off to turn-on(external)|0.5|||μs|
|Allowable inputpulse width|PWIN|ON and OFF|1|||μs|
|Tighteningtorque||‘M3’ type screw|0.6||0.9|Nm|



*1 : Pre-drive power supply (VD4 = 15 ±1.5 V) must have the capacity of Io = 20 mA (DC), 0.5 A (Peak). 

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 

## **Usage Precaution** 

1. This IPM includes internal bootstrap diode and resistor. By adding a bootstrap capacitor “CB”, a high side drive voltage is generated; each phase requires an individual bootstrap capacitor. The recommended value of CB is in the range of 1 to 47 μF, however, this value needs to be verified prior to production. If selecting the capacitance more than 47 μF (±20%), connect a resistor (about 20 Ω) in series between each 3-phase upper side power supply terminals (VB1, 2, 3) and each bootstrap capacitor. 

   - When not using the bootstrap circuit, each upper side pre-drive power supply requires an external independent power supply. 

2. It is essential that wirning length between terminals in the snubber circuit be kept as short as possible to reduce the effect of surge voltages. Recommended value of “CS” is in the range of 0.1 to 10 μF. 

3. The “FLTEN” terminal (Pin 18) is I/O terminal; Fault output / Enable input. It is used to indicate an internal fault condition of the module and also can be used to disable the module operation. 

4. Inside the IPM, a thermistor used as the temperature monitor for internal subatrate  is connected between VSS terminal and TH terminal, therefore, an external pull up resistor connected between the TH terminal and an external power supply should be used. The temperature monitor example application is as follows, please refer the Fig.9, and Fig.10 below. 

5. The pull-down resistor (: 33 kΩ (typ)) is connected with the inside of the signal input terminal, but please connect the pull-down resistor(about 2.2 to 3.3 kΩ) outside to decrease the influence of the noise by wiring etc. 

6. As protection of IPM to the unusual current by a short circuit etc,, it recommends installing shunt resistors and  an over-current protection circuit outside. Moreover, for safety, a fuse on Vcc line is recommended. 

7. Disconnection of terminals U, V, or W during normal motor operation will cause damage to IPM, use caution with this connection. 

. 

8. The “ITRIP” terminal (Pin 16) is the input terminal to shut down. When VITRIP exceeds threshold (0.44 to 0.54 V) all IGBT’s are turned off. And normal operation resumes 2 ms (typ) after over current condition is removed. Therefore, please turn all the input signals off (Low) in case of detecting error at the “FLTEN” terminal. 

9. When input pulse width is less than 1 μs, an output may not react to the pulse. (Both ON signal and OFF signal) 

   -  This data shows the example of the application circuit ~~,~~ and does not guarantee a design as the mass production set. 

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**STK554U362A-E** 

## **The characteristic of thermistor** 

|Parameter|Symbol|Condition|Min|Typ.|Max|Unit|
|---|---|---|---|---|---|---|
|Resistance|R25|T = 25C|44.6|47.0|49.4|kΩ|
|Resistance|R125|T = 125C|1.28|1.41|1.53|kΩ|
|B-Constant(25 to 50C)|B||4010|4050|4091|K|
|Temperature Range|||40||+125|C|



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**----- Start of picture text -----**<br>
Case Temperature(Tc) - Thermal resistance(RTH)<br>min<br>typ<br>max<br>Case temperature, Tc-C<br>Fig.9 Variation of thermistor resistance with temperature<br>Case Temperature(Tc) - TH to Vss voltage characteristic<br>min<br>typ<br>max<br>Condition<br>Pull-up resistor = 4.7k phm<br>Pull-up voltage of TH = 5 V<br>Case temperature, Tc-C<br>Thermistor Resistanse, RTH-kΩ<br>TH - Vss terminal voltage, VTH-V<br>**----- End of picture text -----**<br>


Fig.10 Variation of temperature sense voltage with thermistor temperature 

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**STK554U362A-E** 

## **Maximum Phase current** 

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**----- Start of picture text -----**<br>
STK554U362A-E Motor Current vs. Frequency<br>(Sine wave operation, Vcc = 300 V, Tj = 150°C)<br>Switching Frequency : fc  (kHz)<br>Phase Current : Io  (A rms)<br>**----- End of picture text -----**<br>


Fig.11  Maximum sinusoidal phase current as function of switching frequency at Tc = 100C, VCC = 300 V 

## **Switching waveform** 

**==> picture [54 x 86] intentionally omitted <==**

**----- Start of picture text -----**<br>
X:100 nS/div<br>Ic: 5 A/div<br>Vce: 100 V/div<br>**----- End of picture text -----**<br>


Fig. 12  IGBT Turn-on. Typical turn-on waveform at Tc = 100C, VCC = 300 V, Ic = 10 A 

**==> picture [57 x 85] intentionally omitted <==**

**----- Start of picture text -----**<br>
X:100 nS/div<br>Vce: 100 V/div<br>Ic: 5 A/div<br>**----- End of picture text -----**<br>


Fig. 13  IGBT Turn-off. Typical turn-off waveform Tc = 100C, VCC = 300 V, Ic = 10 A 

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**STK554U362A-E** 

## **CB capacitor value calculation for bootstrap circuit** 

## **Calculate condition** 

|Item|Symbol|Value|Unit|
|---|---|---|---|
|Upper side power supply|VBS|15|V|
|Total gate charge of output power IGBT at 15 V|Qg|89|nC|
|Upper side power supply low voltage protection|UVLO|12|V|
|Upper side power dissipation|IDmax|400|μA|
|ON time required for CB voltage to fall from 15 V to UVLO|Ton-max|-|s|



## **Capacitance calculation formula** 

CB must not be discharged below to the upper limit of the UVLO - the maximum allowable on-time (Ton-max) of the upper side is calculated as follows: 

VBS  CB – Qg – IDmax  Ton-max = UVLO  CB 

CB = (Qg + IDmax  Ton-max) / (VBS – UVLO) 

The relationship between Ton-max and CB becomes as follows. CB is recommended to be approximately 3 times the value calculated above. The recommended value of CB is in the range of 1 to 47 μF, however, the value needs to be verified prior to production. 

**==> picture [350 x 223] intentionally omitted <==**

**----- Start of picture text -----**<br>
CB vs Ton-maxCb  vs  Tonmax<br>Ton-max[ms]<br>F]<br><br>Bootstrap Capacitance CB [<br>**----- End of picture text -----**<br>


Fig.14 Ton-max vs CB characteristic 

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**STK554U362A-E** 

**PACKAGE DIMENSIONS** unit : mm 

 The tolerances of length are +/ 0.5 mm unless otherwise specified. 

**SIP29 56x21.8** CASE 127BW ISSUE O 

**==> picture [249 x 359] intentionally omitted <==**

**----- Start of picture text -----**<br>
56.0<br>R1.7<br>1 29<br>+0 . 2<br>1.27 0.6−0.05<br>1.27  × 28=35.56<br>46.2<br>50.0<br>62.0<br>5.7<br>2.0<br>**----- End of picture text -----**<br>


missing pin : 3,4,7,8,11,12,14,15 

**==> picture [149 x 134] intentionally omitted <==**

**----- Start of picture text -----**<br>
3.2<br>+0 . 1<br>6.7−0.5<br>3.4<br>21.8<br>13.9 (10.9)<br>0.5<br>2<br>.<br>5.0<br>0.05<br>+0 −<br>0.5<br>**----- End of picture text -----**<br>


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**14** 

**STK554U362A-E** 

|**ORDERING INFORMATION**|||
|---|---|---|
|Device|Package|Shipping (Qty / Packing)|
|STK554U362A-E|SIP29 56x21.8<br>(Pb-Free)|8 / Tube|



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