STK544UC63K-E

STK544UC63K-E 

## Intelligent Power Module (IPM), 600 V, 10 A 

The STK544UC63K−E is a fully-integrated inverter power stage consisting of a high-voltage driver, six IGBT’s and a thermistor, suitable for driving permanent magnet synchronous (PMSM) motors, brushless-DC (BLDC) motors and AC asynchronous motors. The IGBT’s are configured in a 3-phase bridge with separate emitter connections for the lower legs for maximum flexibility in the choice of control algorithm. The power stage has a full range of protection functions including cross-conduction protection, external shutdown and under-voltage lockout functions. An internal comparator and reference connected to the over-current protection circuit allows the designer to set the over-current protection level. 

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## **Features** 

- Three-phase 10 A/600 V IGBT Module with Integrated Drivers 

**SIP23 62x21.8 CASE 127FC** 

- Built-in Under Voltage Protection 

- Cross-conduction Protection 

- ITRIP Input to Shut Down All IGBTs 

- Integrated Bootstrap Diodes and Resistors 

- Thermistor for Substrate Temperature Measurement 

- UL1557 Certification (File Number: E339285) 

- These Devices are Pb-Free and are RoHS Compliant 

## **Typical Applications** 

- Industrial Drives 

- Industrial Pumps 

- Industrial Fans 

- Industrial Automation 

**MARKING DIAGRAM** STK544UC63K ZZZATYWW ~~<~~ STK544UC63K = Specific Device Code ZZZ = Assembly Lot Code A = Assembly Location T = Test Location Y = Year WW = Work Week 

Device marking is on package top side 

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ORDERING INFORMATION<br>Shipping<br>Device Package (Qty/Packing)<br>STK544UC63K−E SIP23 80/Box<br>HIN(U) HS1 62x21.8FP−4<br>LIN(U) LS1 HS1 HS2 HS3 (Pb−Free)<br>Three channel<br>HIN(V) half−bridge HS2<br>driver<br>LIN(V) with LS2<br>protection<br>HIN(W) circuits HS3<br>LIN(W) LS3 LS1 LS2 LS3<br>Te<br>Figure 1. Functional Diagram<br>©   Semiconductor Components Industries, LLC, 2017 1 Publication Order Number:<br>May, 2019 − Rev. 0 STK544UC63K−E/D<br>VB(U) VB(V) VB(W) VDD GND T/ITRIP P VS(U), U VS(V), V VS(W), W<br>NU NV NW<br>**----- End of picture text -----**<br>


**STK544UC63K−E** 

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STK544UC63K<br>VCC<br>P: 10<br>+ RC filtering for<br>C1 CS HINx and LINx<br>not shown.<br>HV Ground Recommended<br>in noisy<br>RSU<br>environments.<br>NU: 12<br>From HV<br>Power<br>RSV<br>Source NV: 13 HIN(U): 15<br>HIN(V): 16<br>RSW<br>NW: 14 HIN(W): 17<br>To current LIN(U): 18<br>senser LIN(V): 19<br>LIN(W): 20<br>VB(U): 7<br>+<br>VS(U), U: 8<br>Controller<br>VB(V): 4<br>+<br>T/ITRIP: 21<br>Motor VS(V), V: 5 RP<br>VDD = 15 V<br>VB(W): 1 VDD: 22 from<br>+ CD4 + external<br>regulator<br>VS(W), W: 2 VSS: 23<br>LV Ground<br>Star connection to HV Ground<br>**----- End of picture text -----**<br>


**Figure 2. Application Schematic** 

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**STK544UC63K−E** 

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RBS<br>VB(U) (7)<br>RBS<br>VB(V) (4)<br>RBS<br>VB(W) (1)<br>BD BD BD<br>P (10)<br>RBC<br>VDD (22)<br>GND (23) VS(W), W (2)<br>VS(V), V (5)<br>VS(U), U (8)<br>NU (12)<br>NV (13)<br>NW (14)<br>Level Level Level<br>Shifter Shifter Shifter<br>HIN(U) (15)<br>HIN(V) (16)<br>HIN(W) (17)<br>Logic Logic Logic<br>LIN(U) (18)<br>LIN(V) (19)<br>LIN(W) (20)<br>VDD<br>VDD undervoltage<br>shutdown<br>Thermistor<br>T/ITRIP (21) Over current<br>Internal Voltage protection<br>reference<br>**----- End of picture text -----**<br>


**Figure 3. Simplified Block Diagram** 

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**STK544UC63K−E** 

## **PIN DESCRIPTION** 

|**Pin No.**|**Name**|**Description**|
|---|---|---|
|1|VB(W)|High Side Floating Supply Voltage for W phase|
|2|VS(W), W|Internally connected to W phase high side driver ground. W phase output|
|4|VB(V)|High Side Floating Supply voltage for V phase|
|5|VS(V), V|Internally connected to V phase high side driver ground. V phase output|
|7|VB(U)|High Side Floating Supply voltage for U phase|
|8|VS(U), U|Internally connected to U phase high side driver ground. U phase output|
|10|P|Positive Bus Input Voltage|
|12|NU|Low Side Emitter Connection − Phase U|
|13|NV|Low Side Emitter Connection − Phase V|
|14|NW|Low Side Emitter Connection − Phase W|
|15|HIN(U)|Logic Input High Side Gate Driver − Phase U|
|16|HIN(V)|Logic Input High Side Gate Driver − Phase V|
|17|HIN(W)|Logic Input High Side Gate Driver − Phase W|
|18|LIN(U)|Logic Input Low Side Gate Driver − Phase U|
|19|LIN(V)|Logic Input Low Side Gate Driver − Phase V|
|20|LIN(W)|Logic Input Low Side Gate Driver − Phase W|
|21|T/ITRIP|Temperature Monitor and Shut−down pin|
|22|VDD|+15 V Main Supply|
|23|VSS|Negative Main Supply|



1. Pins 3, 6, 9 and 11 are not present 

## **ABSOLUTE MAXIMUM RATINGS** (at Tc = 25 ° C) (Note 2) 

|**Symbol**|**Rating**|**Conditions**|**Value**|**Unit**|
|---|---|---|---|---|
|VCC|Supply voltage|P to NU, NV, NW, surge < 500 V (Note 3)|450|V|
|VCE|Collector-emitter voltage|P to U, V, W; U to NU; V to NV; W to NW|600|V|
|Io|Output current|P, U, V, W, NU, NV, NW terminal current|±10|A|
|||P, U, V, W, NU, NV, NW terminal current, Tc = 100°C|±5|A|
|Iop|Output peak current|P, U, V, W, NU, NV, NW terminal current, pulse width 1 ms|±20|A|
|Pd|Maximum power dissipation|IGBT per 1 channel|20|W|
|VBS|Gate driver supply voltage|VB(U) to VS(U), VB(V) to VS(V), VB(W) to VS(W), VDD to<br>VSS (Note 4)|−0.3 to +20.0|V|
|VIN|Input signal voltage|HIN(U), HIN(V), HIN(W), LIN(U), LIN(V), LIN(W)|−0.3 to +7.0|V|
|VITRIP|ITRIP terminal voltage|T/ITRIP terminal|VSS to +5.0|V|
|Tj|Junction temperature|IGBT, FRD|150|°C|
|Tstg|Storage temperature||−40 to +125|°C|
|Tc|Operating case temperature|IPM case temperature|−40 to +100|°C|
|MT|Tightening torque|Case mounting screws|0.9|Nm|
|Vis|Isolation voltage|50 Hz sine wave AC 1 minute (Note 5)|2000|Vrms|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

2. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 

3. This surge voltage developed by the switching operation due to the wiring inductance between P and NU, NV, NW terminal. 4. VBS = VB(U) to VS(U), VB(V) to VS(V), VB(W) to VS(W). 

5. Test conditions: AC2500V, 1 s. 

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**STK544UC63K−E** 

## **RECOMMENDED OPERATING CONDITIONS** 

|**Symbol**|**Rating**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VCC|Supply voltage|P to NU, NV, NW|0|280|450|V|
|VBS|Gate driver supply voltage|VB(U) to VS(U), VB(V) to VS(V),<br>VB(W) to VS(W)|13.0|15|17.5|V|
|VDD||VDD to VSS|14.0|15|16.5|V|
|VIN(ON)|ON-state input voltage|HIN(U), HIN(V), HIN(W), LIN(U),<br>LIN(V), LIN(W)|0|−|0.3|V|
|VIN(OFF)|OFF-state input voltage||3.0|−|5.0|V|
|fPWM|PWM frequency||1|−|20|kHz|
|DT|Dead time|Turn-off to Turn-on (external)|0.5|−|−|�s|
|PWIN|Allowable input pulse width|ON and OFF|1|−|−|�s|
||Tightening torque|‘M3’ type screw|0.6|−|0.9|Nm|



Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 

**ELECTRICAL CHARACTERISTICS** (Tc = 25 ° C, VBIAS (VBS, VDD) = 15 V unless otherwise noted) 

|**ELECTR**|**ICAL CHARACTERISTICS**(Tc = 25°C, VBIAS|(VBS, VDD) = 15 V unless otherwise noted)|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|**POWER OUTPUT SECTION**|||||||
|ICE|Collector-emitter leakage current|VCE= 600 V|−|−|0.1|mA|
|IR(BD)|Bootstrap diode reverse current|VR(DB) = 600 V|−|−|0.1|mA|
|VCE(SAT)|Collector to emitter saturation voltage|IC = 10 A, Tj = 25°C|−|2.1|2.7|V|
|||IC = 5 A, Tj = 100°C|−|1.7|−|V|
|VF|Diode forward voltage|IF = 10 A, Tj = 25°C|−|2.2|2.8|V|
|||IF = 5 A, Tj = 100°C|−|1.7|−|V|
|VF(BD)|Bootstrap diode forward voltage|IF = 0.1 A|−|2.0|−|V|
|RBC|Bootstrap circuit resistance|Resistor value for common boot charge line|−|2|−|�|
|RBS||Resistor value for separate boot charge line|−|10|−|�|
|�j−c(T)|Junction to case thermal resistance|IGBT|−|4.9|6.2|°C/W|
|�−c(D)||FRD|−|8.5|10.6|°C/W|
|**DRIVER SECTION**|||||||
|ID|Gate driver consumption current|VBS= 15 V (Note 6), per driver|−|0.08|0.4|mA|
|ID||VDD= 15 V, total|−|2.0|4.0|mA|
|VIN H|High level Input voltage|HIN(U), HIN(V), HIN(W), LIN(U), LIN(V),<br>LIN(W) to VSS|2.5|−|−|V|
|VIN L|Low level Input voltage||−|−|0.8|V|
|IIN+|Logic 0 input leakage current||76|118|160|�A|
|IIN−|Logic 1 input leakage current||97|150|203|�A|
|VITRIP|ITRIP threshold voltage|T/ITRIP to VSS|3.67|4.17|4.67|V|
|tITRIP|ITRIP to shutdown propagation delay||0.8|1.1|1.4|�s|
|tITRIPBL|ITRIP blanking time||−|0.9|−|�s|
|FLTCLR|FAULT clearance delay time|Automatic reset after protection|6|9|12|ms|
|DT|Dead time (Internal dead time injected by driver)||220|300|380|�s|
|VCCUV+<br>VBSUV+|VDDand VBSsupply undervoltage positive<br>going input threshold||10.5|11.1|11.7|V|
|VCCUV−<br>VBSUV−|VDDand VBSsupply undervoltage negative<br>going input threshold||10.3|10.9|11.5|V|



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## **STK544UC63K−E** 

**ELECTRICAL CHARACTERISTICS** (Tc = 25 ° C, VBIAS (VBS, VDD) = 15 V unless otherwise noted) 

|**ELECTR**|**ICAL CHARACTERISTICS**(Tc = 25°C, VBIAS|(VBS, VDD) = 15 V unless otherwise noted)|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|VCCUVH<br>VBSUVH|VDDand VBSsupply undervoltage Iockout<br>hysteresis||0.14|0.2|−|V|
|**SWITCHING CHARACTER**|||||||
|tON|Switching time|IC = 10 A, Tj = 25°C|−|0.35|0.7|�s|
|tOFF|||−|0.45|0.8|�s|
|EON|Turn-on switching loss|IC = 5 A, Tj = 25°C|−|89|−|�J|
|EOFF|Turn-off switching loss||−|74|−|�J|
|ETOT|Total switching loss||−|163|−|�J|
|EON|Turn-on switching loss|IC = 5 A, Tj = 100°C|−|125|−|�J|
|EOFF|Turn-off switching loss||−|82|−|�J|
|ETOT|Total switching loss||−|207|−|�J|
|EREC|Diode reverse recovery energy|IC = 5 A, Tj = 100°C|−|40|−|�J|
|tRR|Diode reverse recovery time||−|150|−|ns|
|RBSOA|Reverse bias safe operating area|IC = 20 A, VCE= 450 V|Full Square||||
|SCSOA|Short circuit safe operating area|VCE= 400 V, Tj = 150°C|5|−|−|�s|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 6. VBS = VBU to U, VBV to V, VBW to W 

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**6** 

**STK544UC63K−E** 

## **TYPICAL CHARACTERISTICS INV SECTION** 

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20<br>15 PPL | ver<br>Tj = 25 ° C<br>10<br>pf i ve Tj = 100 ° C<br>5<br>0 EeZanaeeana<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0<br>VCE , COLLECTOR [−] EMITTER VOLTAGE (V)<br>Figure 4. VCE versus IC for Different Temperatures<br>(VDD = 15 V)<br>1.5<br>VCC = 300 V<br>1.2 V DD  = 15 V<br>0.9 Fyes<br>0.6<br>ee Tj = 100 ° C<br>0.3<br>ee Tj = 25 ° C<br>0.0 ee ee<br>0 5 10 15 20<br>IC, COLLECTOR CURRENT (A)<br>Figure 6. EON versus IC for Different Temperatures<br>1.0<br>0.8 BN 0<br>0.6 BH EN A A<br>0.4<br>Bi 0PA<br>0.2<br>BN<br>0.0 TA ELATT<br>0.000001 0.00001 0.0001 0.001 0.01 0.1 1<br>ON − PULSE WIDTH (S)<br> , COLLECTOR CURRENT (A)I C , FORWARD CURRENT (A)IFIFF<br>, SWITCHING LOSS (mJ) , SWITCHING LOSS (mJ)<br>EON OFF<br>E<br>PEAK R (t)<br>STANDARDIZED SQUARE−WAVE<br>**----- End of picture text -----**<br>


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20<br>15 P| ft | |Ae<br>10<br>Pt} EE AL<br>5 Tj = 100 ° C<br>Tj = 25 ° C<br>0 |pee| LAaaae<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5<br>VF, FORWARD VOLTAGE (V)<br>Figure 5. VF versus IF for Different Temperatures<br>0.4<br>VCC = 300 V<br>VDD = 15 V<br>0.3<br>es<br>0.2<br>Tj = 100 ° C<br>rn<br>0.1<br>LZ Tj = 25 ° C<br>0.0 eee<br>0 5 10 15 20<br>IC , COLLECTOR CURRENT (A)<br>, FORWARD CURRENT (A)IFIFF<br>, SWITCHING LOSS (mJ)<br>OFF<br>E<br>**----- End of picture text -----**<br>


**Figure 7. EOFF versus IC for Different Temperatures** 

**Figure 8. Thermal Impedance Plot** 

**Figure 9. Turn-on Waveform Tj = 100** ° **C, VCC = 300 V** 

**Figure 10. Turn-off Waveform Tj = 100** ° **C, VCC = 300 V** 

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**STK544UC63K−E** 

## **APPLICATIONS INFORMATION** 

## **Input/Output Timing Chart** 

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VBS undervoltage protection reset signal<br>HIN<br>LIN<br>VDD undervoltage protection reset voltage (Note 8)<br>VDD VBS undervoltage protection reset voltage (Note 9)<br>VB(U), VB(V),<br>VB(W) Voltage  ≥  4.67 V<br>Note 10<br>Voltage < 3.67 V<br>T/ITRIP<br>Cross-conduction prevention period (Note 7)<br>Upper IGBT<br>Gate Drive<br>Lower IGBT<br>Gate Drive<br>FAULT clearance delay time (typ 9 ms)<br>**----- End of picture text -----**<br>


**Figure 11. Input/Output Timing Chart** 

NOTES: 

7. This section of the timing diagram shows the effect of cross-conduction prevention. 

8. This section of the timing diagram shows that when the voltage on VDD decreases sufficiently all gate output signals will go low, switching off all six IGBTs. When the voltage on VDD rises sufficiently, normal operation will resume. 

9. This section shows that when the bootstrap voltage on VB(U) (VB(V), VB(W)) drops, the corresponding high side output U (V, W) is switched off. When the voltage on VB(U) (VB(V), VB(W)) rises sufficiently, normal operation will resume. 

- 10.This section shows that when the voltage on ITRIP exceeds the threshold, all IGBT’s are turned off. Normal operation resumes later after the over-current condition is removed. 

## **Input/Output Logic Table** 

**Table 1. INPUT/OUTPUT LOGIC TABLE** 

||**INPUT**|||**OUTPUT**||
|---|---|---|---|---|---|
|**HIN**|**LIN**|**T/ITRIP**|**High Side IGBT**|**Low Side IGBT**|**U, V, W**|
|L|H|L|ON|OFF|P|
|H|L|L|OFF|ON|NU, NV, NW|
|H|H|L|OFF|OFF|High Impedance|
|L|L|L|OFF|OFF|High Impedance|
|X|X|H|OFF|OFF|High Impedance|



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**STK544UC63K−E** 

## **Thermistor Characteristics** 

**Table 2. THERMISTOR CHARACTERISTICS** 

|**Symbol**|**Parameter**|**Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|R25|Resistance|Tth = 25°C|99|100|101|k�|
|R125||Tth = 125°C|2.40|2.52|2.65|k�|
|B|B-Constant (25 to 50°C)||−4207|4250|4293|K|
||Temperature Range||−40|−|+125|°C|



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Thermistor Temperature (Tth) − Thermistor Resistance (RTH)<br>10000<br>min<br>typ<br>1000<br>max<br>100<br>10<br>1<br>−40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 110 120 130<br>Tth, Thermistor Temperature ( � C)<br>Figure 12. Thermistor Resistance versus Thermistor Temperature<br>Thermistor Temperature (Tth) − T/ITRIP to GND Voltage Characteristics (Vsense)<br>4.0<br>3.5<br>3.0<br>2.5<br>2.0<br>1.5<br>min<br>1.0<br>typ<br>0.5<br>max<br>0.0<br>−40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 110 120 130<br>Tth, Thermistor Temperature ( � C)<br>) �<br>RTH, Thermistor Resistance (k<br>Voltage (V)<br>Vsense, T/ITRIP − GND Terminal<br>**----- End of picture text -----**<br>


**Figure 13. Thermistor Voltage versus Thermistor Temperature Conditions: RP = 4.3 k � 1% Pull-down and VDD = 15.0 V (See below)** 

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15 V<br>VDD (22)<br>Thermistor Driver IC<br>9.1 k �<br>T/ITRIP (21)<br>18 k �<br>4.3 k �<br>2.4 k � 47 pF<br>VSS (23)<br>**----- End of picture text -----**<br>


**Figure 14. Sample Application Circuit for Temperature Monitoring** 

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**9** 

**STK544UC63K−E** 

## **TEST CIRCUITS** 

## • ICE, IR(DB) 

||**U+**|**V+**|**W+**|**U−**|**V−**|**W−**|
|---|---|---|---|---|---|---|
|A|10|10|10|8|5|2|
|B|8|5|2|12|13|14|



U+,V+,W+: High side phase U−,V−,W−: Low side phase 

||**U(DB)**|**V(DB)**|**W(DB)**|
|---|---|---|---|
|A|7|4|1|
|B|23|23|23|



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VBS = 15 V 7 ICE, IR<br>A A<br>8<br>VBS = 15 V 4<br>VCE, VR<br>5<br>VBS = 15 V 1<br>2<br>VDD = 15 V 22 B<br>23, 12, 13, 14<br>**----- End of picture text -----**<br>


**Figure 15. Test Circuit for ICE** 

## • VCE(sat) (Test by pulse) 

||**U+**|**V+**|**W+**|**U−**|**V−**|**W−**|
|---|---|---|---|---|---|---|
|A|10|10|10|8|5|2|
|B|8|5|2|12|13|14|
|C|15|16|17|18|19|20|



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VBS = 15 V 7<br>A<br>8<br>VBS = 15 V 4<br>5<br>V IC<br>VBS = 15 V 1<br>VCE(sat)<br>2<br>VDD = 15 V 22<br>C B<br>23, 12, 13, 14<br>**----- End of picture text -----**<br>


**Figure 16. Test Circuit for VCE(SAT)** 

## • VF (Test by pulse) 

||**U+**||**V+**|**W+**|**W+**|**U−**||**V−**|**W−**|
|---|---|---|---|---|---|---|---|---|---|
|A|10||10|10||8||5|2|
|B|8||5|2||12||13|14|
|||||||||||
||||**U(DB)**|||**V(DB)**||**W(DB)**||
|A|||7|||4||1||
|B|||22|||22||22||



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A<br>V IF<br>B<br>**----- End of picture text -----**<br>


**Figure 17. Test Circuit for VF** 

## • ID 

||**VBS U+**|**VBS V+**|**VBS W+**|**VDD**|
|---|---|---|---|---|
|A|7|4|1|22|
|B|8|5|2|23|



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ID<br>A A<br>VD*<br>B<br>**----- End of picture text -----**<br>


**Figure 18. Test Circuit for ID** 

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**10** 

**STK544UC63K−E** 

• Switching time (The circuit is a representative example of the lower side U phase.) 

||**U+**|**V+**|**W+**|**U−**|**V−**|**W−**|
|---|---|---|---|---|---|---|
|A|10|10|10|10|10|10|
|B|12|13|14|12|13|14|
|C|8|5|2|10|10|10|
|D|12|13|14|8|5|2|
|E|15|16|17|18|19|20|



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Input Signal<br>(0 to 5 V)<br>90%<br>lo<br>10%<br>tON tOFF<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
VBS = 15 V 7<br>A<br>8<br>VBS = 15 V 4 C<br>5 CS VCC<br>VBS = 15 V 1<br>D<br>2<br>VDD = 15  V 22<br>E B<br>23, 12, 13, 14 Io<br>**----- End of picture text -----**<br>


**Figure 19. Test Circuit for Switching Time** 

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MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

## **SIP23, 62x21.8 FP−4** 

## CASE 127FC ISSUE O 

## DATE 07 JAN 2019 

**GENERIC MARKING DIAGRAM*** XXXX = Specific Device Code *This information is generic. Please refer to XXXXXXXXXXXXXXXXX ZZZ = Assembly Lot Code device data sheet for actual part marking. ZZZATYWW AT = Assembly & Test Location Pb−Free indicator, “G” or microdot “ ”, may Y = Year or may not be present. Some products may WW = Work Week not follow the Generic Marking. 

## **DOCUMENT NUMBER:** 

## **98AON01973H** 

**DESCRIPTION: SIP23, 62x21.8 FP−4** 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

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