SSN1N45BTA

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## **SSN1N45B** 

## **N-Channel B-FET** 

## **450 V, 0.5 A, 4.25 Ω** 

## **Description** 

These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for electronic ballasts based on half bridge configuration. 

## **Features** 

• 0.5 A, 450 V, RDS(on) = 4.25 Ω @ VGS = 10 V • Low Gate Charge (typical 6.5 nC) • Low Crss (typical  6.5 pF) 

- 100% Avalanche Tested 

- Improved dv/dt Capability 

- Gate-Source Voltage ± 50V Guaranteed 

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D<br>G<br>G D S TO-92<br>S<br>**----- End of picture text -----**<br>


**Absolute Maximum Ratings** TC = 25oC unless otherwise noted. 

|**Absolute Maximum Ratings **TC = 25oC unless otherwise noted.C = 25oC unless otherwise noted.= 25oC unless otherwise noted.<br>oC unless otherwise noted.C unless otherwise noted.|~~ts~~|
|---|---|
|**Parameter**<br>~~MO~~|**SSN1N45BTA**<br>~~MO~~<br>~~ts~~|
|Drain-Source Voltage<br>~~a~~|450<br>~~ts~~<br>~~a~~|
|Drain Current<br>- Continuous (TC= 25°C)<br>- Continuous (TC= 100°C)<br>~~a~~|0.5<br>~~a~~|
||0.32|
|Drain Current<br>- Pulsed<br>(Note 1)|4.0|
|Gate-Source Voltage|± 50|
|Single Pulsed Avalanche Energy<br>(Note 2)|108|
|Avalanche Current<br>(Note 1)|0.5|
|Repetitive Avalanche Energy<br>(Note 1)<br>~~_~~|0.25<br>~~_~~|
|Peak Diode Recoverydv/dt<br>(Note 3)<br>~~_~~<br>~~eee~~<br>~~—~~<br>~~°°~~<br>~~»»}}}}»}©|0UUULLLUT~~|5.5<br>~~_~~<br>~~eee~~<br>~~}»}©|0UUULLLUT~~|
|Power Dissipation (TA= 25°C)<br>~~_~~<br>~~eee~~<br>~~—~~<br>~~°°~~<br>~~»»}}}}»}©|0UUULLLUT~~<br>~~—~~|0.9<br>~~_~~<br>~~eee~~<br>~~}»}©|0UUULLLUT~~<br>~~—~~<br>~~§€§~—S~~|
|Power Dissipation (TL= 25°C)<br>- Derate above 25°C<br>~~—~~<br>~~°°~~<br>~~» » } } }}»}©|0UUULLLUT~~<br>~~—~~<br>~~_~~|2.5<br>~~}»}©|0UUULLLUT~~<br>~~—~~<br>~~§€§~—S~~<br>~~_~~|
||0.02<br>~~—~~<br>~~§€§~—S~~<br>~~_~~|
|Operating and Storage Temperature Range<br>~~_~~<br>~~LOO~~|-55 to +150<br>~~_~~<br>~~LOO~~|
|Maximum Lead Temperature for Soldering,<br>1/8"from Case for 5 Seconds|300|



## **Thermal Characteristics** 

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©2002 Fairchild Semiconductor Corporation SSN1N45B Rev. C0 

**1** 

## **Package Marking and Ordering Information** 

|**Top Mark**|**Package**|**Packing Method**|**Reel Size**|**Tape Width**|
|---|---|---|---|---|
|1N45B|TO-92|AMMO|N/A|N/A|



**Electrical Characteristics** TC = 25oC unless otherwise noted. 

|**Symbol**<br>**Parameter**<br>**Test Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>**Off Characteristics**<br>BVDSS<br>Drain-Source Breakdown Voltage<br>VGS= 0 V, ID= 250µA<br>450<br>--<br>--<br>V<br>∆BVDSS<br>/∆TJ<br>Breakdown Voltage Temperature<br>Coefficient<br>ID= 250µA, Referenced to 25°C<br>--<br>0.5<br>--<br>V/°C<br>IDSS<br>Zero Gate Voltage Drain Current<br>VDS= 450 V, VGS= 0 V<br>--<br>--<br>10<br>µA<br>VDS= 360 V, TC= 125°C<br>--<br>--<br>100<br>µA<br>IGSSF<br>Gate-Body Leakage Current, Forward<br>VGS= 50 V, VDS= 0 V<br>--<br>--<br>100<br>nA<br>IGSSR<br>Gate-Body Leakage Current, Reverse<br>VGS= -50 V, VDS= 0 V<br>--<br>--<br>-100<br>nA<br>**On Characteristics**<br>VGS(th)<br>Gate Threshold Voltage<br>VDS= VGS, ID= 250µA<br>2.3<br>3.0<br>3.7<br>V<br>VDS= VGS, ID= 250 mA<br>3.5<br>4.2<br>4.9<br>V<br>RDS(on)<br>Static Drain-Source<br>On-Resistance<br>VGS= 10 V, ID= 0.25 A<br>--<br>3.4<br>4.25<br>Ω<br>gFS<br>Forward Transconductance<br>VDS= 50 V, ID= 0.25 A<br>--<br>0.7<br>--<br>S<br>**Dynamic Characteristics**<br>Ciss<br>Input Capacitance<br>VDS= 25 V, VGS= 0 V,<br>f = 1.0 MHz<br>--<br>185<br>240<br>pF<br>Coss<br>Output Capacitance<br>--<br>29<br>40<br>pF<br>Crss<br>Reverse Transfer Capacitance<br>--<br>6.5<br>8.5<br>pF<br>**Switching Characteristics**<br>~~—— eee~~<br>~~SE~~<br>~~=—~~<br>~~ee~~|
|---|
|td(on)<br>Turn-On Delay Time<br>VDD= 225 V, ID= 0.5 A,<br>RG= 25Ω<br>(Note 4)<br>--<br>7.5<br>25<br>ns<br>tr<br>Turn-On Rise Time<br>--<br>21<br>50<br>ns<br>td(off)<br>Turn-Off Delay Time<br>--<br>23<br>55<br>ns<br>tf<br>Turn-Off Fall Time<br>--<br>36<br>80<br>ns<br>Qg<br>Total Gate Charge<br>VDS= 360 V, ID= 0.5 A,<br>VGS= 10 V<br>(Note 4)<br>--<br>6.5<br>8.5<br>nC<br>Qgs<br>Gate-Source Charge<br>--<br>0.9<br>--<br>nC<br>Qgd<br>Gate-Drain Charge<br>--<br>3.2<br>--<br>nC<br>~~===~~|
|**Drain-Source Diode Characteristics and Maximum Ratings**|
|IS<br>Maximum Continuous Drain-Source Diode Forward Current<br>--<br>--<br>0.5<br>A|
|ISM<br>Maximum Pulsed Drain-Source Diode Forward Current<br>--<br>--<br>4.0<br>A|
|VSD<br>Drain-Source Diode Forward Voltage<br>VGS= 0 V, IS= 0.5 A<br>--<br>--<br>1.4<br>V|
|trr<br>Reverse Recovery Time<br>VGS= 0 V, IS= 0.5 A,<br>--<br>102<br>--<br>ns|
|dIF/ dt = 100 A/µs<br>Qrr<br>Reverse Recovery Charge<br>--<br>0.26<br>--<br>µC|



1. Repetitive Rating : Pulse width limited by maximum junction temperature. 

2. L = 75 mH, IAS = 1.6 A, VDD = 50 V, RG = 25 Ω , starting TJ = 25[o] C. 

3. ISD ≤ 0.5 A, di/dt ≤ 300 A/μs, VDD ≤ BVDSS, starting TJ = 25[o] C. 

4. Essentially independent of operating temperature. 

5. a) Reference point of the RθJL is the drain lead. 

- b) When mounted on 3”x4.5” FR-4 PCB without any pad copper in a still air environment. 

- (RθJA  is the sum of the junction-to-case and case-to-ambient thermal resistance. RθCA  is determined by the user’s board design) 

www.fairchildsemi.com 

©2002 Fairchild Semiconductor Corporation SSN1N45B Rev. C0 

**2** 

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                    VTop :       15.0 VGS<br>                10.0 V<br>8.0 V<br>6.0 V ro —<br>5.5 V<br>100 5.0 V<br>Bottom :    4.5 V<br>100 150℃<br>25℃<br>-55℃<br>10-1 v=<br>※ Notes : ※ Notes :<br>1. 2502. TC = 25μ s Pulse Test℃  1. V 2. 250DS = 50Vμ s Pulse Test<br>10-1 100 101 10-1 2 4 6 8 10<br>VDS, Drain-Source Voltage [V] VGS , Gate-Source Voltage  [V]<br>Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics<br>12<br>10<br>8 VGS = 10V 100<br>VGS = 20V<br>6<br>4<br>150℃ 25℃<br>2 ※ Note : TJ = 25℃ ※1. V2. 250 Notes :GS = 0Vμ s Pulse Test<br>0 10-1<br>0 1 2 3 4 5 0.2 0.4 0.6 0.8 1.0 1.2 1.4<br>ID, Drain Current [A] VSD, Source-Drain voltage [V]<br>Figure 3. On-Resistance Variation  vs. Figure 4. Body Diode Forward Voltage<br>Drain Current and Gate Voltage Variation with Source Current<br>and Temperature<br>400 CCCissossrss = C = C = Cgsgdds + C + Cgdgd (Cds = shorted) 12 VDS = 90V<br>10<br>300 VDS = 225V Ss<br>Ciss 8 VDS = 360V<br>200 Coss 6<br>Li<br>4<br>100 Crss ※   1. V2. f = 1 MHz Note ;GS = 0 V<br>2<br>※ Note : ID = 0.5 A<br>010-1 100 101 0 0 1 2 3 4 5 6 7<br>VDS, Drain-Source Voltage [V] QG, Total Gate Charge [nC]<br>, Drain Current [A]ID  , Drain Current  [A]ID<br>],<br>Ω  [<br>DS(ON)<br>R<br>, Reverse Drain Current [A]<br>IDR<br>Drain-Source On-Resistance<br>Capacitance [pF]<br>, Gate-Source Voltage [V]<br>GS<br>V<br>**----- End of picture text -----**<br>


**Figure 5. Capacitance Characteristics** 

**Figure 6. Gate Charge Characteristics** 

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©2002 Fairchild Semiconductor Corporation SSN1N45B Rev. C0 

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(continued)<br>1.2 3.0<br>2.5<br>1.1<br>2.0<br>1.0 1.5<br>1.0<br>0.9 ※ Notes :<br>2. I1. VDGS = 250  = 0 Vμ A 0.5 ※1. V2. I Notes :DGS = 0.25 A = 10 V<br>0.8 0.0<br>-100 -50 0 50 100 150 200 -100 -50 0 50 100 150 200<br>TJ, Junction Temperature [oC] TJ, Junction Temperature [oC]<br>Figure 7. Breakdown Voltage Variation Figure 8. On-Resistance Variation<br>vs. Temperature vs. Temperature<br>0.6<br>Operation in This Area<br>101 is Limited by R DS(on) 0.5<br>100 µs<br>100 1 ms 0.4<br>10 ms<br>100 ms<br>1 s 0.3<br>10-1<br>DC<br>0.2<br>※ Notes :<br>10-2 1. T3. Single Pulse2. TCJ = 150  = 25 oCoC 0.1<br>10-310 4Sa 0 101 10 o 2 103 0.025 ia 50 75 100 125 150<br>VDS, Drain-Source Voltage [V] TC, Case Temperature [℃]<br>Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current<br>vs. Case Temperature<br>1 0 2<br>D = 0 .5<br>1 0 1 0 .2<br>0 .1<br>0 .0 5 PDM<br>1 0 0 0 .0 20 .0 1 =— ee t1 t2<br>s in g le  p u ls e ※  N o te s  :<br>   1 . Z θ JL [(t) =  5 0 ] ℃ /W  M a x.<br>   2 . D u ty  F a ctor, D = t   3 . T JM  - T L =  P D M * Z1 θ/tJL 2 [(t)]<br>1 0 -11 0 Fw Patti -5 1 0 -4 1 0 -3 1 0 -2 1 0 -1 1 0 0 1 0 1 1 0 2 1 0 3<br>t1,  R e c t a n g u l a r  P u l s e  D u r a t i o n  [ s e c ]<br>Figure 11. Transient Thermal Response Curve<br>, (Normalized)  , (Normalized)<br>DSS DS(ON)<br>BV R<br>Drain-Source On-Resistance<br>Drain-Source Breakdown Voltage<br>, Drain Current [A]ID , Drain Current [A]ID<br>oC/W](t), Thermal Response [<br>ZJL θ<br>**----- End of picture text -----**<br>


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©2002 Fairchild Semiconductor Corporation SSN1N45B Rev. C0 

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VGS<br>Same Type<br>50KΩ as DUT Qg<br>12V 200nF 300nF 10V<br>VGS VDS Qgs Qgd<br>DUT<br>IG = const. 3mA<br>Charge<br>**----- End of picture text -----**<br>


**Figure 12. Gate Charge Test Circuit & Waveform** 

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VDS RL VDS 90%<br>VGS VDD<br>RG<br>10%<br>V 10V GS DUT VGS<br>td(on) tr td(off) tf<br>t on t off<br> Figure 13. Resistive Switching Test Circuit & Waveforms<br>VDS L EAS = ----12 L IAS2 --------------------BVBVDSSDSS- VDD<br>I D BVDSSIAS<br>RG VDD ID (t)<br>VV 10V GSGS DUT VDD VDS (t)<br>t p t p Time<br>**----- End of picture text -----**<br>


**Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms** 

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©2002 Fairchild Semiconductor Corporation SSN1N45B Rev. C0 

**5** 

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DUT +<br>VDS<br>_<br>I SD<br>L<br>Driver<br>RG<br>Same Type<br>as DUT VDD<br>VGS • dv/dt controlled by  RG<br>• ISD controlled by pulse period<br>Gate Pulse Width<br>VGS D = --------------------------<br>Gate Pulse Period 10V<br>( Driver )<br>AB<br>IFM , Body Diode Forward Current<br>I SD<br>( DUT ) di/dt<br>IRM<br>4 Ne<br>Body Diode Reverse Current<br>VDS<br>( DUT ) Body Diode Recovery dv/dt<br>VSD VDD<br>tT<br>Body Diode<br>Forward Voltage Drop<br>**----- End of picture text -----**<br>


**Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms** 

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©2002 Fairchild Semiconductor Corporation SSN1N45B Rev. C0 

**6** 

## **Mechanical Dimensions** 

## **Figure 16. TO92, Molded, 3-Lead, 0.200 In Line Spacing LD Form ( J61Z Option)** 

_Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products._ 

_Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:_ 

_http://www.fairchildsemi.com/package/packageDetails.html?id=PN_TO92-F03_ 

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©2002 Fairchild Semiconductor Corporation SSN1N45B Rev. C0 

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