SRDA05-4R2G.

## SRDA05-4R2 

## Low Capacitance Surface Mount TVS for High-Speed Data Interfaces 

The SRDA05-4 transient voltage suppressor is designed to protect equipment attached to high speed communication lines from ESD, EFT, and lightning. 

## **Features** 

## • 

## • S 

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IEC 61000-4-2 (ESD) 15 kV (air) 8 kV (contact) IEC 61000-4-4 (EFT) 40 A (5/50 ns) IEC 61000-4-5 (lightning) 23 (8/20 s) u 

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## **SO-8  LOW CAPACITANCE VOLTAGE SUPPRESSOR 500 WATTS PEAK POWER 6 VOLTS** 

## **PIN CONFIGURATION AND SCHEMATIC** 

- 

## • 

## **Typical Applications** 

## • 

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I/O 1   1 8   REF 2<br>REF 1   2 7   I/O 4<br>REF 1   3 6   I/O 3<br>I/O 2   4 5   REF 2<br>**----- End of picture text -----**<br>


## **MAXIMUM RATINGS** 

|**MAXIMUM RATINGS**||||
|---|---|---|---|
|**Rating**|**Symbol**|**Value**|**Unit**|
|Peak Power Dissipation<br>8 x 20 S @ TA= 25°C (Note 1)<br>wu|Ppk|500|W|
|Junction and Storage Temperature Range|TJ, Tstg||°C|
|Lead Solder Temperature -<br>Maximum 10 Seconds Duration|TL|260|°C|



Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Non-repetitive current pulse 8 x 20 S exponential decay waveform 

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SOIC-8<br>8<br>CASE 751<br>1 PLASTIC<br>**----- End of picture text -----**<br>


## **MARKING DIAGRAM** 

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8<br>SRDA5<br>AYWW<br>1<br>**----- End of picture text -----**<br>


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SRDA5 = Device Code<br>A = Assembly Location<br>Y = Year<br>WW = Work Week<br>= Pb-Free Package<br>**----- End of picture text -----**<br>


(Note: Microdot may be in either location) 

## **ORDERING INFORMATION** 

|**Device**|**Package**|**Shipping**†|
|---|---|---|
|SRDA05-4R2|SO-8|2500/Tape & Reel|
|SRDA05-4R2G|SO-8<br>(Pb-Free)|2500/Tape & Reel|



†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 

Publication Order Number: **SRDA05-4R2/D** 

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© Semiconductor **June, 2007 - Rev. 5** 

**SRDA05-4R2** 

## **ELECTRICAL CHARACTERISTICS** 

|**ELECTRICAL CHARACTERISTICS**||||||
|---|---|---|---|---|---|
|**Characteristic**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|Reverse Breakdown Voltage @ It= 1.0 mA|VBR|6.0|-|-|V|
|Reverse Leakage Current @ VRWN= 5.0 V|IR|N/A|-|10|�A|
|Maximum Clamping Voltage @ IPP= 1.0 A, 8 x 20�S|VC|N/A|-|9.8|V|
|Maximum Clamping Voltage @ IPP= 10 A, 8 x 20�S|VC|N/A|-|12|V|
|Between I/O Pins and Ground @ VR= 0 V, 1.0 MHz|Capacitance|-|10|15|pF|
|Between I/O Pins @ VR= 0 Volts, 1.0 MHz|Capacitance|-|5|8|pF|



## **ELECTRICAL CHARACTERISTICS** 

(TA = 25°C unless otherwise noted) 

**UNIDIRECTIONAL** (Circuit tied to Pins 1 and 3 or 2 and 3) 

|**Symbol**|**Parameter**|
|---|---|
|IPP|Maximum Reverse Peak Pulse Current|
|VC|Clamping Voltage @ IPP|
|VRWM|Working Peak Reverse Voltage|
|IR|Maximum Reverse Leakage Current @ VRWM|
|VBR|Breakdown Voltage @ IT|
|IT|Test Current|
|�VBR|Maximum Temperature Coefficient of VBR|
|IF|Forward Current|
|VF|Forward Voltage @ IF|
|ZZT|Maximum Zener Impedance @ IZT|
|IZK|Reverse Current|
|ZZK|Maximum Zener Impedance @ IZK|



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I<br>IF<br>VC VBR VRWM<br>V<br>IR VF<br>IT<br>IPP<br>Uni-Directional TVS<br>**----- End of picture text -----**<br>


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**SRDA05-4R2** 

## **TYPICAL CHARACTERISTICS** 

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9 8<br>8 7<br>7<br>6<br>6<br>5<br>5<br>4<br>4<br>3<br>3<br>2<br>2<br>1 1<br>0 0<br>-100 -50 0 50 100 150 200 -100 -50 0 50 100 150 200<br>T, TEMPERATURE (°C) T, TEMPERATURE (°C)<br>Figure 1. Reverse Breakdown versus Figure 2. Reverse Leakage versus<br>Temperature Temperature<br>100 35<br>tr PEAK VALUE IRSM @ 8 �s<br>90<br>30<br>80 PULSE WIDTH (tP) IS DEFINED<br>AS THAT POINT WHERE THE<br>70 PEAK CURRENT DECAY = 8 �s 25<br>60<br>20<br>HALF VALUE IRSM/2 @ 20 �s<br>50<br>15<br>40<br>30 10<br>tP<br>20<br>5<br>10<br>0 0<br>0 20 40 60 80 0 10 20 30 40 50 60 70 80 90<br>t, TIME (�s) IPP, PEAK PULSE CURRENT (A)<br>A)<br>�<br>, REVERSE LEAKAGE (<br>, REVERSE BREAKDOWN (V)Z IR<br>V<br>, CLAMPING VOLTAGE (V)<br>C<br>% OF PEAK PULSE CURRENT V<br>**----- End of picture text -----**<br>


**Figure 3. 8 x 20 �s Pulse Waveform** 

**Figure 4. Clamping Voltage versus Peak Pulse Current** 

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**SRDA05-4R2** 

## **APPLICATIONS INFORMATION** 

The SRDA05-4R2 is a low capacitance TVS diode array designed to protect sensitive electronics such as communications systems, computers, and computer peripherals against damage due to ESD events or transient overvoltage conditions. Because of its low capacitance, it can be used in high speed I/O data lines. The integrated design of the SRDA05-4R2 offers surge rated, low capacitance steering diodes and a TVS diode integrated in a single package (SO-8). If a transient condition occurs, the steering diodes will drive the transient to the positive rail of the power supply or to ground. The TVS device protects the power line against overvoltage conditions avoiding damage to the power supply and other downstream components. 

## **SRDA05-4R2  Configuration Options** 

The SRDA05-4R2 is able to protect up to four data lines against transient overvoltage conditions by driving them to a fixed reference point for clamping purposes. The steering diodes will be forward biased whenever the voltage on the protected line exceeds the reference voltage (Vf or Vcc+Vf). The diodes will force the transient current to bypass the sensitive circuit. 

Data lines are connected at pins 1, 4, 6 and 7. The negative reference is connected at pins 5 and 8. These pins must be connected directly to ground using a ground plane to minimize the PCB's ground inductance. It is very important to reduce the PCB trace lengths as much as possible to minimize parasitic inductances. 

## **Option 1** 

Protection of four data lines and the power supply using Vcc as reference. 

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I/O 1<br>I/O 2<br>1 8<br>2 7<br>VCC<br>3 6<br>4 5<br>I/O 3<br>I/O 4<br>**----- End of picture text -----**<br>


**Figure 5.** 

For this configuration, connect pins 2 and 3 directly to the positive supply rail (Vcc). The data lines are referenced to the supply voltage. The internal TVS diode prevents overvoltage on the supply rail. Biasing of the steering diodes reduces their capacitance. 

## **Option 2** 

Protection of four data lines with bias and power supply isolation resistor. 

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I/O 1<br>I/O 2<br>VCC<br>1 8<br>10 K<br>2 7<br>3 6<br>4 5<br>I/O 3<br>I/O 4<br>**----- End of picture text -----**<br>


**Figure 6.** 

The SRDA05-4R2 can be isolated from the power supply by connecting a series resistor between pins 2 and 3 and Vcc. A 10 k� resistor is recommended for this application. This will maintain a bias on the internal TVS and steering diodes, reducing their capacitance. 

## **Option 3** 

Protection of four data lines using the internal TVS diode as reference. 

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I/O 1<br>I/O 2<br>1 8<br>NC 2 7<br>NC 3 6<br>4 5<br>I/O 3<br>I/O 4<br>**----- End of picture text -----**<br>


**Figure 7.** 

In applications lacking a positive supply reference or those cases in which a fully isolated power supply is required, the internal TVS can be used as the reference. For these applications, pins 2 and 3 are not connected. In this configuration, the steering diodes will conduct whenever the voltage on the protected line exceeds the working voltage of the TVS plus one diode drop (Vc=Vf + VTVS). 

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**SRDA05-4R2** 

## **ESD Protection of Power Supply Lines** 

When using diodes for data line protection, referencing to a supply rail provides advantages. Biasing the diodes reduces their capacitance and minimizes signal distortion. Implementing this topology with discrete devices does have disadvantages. This configuration is shown below: 

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Power<br>Supply IESDpos<br>VCC<br>D1 IESDpos<br>Protected Data Line IESDneg<br>Device<br>D2<br>IESDneg VF + VCC<br>-VF<br>**----- End of picture text -----**<br>


**Figure 8.** 

Looking at the figure above, it can be seen that when a positive ESD condition occurs, diode D1 will be forward biased while diode D2 will be forward biased when a negative ESD condition occurs. For slower transient conditions, this system may be approximated as follows: 

For positive pulse conditions: Vc = Vcc + VfD1 

For negative pulse conditions: 

Vc = -VfD2 

ESD events can have rise times on the order of some number of nanoseconds. Under these conditions, the effect of parasitic inductance must be considered. A pictorial representation of this is shown below. 

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Power<br>Supply IESDpos<br>VCC<br>D1 IESDpos<br>Protected IESDneg<br>Device<br>Data Line<br>D2 VC = VCC + Vf + (L diESD/dt)<br>IESDneg<br>VC = -Vf - (L diESD/dt)<br>Figure 9.<br>**----- End of picture text -----**<br>


An approximation of the clamping voltage for these fast transients would be: 

For positive pulse conditions: Vc = Vcc + Vf + (L diESD/dt) 

For negative pulse conditions: Vc = -Vf – (L diESD/dt) 

As shown in the formulas, the clamping voltage (Vc) not only depends on the Vf of the steering diodes but also on the 

L diESD/dt factor. A relatively small trace inductance can result in hundreds of volts appearing on the supply rail. This endangers both the power supply and anything attached to that rail. This highlights the importance of good board layout. Taking care to minimize the effects of parasitic inductance will provide significant benefits in transient immunity. 

Even with good board layout, some disadvantages are still present when discrete diodes are used to suppress ESD events across datalines and the supply rail. Discrete diodes with good transient power capability will have larger die and therefore higher capacitance. This capacitance becomes problematic as transmission frequencies increase. Reducing capacitance generally requires reducing die size. These small die will have higher forward voltage characteristics at typical ESD transient current levels. This voltage combined with the smaller die can result in device failure. 

The ON Semiconductor SRDA05- 4R2 was developed to overcome the disadvantages encountered when using discrete diodes for ESD protection. This device integrates a TVS diode within a network of steering diodes. 

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D1 D3 D5 D7<br>D2 D4 D6 D8<br>0<br>**----- End of picture text -----**<br>


**Figure 10. SRDA05-4R2 Equivalent Circuit** 

During an ESD condition, the ESD current will be driven to ground through the TVS diode as shown below. 

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Power<br>Supply<br>VCC<br>D1 IESDpos<br>Protected<br>Device<br>Data Line<br>D2<br>**----- End of picture text -----**<br>


**Figure 11.** 

The resulting clamping voltage on the protected IC will be: 

Vc = VFD1 + VTVS. 

The clamping voltage of the TVS diode is provided in Figure 4 and depends on the magnitude of the ESD current. The steering diodes are fast switching devices with unique forward voltage and low capacitance characteristics. 

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**SRDA05-4R2** 

## **TYPICAL APPLICATIONS** 

UPSTREAM USB PORT 

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VBUS<br>VBUS<br>VBUS<br>RT VBUS<br>D+ D+<br>DOWNSTREAM<br>RT<br>D- D- USB PORT<br>VBUS USB VBUS<br>GND Controller SRDA05-4R2 GND<br>CT CT<br>VBUS<br>VBUS<br>NUP2201MR6 RT<br>D+ DOWNSTREAM<br>RT USB PORT<br>D-<br>GND<br>CT CT<br>**----- End of picture text -----**<br>


**Figure 12. ESD Protection for USB Port** 

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RJ45<br>Connector<br>TX+ TX+<br>TX-<br>TX-<br>Coupling<br>PHY Transformers<br>RX+<br>Ethernet RX+<br>(10/100)<br>RX-<br>RX-<br>SRDA05-4R2<br>VCC<br>GND<br>N/C N/C<br>**----- End of picture text -----**<br>


**Figure 13. Protection for Ethernet 10/100 (Differential Mode)** 

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**SRDA05-4R2** 

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R1<br>RTIP<br>R3<br>R2<br>RRING<br>T1<br>VCC<br>T1/E1<br>TRANCEIVER<br>SRDA05-4R2<br>R4<br>TTIP<br>R5<br>TRING<br>T2<br>**----- End of picture text -----**<br>


**Figure 14. TI/E1 Interface Protection** 

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**SRDA05-4R2** 

## **PACKAGE DIMENSIONS** 

**SOIC-8  NB** CASE 751-07 ISSUE AH 

- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 

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-X- 1. DIMENSIONING AND TOLERANCING PER<br>ANSI Y14.5M, 1982.<br>A 2. CONTROLLING DIMENSION: MILLIMETER.<br>3. DIMENSION A AND B DO NOT INCLUDE<br>MOLD PROTRUSION.<br>4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)<br>8 5 PER SIDE.<br>ars 5. DIMENSION D DOES NOT INCLUDE DAMBAR<br>B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR<br>PROTRUSION SHALL BE 0.127 (0.005) TOTAL<br>1 IN EXCESS OF THE D DIMENSION AT<br>4 MAXIMUM MATERIAL CONDITION.<br>-Y- K 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW<br>STANDARD IS 751-07.<br>a G MILLIMETERS INCHES<br>DIM MIN MAX MIN MAX<br>C N X 45 A 4.80 5.00 0.189 0.197<br>B 3.80 4.00 0.150 0.157<br>SEATINGPLANE 4 p ee C 1.35 1.75 0.053 0.069<br>-Z- D 0.33 0.51 0.013 0.020<br>G 1.27 BSC 0.050 BSC<br>0.10 (0.004) H 0.10 0.25 0.004 0.010<br>=S H D L Ry M J KJ 0.190.40 0.251.27 0.0070.016 0.0100.050 =<br>M 0  8  0  8<br>N 0.25 0.50 0.010 0.020<br>0.25 (0.010) M Z Y S X S S 5.80 6.20 0.228 0.244<br>SOLDERING FOOTPRINT*<br>1.52<br>0.060<br>aan<br>7.0 4.0<br>0.275 a 0.155<br>0.6 1.270<br>0.024 9006 0.050<br>SCALE 6:1 mm<br>inches<br>*For additional information on our Pb-Free strategy and soldering<br>details, please download the ON Semiconductor Soldering and<br>Mounting Techniques Reference Manual, SOLDERRM/D.<br>**----- End of picture text -----**<br>


5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 

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**SRDA05-4R2/D** 

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