SMMBF4393LT1G

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## JFET Switching Transistors 

## N **-** Channel 

## MMBF4391L, MMBF4392L, MMBF4393L 

2 SOURCE 

## **Features** 

- S Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC-Q101 Qualified and PPAP Capable 

- These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant 

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3<br>GATE<br>**----- End of picture text -----**<br>


1 DRAIN 

**MAXIMUM RATINGS** 

|**MAXIMUM RATINGS**|**MAXIMUM RATINGS**|
|---|---|
|**Rating**<br>**Symbol**<br>**Value**<br>**Unit**<br>Drain-Source Voltage<br>VDS<br>30<br>Vdc<br>Drain-Gate Voltage<br>VDG<br>30<br>Vdc<br>Gate-Source Voltage<br>VGS<br>30<br>Vdc<br>Forward Gate Current<br>IG(f)<br>50<br>mAdc<br>~~ee~~||
|**THERMAL CHARACTERISTICS**<br>**Characteristic**<br>**Symbol**<br>**Max**<br>**Unit**<br>Total Device Dissipation FR-5 Board<br>(Note 1) TA= 25C<br>Derate above 25C<br>PD<br>225<br>1.8<br>mW<br>mW/<br>C<br>Thermal Resistance, Junction-to-Ambient<br>R JA<br>556<br>C/W<br>Junction and Storage Temperature<br>Range<br>TJ, Tstg<br>−55 to<br>+150<br>C<br>Stresses exceeding those listed in the Maximum Ratings table may damage the<br>~~oT~~<br>~~ee~~<br>~~ee ee~~||
|device. If any of these limits are exceeded, device functionality should not be||
|assumed, damage may occur and reliability may be affected.||
|1. FR-5 = 1.00.750.062 in.||



## **MARKING DIAGRAM** 

XXX M 

1 

XXX = Specific Device Code M = Date Code* = Pb−Free Package 

(Note: Microdot may be in either location) 

- Date Code orientation and/or overbar may vary depending upon manufacturing location. 

## **MARKING & ORDERING INFORMATION** 

See detailed ordering, marking and shipping information on page 2 of this data sheet. 

Publication Order Number: **MMBF4391LT1/D** 

**1** 

 Semiconductor Components Industries, LLC, 1994 **July, 2025 − Rev. 14** 

## **MMBF4391L, MMBF4392L, MMBF4393L** 

**ELECTRICAL CHARACTERISTICS** (TA = 25 C unless otherwise noted) 

|**Characteristic**<br>**Symbol**<br>**Min**<br>**Max**<br>**Unit**<br>**OFF CHARACTERISTICS**<br>~~a~~|
|---|
|Gate-Source Breakdown Voltage<br>(IG= 1.0 Adc, VDS= 0)<br>V(BR)GSS<br>30<br>−<br>Vdc<br>Gate Reverse Current<br>(VGS= 15 Vdc, VDS= 0, TA= 25C)<br>(VGS= 15 Vdc, VDS= 0, TA= 100C)<br>IGSS<br>−<br>−<br>1.0<br>0.20<br>nAdc<br>Adc<br>Gate-Source Cutoff Voltage<br>(VDS= 15 Vdc, ID= 10 nAdc)<br>MMBF4391LT1<br>MMBF4392LT1<br>MMBF4393LT1<br>VGS(off)<br>−4.0<br>−2.0<br>−0.5<br>−10<br>−5.0<br>−3.0<br>Vdc<br>Off-State Drain Current<br>(VDS= 15 Vdc, VGS= −12 Vdc)<br>(VDS= 15 Vdc, VGS= −12 Vdc, TA= 100C)<br>ID(off)<br>−<br>−<br>1.0<br>1.0<br>nAdc<br>Adc<br>**ON CHARACTERISTICS**<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee ee ee~~<br>~~Po~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|Zero-Gate-Voltage Drain Current<br>(VDS= 15 Vdc, VGS= 0)<br>MMBF4391LT1<br>MMBF4392LT1<br>MMBF4393LT1<br>IDSS<br>50<br>25<br>5.0<br>150<br>75<br>30<br>mAdc<br>~~po~~|
|Drain-Source On-Voltage<br>VDS(on)<br>Vdc|
|(ID= 12 mAdc, VGS= 0)|
|MMBF4391LT1<br>−<br>0.4|
|(ID= 6.0 mAdc, VGS= 0)|
|MMBF4392LT1<br>−<br>0.4|
|(ID= 3.0 mAdc, VGS= 0)|
|MMBF4393LT1<br>−<br>0.4|
|Static Drain-Source On-Resistance<br>(ID= 1.0 mAdc, VGS= 0)<br>MMBF4391LT1<br>MMBF4392LT1<br>MMBF4393LT1<br>rDS(on)<br>−<br>−<br>−<br>30<br>60<br>100<br>~~po~~|
|**SMALL-SIGNAL CHARACTERISTICS**|
|Input Capacitance<br>(VDS= 0 Vdc, VGS= −15 Vdc, f = 1.0 MHz)<br>Ciss<br>−<br>14<br>pF<br>Reverse Transfer Capacitance<br>(VDS= 0 Vdc, VGS= −12 Vdc, f = 1.0 MHz)<br>Crss<br>−<br>3.5<br>pF<br>Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product<br>performance may not be indicated by the Electrical Characteristics if operated under different conditions.<br>~~————~~<br>~~oe~~|



## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**||||
|---|---|---|---|
|**Device**|**Marking**|**Package**|**Shipping**†|
|MMBF4391LT1G|6J|SOT-23<br>(Pb-Free)|3,000 / Tape & Reel|
|SMMBF4391LT1G*|6J|||
|MMBF4392LT1G|6K|||
|MMBF4393LT1G|M6G|||
|SMMBF4393LT1G*|M6G|||



† For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

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**MMBF4391L, MMBF4392L, MMBF4393L** 

## **TYPICAL CHARACTERISTICS** 

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1000<br>500 = — T J  = 25  C<br>200 Billie RK = RD' el MMBF4391MMBF4392 ie VGS(off) = 12 V= 7.0 V<br>MMBF4393 = 5.0 V<br>100<br>50<br>20 PPS<br>10<br>At ss,<br>5.0 RK = 0<br>2.0 Soe sae a<br>1.0<br>0.5 PEP 0.7 1.0 P = fe 2.0 3.0 PST 5.0 7.0 10 20 30 dd 50<br>ID , DRAIN CURRENT (mA)<br>, TURN-ON DELAY TIME (ns)<br>d(on)<br>t<br>**----- End of picture text -----**<br>


**Figure 1. Turn-On Delay Time** 

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1000 T J  = 25  C<br>500 S55SoH RK = R oT D' SSS MMBF4391 eee VGS(off) = 12 V ———<br>MMBF4392 = 7.0 V<br>200<br>MMBF4393 = 5.0 V<br>100<br>50<br>20 Pe<br>10 U RK = 0 T<br>5.0<br>2.0<br>Sa N T<br>1.0<br>0.5 PUTT 0.7 1.0 Per 2.0 3.0 5.0 7.0 10 gk 20 30 db 50<br>ID , DRAIN CURRENT (mA)<br>, RISE TIME (ns)<br>rt<br>**----- End of picture text -----**<br>


**Figure 2. Rise Time** 

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**----- Start of picture text -----**<br>
1000<br>500 TJ = 25  C<br>200 MMBF4391MMBF4392 VGS(off) = 12 V= 7.0 V<br>100 MMBF4393 = 5.0 V<br>50 RK = RD'<br>S270 SS ee ee<br>20<br>10 Pssta | | See<br>a SS St<br>5.0 RK = 0<br>a ptePPtry | a a SnSs eee<br>2.0<br>1.0 LIT se<br>0.5 0.7 1.0 TT 2.0 3.0 | PP 5.0 7.0 10 Pt 20 30 50<br>ID , DRAIN CURRENT (mA)<br>, TURN-OFF DELAY TIME (ns)<br>td(off)<br>**----- End of picture text -----**<br>


**Figure 3. Turn-Off Delay Time** 

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1000<br>500 T J  = 25  C<br>R K  = R D' MMBF4391 VGS(off) = 12 V<br>200 MMBF4392 = 7.0 V<br>MMBF4393 = 5.0 V<br>100<br>50<br>Potty PSSA OTSNe<br>20<br>RK = 0<br>10 FE | ZaRRSSERRR |}<br>eee See<br>5.0<br>PPee T eePsee ee e e<br>2.0<br>1.0 Ps<br>0.5 LUT 0.7 1.0 TT 2.0 3.0 TPT 5.0 7.0 10 Pt 20 30 50<br>ID , DRAIN CURRENT (mA)<br>, FALL TIME (ns)<br>ft<br>**----- End of picture text -----**<br>


**Figure 4. Fall Time** 

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## **NOTE 1** 

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VDD<br>RD<br>SET VDS(off) = 10 V<br>INPUT RK Drain-Source Voltage (VDS) is slightly lower than Drain Supply<br>RT Voltage (VDDDD) due to the voltage divider. Thus Reverse Transfer<br>R50 GEN = RGG €) OUTPUT Capacitance (Crssrss) of Gate-Drain Capacitance (Cgd) is charged to<br>QQ 50  VGG + VDS.GG + VDS. + VDS.DS..<br>50  Q<br>VGEN VGG<br>miele<br>INPUT PULSE RGG > RK discharge to VDS(on)DS(on) through RG and RK in series with the parallel<br>tr  0.25 ns<br>tf  0.5 ns RD’ = RD(RT + 50)<br>PULSE WIDTH = 2.0 s vo RD + RT + 50 Resistance (rDSDS). During the turn-off, this charge flow is reversed.<br>DUTY CYCLE  2.0%<br>resistance rDSDS is a function of the gate-source voltage. While Cgs<br>Figure 5. Switching Time Test Circuit discharges, VGSGS approaches zero and rDS decreases. Since Cgd<br>discharges through rDSDS, turn-on time is non-linear. During turn-off,<br>RK is equal to RD’K is equal to RD’ is equal to RD’D’ which simulates the switching behavior of<br>20 1510<br>THLE MMBF4392 EA 10<br>MMBF4391<br>10 -Laat2cin| 7.0<br>MMBF4393<br>7.0 5.0<br>5.0 A. CA Tchannel = 25  C oo OA<br>pea VDS = 15 V Ht ++ 3.0 atl<br>2.0<br>3.0 ZeTE WEHt fttT tTTT 1.5 itmailmail<br>2.0 TTA TTI 1.0<br>0.03 0.05 0.1<br>0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50<br>ID , DRAIN CURRENT (mA)<br>C, CAPACITANCE (pF)<br>, FORWARD TRANSFER ADMITTANCE (mmhos)<br>fs<br>Y<br>**----- End of picture text -----**<br>


The switching characteristics shown above were measured using a test circuit similar to Figure 5. At the beginning of the switching interval, the gate voltage is at Gate Supply Voltage (−VGG). The Drain-Source Voltage (VDS) is slightly lower than Drain Supply Voltage (VDDDD) due to the voltage divider. Thus Reverse Transfer Capacitance (Crssrss) of Gate-Drain Capacitance (Cgd) is charged to VGG + VDS.GG + VDS. + VDS.DS.. 

During the turn-on interval, Gate-Source Capacitance (Cgs) discharges through the series combination of RGen and RK. Cgd must discharge to VDS(on)DS(on) through RG and RK in series with the parallel combination of effective load impedance (R’D) and Drain-Source Resistance (rDSDS). During the turn-off, this charge flow is reversed. 

Predicting turn-on time is somewhat difficult as the channel resistance rDSDS is a function of the gate-source voltage. While Cgs discharges, VGSGS approaches zero and rDS decreases. Since Cgd discharges through rDSDS, turn-on time is non-linear. During turn-off, the situation is reversed with rDS increasing as Cgd charges. 

The above switching curves show two impedance conditions; 1) RK is equal to RD’K is equal to RD’ is equal to RD’D’ which simulates the switching behavior of cascaded stages where the driving source impedance is normally the load impedance of the previous stage, and 2) RK = 0 (low impedance) the driving source impedance is that of the generator. 

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1510 Un<br>C gs<br>7.0 PSHEa<br>5.0 C gd<br>HESSOA AsSS<br>3.0 atl T channel  = 25  C PAIS<br>2.0 (C ds  is negligible<br>1.5 itmailmail SoSie<br>1.0 CACO Coin<br>0.03 0.05 0.1 0.3 0.5 1.0 3.0 5.0 10 30<br>VR, REVERSE VOLTAGE (VOLTS)<br>Figure 7. Typical Capacitance<br>2.0<br>ID = 1.0 mA<br>1.8 VGS = 0 | [| | | |<br>1.6 EE -<br>1.4 A<br>a<br>1.2 | | | | Pe<br>1.0 Pt |Prt<br>0.8 tt<br>P| PT tT<br>0.6 aT<br>0.4 |a| [ | | {| | | |<br>-70 -40 -10 20 50 80 110 140 170<br>Tchannel, CHANNEL TEMPERATURE (  C)<br>C, CAPACITANCE (pF)<br>, DRAIN-SOURCE ON-STATE<br>RESISTANCE (NORMALIZED)<br>DS(on)<br>r<br>**----- End of picture text -----**<br>


**Figure 6. Typical Forward Transfer Admittance** 

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**----- Start of picture text -----**<br>
200<br>IDSS 25 mA 50 mA 75 mA 100 mA 125 mA<br>= 10 es ee<br>160 mA<br>eae<br>120 TATvray eeei of<br>A) ee<br>80 (anVAVAVAV7 an Aw Aan<br>40 ZZ  AES ane<br>2a Tchannel = 25  C<br>0 ee<br>0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0<br>VGS, GATE‐SOURCE VOLTAGE (VOLTS)<br>RESISTANCE (OHMS)<br>, DRAIN-SOURCE ON-STATE<br>DS(on)<br>r<br>**----- End of picture text -----**<br>


**Figure 8. Effect of Gate-Source Voltage on Drain-Source Resistance** 

**Figure 9. Effect of Temperature on Drain-Source On-State Resistance** 

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## **NOTE 2** 

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**----- Start of picture text -----**<br>
100 Tchannel = 25  C 10<br>90 ee e 9.0<br>a e<br>80 8.0<br>70 rDS(on) @ VGS = 0 7.0<br>Nee ae<br>60 Ni Vanuen 6.0<br>50 VGS(off) 5.0<br>PRET<br>40 ONE 4.0<br>30 oe-Saeee 3.0<br>Se2e8en.——=2008<br>20 ACE 2.0<br>10 PEEP ere eee 1.0<br>0 0<br>10 20 30 40 50 60 70 80 90 100 110 120 130 140 150<br>IDSS, ZERO‐GATE VOLTAGE DRAIN CURRENT (mA)<br>(VOLTS)<br>, DRAIN-SOURCE ON-STATE RESISTANCE (OHMS) , GATE-SOURCE VOLTAGE<br>GS<br>V<br>rDS(on)<br>**----- End of picture text -----**<br>


The Zero-Gate-Voltage Drain Current (IDSS) is the principle determinant of other J-FET characteristics. Figure 10 shows the relationship of Gate-Source Off Voltage (VGS(off)) and Drain-Source On Resistance (rDS(on)) to IDSS. Most of the devices will be within  10% of the values shown in Figure 10. This data will be useful in predicting the characteristic variations for a given part number. 

The electrical characteristics table indicates that an MMBF4392 has an IDSS range of 25 to 75 mA. Figure 10 shows rDS(on) = 52 Q for IDSS = 25 mA and 30  for Q IDSS = 75 mA. The corresponding VGS values are 2.2 V and 4.8 V. 

**Figure 10. Effect of IDSS on Drain-Source Resistance and Gate-Source Voltage** 

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## **REVISION HISTORY** 

|**Revision**|**Description of Changes**|**Date**|
|---|---|---|
|14|The Y−axis label in Figure 6 has been corrected.<br>Removed missing information of NOTE 2.|07/03/2025|



This document has undergone updates prior to the inclusion of this revision history table. The changes tracked here only reflect updates made on the noted approval dates. 

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MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

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SOT−23 (TO−236) 2.90x1.30x1.00 1.90P<br>CASE 318<br>ISSUE AU<br>DATE 14 AUG 2024<br>**----- End of picture text -----**<br>


**SCALE 4:1** 

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GENERIC<br>MARKING DIAGRAM*<br>XXXM �<br>�<br>1<br>XXX = Specific Device Code<br>M = Date Code<br>� = Pb−Free Package<br>**----- End of picture text -----**<br>


*This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ � ”, may or may not be present. Some products may not follow the Generic Marking. 

## **STYLES ON PAGE 2** 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98ASB42226B** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: SOT−23 (TO−236) 2.90x1.30x1.00 1.90P PAGE 1 OF 2** 

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DATE 14 AUG 2024 

## **SOT−23 (TO−236) 2.90x1.30x1.00 1.90P** CASE 318 ISSUE AU 

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STYLE 1 THRU 5: STYLE 6: STYLE 7: STYLE 8:<br>CANCELLED PIN 1. BASE PIN 1. EMITTER PIN 1. ANODE<br>2. EMITTER 2. BASE 2. NO CONNECTION<br>3. COLLECTOR 3. COLLECTOR 3. CATHODE<br>STYLE 9: STYLE 10: STYLE 11: STYLE 12: STYLE 13: STYLE 14:<br>PIN 1. ANODE PIN 1. DRAIN PIN 1. ANODE PIN 1. CATHODE PIN 1. SOURCE PIN 1. CATHODE<br>2. ANODE 2. SOURCE 2. CATHODE 2. CATHODE 2. DRAIN 2. GATE<br>3. CATHODE 3. GATE 3. CATHODE−ANODE 3. ANODE 3. GATE 3. ANODE<br>STYLE 15: STYLE 16: STYLE 17: STYLE 18: STYLE 19: STYLE 20:<br>PIN 1. GATE PIN 1. ANODE PIN 1. NO CONNECTION PIN 1. NO CONNECTION PIN 1. CATHODE PIN 1. CATHODE<br>2. CATHODE 2. CATHODE 2. ANODE 2. CATHODE 2. ANODE 2. ANODE<br>3. ANODE 3. CATHODE 3. CATHODE 3. ANODE 3. CATHODE−ANODE 3. GATE<br>STYLE 21: STYLE 22: STYLE 23: STYLE 24: STYLE 25: STYLE 26:<br>PIN 1. GATE PIN 1. RETURN PIN 1. ANODE PIN 1. GATE PIN 1. ANODE PIN 1. CATHODE<br>2. SOURCE 2. OUTPUT 2. ANODE  2. DRAIN  2. CATHODE  2. ANODE<br>3. DRAIN 3. INPUT 3. CATHODE  3. SOURCE  3. GATE  3. NO CONNECTION<br>STYLE 27: STYLE 28:<br>PIN 1. CATHODE PIN 1. ANODE<br> 2. CATHODE  2. ANODE<br> 3. CATHODE  3. ANODE<br>**----- End of picture text -----**<br>


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Electronic versions are uncontrolled except when accessed directly from the Document Repository.<br>DOCUMENT NUMBER: 98ASB42226B Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red.<br>DESCRIPTION: SOT−23 (TO−236) 2.90x1.30x1.00 1.90P PAGE 2 OF 2<br>**----- End of picture text -----**<br>


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