SI7129DN-T1-GE3

**Si7129DN** 

~~—~~ www.vishay.com 

Vishay Siliconix 

## **P-Channel 30 V (D-S) MOSFET** 

## **FEATURES** 

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PowerPAK [®]  1212-8 Single<br>D<br>D 8<br>D 7<br>D 6<br>5<br>1<br>2 S<br>3 S<br>1 4 S<br>G<br>Top View Bottom View<br>3.3 mm<br>3.3 mm<br>**----- End of picture text -----**<br>


- TrenchFET[®] power MOSFET 

- Low thermal resistance PowerPAK[®] package with small size and low 1.07 mm profile 

- 100 % Rg and UIS tested 

- Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 

## **APPLICATIONS** 

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S<br>G<br>D<br>P-Channel MOSFET<br>**----- End of picture text -----**<br>


- Load switch 

- Adaptor switch 

**PRODUCT SUMMARY** • Notebook PC VDS (V) -30 RDS(on) max. (  ) at VGS = -10 V 0.0114 RDS(on) max. (  ) at VGS = -4.5 V 0.0200 Qg typ. (nC) 24.6 ID (A)[e, f] -35 Configuration Single ~~oo~~ **ORDERING INFORMATION** Package PowerPAK 1212-8 Lead (Pb)-free and halogen-free Si7129DN-T1-GE3 

- Notebook PC 

~~pC~~ **ABSOLUTE MAXIMUM RATINGS** (TA = 25 °C, unless otherwise noted) ~~GO~~ **PARAMETER SYMBOL LIMIT UNIT** Drain-source voltage VDS -30 V Gate-source voltage VGS ± 20 TC = 25 °C -35[e] ~~apT PO~~ TC = 70 °C -35[e] Continuous drain current (TJ = 150 °C) ID TA = 25 °C -14.4[a, b] ~~apo~~ TA = 70 °C ~~po~~ -11.5[a, b] A Pulsed drain current IDM -60 ~~J — a po~~ TC = 25 °C -35[e] Continuous source-drain diode current IS ~~SS~~ TA = 25 °C -3.2[a, b] Avalanche current IAS -25 ~~po~~ L = 0.1 mH ~~po~~ Single pulse avalanche energy EAS 31.25 mJ TC = 25 °C 52.1 ~~a pT pO~~ TC = 70 °C 3.3 Maximum power dissipation ~~po~~ PD ~~pO~~ W TA = 25 °C 3.8[a, b] TA = 70 °C 2.4[a, b] ~~po pO~~ Operating junction and storage temperature range TJ, Tstg -50 to +150 °C ~~SSa~~ Soldering recommendations (peak temperature)[c, d ] 260 **Notes** a. Surface mounted on 1" x 1" FR4 board 

b. t = 10 s 

- c. See solder profile (www.vishay.com/doc?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection 

- d. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components 

- e. Package limited 

- f. Based on TC = 25 °C 

S10-2023-Rev. B, 06-Sep-10 

Document Number: 68966 

**1** 

For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Si7129DN** 

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www.vishay.com 

Vishay Siliconix 

|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|**THERMAL RESISTANCE RATINGS**|||
|---|---|---|---|---|---|
|**PARAMETER**||**SYMBOL**|**TYPICAL**|**MAXIMUM**|**UNIT**|
|Maximum junction-to-ambienta, b|t10 s|RthJA|26|33|°C/W|
|Maximum junction-to-case (drain)|Steady state|RthJC|1.9|2.4||



## **Notes** 

a. Surface mounted on 1" x 1" FR4 board b. Maximum under steady state conditions is 81 °C/W 

|**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)|**SPECIFICATIONS**(TJ= 25 °C,unless otherwise noted)|||||
|---|---|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**TEST CONDITIONS**|**MIN.**|**TYP.**|**MAX.**|**UNIT**|
|**Static**|||||||
|Drain-source breakdown voltage|VDS|VGS= 0 V, ID= -250μA|-30|-|-|V|
|VDStemperature coefficient|VDS/TJ|ID= -250 μA|-|-20|-|mV/°C|
|VGS(th)temperature coefficient|VGS(th)/TJ||-|5|-||
|Gate-source threshold voltage|VGS(th)|VDS= VGS, ID= -250μA|-1.5|-|-2.8|V|
|Gate-source leakage|IGSS|VDS= 0 V, VGS= ± 20 V|-|-|± 100|nA|
|Zero gate voltage drain current|IDSS|VDS= -30 V, VGS= 0 V|-|-|-1|μA|
|||VDS= -30 V, VGS= 0 V, TJ= 55 °C|-|-|-10||
|On-state drain currenta|ID(on)|VDS-5 V, VGS= -10 V|-20|-|-|A|
|Drain-source on-state resistancea|RDS(on)|VGS= -10 V, ID= -14.4 A|-|0.0095|0.0114||
|||VGS= -4.5 V, ID= -11.5 A|-|0.0160|0.0200||
|Forward transconductancea|gfs|VDS= -15 V, ID= -14.4 A|-|37|-|S|
|**Dynamicb**|||||||
|Input capacitance|Ciss|VDS= -15 V, VGS= 0 V, f = 1 MHz|-|2230|3345|pF|
|Output capacitance|Coss||-|385|578||
|Reverse transfer capacitance|Crss||-|322|-||
|Total gate charge|Qg|VDS= -15 V, VGS= -10 V, ID= -14.4 A|-|47.5|71|nC|
|||VDS= -15 V, VGS= -4.5 V, ID= -14.4 A|-|24.6|37||
|Gate-source charge|Qgs||-|7.7|-||
|Gate-drain charge|Qgd||-|12|-||
|Gate resistance|Rg|f = 1 MHz|0.4|1.8|3.6||
|Turn-on delaytime|td(on)|VDD= -15 V, RL= 1.5<br>ID -10 A, VGEN= -4.5 V, Rg= 1|-|50|75|ns|
|Rise time|tr||-|43|65||
|Turn-off delaytime|td(off)||-|30|45||
|Fall time|tf||-|14|21||
|Turn-on delaytime|td(on)|VDD= -15 V, RL= 1.5<br>ID -10 A, VGEN= -10 V, Rg= 1|-|14|21||
|Rise time|tr||-|9|18||
|Turn-off delaytime|td(off)||-|36|54||
|Fall time|tf||-|10|20||
|**Drain-Source Body Diode Characteristics**|||||||
|Continuous source-drain diode current|IS|TC= 25 °C|-|-|-35|A|
|Pulse diode forward currenta|ISM||-|-|-60||
|Bodydiode voltage|VSD|IF= -10 A|-|-0.8|-1.2|V|
|Bodydiode reverse recoverytime|trr|IF= -10 A, di/dt = 100 A/μs,<br>TJ= 25 °C|-|31|47|ns|
|Bodydiode reverse recoverycharge|Qrr||-|30|45|nC|
|Reverse recoveryfall time|ta||-|15|-|ns|
|Reverse recoveryrise time|tb||-|16|-||



## **Notes** 

a. Pulse test: pulse width  300 μs, duty cycle  2 % 

b. Guaranteed by design, not subject to production testing 

_Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability._ 

S10-2023-Rev. B, 06-Sep-10 

Document Number: 68966 

**2** For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Si7129DN** 

Vishay Siliconix 

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www.vishay.com 

## **TYPICAL CHARACTERISTICS** (25 °C, unless otherwise noted) 

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60<br>VGS = 10 V thru 5 V<br>45<br>4 V<br>30<br>15<br>0<br>0 3 6 9 12 15<br>VDS - Drain-to-Source Voltage (V)<br>Output Characteristics<br>0.030<br>0.025<br>VGS = 4.5 V<br>0.020<br>0.015<br>VGS = 10 V<br>0.010<br>0.005<br>0.000<br>0 10 20 30 40 50 60<br>ID - Drain Current (A)<br>On-Resistance vs. Drain Current and Gate Voltage<br>10<br>8<br>VDS = 15 V, ID = 14.4 A<br>6<br>4<br>VDS = 24 V, ID = 14.4 A<br>2<br>0<br>0 10 20 30 40 50<br>Qg - Total Gate Charge (nC)<br>Gate Charge<br> - Drain Current (A)<br>ID<br>)Ω<br> (m<br> - On-Resistance<br>DS<br>R<br>- Gate-to-Source Voltage (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**On-Resistance vs. Drain Current and Gate Voltage** 

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1.2<br>0.9<br>125 ºC<br>0.6<br>25 ºC<br>0.3<br>-55 ºC<br>0.0<br>0 1 2 3 4<br>VGS - Gate-to-Source Voltage (V)<br> - Drain Current (A)<br>ID<br>**----- End of picture text -----**<br>


## **Transfer Characteristics** 

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3600<br>3000<br>Ciss<br>2400<br>1800<br>1200<br>600 Coss<br>Crss<br>0<br>0 6 12 18 24 30<br>VDS - Drain-Source Voltage (V)<br>C - Capacitance (pF)<br>**----- End of picture text -----**<br>


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Capacitance<br>**----- End of picture text -----**<br>


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1.8<br>ID = 14.4 A<br>1.5<br>VGS = 10 V<br>1.2<br>VGS = 4.5 V<br>0.9<br>0.6<br>-50 -25 0 25 50 75 100 125 150<br>TJ - Junction Temperature (ºC)<br>On-Resistance vs. Junction Temperature<br> - On-Resistance (normalized)<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


S10-2023-Rev. B, 06-Sep-10 

Document Number: 68966 

**3** 

For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Si7129DN** 

Vishay Siliconix 

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www.vishay.com<br>**----- End of picture text -----**<br>


## **TYPICAL CHARACTERISTICS** (25 °C, unless otherwise noted) 

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100<br>TJ = 150 ºC<br>10<br>TJ = 25 ºC<br>1<br>0.1<br>0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VSD - Source-to-Drain Voltage (V)<br> - Source Current (A)<br>IS<br>**----- End of picture text -----**<br>


## **Source-Drain Diode Forward Voltage** 

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2.4<br>ID = 250 µA<br>2.2<br>2.0<br>1.8<br>1.6<br>1.4<br>1.2<br>-50 -25 0 25 50 75 100 125 150<br>TJ - Temperature (ºC)<br> (V)<br>GS(th)<br>V<br>**----- End of picture text -----**<br>


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Threshold Voltage<br>**----- End of picture text -----**<br>


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0.04<br>0.03<br>0.02<br>TJ = 125 ºC<br>0.01<br>TJ = 25 ºC<br>0.00<br>0 2 4 6 8 10 12 14 16 18 20<br>VGS - Gate-to-Source Voltage (V)<br>On-Resistance vs. Gate-to-Source Voltage<br>50<br>40<br>30<br>20<br>10<br>0<br>0.01 0.1 1.0 10 100 1000<br>Time (s)<br>)Ω<br> - Drain-to-Source On-Resistance (<br>DS(on)<br>R<br>(W)<br>Power<br>**----- End of picture text -----**<br>


**Single Pulse Power, Junction-to-Ambient** 

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100<br>Limited  by RDS(on) (1) 100 µs<br>10<br>1 ms<br>10 ms<br>1<br>100 ms<br>1 s<br>10 s<br>0.1<br>TA = 25 ºC DC<br>Single pulse BVDSS limited<br>0.01<br>0.1 1 10 100<br>            VDS - Drain-to-Source Voltage (V)<br>(1) VGS > minimum VGS at which RDS(on) is specified<br>Safe Operating Area, Junction-to-Ambient<br> - Drain Current (A)<br>ID<br>**----- End of picture text -----**<br>


S10-2023-Rev. B, 06-Sep-10 

Document Number: 68966 

**4** 

For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Si7129DN** 

Vishay Siliconix 

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www.vishay.com 

## **TYPICAL CHARACTERISTICS** (25 °C, unless otherwise noted) 

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60<br>50<br>40<br>30<br>20<br>10<br>0<br>0 25 50 75 100 125 150<br>TC - CaseTemperature (°C)<br> - Drain Current (A)<br>ID<br>**----- End of picture text -----**<br>


**Current Derating[a]** 

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75 2<br>60<br>1.5<br>45<br>1<br>30<br>0.5<br>15<br>0 0<br>0 25 50 75 100 125 150 0 25 50 75 100 125 150<br>TC - Case Temperature (ºC) TA - Ambient Temperature (ºC)<br>Power, Junction-to-Case Power, Junction-to-Ambient<br>Power (W) Power (W)<br>**----- End of picture text -----**<br>


## **Note** 

a. The power dissipation PD is based on TJ max. = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit 

S10-2023-Rev. B, 06-Sep-10 

Document Number: 68966 

**5** For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Si7129DN** 

Vishay Siliconix 

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## **TYPICAL CHARACTERISTICS** (25 °C, unless otherwise noted) 

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1<br>Duty cycle = 0.5<br>0.2<br>0.1 Notes:<br>0.1<br>P DM<br>0.05<br>t1<br>0.02 1. Duty cycle, D = t2 tt12<br>2. Per unit base = RthJA = 50 °C/W<br>3. TJM - TA = PDMZthJA [(t)]<br>Single pulse 4. Surface mounted<br>0.01<br>10 [-4] 10 [-3] 10 [-2] 10 [-1] 1 10 100 1000<br>Square Wave Pulse Duration (s)<br>Thermal Impedance<br>Normalized Effective Transient<br>**----- End of picture text -----**<br>


## **Normalized Thermal Transient Impedance, Junction-to-Ambient** 

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1<br>Duty cycle = 0.5<br>0.2<br>0.1<br>0.1<br>0.05<br>0.02<br>Single pulse<br>0.01<br>10 [-4] 10 [-3] 10 [-2] 10 [-1] 1<br>Square Wave Pulse Duration (s)<br>Thermal Impedance<br>Normalized Effective Transient<br>**----- End of picture text -----**<br>


**Normalized Thermal Transient Impedance, Junction-to-Case** 

_Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?68966._ 

S10-2023-Rev. B, 06-Sep-10 

Document Number: 68966 

**6** 

For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**Package Information** Vishay Siliconix 

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## **PowerPAK[®] 1212-8, (Single / Dual)** 

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L<br>H E2 K<br>W E4<br>8<br>1 1<br>Z<br>2<br>2<br>3<br>4 5 4<br>L1 E3<br>A1<br>Backside view of single pad<br>L<br>H E2 K<br>E4<br>H<br>2<br>1<br>E1 Detail Z D1<br>E 2<br>Notes 3<br>1. Inch will govern<br>2  Dimensions exclusive of mold gate burrs D2 4<br>3. Dimensions exclusive of mold flash and cutting burrs<br>E3<br>Backside view of dual pad<br>θ θ<br>θ<br>θ<br>D4<br>M<br>e<br>D1 D D2 D5<br>b<br>A<br>c<br>D4<br>3(2x)<br>D<br>D2 D5<br>K1<br>b<br>**----- End of picture text -----**<br>


|**DIM.**|**MILLIMETERS**<br>**INCH**|**MILLIMETERS**<br>**INCH**|**MILLIMETERS**<br>**INCH**|
|---|---|---|---|
||**MIN.**|**NOM.**|**MAX.**<br>**MIN.**<br>**NOM**|
|A|0.97|1.04|1.12<br>0.038<br>0.04|
|A1|0.00|-|0.05<br>0.000<br>-|
|b|0.23|0.30|0.41<br>0.009<br>0.01|
|c|0.23|0.28|0.33<br>0.009<br>0.01|
|D|3.20|3.30|3.40<br>0.126<br>0.13|
|D1|2.95|3.05|3.15<br>0.116<br>0.12|
|D2|1.98|2.11|2.24<br>0.078<br>0.08|
|D3|0.48|-|0.89<br>0.019<br>-|
|D4|0.47 typ.<br>0.0185|||
|D5|2.3 typ.<br>0.090|||
|E|3.20|3.30|3.40<br>0.126<br>0.13|
|E1|2.95|3.05|3.15<br>0.116<br>0.12|
|E2|1.47|1.60|1.73<br>0.058<br>0.06|
|E3|1.75|1.85|1.98<br>0.069<br>0.07|
|E4|0.034 typ.<br>0.013|||
|e|0.65 BSC<br>0.026|||
|K|0.86 typ.<br>0.034|||
|K1|0.35|-|-<br>0.014<br>-|
|H|0.30|0.41|0.51<br>0.012<br>0.01|
|L|0.30|0.43|0.56<br>0.012<br>0.01|
|L1|0.06|0.13|0.20<br>0.002<br>0.00|
||0°|-|12°<br>0°<br>-|
|W|0.15|0.25|0.36<br>0.006<br>0.01|
|M|0.125 typ.<br>0.005|||
|ECN: S16-2667-Rev. M, 09-Jan-17<br>DWG: 5882||||



Revison: 09-Jan-17 

**1** 

Document Number: 71656 

For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 

**AN822** 

Vishay Siliconix 

## **PowerPAK**[®] 

## **1212 Mounting and Thermal Considerations** 

## **Johnson Zhao** 

MOSFETs for switching applications are now available with die on resistances around 1 m Ω and with the capability to handle 85 A. While these die capabilities represent a major advance over what was available just a few years ago, it is important for power MOSFET packaging technology to keep pace. It should be obvious that degradation of a high performance die by the package is undesirable. PowerPAK is a new package technology that addresses these issues. The PowerPAK 1212-8 provides ultra-low thermal impedance in a small package that is ideal for space-constrained applications. In this application note, the PowerPAK 1212-8’s construction is described. Following this, mounting information is presented. Finally, thermal and electrical performance is discussed. 

## **THE PowerPAK PACKAGE** 

The PowerPAK 1212-8 package (Figure 1) is a derivative of PowerPAK SO-8. It utilizes the same packaging technology, maximizing the die area. The bottom of the die attach pad is exposed to provide a direct, low resistance thermal path to the substrate the device is mounted on. The PowerPAK 1212-8 thus translates the benefits of the PowerPAK SO-8 into a smaller package, with the same level of thermal performance. (Please refer to application note “PowerPAK SO-8 Mounting and Thermal Considerations.”) 

The PowerPAK 1212-8 has a footprint area comparable to TSOP-6. It is over 40 % smaller than standard TSSOP-8. Its die capacity is more than twice the size of the standard TSOP-6’s. It has thermal performance an order of magnitude better than the SO-8, and 20 times better than TSSOP-8. Its thermal performance is better than all current SMT packages in the market. It will take the advantage of any PC board heat sink capability. Bringing the junction temperature down also 

increases the die efficiency by around 20 % compared with TSSOP-8. For applications where bigger packages are typically required solely for thermal consideration, the PowerPAK 1212-8 is a good option. 

Both the single and dual PowerPAK 1212-8 utilize the same pin-outs as the single and dual PowerPAK SO-8. The low 1.05 mm PowerPAK height profile makes both versions an excellent choice for applications with space constraints. 

## **PowerPAK 1212 SINGLE MOUNTING** 

To take the advantage of the single PowerPAK 1212-8’s thermal performance see Application Note 826, 

_Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs._ Click on the PowerPAK 1212-8 single in the index of this document. 

In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package. 

This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in[2] of will yield little improvement in thermal performance. 

**Figure 1.** PowerPAK 1212 Devices 

Document Number 71681 03-Mar-06 

www.vishay.com 

1 

**AN822** ~~oC~~ Vishay Siliconix 

## **PowerPAK 1212 DUAL** 

To take the advantage of the dual PowerPAK 1212-8’s thermal performance, the minimum recommended land pattern can be found in Application Note 826, _Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs_ . Click on the PowerPAK 1212-8 dual in the index of this document. 

ture profile used, and the temperatures and time duration, are shown in Figures 2 and 3. For the lead (Pb)-free solder profile, see http://www.vishay.com/ doc?73257. 

The gap between the two drain pads is 10 mils. This matches the spacing of the two drain pads on the PowerPAK 1212-8 dual package. 

This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions 

of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in[2] of will yield little improvement in thermal performance. 

## **REFLOW SOLDERING** 

Vishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a preconditioning test and are then reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow tempera- 

|Ramp-Up Rate|+ 6°C /Second Maximum|
|---|---|
|Temperature at 155 ± 15°C|120 Seconds Maximum|
|Temperature Above 180°C|70 - 180 Seconds|
|Maximum Temperature|240 + 5/- 0°C|
|Time at Maximum Temperature|20 - 40 Seconds|
|Ramp-Down Rate|+ 6°C/Second Maximum|



**Figure 2.** Solder Reflow Temperature Profile 

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| 10 s (max) |<br>210 - 220 °C —_—_<br>3 °C/s (max) —— 4 °C/s (max)<br>183 °C<br>140 - 170 °C | |<br>50 s (max)<br>pe —|<br>| |<br>3° C/s (max) 60 s (min) Reflow Zone<br>Pre-Heating Zone<br>| i |<br>Maximum peak temperature at 240 °C is allowed.<br>**----- End of picture text -----**<br>


**Figure 3.** Solder Reflow Temperatures and Time Durations 

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Vishay Siliconix 

|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|**TABLE 1: EQIVALENT STEADY STATE PERFORMANCE**|
|---|---|---|---|---|---|---|---|---|---|---|
|**Package**|**SO-8**||**TSSOP-8**||**TSOP-8**||**PPAK 1212**||**PPAK SO-8**||
|**Configuration**|**Single**|**Dual**|**Single**|**Dual**|**Single**|**Dual**|**Single**|**Dual**|**Single**|**Dual**|
|Thermal Resiatance RthJC(C/W)|20|40|52|83|40|90|2.4|5.5|1.8|5.5|
||||||||||||
|PowerPAK 1212<br>Standard SO-8<br>Standard TSSOP-8<br>TSOP-6|||||||||||
|2.4 °C/W<br>49.8 °C<br>20 °C/W<br>85 °C<br>PC Board at 45 °C<br>52 °C/W<br>149 °C<br>40 °C/W<br>125 °C|||||||||||
||||||||||||



**Figure 4.** Temperature of Devices on a PC Board 

## **THERMAL PERFORMANCE** 

## **Introduction** 

## **Spreading Copper** 

A basic measure of a device’s thermal performance is the junction-to-case thermal resistance, R θ jc, or the junction to- foot thermal resistance, R θ jf. This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows a comparison of the PowerPAK 1212-8, PowerPAK SO-8, standard TSSOP-8 and SO-8 equivalent steady state performance. 

By minimizing the junction-to-foot thermal resistance, the MOSFET die temperature is very close to the temperature of the PC board. Consider four devices mounted on a PC board with a board temperature of 45 °C (Figure 4). Suppose each device is dissipating 2 W. Using the junction-to-foot thermal resistance characteristics of the PowerPAK 1212-8 and the other SMT packages, die temperatures are determined to be 49.8 °C for the PowerPAK 1212-8, 85 °C for the standard SO-8, 149 °C for standard TSSOP-8, and 125 °C for TSOP-6. This is a 4.8 °C rise above the board temperature for the PowerPAK 1212-8, and over 40 °C for other SMT packages. A 4.8 °C rise has minimal effect on r whereas a rise DS(ON) of over 40 °C will cause an increase in rDS(ON) as high as 20 %. 

Designers add additional copper, spreading copper, to the drain pad to aid in conducting heat from a device. It is helpful to have some information about the thermal performance for a given area of spreading copper. 

Figure 5 and Figure 6 show the thermal resistance of a PowerPAK 1212-8 single and dual devices mounted on a 2-in. x 2-in., four-layer FR-4 PC boards. The two internal layers and the backside layer are solid copper. The internal layers were chosen as solid copper to model the large power and ground planes common in many applications. The top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken. The results indicate that an area above 0.2 to 0.3 square inches of spreading copper gives no additional thermal performance improvement. A subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces, and then totally removed. No significant effect was observed. 

Document Number 71681 03-Mar-06 

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## Vishay Siliconix 

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105<br>Spreading Copper (sq. in.)<br>95<br>85<br>75<br>65<br>100 %<br>55<br>50 %<br>0 %<br>45<br>0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00<br>Figure 5.  Spreading Copper - Si7401DN<br>(°C/W)<br>A<br>J<br>Rht<br>**----- End of picture text -----**<br>


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130<br>120 Spreading Copper (sq. in.)<br>110<br>100<br>90<br>80<br>50 % 100 %<br>70<br>0 %<br>60<br>50<br>0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00<br>(°C/W)<br>A<br>RhJ     t<br>**----- End of picture text -----**<br>


**Figure 6.** Spreading Copper - Junction-to-Ambient Performance 

## **CONCLUSIONS** 

As a derivative of the PowerPAK SO-8, the PowerPAK 1212-8 uses the same packaging technology and has been shown to have the same level of thermal performance while having a footprint that is more than 40 % smaller than the standard TSSOP-8. 

Recommended PowerPAK 1212-8 land patterns are provided to aid in PC board layout for designs using this new package. 

The PowerPAK 1212-8 combines small size with attractive thermal characteristics. By minimizing the thermal rise above the board temperature, PowerPAK simplifies thermal design considerations, allows the device to run cooler, keeps rDS(ON) low, and permits the device to handle more current than a same- or larger-size MOSFET die in the standard TSSOP-8 or SO-8 packages. 

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Revision: 01-Jan-2022 

Document Number: 91000 

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