SI5468DC-T1-GE3

**Si5468DC** 

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Vishay Siliconix 

## **N-Channel 30-V (D-S) MOSFET** 

|**PRODUCT SUMMARY**|**PRODUCT SUMMARY**|**PRODUCT SUMMARY**|**PRODUCT SUMMARY**|
|---|---|---|---|
|**VDS (V)**|**RDS(on) (**Ω**)**|**ID (A)**a|**Qg (Typ.)**|
|30|0.028 at VGS= 10 V|6|3.8 nC|
||0.034 at VGS= 4.5 V|6||



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1206-8 ChipFET [®]<br>1<br>D<br>D D<br>D D<br>Marking Code<br>D G<br>AK    XXX<br>S Lot Traceability<br>and Date Code<br>Part #<br>Code<br>Bottom View<br>**----- End of picture text -----**<br>


**Ordering Information:** Si5468DC-T1-GE3 (Lead (Pb)-free and Halogen-free) 

## **FEATURES** 

- **Halogen-free According to IEC 61249-2-21 Definition** 

- TrenchFET[®] Power MOSFET 

- 100 % R Tested g 

## **APPLICATIONS** 

- System Power 

   - Notebook 

   - Netbook 

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D<br>G<br>S<br>N-Channel MOSFET<br>**----- End of picture text -----**<br>


- Load Switch 

- Low Current DC/DC 

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## **ABSOLUTE MAXIMUM RATINGS** TA = 25 °C, unless otherwise noted 

|**ABSOLUTE MAXIMUM RATINGS**TA= 25 °C, unless otherwise noted|**ABSOLUTE MAXIMUM RATINGS**TA= 25 °C, unless otherwise noted|**ABSOLUTE MAXIMUM RATINGS**TA= 25 °C, unless otherwise noted|**ABSOLUTE MAXIMUM RATINGS**TA= 25 °C, unless otherwise noted|**ABSOLUTE MAXIMUM RATINGS**TA= 25 °C, unless otherwise noted|**ABSOLUTE MAXIMUM RATINGS**TA= 25 °C, unless otherwise noted|
|---|---|---|---|---|---|
|**Parameter**||**Symbol**|**Limit**||**Unit**|
|Drain-Source Voltage||VDS|30||V|
|Gate-Source Voltage||VGS|± 20|||
|Continuous Drain Current (TJ= 150 °C)|TC= 25 °C|ID|6a||A|
||TC= 70 °C||6a|||
||TA= 25 °C||6a,b, c|||
||TA= 70 °C||5.5a,b, c|||
|Pulsed Drain Current||IDM|30|||
|Continuous Source-Drain Diode Current|TC= 25 °C|IS|4.8|||
||TA= 25 °C||1.9b, c|||
|Maximum Power Dissipation|TC= 25 °C|PD|5.7||W|
||TC= 70 °C||3.6|||
||TA= 25 °C||2.3b, c|||
||TA= 70 °C||1.5b, c|||
|OperatingJunction and Storage Temperature Range||TJ, Tstg|- 55 to 150||°C|
|SolderingRecommendations(Peak Temperature)d, e|||260|||
|||||||
|**THERMAL RESISTANCE RATINGS**||||||
|**Parameter**||**Symbol**|**Typical**|**Maximum**|**Unit**|
|Maximum Junction-to-Ambientb, f|t≤5 s|RthJA|45|55|°C/W|
|Maximum Junction-to-Foot(Drain)|SteadyState|RthJF|18|22||



Notes: 

a. Package limited. 

b. Surface Mounted on 1" x 1" FR4 board. 

c. t = 5 s. 

- d. See Solder Profile ( _www.vishay.com/ppg?73257_ ). The 1206-8 ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. 

- e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under Steady State conditions is 95 °C/W. 

Document Number: 69072 S09-0316-Rev. A, 02-Mar-09 

www.vishay.com 

1 

**Si5468DC** 

## Vishay Siliconix 

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|**SPECIFICATIONS**TJ= 25 °C, unless otherwise noted|**SPECIFICATIONS**TJ= 25 °C, unless otherwise noted|**SPECIFICATIONS**TJ= 25 °C, unless otherwise noted|||||
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|**Static**|||||||
|Drain-Source Breakdown Voltage|VDS|VGS= 0 V, ID= 250 µA|30|||V|
|VDSTemperature Coefficient|ΔVDS/TJ|ID= 250 µA||35||mV/°C|
|VGS(th)Temperature Coefficient|ΔVGS(th)/TJ|||- 4.5|||
|Gate-Source Threshold Voltage|VGS(th)|VDS= VGS, ID= 250 µA|1.0||2.5|V|
|Gate-Source Leakage|IGSS|VDS= 0 V, VGS= ± 20 V|||± 100|nA|
|Zero Gate Voltage Drain Current|IDSS|VDS= 30 V, VGS= 0 V|||1|µA|
|||VDS= 30 V, VGS= 0 V, TJ= 55 °C|||5||
|On-State Drain Currenta|ID(on)|VDS≥5 V, VGS= 10 V|20|||A|
|Drain-Source On-State Resistancea|RDS(on)|VGS=10 V, ID= 6.8 A||0.023|0.028|Ω|
|||VGS=4.5 V, ID= 6.2 A||0.028|0.034||
|Forward Transconductancea|gfs|VDS= 10 V, ID= 6.8 A||17||S|
|**Dynamicb**|||||||
|Input Capacitance|Ciss|VDS= 15 V, VGS= 0 V, f = 1 MHz||435||pF|
|Output Capacitance|Coss|||95|||
|Reverse Transfer Capacitance|Crss|||42|||
|Total Gate Charge|Qg|VDS= 15 V, VGS= 10 V, ID= 7.8 A||8|12|nC|
|||VDS= 15 V, VGS= 4.5 V, ID= 7.8 A||3.8|6||
|Gate-Source Charge|Qgs|||1.4|||
|Gate-Drain Charge|Qgd|||1.1|||
|Gate Resistance|Rg|f = 1 MHz|1.5|3.2|4.5|Ω|
|Turn-On Delay Time|td(on)|VDD= 15 V, RL= 2.4Ω<br>ID ≅6.3 A, VGEN= 4.5 V, Rg= 1Ω||15|25|ns|
|Rise Time|tr|||12|20||
|Turn-Off Delay Time|td(off)|||13|20||
|Fall Time|tf|||10|15||
|Turn-On Delay Time|td(on)|VDD= 15 V, RL= 2.4Ω<br>ID ≅6.3 A, VGEN= 10 V, Rg= 1Ω||5|10||
|Rise Time|tr|||10|15||
|Turn-Off Delay Time|td(off)|||15|25||
|Fall Time|tf|||10|15||
|**Drain-Source Body Diode Characteristics**|||||||
|Continuous Source-Drain Diode Current|IS|TC= 25 °C|||4.2|A|
|Pulse Diode Forward Current|ISM||||30||
|Body Diode Voltage|VSD|IS= 6.3 A, VGS= 0 V||0.8|1.2|V|
|Body Diode Reverse Recovery Time|trr|IF= 6.3 A, dI/dt = 100 A/µs, TJ= 25 °C||15|25|ns|
|Body Diode Reverse Recovery Charge|Qrr|||7|12|nC|
|Reverse Recovery Fall Time|ta|||9||ns|
|Reverse Recovery Rise Time|tb|||6|||



Notes: 

a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 % 

b. Guaranteed by design, not subject to production testing. 

_Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability._ 

www.vishay.com 2 

Document Number: 69072 S09-0316-Rev. A, 02-Mar-09 

**Si5468DC** 

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## Vishay Siliconix 

## **TYPICAL CHARACTERISTICS** 25 °C, unless otherwise noted 

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30<br>VGS = 10 V thru 4 V<br>25<br>20<br>15<br>VGS = 3 V<br>10<br>5<br>0<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0<br>VDS - Drain-to-Source Voltage (V)<br>Output Characteristics<br>0.035<br>0.030<br>VGS = 4.5 V<br>0.025 VGS = 10 V<br>0.020<br>0.015<br>0.010<br>0 5 10 15 20 25 30<br>ID - Drain Current (A)<br>On Resistance vs. Drain Current<br>10<br>ID = 7.8 A<br>8<br>6<br>VDS = 15 V VDS = 24 V<br>4<br>2<br>0<br>0 2 4 6 8<br>Qg - Total Gate Charge (nC)<br>Gate Charge<br>- Drain Current (A)<br>I D<br>)Ω<br>- On-Resistance (<br>DS(on)<br>R<br>- Gate-to-Source Voltage (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


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10<br>8<br>6<br>TC = - 55 °C<br>4<br>TC = 25 °C<br>2<br>TC = 125 °C<br>0<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0<br>VGS - Gate-to-Source Voltage (V)<br>Transfer Characteristics<br>600<br>500 Ciss<br>400<br>300<br>200<br>Coss<br>100<br>Crss<br>0<br>0 5 10 15 20 25 30<br>VDS - Drain-to-Source Voltage (V)<br>Capacitance<br>1.8<br>ID = 6.8 A<br>1.6<br>VGS = 10 V<br>1.4<br>VGS = 4.5 V<br>1.2<br>1.0<br>0.8<br>0.6<br>- 50 - 25 0 25 50 75 100 125 150<br>TJ - Junction Temperature (°C)<br>On-Resistance vs. Junction Temperature<br>- Drain Current (A)<br>I D<br>C - Capacitance (pF)<br>- On-Resistance<br>(Normalized)<br>DS(on)<br>R<br>**----- End of picture text -----**<br>


Document Number: 69072 S09-0316-Rev. A, 02-Mar-09 

www.vishay.com 

3 

**Si5468DC** 

## Vishay Siliconix 

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## **TYPICAL CHARACTERISTICS** 25 °C, unless otherwise noted 

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100 0.08<br>ID = 6.8 A<br>0.06<br>TJ = 125 °C<br>10 0.04<br>TJ = 25 °C<br>TJ = 150 °C<br>0.02 TJ = 25 °C<br>1 0.00<br>0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 2 4 6 8 10<br>VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V)<br>)Ω<br>- On-Resistance (<br>- Source Current (A)<br>I S DS(on)<br>R<br>**----- End of picture text -----**<br>


**Forward Diode Voltage vs. Temperature** 

**On-Resistance vs. Gate-Source Voltage** 

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1.9 50<br>1.8<br>1.7 40<br>ID = 250 µA<br>1.6<br>1.5 30<br>1.4<br>1.3 20<br>1.2<br>1.1 10<br>1.0<br>0.9 0<br>- 50 - 25 0 25 50 75 100 125 150 10 [-3] 10 [-2] 10 [-1] 1 10 100 600<br>TJ - Temperature (°C) Time (s)<br>Threshold Voltage Single Pulse Power<br>(V)<br>GS(th)<br>V Power  (W)<br>**----- End of picture text -----**<br>


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100<br>Limited by RDS(on)*<br>10<br>1 ms<br>10 ms<br>1<br>TA = 25 °C 100 ms<br>Single Pulse 1 s<br>0.1 10 s<br>100 s<br>DC<br>BVDSS Limited<br>0.01<br>0.1 1 10 100<br>VDS - Drain-to-Source Voltage (V)<br>* VGS > minimum VGS at which RDS(on) is specified<br>Safe Operating Area, Junction-to-Ambient<br>Drain Current (A)<br>-<br>ID<br>**----- End of picture text -----**<br>


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Document Number: 69072 S09-0316-Rev. A, 02-Mar-09 

**Si5468DC** 

Vishay Siliconix 

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## **TYPICAL CHARACTERISTICS** 25 °C, unless otherwise noted 

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12<br>9<br>Package Limited<br>6<br>3<br>0<br>0 25 50 75 100 125 150<br>TC - Case Temperature (°C)<br>Current Derating*<br>Drain Current (A)<br>-<br>I D<br>**----- End of picture text -----**<br>


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6<br>5<br>4<br>3<br>2<br>1<br>0<br>25 50 75 100 125 150<br>TC - Case Temperature (°C)<br>Power Derating<br>Power (W)<br>**----- End of picture text -----**<br>


* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. 

Document Number: 69072 S09-0316-Rev. A, 02-Mar-09 

www.vishay.com 

5 

**Si5468DC** 

## Vishay Siliconix 

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## **TYPICAL CHARACTERISTICS** 25 °C, unless otherwise noted 

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2<br>1<br>Duty Cycle = 0.5<br>0.2<br>Notes:<br>0.1<br>0.1 PDM<br>0.05<br>t1<br>t2 t1<br>0.02 1. Duty Cycle, D = t2<br>2. Per Unit Base = R thJA = 80 °C/W<br>3. TJM  - TA = PDMZthJA [(t)]<br>Single Pulse 4. Surface Mounted<br>0.01<br>10 [-4] 10 [-3] 10 [-2] 10 [-1] 1 10 100 600<br>Square Wave Pulse Duration (s)<br>Normalized Thermal Transient Impedance, Junction-to-Ambient<br>2<br>1<br>Duty Cycle = 0.5<br>0.2<br>0.1<br>0.1<br>0.05<br>0.02<br>Single Pulse<br>0.01<br>10 [-4] 10 [-3] 10 [-2] 10 [-1] 1 10<br>Square Wave Pulse Duration (s)<br>Thermal Impedance<br>Normalized Effective Transient<br>Thermal Impedance<br>Normalized Effective Transient<br>**----- End of picture text -----**<br>


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Normalized Thermal Transient Impedance, Junction-to-Foot<br>**----- End of picture text -----**<br>


_Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?69072._ 

www.vishay.com 

Document Number: 69072 S09-0316-Rev. A, 02-Mar-09 

6 

**Package Information Vishay Siliconix** 

## 1206-8 ChipFET 

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4<br>L<br>D<br>8 7 6 5<br>5 6 7 8<br>4 E1 E<br>PC —T T1 L —_<br>4 3 2 1<br>1 2 3 4<br>lta<br>x<br>S e b c Backside View<br>Pt fo ; —<br>2X 0.10/0.13 R<br>A<br>C i l e<br>DETAIL X<br>C1<br>**----- End of picture text -----**<br>


A C ~~i~~ 

## NOTES: 

1. All dimensions are in millimeaters. 

2. Mold gate burrs shall not exceed 0.13 mm per side. 

3. Leadframe to molded body offset is horizontal and vertical shall not exceed 0.08 mm. 

4. Dimensions exclusive of mold gate burrs. 

5. No  mold flash allowed on the top and bottom lead surface. 

|**Dim**<br>~~_~~|MILLIMETERS<br>~~rr~~|MILLIMETERS<br>~~rr~~|MILLIMETERS<br>~~rr~~|INCHES<br>~~rr~~|INCHES<br>~~rr~~|INCHES<br>~~rr~~|
|---|---|---|---|---|---|---|
||**Min**<br>~~rr~~|**Nom**<br>~~rr~~|**Max**<br>~~rr~~|**Min**<br>~~rr~~|**Nom**<br>~~rr~~|**Max**<br>~~rr~~|
|**A**<br>~~_~~|1.00<br>~~rr~~|−<br>~~rr~~|1.10<br>~~rr~~|0.039<br>~~rr~~|−<br>~~rr~~|0.043<br>~~rr~~|
|**b**<br>~~_~~|0.25<br>~~rr~~|0.30<br>~~rr~~|0.35<br>~~rr~~|0.010<br>~~rr~~|0.012<br>~~rr~~|0.014<br>~~rr~~|
|**c**|0.1|0.15|0.20|0.004|0.006|0.008|
|**c1**|0|−|0.038|0|−|0.0015|
|**D**|2.95|3.05|3.10|0.116|0.120|0.122|
|**E**|1.825|1.90|1.975|0.072|0.075|0.078|
|**E1**|1.55|1.65|1.70|0.061|0.065|0.067|
|**e**|0.65 BSC|||0.0256 BSC|||
|**L**<br>~~——~~|0.28<br>~~——~~|−<br>~~——~~|0.42<br>~~——~~|0.011|−|0.017|
|**S**<br>~~——~~|0.55 BSC<br>~~——~~|||0.022 BSC|||
|~~——~~|5 Nom<br>~~——~~|||5 Nom|||
|ECN:  C-03528—Rev. F, 19-Jan-04<br>DWG:  5547<br>~~——~~|||||||



Document Number:  71151 15-Jan-04 

www.vishay.com 

**1** 

**AN811** ~~So~~ **Vishay Siliconix** 

## **Single-Channel 1206-8 ChipFET** ® **Power MOSFET Recommended Pad Pattern and Thermal Performance** 

## INTRODUCTION 

New Vishay Siliconix ChipFETs in the leadless 1206-8 package feature the same outline as popular 1206-8 resistors and capacitors but provide all the performance of true power semiconductor devices. The 1206-8 ChipFET has the same footprint as the body of the LITTLE FOOT TSOP-6, and can be thought of as a leadless TSOP-6 for purposes of visualizing ® board area, but its thermal performance bears comparison with the much larger SO-8. 

This technical note discusses the single-channel ChipFET 1206-8 pin-out, package outline, pad patterns, evaluation board layout, and thermal performance. 

## PIN-OUT 

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a 80 mil<br>F fF<br>Ei 68 mil<br>E<br>F J<br>mm<br>28 mil<br>26 mil Jal<br>**----- End of picture text -----**<br>


**FIGURE 2.** Footprint With Copper Spreading 

Figure 1 shows the pin-out description and Pin 1 identification for the single-channel 1206-8 ChipFET device. The pin-out is similar to the TSOP-6 configuration, with two additional drain pins to enhance power dissipation and thermal performance. The legs of the device are very short, again helping to reduce the thermal path to the external heatsink/pcb and allowing a larger die to be fitted in the device if necessary. 

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Single 1206-8 ChipFE T<br>1<br>D<br>D D<br>D D<br>D G<br>S<br>Bottom View<br>FIGURE 1.<br>**----- End of picture text -----**<br>


For package dimensions see the 1206-8 ChipFET package outline drawing (http://www.vishay.com/doc?71151). 

## BASIC PAD PATTERNS 

The basic pad layout with dimensions is shown in Application Note 826, _Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFET_ s, (http://www.vishay.com/doc?72286). This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. 

The pad pattern with copper spreading shown in Figure 2 improves the thermal area of the drain connections (pins 1,2,3,6.7,8) while remaining within the confines of the basic footprint. The drain copper area is 0.0054 sq. in. or 3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. An example of this method is implemented on the Vishay Siliconix Evaluation Board described in the next section (Figure 3). 

## THE VISHAY SILICONIX EVALUATION BOARD FOR THE SINGLE 1206-8 

The ChipFET 1206-08 evaluation board measures 0.6 in by 0.5 in. Its copper pad pattern consists of an increased pad area around the six drain leads on the top-side—approximately 0.0482 sq. in. 31.1 sq. mm—and vias added through to the underside of the board, again with a maximized copper pad area of approximately the board-size dimensions. The outer package outline is for the 8-pin DIP, which will allow test sockets to be used to assist in testing. 

The thermal performance of the 1206-8 on this board has been measured with the results following on the next page. The testing included comparison with the minimum recommended footprint on the evaluation board-size pcb and the industry standard one-inch square FR4 pcb with copper on both sides of the board. 

Document Number:  71126 12-Dec-03 

www.vishay.com 

**1** 

## **AN811 Vishay Siliconix** ~~a~~ wv 

Front of Board 

Back of Board 

**FIGURE 3.** 

## THERMAL PERFORMANCE 

## **Junction-to-Foot Thermal Resistance (the Package Performance)** 

Thermal performance for the 1206-8 ChipFET measured as junction-to-foot thermal resistance is 15 C/W typical, 20 C/W maximum for the single device. The “foot” is the drain lead of the device as it connects with the body. This is identical to the SO-8 package R jf[ performance, a feat made possible by] shortening the leads to the point where they become only a small part of the total footprint area. | **Junction-to-Ambient Thermal Resistance (dependent on pcb size)** The typical R ja[ for the single-channel 1206-8 ChipFET is] 80 C/W steady state, compared with 68 C/W for the SO-8. a Maximum ratings are 95 C/W for the 1206-8 versus 80 C/W for the SO-8. 

## **Testing** 

To aid comparison further, Figure 4 illustrates ChipFET 1206-8 thermal performance on two different board sizes and three different pad patterns. The results display the thermal performance out to steady state and produce a graphic account of how an increased copper pad area for the drain connections can enhance thermal performance. The measured steady state values of R ja[ for the single 1206-8] ChipFET are : 

1) Minimum recommended pad pattern (see 156 C/W Figure 2) on the evaluation board size of 0.5 in x 0.6 in. 2) The evaluation board with the pad pattern 111 C/W described on Figure 3. ~~ee~~ 3) Industry standard 1” square pcb with 78 ~~ee~~ C/W maximum copper both sides. ~~eeee~~ 

The results show that a major reduction can be made in the thermal resistance by increasing the copper drain area. In this example, a 45 C/W reduction was achieved without having to increase the size of the board. If increasing board size is an option, a further 33 C/W reduction was obtained by maximizing the copper from the drain on the larger 1” square pcb. 

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160120 UA AD A {| Single EVB<br>Min. Footprint<br>80 |<br>s a<br>40 1” Square PCB<br>U e<br>0 WaT<br>10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 1 10 100 1000<br>Time (Secs)<br>FIGURE 4.  Single 1206 − 8 ChipFET<br>Thermal Resistance (C/W)<br>**----- End of picture text -----**<br>


## SUMMARY 

The thermal results for the single-channel 1206-8 ChipFET package display similar power dissipation performance to the SO-8 with a footprint reduction of 80%. Careful design of the package has allowed for this performance to be achieved. The short leads allow the die size to be maximized and thermal resistance to be reduced within the confines of the TSOP-6 body size. 

## ASSOCIATED DOCUMENT 

1206-8 ChipFET Dual Thermal performance, AN812 (http://www.vishay.com/doc?71127). 

www.vishay.com 

Document Number:  71126 12-Dec-03 

**2** 

**Application Note 826** 

Vishay Siliconix 

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## **RECOMMENDED MINIMUM PADS FOR 1206-8 ChipFET[®]** 

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**----- Start of picture text -----**<br>
0.093<br>(2.357)<br>0.026 0.016 0.010<br>(0.650) (0.406) (0.244)<br>Recommended Minimum Pads<br>Dimensions in Inches/(mm)<br>0.080 (2.032) 0.036 (0.914)<br>0.022 (0.559)<br>**----- End of picture text -----**<br>


Return to Index 

Return to Index 

## 

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Document Number: 72593 Revision: 21-Jan-08 

**Legal Disclaimer Notice** Vishay 

www.vishay.com 

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## **Disclaimer** 

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 

Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product.  To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability. 

Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications.  Such statements are not binding statements about the suitability of products for a particular application.  It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application.  Parameters provided in datasheets and/or specifications may vary in different applications and performance may vary over time.  All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein. 

Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk.  Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. 

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.  Product names and markings noted herein may be trademarks of their respective owners. 

## **Material Category Policy** 

**Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (EEE) - recast, unless otherwise specified as non-compliant.** 

**Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.** 

**Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards.  Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition.  We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards.** 

Revision: 02-Oct-12 

Document Number: 91000 

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