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SH63N65DM6AG
Dual MOSFET, AQG 324, Dual N Channel, 650 V, 53 A, 0.064 ohm
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: STMICROELECTRONICS
- Product type: Dual MOSFETs
- SVHC: No SVHC (25-Jun-2025)
- No. of Pins: 9Pins
- Channel Type: Dual N Channel
- Product Range: -
- Qualification: -
- Transistor Case Style: ACEPACK SMIT
- Operating Temperature Max: 150°C
- Power Dissipation N Channel: 424W
- Power Dissipation P Channel: -
- Drain Source Voltage Vds N Channel: 650V
- Drain Source Voltage Vds P Channel: -
- Continuous Drain Current Id N Channel: 53A
- Continuous Drain Current Id P Channel: -
- Drain Source On State Resistance N Channel: 0.064ohm
- Drain Source On State Resistance P Channel: -
| Delivery and price | |
|---|---|
| Units per pack | 10 |
| Price | 17.7 € |
| Current stock | 25+ |
| Lead time | 30 days |
Datasheet
**SH63N65DM6AG**
Datasheet
Automotive-grade N-channel 650 V, 56 mΩ typ., 53 A MDmesh DM6 ‑ half bridge topology Power MOSFET in an ACEPACK SMIT package
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7 Features<br>9 97 ACEPACK SMIT 79 61 16 Order code VDS RDS(on) max. ID<br>6<br>SH63N65DM6AG 650 V 64 mΩ 53 A<br>oo Es<br>1<br>9<br>7 • AQG 324 qualified<br>• Half-bridge power module<br>1<br>• 650 V blocking voltage<br>> 6 • Fast recovery body diode [-]<br>ACEPACK SMIT •<br>**----- End of picture text -----**<br>
- Very low switching energies
- Low package inductance
- Dice on direct bond copper (DBC) substrate
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9 (DC+)<br>1 (GHS)<br>2 (KHS)<br>7 (U)<br>3, 4 (NC)<br>6 (GLS)<br>5 (KLS)<br>8 (DC-)<br>GADG060720221002SA<br>**----- End of picture text -----**<br>
- Low thermal resistance
- Isolation rating of 3.4 kVrms/min
## **Applications**
- Switching applications
## **Description**
This device combines two MOSFETs in a half-bridge topology. The ACEPACK SMIT is a very compact and rugged power module in a surface mount package for easy assembly. Thanks to the DBC substrate, the ACEPACK SMIT package offers low thermal resistance coupled with an isolated top-side thermal pad. The high design flexibility of the package enables several configurations, including phase legs, boost,
and single switch through different combinations of the internal power switches.
**Product status link** SH63N65DM6AG
## **Product summary**
|**Order code**|SH63N65DM6AG|
|---|---|
|**Marking**|H63N65DM6|
|**Package**|ACEPACK SMIT|
|**Packing**|Tape and reel|
**DS14369** - **Rev 1** - **June 2023** For further information contact your local STMicroelectronics sales office.
www.st.com
**SH63N65DM6AG Electrical ratings**
## **1 Electrical ratings**
## **Table 1. Absolute maximum ratings**
|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|VGS|Gate-source voltage|±25|V|
|ID|Drain current (continuous) at TC= 25 °C|53|A|
||Drain current (continuous) at TC= 100 °C|33||
|IDM (1)|Drain current (pulsed)|170|A|
|PTOT|Total power dissipation at TC= 25 °C|424|W|
|dv/dt(2)|Peak diode recovery voltage slope|100|V/ns|
|di/dt(2)|Peak diode recovery current slope|1000|A/μs|
|dv/dt(3)|MOSFET dv/dt ruggedness|100|V/ns|
|VISO|Isolation withstand voltage applied between each pin and heat sink plate<br>(AC voltage 50/60 Hz, t = 60 s)|3.4|kVrms|
|TSTG|Storage temperature range|-55 to 150|°C|
|TJ|Operating junction temperature range||°C|
_1. Pulse width limited by safe operating area._
_2. ISD ≤ 53 A, VDS (peak) < V(BR)DSS, VDD = 400 V._
_3. VDS ≤ 520 V._
## **Table 2. Thermal data**
|**Symbol**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|
|RthJC|Thermal resistance, junction-to-case|0.29|°C/W|
|**Table 3.Avalanche characteristics**||||
|**Symbol**|**Parameter**|**Value**|**Unit**|
|IAR|Avalanche current, repetitive or not repetitive (tplimited by TJmax.)|6|A|
|EAS|Single pulse avalanche energy (starting TJ= 25 °C, ID= IAR)|778|mJ|
**DS14369** - **Rev 1**
**page 2/13**
**SH63N65DM6AG Electrical characteristics**
## **2 Electrical characteristics**
TC = 25 °C unless otherwise specified
**Table 4. On/off states**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-source breakdown voltage|VGS= 0 V, ID= 1 mA|650|||V|
|IDSS|Zero gate voltage drain current|VGS= 0 V, VDS= 650 V|||5|μA|
|||VGS= 0 V, VDS= 650 V, TC(1)|||300||
|IGSS|Gate-body leakage current|VDS= 0 V, VGS= ±25 V|||±5|μA|
|VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 μA|3.25|4|4.75|V|
|RDS(on)|Static drain-source on resistance|VGS= 10 V, ID= 23 A||56|64|mΩ|
_1. Specified by design, not tested in production._
**Table 5. Dynamic characteristics**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Ciss|Input capacitance|VDS= 100 V, f = 1 MHz, VGS= 0 V|-|3344|-|pF|
|Coss|Output capacitance||-|161|-|pF|
|Crss|Reverse transfer capacitance||-|0.4|-|pF|
|Coss eq.(1)|Equivalent output capacitance|VDS= 0 to 520 V, VGS= 0 V|-|510|-|pF|
|RG|Intrinsic gate resistance|f = 1 MHz, ID= 0 A|-|1.4|-|Ω|
|Qg|Total gate charge|VDD= 520 V, ID= 50 A, VGS= 0 to 10 V<br>(seeFigure 13. Test circuit for gate<br>charge behavior)|-|80|-|nC|
|Qgs|Gate-source charge||-|21.5|-|nC|
|Qgd|Gate-drain charge||-|36|-|nC|
_1. Coss eq is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS._
**Table 6. Switching characteristics (resistive load)**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|td(on)|Turn-on delay time|VDD= 325 V, ID= 23 A,<br>RG= 4.7 Ω , VGS= 10 V<br>(seeFigure 12. Switching times test<br>circuit for resistive loadand<br>Figure 17. Switching time waveform)|-|28|-|ns|
|tr|Rise time||-|8|-|ns|
|td(off)|Turn-off delay time||-|68|-|ns|
|tf|Fall time||-|8|-|ns|
**DS14369** - **Rev 1**
**page 3/13**
**SH63N65DM6AG Electrical characteristics**
## **Table 7. Source-drain diode**
|**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|ISD|Source-drain current||-||53|A|
|ISDM(1)|Source-drain current (pulsed)||-||170|A|
|VSD(2)|Forward on voltage|VGS= 0 V, ISD= 46 A|-||1.55|V|
|trr|Reverse recovery time|ISD= 46 A, di/dt = 100 A/μs,<br>VDD= 60 V<br>(seeFigure 14. Test circuit for inductive<br>load switching and diode recovery times)|-|162||ns|
|Qrr|Reverse recovery charge||-|0.95||µC|
|IRRM|Reverse recovery current||-|10.7||A|
|trr|Reverse recovery time|ISD= 46 A, di/dt = 100 A/μs,<br>VDD= 60 V, TJ= 150 °C<br>(seeFigure 14. Test circuit for inductive<br>load switching and diode recovery times)|-|355||ns|
|Qrr|Reverse recovery charge||-|4.8||µC|
|IRRM|Reverse recovery current||-|25.3||A|
_1. Pulse width is limited by safe operating area._
_2. Pulsed: pulse duration = 300 μs, duty cycle 1.5%._
**DS14369** - **Rev 1**
**page 4/13**
**SH63N65DM6AG Electrical characteristics (curves)**
## **2.1 Electrical characteristics (curves)**
**Figure 1. Safe operating area**
**Figure 2. Maximum transient thermal impedance**
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ID GADG270620231556SOA ZthJC GADG270620231556ZTH<br>(A) IDM (°C/W)<br>10 [2] tp =1µs δ = 0.5 0.4 0.3<br>10 [-1 ]<br>pe ANNAN tp =10µs See eg Ge ce<br>10 [1] 0.2<br>RDS(on) max.<br>10 [-2 ]<br>SS EN tp =100µs emu00 0.1<br>10 [0] 0.05<br>V (BR)DSS<br>Saarinen esti il rH Er PPE RthJC = 0.29 °C/W<br>10 [-1] Ht Single pulseTTJC = 25 °C≤ 150 NN °C,, t t pp =1ms =10ms 10 [-3 ] uy Single pulse tδ = ton T on / T<br>10 [-2] ait Ft 10 [-4 ] ti —~<br>10 [-1] 10 [0] 10 [1] 10 [2] VDS (V) 10 [-6 ] 10 [-5 ] 10 [-4 ] 10 [-3 ] 10 [-2 ] 10 [-1 ] tp (s)<br>DS(on)<br>Operation in this area<br>is limited by R<br>**----- End of picture text -----**<br>
**Figure 3. Typical output characteristics**
**Figure 4. Typical transfer characteristics**
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ID GADG270620231556OCH ID GADG280620231601TCH<br>(A) (A)<br>VGS = 9, 10 V<br>LILI {| B PTT TTT ETT Eye<br>160 pe 8 V 160 PET TTT EL ArT<br>eee Aan PETTITTE ETAT Te<br>VDS = 20 V<br>120 See 4eeee 120 Pit<br>7 V<br>80 80<br>sarHf 2Guuees i fataceUEfateVT TE<br>40 Lf BREe 40 facen/eeeenPET TT ALT<br>[ALT ET 6 V PET [TVET] TTT<br>0 LT 0 PEETTT<br>0 4 8 12 16 VDS (V) 4 5 6 TET 7 TTT 8 9 TI VGS (V)<br>**----- End of picture text -----**<br>
**Figure 5. Typical drain-source on-resistance**
**Figure 6. Typical gate charge characteristics**
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RDS(on) GADG270620231558RID VDS GADG040820211515QVG VGS<br>(mΩ)61 a 600(V) ee VDD = 520 V, ID = 50 AQg 12(V)<br>Se BSAHAUONEREALBLEDYRES E REED<br>60 es 500 PEARCE2 10<br>pr VDS a VGS<br>VGS = 10 V Qgs Qgd<br>59 400 8<br>seeeee ZeaA Ptebat AAVeNEanOYorALLE<br>58 ee 300 PCR 6<br>57 REE EEEEEHA 200 PEELS 4<br>COVE<br>TOAZCE [eee] LE<br>56 oe 100 CC C C CECC 2<br>55 HEE EEE 0 PEAR 0<br>0 20 40 60 80 ID (A) 0 20 40 60 80 Qg (nC)<br>**----- End of picture text -----**<br>
**DS14369** - **Rev 1**
**page 5/13**
**SH63N65DM6AG Electrical characteristics (curves)**
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**----- Start of picture text -----**<br>
Figure 7. Typical capacitance characteristics Figure 8. Normalized gate threshold vs temperature<br>C GADG080420211008CVR VGS(th) GADG080420211010VTH<br>(pF) (norm.)<br>10 [4 ] 1.1<br>Ciss ID = 250 µA<br>10 [3 ] 1.0<br>10 [2 ] Coss 0.9<br>10 [1 ] Crss 0.8<br>f = 1 MHz<br>10 [0 ] 0.7<br>10 [-1 ] 0.6<br>10 [-1 ] 10 [0 ] 10 [1 ] 10 [2 ] VDS (V) -75 -25 25 75 125 TJ (°C)<br>**----- End of picture text -----**<br>
**Figure 9. Normalized on-resistance vs temperature Figure 10. Normalized breakdown voltage vs temperature**
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RDS(on) GADG080420211010RON V(BR)DSS GADG080420211011BDV<br>(norm.) (norm.)<br>2.5 1.10<br>VDS = 10 V ID = 1 mA<br>2.0 1.05<br>1.5 1.00<br>1.0 0.95<br>0.5 0.90<br>0.0 0.85<br>-75 -25 25 75 125 TJ (°C) -75 -25 25 75 125 TJ (°C)<br>**----- End of picture text -----**<br>
**Figure 11. Typical reverse diode forward characteristics**
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VSD GADG270620231558SDF<br>(V)<br>1.3<br>TJ = -40 °C<br>1.2<br>1.1<br>1.0<br>TJ = 25 °C<br>0.9<br>0.8 TJ = 150 °C<br>0.7<br>0 20 40 60 80 ISD (A)<br>**----- End of picture text -----**<br>
**DS14369** - **Rev 1**
**page 6/13**
**SH63N65DM6AG Test circuits**
## **3 Test circuits**
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Figure 13. Test circuit for gate charge behavior<br>Figure 12. Switching times test circuit for resistive load<br>VDD<br>RL<br>RL 2200 3.3<br>µF µF<br>VD + VDD VGS IG= CONST 100 Ω D.U.T.<br>VGS<br>RG D.U.T. pulse width 2200 + 2.7 kΩ VG<br>μF<br>PW 47 kΩ<br>GND1 GND2 1 kΩ<br>(driver signal) (power)<br>AM15855v1 GND1 GND2<br>GADG180720181011SA<br>**----- End of picture text -----**<br>
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Figure 14. Test circuit for inductive load switching and<br>Figure 15. Unclamped inductive load test circuit<br>diode recovery times<br>A A A L<br>D<br>FAST L=100µH<br>G D.U.T. DIODE VD<br>2200 3.3<br>25Ω S B B B D 3.3µF + 1000µF VDD + µF µF VDD<br>ID<br>G<br>RG S<br>D.U.T.<br>Vi D.U.T.<br>GND1 GND2 Pw<br>GND1 GND2 AM15858v1<br>AM15857v1<br>**----- End of picture text -----**<br>
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**----- Start of picture text -----**<br>
Figure 16. Unclamped inductive waveform Figure 17. Switching time waveform<br>ton toff<br>V(BR)DSS td(on) tr td(off) tf<br>VD<br>90% 90%<br>IDM<br>ID 0 10% VDS 10%<br>VDD VDD VGS 90%<br>0 10%<br>AM01472v1 AM01473v1<br>**----- End of picture text -----**<br>
**DS14369** - **Rev 1**
**page 7/13**
**SH63N65DM6AG Package information**
## **4 Package information**
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
## **4.1 ACEPACK SMIT package information**
**Figure 18. ACEPACK SMIT package outline**
**==> picture [80 x 86] intentionally omitted <==**
**==> picture [103 x 36] intentionally omitted <==**
**==> picture [117 x 89] intentionally omitted <==**
DM00447519_Rev.6
**DS14369** - **Rev 1**
**page 8/13**
**SH63N65DM6AG ACEPACK SMIT package information**
**Table 8. ACEPACK SMIT package mechanical data**
|**Di**|**mm**|**mm**|**mm**|
|---|---|---|---|
|**m.**|**Min.**|**Typ.**|**Max.**|
|A|19.50|20.00|20.50|
|B|21.50|22.00|22.50|
|C|22.80|23.00|23.20|
|D|24.80|25.00|25.20|
|E|32.20|32.70|33.20|
|b||9.00||
|b1||4.00||
|b2||6.75||
|b3||9.50||
|c|0.95|1.00|1.10|
|c1|1.95|2.00|2.10|
|d|0.00||0.15|
|d1|0.45|0.55|0.65|
|e|1.30|1.50|1.70|
|e1|4.65|4.85|5.05|
|L|3.95|4.00|4.05|
|L1|5.40|5.50|5.60|
|m|1.30|1.50|1.80|
|m1|1.30|1.50|1.80|
|V|0°|2°|4°|
|aaa|0.01||0.05|
|bbb|0.00||0.10|
**DS14369** - **Rev 1**
**page 9/13**
**SH63N65DM6AG ACEPACK SMIT package information**
**Figure 19. ACEPACK SMIT recommended footprint**
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4.00 (x9)<br>30.10<br>= =<br>DM00447519_FP_Rev.6<br>2.75 (x4)<br>9.00 (x2)<br>4.00 (x2)<br>2.40 (x3) 1.40 (x6)<br>**----- End of picture text -----**<br>
_Note:_
_Dimensions in mm._
**Figure 20. ACEPACK SMIT marking orientation vs pinout**
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FRONT SIDE<br>9 7<br>d<br>B<br>A C D<br>E<br>F G H I J K L<br>M<br>1 6<br>BACK SIDE<br>7 9<br>D A B C<br>E F G H<br>I<br>6 1<br>**----- End of picture text -----**<br>
DM00447519_MO_Rev.6
**DS14369** - **Rev 1**
**page 10/13**
**SH63N65DM6AG**
## **Revision history**
## **Table 9. Document revision history**
|**Date**|**Revision**|**Changes**|
|---|---|---|
|29-Jun-2023|1|First release.|
**DS14369** - **Rev 1**
**page 11/13**
**SH63N65DM6AG Contents**
|**Contents**|**Contents**|
|---|---|
|**1**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2**|
|**2**|**Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3**|
||**2.1**<br>Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5|
|**3**|**Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7**|
|**4**|**Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8**|
||**4.1**<br>ACEPACK SMIT package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8|
|**Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11**||
**DS14369** - **Rev 1**
**page 12/13**
**SH63N65DM6AG**
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- © 2023 STMicroelectronics – All rights reserved
**DS14369** - **Rev 1**
**page 13/13**
Updated at June 9, 2026
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