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SH32N65DM6AG
Dual MOSFET, AQG 324, Dual N Channel, 650 V, 32 A, 0.097 ohm
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- Manufacturer: STMICROELECTRONICS
- Product type: Dual MOSFETs
- SVHC: No SVHC (25-Jun-2025)
- No. of Pins: 9Pins
- Channel Type: Dual N Channel
- Product Range: -
- Qualification: -
- Transistor Case Style: ACEPACK SMIT
- Operating Temperature Max: 150°C
- Power Dissipation N Channel: 208W
- Power Dissipation P Channel: -
- Drain Source Voltage Vds N Channel: 650V
- Drain Source Voltage Vds P Channel: -
- Continuous Drain Current Id N Channel: 32A
- Continuous Drain Current Id P Channel: -
- Drain Source On State Resistance N Channel: 0.097ohm
- Drain Source On State Resistance P Channel: -
| Delivery and price | |
|---|---|
| Units per pack | 100 |
| Price | 10.34 € |
| Current stock | 100+ |
| Lead time | 30 days |
Datasheet
**SH32N65DM6AG** Datasheet Automotive-grade N-channel 650 V, 89 mΩ typ., 32 A MDmesh DM6 ‑ half bridge topology Power MOSFET in an ACEPACK SMIT package **==> picture [509 x 286] intentionally omitted <==** **----- Start of picture text -----**<br> 8 9 Features<br>7<br>Order code VDS RDS(on) max. ID<br>1<br>SH32N65DM6AG 650 V 97 mΩ 32 A<br>3<br>4<br>6<br>7<br>8 • AQG 324 qualified<br>9 • Half-bridge power module<br>6 • 650 V blocking voltage<br>4 •<br>> 3 —— Fast recovery body diode<br>1<br>ACEPACK SMIT • Very low switching energies<br>GADG060720221002SA 9 (DC+) • Low package inductance<br>• Dice on direct bond copper (DBC) substrate<br>• Low thermal resistance<br>1 (GHS) • Isolation rating of 3.4 kVrms/min<br>2 (KHS)<br>7 (U) Applications<br>3, 4 (NC)<br>• Switching applications<br>6 (GLS)<br>5 (KLS) Description<br>8 (DC-) This device combines two MOSFETs in a half-bridge topology. The ACEPACK SMIT<br>**----- End of picture text -----**<br> 8 (DC-) This device combines two MOSFETs in a half-bridge topology. The ACEPACK SMIT is a very compact and rugged power module in a surface mount package for easy assembly. Thanks to the DBC substrate, the ACEPACK SMIT package offers low thermal resistance coupled with an isolated top-side thermal pad. The high design flexibility of the package enables several configurations, including phase legs, boost, and single switch through different combinations of the internal power switches. ~~©~~ ## **Product status link** SH32N65DM6AG |**Product summary**<br>~~—~~|**Product summary**<br>~~—~~| |---|---| |**Order code**|SH32N65DM6AG| |**Marking**|H32N65DM6| |**Package**|ACEPACK SMIT| |**Packing**|Tape and reel| **DS14049** - **Rev 2** - **October 2022** For further information contact your local STMicroelectronics sales office. www.st.com **SH32N65DM6AG Electrical ratings** ## **1 Electrical ratings** **Table 1. Absolute maximum ratings** |**Symbol**|**Parameter**|**Value**|**Unit**| |---|---|---|---| |VGS|Gate-source voltage|±25|V| |ID|Drain current (continuous) at TC= 25 °C|32|A| ||Drain current (continuous) at TC= 100 °C|20|| |IDM (1)|Drain current (pulsed)|120|A| |PTOT|Total power dissipation at TC= 25 °C|208|W| |dv/dt(2)|Peak diode recovery voltage slope|100|V/ns| |di/dt(2)|Peak diode recovery current slope|1000|A/μs| |dv/dt(3)|MOSFET dv/dt ruggedness|100|V/ns| |VISO|Isolation withstand voltage applied between each pin and heat sink plate<br>(AC voltage (50/60 Hz, t = 60 s)|3.4|kVrms| |TSTG|Storage temperature range|-55 to 150|°C| |TJ|Operating junction temperature range||°C| _1. Pulse width limited by safe operating area._ _2. ISD ≤ 32 A, VDS (peak) < V(BR)DSS, VDD = 400 V._ _3. VDS ≤ 520 V._ ## **Table 2. Thermal data** |**Symbol**|**Parameter**|**Value**|**Unit**| |---|---|---|---| |RthJC|Thermal resistance, junction-to-case|0.6|°C/W| ## **Table 3. Avalanche characteristics** |**Symbol**|**Parameter**|**Value**|**Unit**| |---|---|---|---| |IAR|Avalanche current, repetitive or not repetitive (tplimited by TJmax)|6|A| |EAS|Single pulse avalanche energy (starting TJ= 25 °C, ID= IAR)|778|mJ| **DS14049** - **Rev 2** **page 2/14** **SH32N65DM6AG Electrical characteristics** ## **2 Electrical characteristics** TC = 25 °C unless otherwise specified ## **Table 4. On/off states** |**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**| |---|---|---|---|---|---|---| |V(BR)DSS|Drain-source breakdown voltage|VGS= 0 V, ID= 1 mA|650|||V| |IDSS|Zero gate voltage drain current|VGS= 0 V, VDS= 650 V|||5|μA| |||VGS= 0 V, VDS= 650 V, TC(1)|||300|| |IGSS|Gate-body leakage current|VDS= 0 V, VGS= ±25 V|||±5|μA| |VGS(th)|Gate threshold voltage|VDS= VGS, ID= 250 μA|3.25|4|4.75|V| |RDS(on)|Static drain-source on resistance|VGS= 10 V, ID= 23 A||89|97|mΩ| _1. Specified by design, not tested in production._ **Table 5. Dynamic characteristics** |**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**| |---|---|---|---|---|---|---| |Ciss|Input capacitance|VDS= 100 V, f = 1 MHz, VGS= 0 V|-|2211|-|pF| |Coss|Output capacitance||-|106|-|pF| |Crss|Reverse transfer capacitance||-|0.3|-|pF| |Coss eq.(1)|Equivalent output capacitance|VDS= 0 to 520 V, VGS= 0 V|-|396|-|pF| |RG|Intrinsic gate resistance|f = 1 MHz, ID= 0 A|-|1.5|-|Ω| |Qg|Total gate charge|VDD= 520 V, ID= 37 A, VGS= 0 to 10 V<br>(seeFigure 13. Test circuit for gate<br>charge behavior)|-|47|-|nC| |Qgs|Gate-source charge||-|16|-|nC| |Qgd|Gate-drain charge||-|18|-|nC| _1. Coss eq is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS._ **Table 6. Switching characteristics (resistive load)** |**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**| |---|---|---|---|---|---|---| |td(on)|Turn-on delay time|VDD= 325 V, ID= 18.5 A,<br>RG= 4.7 Ω , VGS= 10 V<br>(seeFigure 12. Switching times<br>test circuit for resistive loadand<br>Figure 17. Switching time waveform)|-|23|-|ns| |tr|Rise time||-|10|-|ns| |td(off)|Turn-off delay time||-|54|-|ns| |tf|Fall time||-|9|-|ns| **DS14049** - **Rev 2** **page 3/14** **SH32N65DM6AG Electrical characteristics** **Table 7. Switching characteristics (inductive load)** |**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**| |---|---|---|---|---|---|---| |td(v)|Voltage delay time|VDD= 400 V, VGS= 0 to 10 V, ID= 37 A,<br>RG= 6.8 Ω (seeFigure 14. Test<br>circuit for inductive load switching<br>and diode recovery timesand<br>Figure 18. Turn-off switching time<br>waveform on inductive load)|-|54|-|ns| |tr(v)|Voltage rise time||-|7|-|ns| |tf(i)|Current fall time||-|8|-|ns| |tc(off)|Crossing time off||-|13|-|ns| |td(i)|Current delay time|VDD= 400 V, VGS= 0 to 10 V, ID= 37 A,<br>RG= 82 Ω (seeFigure 14. Test<br>circuit for inductive load switching<br>and diode recovery timesand<br>Figure 19. Turn-on switching time<br>waveform on inductive load)|-|154|-|ns| |tr(i)|Current rise time||-|59|-|ns| |tf(v)|Voltage fall time||-|9|-|ns| |tc(on)|Crossing time on||-|128|-|ns| **Table 8. Source-drain diode** |**Symbol**|**Parameter**|**Test conditions**|**Min.**|**Typ.**|**Max.**|**Unit**| |---|---|---|---|---|---|---| |ISD|Source-drain current||-||32|A| |ISDM(1)|Source-drain current (pulsed)||-||120|A| |VSD(2)|Forward on voltage|VGS= 0 V, ISD= 32 A|-||1.6|V| |trr|Reverse recovery time|ISD= 37 A, di/dt = 100 A/μs, VDD= 60 V<br>(seeFigure 14. Test circuit for inductive<br>load switching and diode recovery times)|-|125||ns| |Qrr|Reverse recovery charge||-|0.52||µC| |IRRM|Reverse recovery current||-|7.5||A| |trr|Reverse recovery time|ISD= 37 A, di/dt = 100 A/μs,<br>VDD= 60 V, TJ= 150 °C<br>(seeFigure 14. Test circuit for inductive<br>load switching and diode recovery times)|-|260||ns| |Qrr|Reverse recovery charge||-|2.5||µC| |IRRM|Reverse recovery current||-|17||A| _1. Pulse width is limited by safe operating area._ _2. Pulsed: pulse duration = 300 μs, duty cycle 1.5%._ **DS14049** - **Rev 2** **page 4/14** **SH32N65DM6AG Electrical characteristics (curves)** ## **2.1 Electrical characteristics (curves)** **Figure 1. Safe operating areaSafe operating area** **==> picture [453 x 186] intentionally omitted <==** **----- Start of picture text -----**<br> Figure 1. Safe operating areaSafe operating area Figure 2. Maximum transient thermal impedance<br>ID GADG060820211149SOA ZthJC GADG020820221211ZTH<br>(A) IDM (°C/W) 4 3<br>SS Sas SE Sr Men Sete Serie<br>duty=0.5<br>10 [2 ] tp =1 µs<br>10 [1 ] tp =10 µs 10 [-1]<br>RDS(on) max.<br>0.05 2<br>10 [0 ] tN AN tp =100 µs ee<br>4a SS SSS PA Cre TnAFo.EO<br>10 [-1 ] 10 [-2]<br>tp =1 ms RthJCduty = 0.6 = t on ℃/W / T<br>10 [-2 ] TJ ≤ 150 ° C, V (BR)DSS Single pulse<br>TC = 25 °C, tp =10 ms t on<br>10 [-3 ] Se Single pulse a 10 [-3] ec T<br>10 [-1 ] 10 [0 ] 10 [1 ] 10 [2 ] VDS (V) 10 [-6] 10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] tp (s)<br>DS(on)<br>Operation in this area<br>is limited by R<br>**----- End of picture text -----**<br> **Figure 3. Typical output characteristics** **Figure 4. Typical transfer characteristics** **==> picture [443 x 168] intentionally omitted <==** **----- Start of picture text -----**<br> ID GADG020820221211OCH ID GADG020820221212TCH<br>(A) Pf | ft ct (A)<br>VGS= 9, 10 V<br>120 VDS =20 V<br>120<br>100 ne SEE<br>VGS= 8 V<br>0<br>90<br>80<br>60 aaa VGS= 7 V aoeeraee<br>60<br>40<br>HA SSS 30 SRA<br>20 fo ,<br>VGS= 6 V<br>0 pone 0<br>0 Ze 5 10 15 VDS (V) | 5 EE 6 7 8 VGS (V)<br>**----- End of picture text -----**<br> **==> picture [452 x 186] intentionally omitted <==** **----- Start of picture text -----**<br> Figure 5. Typical drain-source on-resistance Figure 6. Typical gate charge characteristics<br>RDS(on) GADG020820221213RID VDS GADG020820221213QVG VGS<br>(mΩ) (V) VDD= 520 V, ID = 37 A (V)<br>PT ee Tey yo A Qg VGS (V)<br>500 10<br>VGS= 10 V<br>92<br>400 8<br>aay Qgs Qgd ion<br>Seco sar [eSE][eaD]<br>90 PtPTT||TVETLYE | 300 nnanpferyene 6<br>200 4<br>88<br>VDS (V)<br>100 2<br>vr a7 a taee SoHo<br>PP<br>86 P| tt | tt | 0 VNpe 0<br>0 10 20 30 ID (A) 0 10 20 30 40 50 Qg (nC)<br>**----- End of picture text -----**<br> **DS14049** - **Rev 2** **page 5/14** **SH32N65DM6AG Electrical characteristics (curves)** **Figure 7. Typical capacitance characteristics Figure 8. Normalized gate threshold vs temperature** **==> picture [445 x 167] intentionally omitted <==** **----- Start of picture text -----**<br> C GADG210420210934CVR VGS(th) GADG020820221214VTH<br>(pF) (norm.)<br>ID = 250 μA<br>1.2<br>10 [4 ]<br>Ciss 1.1<br>10 [3 ]<br>1.0<br>10 [2 ]<br>Coss 0.9<br>f = 1 MHz<br>10 [1 ]<br>Crss 0.8<br>10 [0 ] 0.7<br>10 [-1 ] 0.6<br>10 [-1 ] 10 [0 ] 10 [1 ] 10 [2 ] VDS (V) -75 -25 25 75 125 TJ (°C)<br>**----- End of picture text -----**<br> **Figure 9. Normalized on-resistance vs temperature Figure 10. Normalized breakdown voltage vs temperature** **==> picture [456 x 166] intentionally omitted <==** **----- Start of picture text -----**<br> RDS(on) GADG020820221214RON V(BR)DSS GADG020820221214BDV<br> (norm.) (norm.)<br>VGS= 10 V ID = 1 mA<br>2.0 1.10<br>1.5 1.05<br>1.0 1.00<br>0.5 0.95<br>0.0 0.90<br>-75 -25 25 75 125 TJ (°C) -75 -25 25 75 125 TJ (°C)<br>**----- End of picture text -----**<br> **Figure 11. Typical reverse diode forward characteristics** **==> picture [184 x 165] intentionally omitted <==** **----- Start of picture text -----**<br> VSD GADG020820221215SDF<br> (V)<br>TJ= -40 °C<br>1.2<br>1.0<br>TJ= 25 °C<br>0.8<br>TJ= 150 °C<br>0.6<br>0.4<br>0 5 10 15 20 25 30 35 ISD (A)<br>**----- End of picture text -----**<br> **DS14049** - **Rev 2** **page 6/14** **SH32N65DM6AG Test circuits** ## **3 Test circuits** **==> picture [513 x 184] intentionally omitted <==** **----- Start of picture text -----**<br> Figure 13. Test circuit for gate charge behavior<br>Figure 12. Switching times test circuit for resistive load<br>VDD<br>RL<br>RL 2200 3.3<br>µF µF<br>VD + VDD VGS IG= CONST 100 Ω D.U.T.<br>VGS<br>RG D.U.T. pulse width 2200 + 2.7 kΩ VG<br>μF<br>PW 47 kΩ<br>GND1 GND2 1 kΩ<br>(driver signal) (power)<br>AM15855v1 GND1 GND2<br>GADG180720181011SA<br>**----- End of picture text -----**<br> **==> picture [513 x 182] intentionally omitted <==** **----- Start of picture text -----**<br> Figure 14. Test circuit for inductive load switching and<br>Figure 15. Unclamped inductive load test circuit<br>diode recovery times<br>A A A L<br>D<br>FAST L=100µH<br>G D.U.T. DIODE VD<br>2200 3.3<br>25Ω S B B B D 3.3µF + 1000µF VDD + µF µF VDD<br>ID<br>G<br>RG S<br>D.U.T.<br>Vi D.U.T.<br>GND1 GND2 Pw<br>GND1 GND2 AM15858v1<br>AM15857v1<br>**----- End of picture text -----**<br> **==> picture [513 x 195] intentionally omitted <==** **----- Start of picture text -----**<br> Figure 16. Unclamped inductive waveform Figure 17. Switching time waveform<br>ton toff<br>V(BR)DSS td(on) tr td(off) tf<br>VD<br>90% 90%<br>IDM<br>ID 0 10% VDS 10%<br>VDD VDD VGS 90%<br>0 10%<br>AM01472v1 AM01473v1<br>**----- End of picture text -----**<br> **DS14049** - **Rev 2** **page 7/14** **SH32N65DM6AG Test circuits** **==> picture [513 x 191] intentionally omitted <==** **----- Start of picture text -----**<br> Figure 18. Turn-off switching time waveform Figure 19. Turn-on switching time waveform<br>on inductive load on inductive load<br>ID VDS VDS ID<br>90%VDS 90%ID 90%ID 90%VDS<br>VGS 90%VGS 90%VGS<br>10%VDS 10%ID 10%ID 10%VDS<br>10%VGS<br>VDS tr(v) tf(i) ID ID tr(i) tf(v) VDS<br>td(v) tc(off) td(i) tc(on)<br>AM05540v3 GADG241120211046SWTW<br>**----- End of picture text -----**<br> **DS14049** - **Rev 2** **page 8/14** **SH32N65DM6AG Package information** ## **4 Package information** In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. ## **4.1 ACEPACK SMIT package information** ## **Figure 20. ACEPACK SMIT package outline** **==> picture [80 x 86] intentionally omitted <==** **==> picture [103 x 36] intentionally omitted <==** **==> picture [117 x 89] intentionally omitted <==** DM00447519_Rev.6 **DS14049** - **Rev 2** **page 9/14** **SH32N65DM6AG ACEPACK SMIT package information** **Table 9. ACEPACK SMIT package mechanical data** |**Di**|**mm**|**mm**|**mm**| |---|---|---|---| |**m.**|**Min.**|**Typ.**|**Max.**| |A|19.50|20.00|20.50| |B|21.50|22.00|22.50| |C|22.80|23.00|23.20| |D|24.80|25.00|25.20| |E|32.20|32.70|33.20| |b||9.00|| |b1||4.00|| |b2||6.75|| |b3||9.50|| |c|0.95|1.00|1.10| |c1|1.95|2.00|2.10| |d|0.00||0.15| |d1|0.45|0.55|0.65| |e|1.30|1.50|1.70| |e1|4.65|4.85|5.05| |L|3.95|4.00|4.05| |L1|5.40|5.50|5.60| |m|1.30|1.50|1.80| |m1|1.30|1.50|1.80| |V|0°|2°|4°| |aaa|0.01||0.05| |bbb|0.00||0.10| **DS14049** - **Rev 2** **page 10/14** **SH32N65DM6AG ACEPACK SMIT package information** **Figure 21. ACEPACK SMIT recommended footprint** **==> picture [363 x 250] intentionally omitted <==** **----- Start of picture text -----**<br> 4.00 (x9)<br>30.10 DM00447519_FP_Rev.6<br>2.75 (x4)<br>9.00 (x2)<br>4.00 (x2)<br>2.40 (x3) 1.40 (x6)<br>**----- End of picture text -----**<br> _Note: Dimensions in mm._ **Figure 22. ACEPACK SMIT marking orientation vs pinout** **==> picture [83 x 133] intentionally omitted <==** **----- Start of picture text -----**<br> FRONT SIDE<br>9 7<br>d<br>B<br>A C D<br>E<br>F G H I J K L<br>M<br>1 6<br>**----- End of picture text -----**<br> ## **BACK SIDE** **==> picture [83 x 113] intentionally omitted <==** **----- Start of picture text -----**<br> 7 9<br>D A B C<br>E F G H<br>I<br>6 1<br>**----- End of picture text -----**<br> DM00447519_MO_Rev.6 **DS14049** - **Rev 2** **page 11/14** **SH32N65DM6AG** ## **Revision history** **Table 10. Document revision history** |**Date**|**Revision**|**Changes**| |---|---|---| |03-Aug-2022|1|First release.| |03-Oct-2022|2|UpdatedTable 1. Absolute maximum ratings.<br>UpdatedTable 3. Avalanche characteristics.<br>UpdatedTable 4. On/off states.<br>UpdatedTable 5. Dynamic characteristics.<br>UpdatedTable 7. Switching characteristics (inductive load).<br>UpdatedTable 8. Source-drain diode.<br>UpdatedFigure 1. Safe operating area.<br>UpdatedFigure 6. Typical gate charge characteristics.<br>Minor text changes.| **DS14049** - **Rev 2** **page 12/14** **SH32N65DM6AG Contents** ## **Contents** |**1**|**Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2**| |---|---| |**2**|**Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3**| ||**2.1**<br>Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5| |**3**|**Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7**| |**4**|**Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9**| ||**4.1**<br>ACEPACK SMIT package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9| |**Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12**|| **DS14049** - **Rev 2** **page 13/14** **SH32N65DM6AG** ## **IMPORTANT NOTICE – READ CAREFULLY** STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved **DS14049** - **Rev 2** **page 14/14**
Updated at June 9, 2026
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