SFSD8192N3BM1TO-E-GE-2D1-STD

Product Data Sheet 

## durabit™ 

## “the better MLC” 

**Industrial microSDHC / SDXC Memory Card** 

**S-45u Series** UHS-I Interface, MLC 

Extended and Industrial Temperature Grade 

Date: Revision: 

April 29, 2021 1.34 

## **Contents** 

||**Contents**|
|---|---|
|1.|PRODUCT SUMMARY ............................................................................................................ 3|
|2.|PRODUCT FEATURES ............................................................................................................ 4|
|3.|ORDERING INFORMATION ...................................................................................................... 5|
|4.|PRODUCT DESCRIPTION ......................................................................................................... 6|
||4.1 PERFORMANCESPECIFICATION....................................................................................................... 7|
||4.2 ENVIRONMENTALSPECIFICATIONS................................................................................................... 7|
||4.3 REGULATORYCOMPLIANCE......................................................................................................... 8|
||4.4 MECHANICALSPECIFICATIONS...................................................................................................... 8|
||4.5 RELIABILITY ANDENDURANCE.......................................................................................................9|
||4.6 GEOMETRYSPECIFICATION..........................................................................................................9|
|5.|PACKAGE MECHANICAL ......................................................................................................... 9|
|6.|ELECTRICAL INTERFACE ........................................................................................................ 10|
||6.1 POWER UP/ POWER DOWN BEHAVIOR AND RESET.................................................................................. 11|
||6.2 DCCHARACTERISTICS............................................................................................................... 11|
||6.3 SIGNAL LOADING.................................................................................................................. 11|
||6.4 ACCHARACTERISTICS............................................................................................................... 12|
|7.|HOST ACCESS SPECIFICATION .................................................................................................. 12|
||7.1 SDANDSPI BUSMODES.......................................................................................................... 12|
||7.2 SPI BUSMODEPROTOCOL......................................................................................................... 13|
||7.3 CARD REGISTERS................................................................................................................... 13|
|8.|PART NUMBER DECODER ...................................................................................................... 18|
|9.|SWISSBIT SPECIFICATION ...................................................................................................... 20|
||9.1 TOP VIEW......................................................................................................................... 20|
||9.2 BOTTOM VIEW.................................................................................................................... 20|
|10.|REVISION HISTORY ............................................................................................................. 21|



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## **S-45u Series – Industrial microSDHC / SDXC Memory Card 4 GBytes up to 128 GBytes** 

## **1. Product Summary** 

- Capacities: 4 GBytes, 8 GBytes, 16 GBytes, 32 GBytes, 64 GBytes, 128 GBytes 

- Form Factor: Standard microSD Memory card form factor - 15.0mm x 11.0mm x 0.7mm (1.0mm) 

- Compliance[1] : Fully compliant with SD Memory Card specification 2.0 and 

      - 3.0 and MICRO SD Memory Card Addendum 4.00 

   - SDHC/SDXC default/high speed mode and UHS supported 

   - Up to speed class 10 and U1 and according SD3.0 specification 

   - FAT32 / exFAT preformatted 

- Performance: 

   - SD Default speed 

   - SD High speed 

   - SD UHS-I 

   - Read Performance: Sequential Read up to 44 MBytes/s, Random Read IOPS up to 1,349 

   - Write Performance: Sequential Write up to 22 MBytes/s, Random Write IOPS up to 966 

- Operating Temperature Range[2] : 

   - Extended: -25 °C to 85 °C 

   - Industrial: -40 °C to 85 °C 

- Storage Temperature Range: 

   - Extended: -25 °C to 100 °C 

   - Industrial: -40 °C to 100 °C 

- Operating Voltage: 2.7…3.6V normal operating voltage (Low-power CMOS technology) 

- Data Retention: 10 Years @ Life Begin / 1 Year @ Life End 

- Humidity: 85% RH @85°C 1000h 

- Electromagnetic Compatibility Test: Radiated Emission; Radiated Immunity; Electrostatic Discharge 

> 1 The verification of host system and storage device compatibility is in customer’s responsibility. Swissbit can provide guidance and support on request. 

> 2 High Temperature storage without operation reduces the data retention, in operation the data will be refreshed, if data error issues were detected 

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## **2. Product Features** 

- Optimized FW algorithms especially for high read access and long data retention applications 

   - Patented power-off reliability technology 

   - Wear Leveling technology 

   - Write Endurance technology 

   - Read Disturb Management 

   - Data Care Management 

   - Near miss ECC technology 

   - Diagnostic features with Life Time Monitoring tool support 

- High reliability 

   - Designed for industrial market especially read intensive application like navigation, infotainment, POS/POI, medical and general boot medium use case 

   - The product is optimized for long life cycle and provides excellent data retention in high temperature mission profiles. 

   - Number of card insertions/removals 20,000 

   - SIP (System In Package) process for extreme dust, water and ESD proof 

   - Selected AEC-Q100 qualification 

- Manufactured in a TS 16949 certified factory 

- Controlled BOM & PCN process 

- Customized options like CID registers, CPRM keys, firmware incl. settings and marking by projects 

- In-Field Firmware Update[3] 

- Swissbit Life Time Monitoring (SBLTM) Tool and SDK for SBLTM (on request) 

## MAF TALE Lea Oi]ere gs: 

> 3 The support of In-Field FW update capabilities on host systems is recommended. 

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## **3. Ordering Information** 

|**3. Ordering Information**|||
|---|---|---|
|Table 1: Standard Product List|||
|Capacity<br>Temperature<br>Extended<br>Industrial<br>Part Number<br>Part Number<br>4 GBytes<br>SFSD4096NxBM1ff-E-xx-2y1-STD<br>SFSD4096NxBM1ff-I-xx-2y1-STD<br>8 GBytes<br>SFSD8192NxBM1ff-E-xx-2y1-STD<br>SFSD8192NxBM1ff-I-xx-2y1-STD<br>16 GBytes<br>SFSD016GNxBM1ff-E-xx-2y1-STD<br>SFSD016GNxBM1ff-I-xx-2y1-STD<br>32 GBytes<br>SFSD032GNxBM1ff-E-xx-2y1-STD<br>SFSD032GNxBM1ff-I-xx-2y1-STD<br>64 GBytes<br>SFSD064GNxBM1ff-E-xx-2y1-STD<br>SFSD064GNxBM1ff-I-xx-2y1-STD<br>128 GBytes<br>SFSD128GNxBM1ff-E-xx-2y1-STD<br>SFSD128GNxBM1ff-I-xx-2y1-STD<br>~~=——~~|||
|x = product generation/configuration, ff = NAND flash and y = firmware revision|||
|Table 2: Available Part Numbers, MLC NAND Flash 15nm (FW B)|||
|Capacity<br>Temperature<br>Extended<br>Industrial<br>Part Number<br>Part Number<br>4 GBytes<br>SFSD4096N3BM1TO-E-GE-2B1-STD<br>SFSD4096N3BM1TO-I-GE-2B1-STD<br>8 GBytes<br>SFSD8192N3BM1TO-E-GE-2B1-STD<br>SFSD8192N3BM1TO-I-GE-2B1-STD<br>16 GBytes<br>SFSD016GN3BM1TO-E-LF-2B1-STD<br>SFSD016GN3BM1TO-I-LF-2B1-STD<br>32 GBytes<br>SFSD032GN3BM1TO-E-HG-2B1-STD<br>SFSD032GN3BM1TO-I-HG-2B1-STD<br>~~=~~|||
|Table 3: Available Part Numbers, MLC NAND Flash 15nm (FW D)|||
|Capacity<br>Temperature<br>Extended<br>Industrial<br>Part Number<br>Part Number<br>4 GBytes<br>SFSD4096N3BM1TO-E-GE-2D1-STD<br>SFSD4096N3BM1TO-I-GE-2D1-STD<br>8 GBytes<br>SFSD8192N3BM1TO-E-GE-2D1-STD<br>SFSD8192N3BM1TO-I-GE-2D1-STD<br>16 GBytes<br>SFSD016GN3BM1TO-E-LF-2D1-STD<br>SFSD016GN3BM1TO-I-LF-2D1-STD<br>32 GBytes<br>SFSD032GN3BM1TO-E-HG-2D1-STD<br>SFSD032GN3BM1TO-I-HG-2D1-STD<br>~~==~~|||
|Table 4: Available Part Numbers, 3D NAND Flash (FW E)|||
|Capacity<br>Temperature<br>Extended<br>Industrial<br>Part Number<br>Part Number<br>16 GBytes<br>SFSD016GN4BM1MT-E-1E-2E1-STD<br>SFSD016GN4BM1MT-I-1E-2E1-STD<br>32 GBytes<br>SFSD032GN4BM1MT-E-2F-2E1-STD<br>SFSD032GN4BM1MT-I-2F-2E1-STD<br>64 GBytes<br>SFSD064GN4BM1MT-E-3F-2E1-STD<br>SFSD064GN4BM1MT-I-3F-2E1-STD<br>128 GBytes<br>SFSD128GN4BM1MT-E-4G-2E1-STD<br>SFSD128GN4BM1MT-I-4G-2E1-STD<br>~~_——~~|||
|Swissbit AG||Revision: 1.34|
|Industriestrasse 4<br>Confidential||Doc-3667|
|CH-9552 Bronschhofen<br>www.swissbit.com||S-45u_data_sheet_SD-NxBM_Rev134|
|Switzerland<br>industrial@swissbit.com||Page 5 of 21|



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## **4. Product Description** 

The microSD Memory Card is a small form factor non-volatile memory card which provides high capacity data storage. Its aim is to capture, retain and transport data, audio and images, facilitating the transfer of all types of digital information between a large variety of digital systems. The card operates in two basic modes: 

- SDHC/SDXC and UHS-I card modes 

- SPI mode 

The micro SD Memory Card also supports SD Default and High Speed mode with up to 50MHz clock frequency as well as UHS-I modes DDR50, SDR12/25/50 with up to 100MHz clock frequency. The cards are compliant with 

- SD Memory Card Specification Part 1, Physical layer Specification V3.01 

- SD Memory card Specification Part 2, File System Specification V3.00 

- SD Memory card Specification Part 3, Security Specification  V3.00 

- MICRO SD Memory Card Addendum V4.00 

The Card has an internal intelligent controller, which manages interface protocols, data storage and retrieval as well as hardware BCH Error Correction Code (ECC), defect handling, diagnostics and clock control. The advanced wear leveling mechanism assures an equal usage of the Flash memory cells to extend the lifetime. The hardware BCH-code ECC allows to detect and correct up to 40 defect bits per 1kByte. The controller performs control read operations and checks the consistence of the data. If an error of some bits is detected, the card refreshes all data in the flash cells to prevent data retention problems. 

The card has a power-loss management feature to prevent data corruption after power-down. The cards are RoHS compliant and lead-free. 

## Related Documentation 

- Simplified specifications are available at (https://www.sdcard.org/) 

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## _**4.1 Performance Specification**_ 

Table 5: Read/Write Performance FW B 

|Capacity4|Sequential Read<br>(MB/s)|Sequential Write<br>(MB/s)|Random Read 4k<br>(IOPS)|Random Write 4k<br>(IOPS)|
|---|---|---|---|---|
|4 GBytes|31|15|642|689|
|8 GBytes|32|14|698|671|
|16 GBytes|33|14|734|688|
|32 GBytes|33|13|729|679|



## Table 6: Read/Write Performance FW D 

|Capacity4|Sequential Read<br>(MB/s)|Sequential Write<br>(MB/s)|Random Read 4k<br>(IOPS)|Random Write 4k<br>(IOPS)|
|---|---|---|---|---|
|4 GBytes|39|14|1,183|942|
|8 GBytes|38|21|1,170|871|
|16 GBytes|39|22|1,225|908|
|32 GBytes|40|22|1,216|964|



## Table 7: Read/Write Performance FW E 

|Capacity4|Sequential Read<br>(MB/s)|Sequential Write<br>(MB/s)|Random Read 4k<br>(IOPS)|Random Write 4k<br>(IOPS)|
|---|---|---|---|---|
|16 GBytes|42|19|1,312|963|
|32 GBytes|41|19|1,349|966|
|64 GBytes|41|19|1,289|946|
|128 GBytes|44|19|1,310|943|



## _**4.2 Environmental Specifications**_ 

## 4.2.1 Recommended operating conditions 

## Table 8: Recommended Operating Conditions 

|4.2.1 Recommended operating conditions<br>Table 8: Recommended Operating Conditions||
|---|---|
|Parameter|Value|
|Extended Operating Temperature|-25 °C to 85 °C|
|Industrial Operating Temperature|-40 °C to 85 °C|



## 4.2.2 Recommended Storage Conditions 

Table 9: Recommended Storage Conditions[5] Parameter Value Extended Operating Temperature -25 °C to 100 °C Industrial Storage Temperature -40 °C to 100 °C ~~_——~~ 

> 4 Performance measured with USB-SD Memory Card reader with Crystal Disk Mark test tool. 

> 5 High Temperature storage without operation reduces the data retention, in operation the data will be refreshed, if data error issues were detected 

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## 4.2.3 Humidity & EMC 

Table 10: Humidity and EMC 

|4.2.3 Humidity & EMC<br>Table 10: Humidity and EMC||
|---|---|
|Parameter|Value<br>85% RH @85°C 1000h<br>up to ±4 kV (contact discharge),<br>according to IEC61000-4-2 and SDA, Human Body Model 150pF/ 330Ohm,<br>on each contact pad, non-operating<br>up to ±15 kV, (air discharge),<br>according to IEC61000-4-2 and SDA, Human Body Model 150pF/ 330Ohm,<br>isolated contactpad area,non-operating|
|Humidity (non-condensing)||
|ESD||



4.2.4 Environmental conditions Table 11: Environmental conditions Parameter Value UV light exposure UV: 254nm, 15Ws/cm2 according to ISO7816-1 X-Ray 0.1 Gy 70keV to 140KeV (ISO7816-1) according SDA Durability 20,000 mating cycles Drop Test 1.5m free fall Bending / Torque 10N / 0.15Nm ±2.5° max 1500G, 0.5ms, half sine wave ±xyz-axis, 4 pulses each Mechanical Shock non-operating, JESD22B110 Condition B 50G, p-p, 20..2000Hz, sweep xyz-axis, Vibration ~~=——~~ 4 pulses each, non-operating, MIL-STD-883 M2007.3 Condition B _**4.3 Regulatory Compliance**_ The S-45u devices comply with the regulations / standards listed in Table 12. Table 12: Regulatory Compliance Abbreviation Regulation/ Standard (EU) 2014/30 EMC (FCC) 47 CFR Part 15 RoHS (EU) 2011/65/EU with 2015/863 and 2017/2102 REACh (EU) 1907/2006 and 207/2011 WEEE (EU) 2012/19 ~~an~~ _**4.4 Mechanical Specifications**_ Physical dimensions are detailed in the following Table 13. Figure 1 illustrates the S-45u dimensions. Table 13: Physical dimensions Physical Dimensions Unit Length 15.0±0.1 Width 11.0±0.1 mm Thickness (Max) 0.7 (1.)±0.1 Weight (Max Capacity) 0.4 g ~~es~~ Swissbit AG Revision: 1.34 Industriestrasse 4 Confidential Doc-3667 CH-9552 Bronschhofen www.swissbit.com S-45u_data_sheet_SD-NxBM_Rev134 Switzerland 

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## _**4.5 Reliability and Endurance**_ 

Data reliability with effective error tolerance and data retention at the beginning and end of life is provided in the table below. 

Table 14: Reliability 

|Table 14: Reliability||
|---|---|
|Parameter|Value6|
|Data Retention at beginning @ 40°C|10 years|
|Data Retention at life end (2k-3k PE cycles) @ 40°C|1 year|



## _**4.6 Geometry Specification**_ 

Table 15: Drive Geometry 

|Raw Capacity|Total LBA|User Addressable Bytes|
|---|---|---|
||Decimal|(Unformatted)|
|4 GBytes|7,774,208|3,980,394,496|
|8 GBytes|15,802,368|8,090,812,416|
|16 GBytes|31,834,112|16,299,065,344|
|32 GBytes|62,333,952|31,914,983,424|
|64 GBytes|124,735,488|63,864,569,856|
|128 GBytes|250,609,664|128,312,147,968|



## **5. Package Mechanical** 

NOTE: The microSD Memory Card contains a single chip controller and Flash memory module(s). The controller interfaces with a host system allowing data to be written to and read from the Flash memory module(s). 

Figure 1: Simplified mechanical dimensions 

The dimensions and tolerances are according to the SD specification. 

> 6 After every power on the card reads the whole flash and performs a data refresh if necessary. Therefore, the data retention can be much longer in most use cases. 

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## **6. Electrical Interface** 

Figure 2: microSD memory Card shape and interface (bottom view) 

– Table 16: Pin Assignment, Name and Description SD Mode 

|Pin|Signal Name|Type7|Description|
|---|---|---|---|
|1|DAT28|I/O/PP|Data Line [Bit 2]|
|2|CD/DAT39|I/O/PP10|Card Detect/ Data Line [Bit 3]|
|3|CMD|PP|Command/Response|
|4|VDD|S|Supply voltage|
|5|CLK|I|Clock|
|6|VSS|S|Supply voltage ground|
|7|DAT0|I/O/PP|Data Line [Bit 0]|
|8|DAT111|I/O/PP|Data Line [Bit 1]|



– Table 17: Pin Assignment, Name and Description SPI Mode 

|Pin|Signal Name|Type7|Description|
|---|---|---|---|
|1|RSV|||
|2|CS|I10|Chip Select (neg true)|
|3|DI|I|Data In|
|4|VDD|S|Supply voltage|
|5|SCLK|I|Clock|
|6|VSS|S|Supply voltage ground|
|7|DO|O/PP|Data Out|
|8|RSV|||



> 7 S: power supply; I: input; O: output using push-pull drivers; PP: I/O using push-pull drivers 

> 8 DAT2 line may be used as Read Wait signal in SDIO mode (refer to "SDIO Card Specification" for further details). 

> 9 The extended DAT lines (DAT1-DAT3) are input on power up. They start to operate as DAT lines after SET_BUS_WIDTH command. The Host shall keep its own DAT1-DAT3 lines in input mode, as well, while they are not used. 

> 10 At power up this line has a 50kOhm pull up enabled in the card. This resistor serves two functions Card detection and Mode Selection. For Mode Selection, the host can drive the line high or let it be pulled high to select SD mode. If the host wants to select SPI mode it should drive the line low. For Card detection, the host detects that the line is pulled high. The host should disconnect this pull-up during regular data transfer, with SET_CLR_CARD_DETECT (ACMD42) command. 

> 11 DAT1 line may be used as Interrupt Output (from the Card) in SDIO mode during all the times that it is not in use for data transfer operations (refer to "SDIO Card Specification" for further details). 

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## _**6.1 Power up / Power down behavior and reset**_ 

## 6.1.1 Power up 

When the voltage is ramped up the controller is ready (internal reset pin released) if the voltage reaches 1.65V. The host can start with communication 1ms after 2.7V is reached according the SDA specification. That should perform 74 clock cycles and start with the sequence CMD0, CMD8, ACMD41 until card is ready as described in the SD specification 3.01. 

## 6.1.2 Power down 

When the power falls below 2.6V the controller stops the communication to the flash, but enables the flash to finish a started flash program operation (if voltage drop is not fast). 

When the host shuts down the power, the card VDD shall be lowered to less than 0.1 V for a minimum period of 1 ms before the card is powered on again. 

After next initialization the controller checks the last written data for consistency and refreshes the data. Either the new or the old data (if the write operation could not be finished) are available. 

## 6.1.3 Power drop 

If the voltage drops below 2.6V and rises again, the card preforms a reset. The card must be initialized like after a power on. 

## 6.1.4 Operation below minimum voltage 

If the card initialization is performed below the specified voltage of 2.7V, the card may be detected as 1MB card with no useful data. In this case the host should power off and on the card and start initialization above 2.7V. 

## _**6.2 DC characteristics**_ 

Table 18: DC characteristics 

|Symbol<br>~~a ~~|Parameter<br>|Min|Typ|Max|Unit|Notes|
|---|---|---|---|---|---|---|
|IDD<br> <br>~~Co~~<br>~~a~~|Operating Current Read<br> ~~a~~||75|80|mA|@ 25°C|
||Operating Current Write<br> ~~a~~<br>~~a~~||70|80|mA|@ 25°C|
||Background read and refresh12<br>~~a~~||70|80|mA|@ 25°C|
||Pre-initialization Standby Current<br>~~a~~<br>~~es~~<br>~~Co~~|~~es~~<br>~~es~~|5<br>~~es~~|15<br>~~es~~|mA<br>~~es~~|@ 25°C<br>~~es~~|
||Post-initialization Standby Current13<br>~~es~~<br>~~Co~~|~~es~~<br>~~es~~|2<br>~~es~~|9<br>~~es~~|mA<br>~~es~~|@ 25°C<br>~~es~~|
|||~~es~~|5|15|mA|@ 25°C|
|ILI<br>~~Co~~<br>~~a~~|Input Leakage Current<br>~~Co~~|-2<br>~~es~~||2|µA|without pull up R|
|ILO<br>~~Co~~<br>~~aa~~|Output Leakage Current<br>~~Co~~|-2<br>~~es~~||2|||



## _**6.3 Signal loading**_ 

According to SD specification 

> 12 The card can perform auto data read of the whole card to check for ECC errors and performs data refresh 

> 13 Before auto read the idle current is larger than the typical idle current after auto read 

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## _**6.4 AC characteristics**_ 

## 6.4.1 Default speed mode (0-25MHz) 

According to SD specification 

## 6.4.2 High speed mode (0-50MHz) 

According to SD specification 

## 6.4.3 UHS modes 

UHS modes were driven with a signal level of 1.8V. The cards support following UHS-I modes: 

- Table 20: Supported UHS I modes 

|Table 20: Supported UHS-I modes|||
|---|---|---|
|Host request|Card Modes (to select by host)|max. Burst MB/s|
|SDR12|SDR12|up to 12.5|
|SDR25|SDR12, SDR25|up to 25|
|SDR50|SDR12, SDR25, SDR50|up to 50|
|DDR50|SDR12, SDR25, SDR50, DDR50|up to 50|



## **7. Host access specification** 

The following chapters summarize how the host accesses the card. 

## _**7.1 SD and SPI Bus Modes**_ 

The card supports SD and the SPI Bus modes. Application can chose either one of the modes. Mode selection is transparent to the host. The card automatically detects the mode of the reset command and will expect all further communication to be in the same communication mode. The SD mode uses a 4-bit high performance data transfer, and the SPI mode provides compatible interface to MMC host systems with little redesign, but with a lower performance. 

## 7.1.1 SD Bus Mode Protocol 

The SD Bus mode has a single master (host) and multiple slaves (cards) synchronous topology. Clock, power, and ground signals are common to all cards. After power up, the SD Bus mode uses DAT0 only; after initialization, the host can change the cards’ bus width from 1 bit (DAT0) to 4 bits (DAT0-DAT3). In high speed mode, only one card can be connected to the bus. 

Communication over the SD bus is based on command and data bit streams which are initiated by a start bit and terminated by a stop bit. 

- Command: a command is a token which starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line. 

- Response: a response is a token which is sent from an addressed card, or (synchronously) from all connected cards, to the host as an answer to a previously received command. A response is transferred serially on the CMD line. 

- Data: data can be transferred from the card to the host or vice versa. Data is transferred via the data lines. 

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## _**7.2 SPI Bus Mode Protocol**_ 

The Serial Parallel Interface (SPI) Bus is a general purpose synchronous serial interface. The SPI mode consists of a secondary communication protocol. The interface is selected during the first reset command after power up (CMD0) and it cannot be changed once the card is powered on. 

While the SD channel is based on command and data bit streams which are initiated by a start bit and terminated by a stop bit, the SPI channel is byte oriented. Every command or data block is built of 8-bit bytes and is byte aligned to the CS signal. 

The card identification and addressing methods are replaced by a hardware Chip Select (CS) signal. There are no broadcast commands. For every command, a card (slave) is selected by asserting (active low) the CS signal. The CS signal must be continuously active for the duration of the SPI transaction (command, response and data). The only exception occurs during card programming, when the host can de-assert the CS signal without affecting the programming process. 

The bidirectional CMD and DAT lines are replaced by unidirectional dataIn and dataOut signals. 

Table 21: SPI Bus signals 

|Table 21: SPI Bus signals||
|---|---|
|Signal|Description|
|/CS|Host to card chip select|
|CLK|Host to card clock signal|
|Data In|Host to card data signal|
|Data Out|Card to host data signal|
|Vdd, Vss|Power and ground|



## 7.2.1 Mode Selection 

The microSD Memory Card wakes up in the SD mode. It will enter SPI mode if the CS signal is asserted (negative) during the reception of the reset command (CMD0) and the card is in idle_state. If the card recognizes that the SD mode is required it will not respond to the command and remain in the SD mode. 

If SPI mode is required the card will switch to SPI and respond with the SPI mode R1 response. 

The only way to return to the SD mode is by entering the power cycle. In SPI mode the SD Memory Card protocol state machine is not observed. All the SD Memory Card commands supported in SPI mode are always available. During the initialization sequence, if the host gets Illegal Command indication for ACMD41 sent to the card, it may assume that the card is Multimedia Card. In that case it should restart the card as Multimedia Card using CMD0 and CMD1. 

## _**7.3 Card registers**_ 

The microSD Memory Card has the following registers. 

Table 22: microSD Memory Card registers 

|Register name|Bit width|Description|Function|
|---|---|---|---|
|CID|128|Card Identification<br>information|This register contains the card identification information<br>used duringthe Card Identificationphase.|
|OCR|32|Operation Conditions<br>Registers|This register describes the operating voltage range and<br>contains the status bit in thepower supply.|
|CSD|128|Card specific information|This register provides information on how to access the<br>card content. Some fields of this register are writeable<br>byPROGRAM_CSD(CMD27).|
|SCR|64|SD Memory Card’s Special<br>features|This register provides information on special features.|
|RCA14|16|Relative Card Address|This register carries the card address is SD Card mode.|
|SSR|512|SD Status|information about the card proprietary features and<br>vendor specific life time information|



> 14 RCA register is not available in SPI mode 

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|able 23: CID register|||SUWIISSDIT-|
|---|---|---|---|
|Register name|Bit width|Description|Typ. value|
|MID|8|Manufacture ID|0x5d|
|OID|16|OEM/Application ID|0x5342|
|PNM|40|Product Name|e.g.“0008G”|
|PRV|8|Product Revision|0xgg|
|PSN|32|Product Serial Number|xxxxxxxx|
|—|4|Reserved|0x0|
|MDT|12|Manufacture Date|0xyym|
|CRC|7|Check sum of CID contents|chksum|
|—|1|Not used; always=1|1|



## Table 24: OCR register 

|~~a~~|~~ae~~|~~ee~~|~~ee~~|~~ee~~||
|---|---|---|---|---|---|
|OCR bit positon<br>~~a~~|VDD voltage<br>windows<br>~~ae~~|Typ. value<br>~~ee~~|OCR bit<br>position<br>~~ee~~|VDD voltage window<br>~~ee~~|Typ. value|
|0-3<br>~~a~~<br>~~a~~|Reserved<br>~~ae ~~|0<br> ~~ee~~|15<br>~~ee~~|2.7-2.8<br>~~ee~~|1|
|4<br>~~a~~<br>~~es~~|1.6-1.7|0|16|2.8-2.9|1|
|5<br>~~a~~<br>~~es~~|1.7-1.8|0|17|2.9-3.0|1|
|6<br>~~es~~<br>~~a~~|1.8-1.9|0|18|3.0-3.1|1|
|7<br>~~a~~|1.9-2.0|0|19|3.1-3.2|1|
|8<br>~~a~~<br>~~a~~|2.0-2.1|0|20|3.2-3.3|1|
|9<br>~~a~~|2.1-2.2|0|21|3.3-3.4|1|
|10<br>~~a~~|2.2-2.3|0|22|3.4-3.5|1|
|11<br>~~a~~<br>~~a~~<br>~~ee~~|2.3-2.4<br>~~es~~|0<br>~~es~~|23<br>~~es~~|3.5-3.6<br>~~es~~|1|
|12<br>~~ee~~|2.4-2.5<br>~~es~~|0<br>~~es~~|24<br>~~es~~|Switching to 1.8V<br>accepted<br>~~es~~|1|
|13<br>~~ee ~~<br>~~a~~<br>~~es~~|2.5-2.6<br> ~~es~~|0<br>~~es~~|25-29<br>~~es~~|Reserved<br>~~es~~||
|14<br>~~a~~<br>~~es~~|2.6-2.7|0|30|Card Capacity Status (CCS)|*15|
|~~es~~<br>~~a~~|||31|0=busy; 1=ready|*16|



> 15 This bit is valid only when the card power up status bit is set 

> 16 This bit is set to LOW if the card has not finished the power up routine 

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Table 25: CSD register 

|Table 25: CSD register||||SUIISSDIT|
|---|---|---|---|---|
|Register name<br>~~a~~|Bits|Bit width|Description|Typ. value|
|CSD_STRUCTURE<br>~~a~~<br>~~a~~|127:126|2|CSD structure|01|
|—<br>~~a~~<br>~~a~~|125:120|6|Reserved|00000|
|TAAC<br>~~a~~|119:112|8|Data read access time 1|00001110|
|NSAC<br>~~a~~<br>~~a~~<br>~~a~~|111:104<br>~~ae~~|8<br>~~ee ee~~|Data read access time 2 (CLK cycle)<br>~~ee~~|00000000<br>~~ee~~|
|TRAN_SPEED<br>~~a~~<br>~~a~~|103:96<br>~~ae~~|8<br>~~ee ee~~|Data transfer rate<br>~~ee~~|00110010 Default speed<br>00001011 SDR 50<br>or other values<br>~~ee~~|
|CCC<br>~~a~~<br>~~a~~|95:84<br>~~ae ~~|12<br> ~~ee ee~~|Card command classes<br>~~ee~~|010110110101<br>~~ee~~|
|READ_BL_LEN<br>~~a~~|83:80<br>|4<br>|Read data block length<br>|1001<br>|
|READ_BL_PARTIAL<br>~~aee~~|79<br>~~ee~~|1<br>~~ee~~|Partial blocks for read allowed<br>~~ee~~|0<br>~~ee~~|
|WRITE_BLK_MISALIGN<br>~~ee~~<br>~~a~~|78<br>~~ee~~|1<br>~~ee~~|Write block misalignment<br>~~ee~~|0<br>~~ee~~|
|READ_BLK_MISALIGN<br>~~a~~|77<br>|1<br>|Read block misalignment<br>|0<br>|
|DSR_IMP<br>~~ee~~|76<br>~~ee~~|1<br>~~ee~~|DSR implemented<br>~~ee~~|0<br>~~ee~~|
|—<br>~~a~~<br>~~a~~|75:70<br>|6<br>|Reserved<br>|000000<br>|
|C_SIZE<br>~~a~~<br>~~a~~|69:48<br>|22<br>|Device size<br>|xxx17<br>|
|—<br>~~aa~~|47<br>|1<br>|Reserved<br>|0<br>|
|ERASE_BLK_EN<br>~~aee~~<br>~~a~~|46<br>~~ee~~|1<br>~~ee~~|Erase single block enable<br>~~ee~~|1<br>~~ee~~|
|SECTOR_SIZE<br>~~ee~~<br>~~a~~|45:39<br>~~ee~~|7<br>~~ee~~|Erase sector size<br>~~ee~~|1111111<br>~~ee~~|
|WP_GRP_SIZE<br>~~aa~~<br>~~a~~|38:32<br>|7<br>|Write protect group size<br>|0000000<br>|
|WP_GRP_ENABLE<br>~~a~~<br>~~a~~|31<br>|1<br>|Write protect group enable<br>|0<br>|
|—<br>~~aee~~|30:29<br>~~ee~~|2<br>~~ee~~|Reserved<br>~~ee~~|00<br>~~ee~~|
|R2W_FACTOR<br>~~a~~|28:26|3|Write speed factor|010|
|WRITE_BL_LEN<br>~~a~~<br>~~a~~|25:22|4|Write data block length|100117|
|WRITE_BL_PARTIAL<br>~~a~~|21<br>|1<br>|Partial blocks for write allowed<br>|0<br>|
|—<br>~~a~~|20:16<br>|5<br>|Reserved<br>|00000<br>|
|FILE_FORMAT_GRP<br>~~ee~~|15<br>~~ee~~|1<br>~~ee~~|File format group<br>~~ee~~|0 W(1)<br>~~ee~~|
|COPY<br>~~a~~|14<br>|1<br>|Copy flag<br>|0 W(1)<br>|
|PERM_WRITE_PROTECT<br>~~aee~~|13<br>~~ee~~|1<br>~~ee~~|Permanent write protection<br>~~ee~~|0 W(1)<br>~~ee~~|
|TMP_WRITE_PROTECT<br>~~a~~|12|1|Temporary write protection|0 W|
|FILE_FORMAT<br>~~a~~|11:10<br>|2<br>|File format<br>|00 W(1)<br>|
|—<br>~~aee~~|9:8<br>~~ee~~|2<br>~~ee~~|Reserved<br>~~ee~~|00 W<br>~~ee~~|
|CRC<br>~~a~~|7:1|7|Checksum of CSD contents|xxxxxxx W|
|—<br>~~a~~<br>~~a~~|0|1|Always=1|1|



Memory capacity = (C_SIZE+1) * 512kByte 

W value can be changed with CMD27 (PROGRAM_CSD) W(1) value can be changed ONCE with CMD27 (PROGRAM_CSD) 

> 17 Drive size and block sizes vary with card capacity 

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Table 26: SCR register 

|Table 26: SCR register||||SUIISSDIT|
|---|---|---|---|---|
|Field<br>~~a~~|Bits<br>|Bit width<br>|Typ. value<br>|Remark<br>|
|SCR_STRUCTURE<br>~~a~~|63:60<br>|4<br>|0000<br>|SCR 1.01…2.00<br>|
|SD_SPEC<br>~~es~~|59:56<br>~~es~~|4<br>~~es~~|0010<br>~~es~~|SD 2.0 or 3.0<br>~~es~~|
|DATA_STAT_AFTER_ERASE<br>~~a~~|55<br><br>~~es~~|1<br><br>~~Gs~~|1<br><br>~~Gs~~|data are 0xFF after erase<br>|
|SD_SECURITY<br>~~aes~~|54:52<br>~~es~~<br>~~es~~|3<br>~~es~~<br>~~Gs~~|011<br>100<br>~~es~~<br>~~Gs~~|2.00 (SDHC)<br>3.xx(SDXC)<br>~~es~~|
|SD_BUS_WIDTHS<br>~~es~~<br>~~es~~|51:48<br>~~es~~<br>~~es~~<br>~~es~~|4<br>~~es~~<br>~~Gs~~<br>~~es~~|0101<br>~~es~~<br>~~Gs~~<br>~~es~~|1 or 4 bit<br>~~es~~<br>~~es~~|
|SD_SPEC3<br>~~a~~|47<br>|1<br>|1<br>|yesSD3.0<br>|
|EX_SECURITY<br>~~aes~~|46:43<br>~~es~~|4<br>~~es~~|0000<br>~~es~~|no extended security<br>~~es~~|
|Reserved<br>~~a~~|42:34|9|0|0|
|CMD_SUPPORT<br>~~a~~|33:32<br>|2<br>|11<br>|CMD23 and CMD20 supported<br>|
|Reserved<br>~~aes~~|31:0<br>~~es~~|32<br>~~es~~|0<br>~~es~~|0<br>~~es~~|



Table 27: RCA register 

|Table 28: SSR register|||||
|---|---|---|---|---|
|Field<br>~~ne~~|Bits<br>~~ne~~|Bit width<br>~~ne~~|Typ. value<br>~~ne~~|Remark<br>~~ne~~|
|Data bus width<br>~~ne~~<br>~~a~~|511:510<br>~~ne~~|2<br>~~ne~~|0x219<br>~~ne~~|4 bit width<br>~~ne~~|
|Secured mode<br>~~a~~|509:509|1|0x0|not secured|
|Reserved for security<br>~~ee~~|508:502<br>~~ee~~|7<br>~~ee~~|0x00<br>~~ee~~|-<br>~~ee~~|
|Reserved<br>~~ee~~<br>~~a~~|501:496<br>~~ee~~|6<br>~~ee~~|0x00<br>~~ee~~|-<br>~~ee~~|
|SD card type<br>~~ee~~<br>~~a~~|495:480<br>~~ee~~<br>~~ee~~|16<br>~~ee~~<br>~~ee~~|0x0000<br>~~ee~~<br>~~ee~~|Regular SD<br>~~ee~~<br>~~ee~~|
|Size protected area<br>~~ee~~<br>~~a~~|479:448<br>~~ee~~<br>~~ee~~|32<br>~~ee~~<br>~~ee~~|0x03000000<br>0x04000000<br>…<br>~~ee~~<br>~~ee~~|48MB<br>64MB<br>…<br>~~ee~~<br>~~ee~~|
|Speed class<br>~~a~~<br>~~a~~|447:440<br>~~ee ~~|8<br> ~~ee ~~|0x04<br> ~~ee~~|Class 10<br>~~ee~~|
|Move performance<br>~~a~~<br>~~a~~<br>~~a~~|439:432|8|0x05|5 MB/s|
|Allocation unit size<br>~~a~~<br>~~a~~|431:428|4|0x9|4 MB|
|Reserved<br>~~aa~~<br>~~a~~|427:424|4|0x0||
|Erase unit size<br>~~a~~<br>~~a~~|423:408|16|0x0001|1 AU|
|Erase unit timeout<br>~~aa~~|407:402|6|0x01|1 second|
|Erase unit offset<br>~~a~~<br>~~a~~|401:400<br>|2<br>|0x1<br>|1 second<br>|
|UHS mode Speed Grade<br>~~a~~<br>~~a~~|399:396<br>|4<br>|0x1<br>|UHS Grade1<br>|
|Allocation unit size in UHS mode<br>~~ane~~|395:392<br>~~ne~~|4<br>~~ne~~|0x9<br>~~ne~~|4 MB<br>~~ne~~|
|Reserved<br>~~ne~~<br>~~a~~|391:312<br>~~ne~~<br><br>~~ee~~|80<br>~~ne~~<br><br>~~ee~~|~~ne~~<br><br>~~es~~|~~ne~~<br>|
|Data structure version identifier,<br>currently1<br>~~es~~|311:304<br>~~es~~<br>~~ee~~<br>~~ee~~|8<br>~~es~~<br>~~ee~~<br>~~ee~~|0x01<br>~~es~~<br>~~es~~<br>~~es~~|version 1<br>~~es~~|
|Number of manufacturer marked<br>defect blocks<br>~~es~~|303:288<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~ee~~|16<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~ee~~|0x0008<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|8 initial BB<br>~~es~~|
|Number of initial spare blocks<br>(worst chip)<br>~~es~~|287:272<br>~~ee~~<br>~~es~~<br>~~ee~~|16<br>~~ee~~<br>~~es~~<br>~~ee~~|0x0074<br>~~es~~<br>~~es~~<br>~~es~~|116 spare blocks<br>~~es~~|



> 18 After initialization the host can change the RCA register 

> 19 Value changes in operation 

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Number of initial spare blocks 271:256 16 0x0074 116 spare blocks (sum over all chips) ~~ee ee~~ Percentage of remaining spare 255:248 8 0x64[19] 100% ~~ee~~ blocks (worst chip) ~~ee ee ee~~ Percentage of remaining spare 247:240 8 0x64[19] 100% ~~ee~~ blocks (all chips) Number of uncorrectable ECC errors (not including ECC errors 239:224 16 0x0000[19] 0 uncorrectable errors ~~a~~ during startup) ~~ee ee ee eeee~~ Number of correctable ECC errors (not including ECC errors during 223:192 32 0x0045074b[19] 4523851 correctable ECC errors ~~ee~~ startup) ~~ee ee ee~~ Lowest wear level class 191:176 16 0x0000[19] 0 ~~Se~~ Highest wear level class 175:160 16 0x0000[19] 0 ~~Se~~ Wear level threshold 159:144 16 0x003f 63 block erases per WL class ~~SS~~ Total number of block erases 143:96 48 0x00…1ff0[19] 8176 block erase commands ~~Sn~~ Number of flash blocks, in units 95:80 16 0x0008 2048 flash blocks ~~ee~~ of 256 blocks ~~ae ee ee ee~~ Maximum flash block erase count Flash endurance xx 79:64 16 0x00xx ~~ee~~ target, in wear level class units ~~ee ee ee ee~~ WL classes Power on count 63:32 32 0x00000003[19] 3x power on ~~Se~~ Firmware version 31:0 32 0xYYMMDDXX Firmware version ~~SS~~ Bit 311:0 are vendor specific, example values in the table 

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## **8. Part Number Decoder** 

S F SD  128G  N 4 B M 1 MT - I - 4 G - 2E1 - STD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Manuf. Option Memory Type. Configuration Product Type Manuf. Code: Flash Mode Density Manuf. Code: Flash Package Platform Temp. Option Product Generation Flash Vendor Code Memory Organization Channels ~~mm~~ Technology _**8.1 Manufacturer**_ Swissbit code S _**8.2 Memory Type**_ 

Swissbit code S Flash F SATA Interface SD 4 GBytes 4096 8 GBytes 8192 16 GBytes 016G 32 GBytes 032G 64 GBytes 064G 128G GBytes 128G ~~—~~ microSD Memory Card N x8 B S-45u Series M 1 Flash channel 1 

## _**8.3 Product Type**_ 

## _**8.4 Density**_ 

## _**8.5 Platform**_ 

## _**8.6 Product Generation**_ 

## _**8.7 Memory Organization**_ 

## _**8.8 Technology**_ 

## _**8.9 Channels**_ 

## _**8.10 Flash Code**_ 

|Toshiba / Kioxia|TO|
|---|---|
|Micron|MT|



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## _**8.11 Temperature Option**_ 

Extended Temperature Range: -25 °C to 85°C E ~~———~~ Industrial Temperature Range: -40 °C to 85 °C I 

## _**8.12 Die Classification**_ 

|MLC MONO(single diepackage)|G|
|---|---|
|MLC DDP(dual diepackage)|L|
|MLC TDP(triple diepackage)|J|
|MLCQDP(quad diepackage)|H|
|3D MLC MONO(single diepackage)|1|
|3D MLC DDP(dual diepackage)|2|
|3D MLC TDP(triple diepackage)|9|
|3D MLCQDP(quad diepackage|3|
|3D MLC ODP (oct diepackage)|4|



## _**8.13 Pin Mode**_ 

## _**8.14 Configuration XYZ**_ 

Single nCE & R/nB E Dual nCE & R/nB F Triple nCE & R/nB K ~~——_=~~ Quad nCE & R/nB G X = Configuration Default, non UHS 1 UHS-I 2 ~~——ee~~ Y = Firmware Revision durabit version 1 A durabit version 2 B durabit version 5 E ~~———~~ Z = Features Standard 1 2plane 2 ~~———~~ pSLC P 

## _**8.15 Option**_ 

Swissbit/Standard 

STD 

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## **9. Swissbit Specification** 

## _**9.1 Top view**_ 

Figure 3: S-45u top view 

- Swissbit logo 

- Density 

- SD Speedclass 10 logo 

- UHS Speedclass U1 logo 

- microSDXC logo 

- UHS-I interface logo 

## _**9.2 Bottom view**_ 

Figure 4: S-45u bottom view 

**==> picture [80 x 49] intentionally omitted <==**

**----- Start of picture text -----**<br>
SFSD128GN4BM1<br>MT-I-4G-2E1-STD<br>CWYY<br>60123456<br>**----- End of picture text -----**<br>


- Part number 

- Manufacturing date 

- Lot code 

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## **10. Revision History** 

Table 29: Document Revision History 

|Date|Revision|Description|Revision Details|
|---|---|---|---|
|January 27, 2015|0.90|Initial preliminary release|-|
|September 28,<br>2015|1.00|Standby currents, busy times, RoHS, ACPEIP and WEEE<br>declaration|Doc. req. no. 0784|
|February 24, 2016|1.10|Generation 3 added, current performance values, registers|-|
|July 4, 2016|1.20|Updated Chapter 4, 5, 6 and removed CE declaration|Doc. req. no. 1157|
|November 11, 2016|1.21|Corrected typo in chapter Environmental Conditions and<br>updated specification layout|Doc. req. no. 1365|
|June 07, 2017|1.22|Formal layout changes|Doc. req. no. 1710|
|January 07, 2019|1.32|Updated feature icons, removed A19 variations, added new<br>variations with firmware “E”, updated performance values<br>andpart number decoder.|Doc. req. no. 2726|
|March 29, 2019|1.33|Added new variations and changed data sheet layout|Doc. req. no. 2894|
|April 29, 2021|1.34|Formal changes, updated power up/down behavior and<br>regulatorycompliance.|Doc. req. no. 4552|



## Disclaimer: 

No part of this document may be copied or reproduced in any form or by any means, or transferred to any third party, without the prior written consent of an authorized representative of Swissbit AG (“SWISSBIT”). The information in this document is subject to change without notice. SWISSBIT assumes no responsibility for any errors or omissions that may appear in this document, and disclaims responsibility for any consequences resulting from the use of the information set forth herein. SWISSBIT makes no commitments to update or to keep current information contained in this document. The products listed in this document are not suitable for use in applications such as, but not limited to, aircraft control systems, aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. Moreover, SWISSBIT does not recommend or approve the use of any of its products in life support devices or systems or in any application where failure could result in injury or death. If a customer wishes to use SWISSBIT products in applications not intended by SWISSBIT, said customer must contact an authorized SWISSBIT representative to determine SWISSBIT willingness to support a given application. The information set forth in this document does not convey any license under the copyrights, patent rights, trademarks or other intellectual property rights claimed and owned by SWISSBIT. The information set forth in this document is considered to be “Proprietary” and “Confidential” property owned by SWISSBIT. 

ALL PRODUCTS SOLD BY SWISSBIT ARE COVERED BY THE PROVISIONS APPEARING IN SWISSBIT’S TERMS AND CONDITIONS OF SALE ONLY, INCLUDING THE LIMITATIONS OF LIABILITY, WARRANTY AND INFRINGEMENT PROVISIONS. SWISSBIT MAKES NO WARRANTIES OF ANY KIND, EXPRESS, STATUTORY, IMPLIED OR OTHERWISE, REGARDING INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED PRODUCTS FROM INTELLECTUAL PROPERTY INFRINGEMENT, AND EXPRESSLY DISCLAIMS ANY SUCH WARRANTIES INCLUDING WITHOUT LIMITATION ANY EXPRESS, STATUTORY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. 

©2021 SWISSBIT AG All rights reserved. 

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