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SFSD512GL1AM1MT-I-8H-211-STD
Flash Memory Card, 3D TLC, SDXC Card, 512 GB, Class 10
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: SWISSBIT
- Product type: Flash Memory Cards
- SVHC: No SVHC (15-Jan-2018)
- App Rating: -
- Product Range: S-55 Series
- Memory Capacity: 512GB
- Supply Voltage Nom: 3.3V
- Standard Speed Class: Class 10
- Flash Memory Card Type: SDXC Card
- Operating Temperature Max: 85°C
- Operating Temperature Min: -40°C
| Delivery and price | |
|---|---|
| Units per pack | 5 |
| Price | 162.5 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
Product Data Sheet
**Industrial SDXC Memory Card S-55 High reliability series** UHS-I Interface, 3D TLC
Extended and Industrial Temperature Grade
Date: March 25, 2022 Revision: 1.01
## **Contents**
||**Contents**|
|---|---|
|1.|PRODUCT SUMMARY ............................................................................................................ 3|
|2.|PRODUCT FEATURES ............................................................................................................ 3|
|3.|ORDERING INFORMATION ...................................................................................................... 5|
|4.|PRODUCT DESCRIPTION ......................................................................................................... 6|
||4.1 PERFORMANCESPECIFICATIONS..................................................................................................... 6|
||4.2 ENVIRONMENTALSPECIFICATIONS.................................................................................................. 6|
||4.3 REGULATORYCOMPLIANCE.......................................................................................................... 7|
||4.4 PHYSICAL DIMENSIONS............................................................................................................. 8|
||4.5 RELIABILITY....................................................................................................................... 8|
||4.6 ENDURANCE....................................................................................................................... 8|
|5.|USER DENSITY SPECIFICATION ................................................................................................. 8|
|6.|CARD PHYSICAL ................................................................................................................. 9|
||6.1 PHYSICAL DESCRIPTION............................................................................................................. 9|
|7.|ELECTRICAL INTERFACE ........................................................................................................ 10|
||7.1 ELECTRICAL DESCRIPTION........................................................................................................... 10|
||7.2 POWER UP/ POWER DOWN BEHAVIOR AND RESET................................................................................... 11|
||7.3 DCCHARACTERISTICS............................................................................................................... 11|
||7.4 SIGNAL LOADING................................................................................................................... 12|
||7.5 ACCHARACTERISTICS............................................................................................................... 12|
|8.|HOST ACCESS SPECIFICATION .................................................................................................. 13|
||8.1 SDANDSPI BUSMODES.......................................................................................................... 13|
||8.2 CARDREGISTERS.................................................................................................................. 14|
|9.|LIFE TIME MONITORING ....................................................................................................... 19|
|10.|PART NUMBER DECODER ...................................................................................................... 20|
|11.|MARKING SPECIFICATION ..................................................................................................... 22|
||11.1 TOPVIEW.........................................................................................................................22|
||11.2 BACK SIDE MARKING..............................................................................................................22|
|12.|REVISION HISTORY ............................................................................................................. 23|
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## **S-55 High reliability series Industrial SDXC Memory Card – 64 GBytes up to 512 GBytes**
## **1. Product Summary**
- Capacities: 64 GBytes, 128 GBytes, 256 GBytes, 512 GBytes
- Form Factor: Standard SD Memory card form factor - 32.0mm x 24.0mm x 2.1mm, Write Protect slider
- Compliance[1] : Fully compliant with SD Memory Card specification 6.10
- SDXC high speed mode, UHS-I
- Speed class 10/U3/V30/A1/A2 according SD6.10 specification
- SD2.0 backward compliant
- exFAT preformatted
- Environmental: RoHS / REACH Compliant
- Compatibility: Support SD SPI mode
- Performance (max. capacity):
- Read performance: sequential read up to 97 MBytes/s
- Write performance: sequential write up to 60 MBytes/s
- SDR12, SDR25, SDR50, SDR104, DDR50 mode
- Operating Temperature Range:
- Extended: -25 °C to 85 °C
- Industrial: -40 °C to 85 °C
- Storage Temperature Range: -40 °C to 85 °C
- Operating Voltage: 2.7…3.6V
- Data Retention: 10 years @ life begin; 1 year @ life end
- Error Correction: Advanced ECC (Error Correction Code)
- Mean Time Between Failure (MTBF): > 3,000,000 hours
- Number of insertions: up to 20,000
## **2. Product Features**
- High performance 6.10 specification
- SD burst up to 104MB/s
- SD Normal speed 0…25MHz clock rate
- SD High speed 25…50MHz clock rate
- SD UHS-I speed 0...50MHz (DDR) and 0…208MHz (SDR)
- Power Supply: (Low-power CMOS technology)
- 2.7…3.6V normal operating voltage
- Optimized FW algorithms especially for read/write access, highest random write performance and best endurance with long data retention.
- Designed for usage in applications with highest requirements regarding reliability like data logging, POS/POI, Medical and other demanding use-cases.
- Especially suitable for intensive read/write operations
- Advanced power-off reliability technology
- Wear Leveling technology
- Equal wear leveling of static and dynamic data. The wear leveling assures that dynamic data as well as static data is balanced evenly across the memory. With that the maximum write endurance of the device is guaranteed
- The S-55 high reliability series is optimized for high read/write traffic for demanding industrial applications.
> 1 The verification of host system and storage device compatibility is in customer’s responsibility. Swissbit can provide guidance and support on request.
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- Read Disturb Management
- The read commands are monitored and the content is refreshed when critical levels have occurred
- Data Care Management The interruptible background process maintain the user data for Read Disturb effects or Retention degradation due to high temperature effects
- Near miss ECC technology
- Minimize the risk of uncorrectable bit failure over the product life time. Each read command analyzes the ECC margin level and refresh data if necessary
- Diagnostic features with Life Time Monitoring tool support
- High reliability
- The product is optimized for long life cycle that requires superior data retention because of high temperature mission profile
- FW is designed to ensure highest reliability at lowest possible DPPM rates
- Number of card insertions/removals up to 20,000
- Industrial Temperature range -40° up to 85°C
- SIP (System In Package) process for extreme dust, water and ESD proof
- Controlled “Locked” BOM & PCN process
- Customized options like CID registers, CPRM keys, firmware incl. settings and marking on request
- Manufactured in a TS 16949 certified factory
- In-field firmware update[2]
- Swissbit Life Time Monitoring (SBLTM) Tool and SDK for SBLTM (on request)
17 (718 Lec]
> 2 The support of In-Field FW update capabilities on host systems is recommended.
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## **3. Ordering Information**
## Table 1: Standard Product List
|Capacity|Temperature|Temperature|
|---|---|---|
||Extended|Industrial|
||Part Number|Part Number|
|64 GBytes|SFSD064GLgAM1MT-E-xx-2y1-STD|SFSD064GLgAM1MT-I-xx-2y1-STD|
|128 GBytes|SFSD128GLgAM1MT-E-xx-2y1-STD|SFSD128GLgAM1MT-I-xx-2y1-STD|
|256 GBytes|SFSD256GLgAM1MT-E-xx-2y1-STD|SFSD256GLgAM1MT-I-xx-2y1-STD|
|512 GBytes|SFSD512GLgAM1MT-E-xx-2y1-STD|SFSD512GLgAM1MT-I-xx-2y1-STD|
g = product generation, xx = flash configuration, y = firmware revision
Table 2: Available Part Numbers
|Capacity|Temperature|Temperature|
|---|---|---|
||Extended|Industrial|
||Part Number|Part Number|
|64 GBytes|SFSD064GL1AM1MT-E-5E-211-STD|SFSD064GL1AM1MT-I-5E-211-STD|
|128 GBytes|SFSD128GL1AM1MT-E-6F-211-STD|SFSD128GL1AM1MT-I-6F-211-STD|
|256 GBytes|SFSD256GL1AM1MT-E-7G-211-STD|SFSD256GL1AM1MT-I-7G-211-STD|
|512 GBytes|SFSD512GL1AM1MT-E-8H-211-STD|SFSD512GL1AM1MT-I-8H-211-STD|
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## **4. Product Description**
The SD Memory Card is a small form factor non-volatile memory card that provides high capacity data storage. Its aim is to capture, retain and transport data, audio and images, facilitating the transfer of all types of digital information between a large variety of digital systems. The card operates in two basic modes:
- SDXC and UHS-I card modes
- SPI mode
The SD Memory Card also supports SD Default and High Speed mode with up to 50MHz clock frequency as well as UHS-I modes DDR50, SDR12/25/50/104 with up to 208MHz clock frequency.
- SD Memory card Specification Part 1, Physical layer Specification V6.10
- SD Memory card Specification Part 2, File System Specification V3.00
- Standard Size SD Card Mechanical Addendum Ver6.10
## Simplified specifications are available at https://www.sdcard.org/
The Card has an internal intelligent controller that manages interface protocols, data storage and retrieval as well as hardware LDPC Error Correction Code (ECC), defect handling, diagnostics and clock control. The advanced wear leveling mechanism assures an equal usage of the Flash memory cells to extend the lifetime.
The hardware LDPC-code ECC allows to detect and correct up to 120 defect bits per 1kByte.
The card has a power-loss management feature to prevent data corruption after power-down.
The cards are RoHS compliant and lead-free.
## _**4.1 Performance Specifications**_
The S-55 read/write sequential and random CDM performance benchmarks are detailed in Table 3.
Table 3: Read/Write Performance
|Table 3: Read/Write Performance||||||
|---|---|---|---|---|---|
|System Performance|typ3||||Unit|
||64GB|128GB|256GB|512GB||
|Sequential Read|97|97|97|97|MB/s|
|Sequential Write|31|58|60|60||
|Random Read 4k|1970|1970|1970|1970|IOPS|
|Random Write 4k|760|760|760|840||
## _**4.2 Environmental Specifications**_
|Parameter|min|typ|max|unit|
|---|---|---|---|---|
|Extended Operating Temperature|-25|25|85|°C|
|Industrial Operating Temperature|-40|25|85|°C|
> 3 Card Speed measured with USB-SD Memory Card reader with Crystal Disk Mark 5.1.2 test tool 5x 1GB.
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## Recommended storage conditions
Table 5: SD Memory Card recommended storage conditions[4]
|Parameter|min|typ|max5|unit|
|---|---|---|---|---|
|Extended Storage Temperature|-25|25|100|°C|
|Industrial Storage Temperature|-40|25|100|°C|
## Humidity & EMC
Table 6: Humidity & EMC
|Humidity & EMC<br>Table 6: Humidity & EMC||
|---|---|
|Parameter|Condition|
|Humidity (non-condensing)|85% RH @85°C 1000h|
|ESD|up to ±4 kV (contact discharge),<br>according to IEC61000-4-2 and SDA, Human Body Model 150pF/ 330Ohm,<br>on each contact pad, non-operating<br>up to ±15 kV, (air discharge),<br>according to IEC61000-4-2 and SDA, Human Body Model 150pF/ 330Ohm,<br>isolated contactpad area,non-operating|
## Environmental conditions
## Table 7: Environmental conditions
|Parameter|Condition|
|---|---|
|UV light exposure|UV: 254nm, 15Ws/cm<br>2according to ISO7816-1|
|X-Ray|0.1 Gy 70keV to 140KeV (ISO7816-1) according SDA|
|Durability|20,000 mating cycles|
|Drop Test|1.5m free fall|
|Bending / Torque|10N / 0.15Nm ±2.5° max|
|Mechanical Shock|1500G, 0.5ms, half sine wave ±xyz-axis, 4 pulses each<br>non-operating,JESD22B110/B104 Condition B|
|Vibration|Non-operating, JESD22B110/B104 Condition B|
## _**4.3 Regulatory Compliance**_
The S-55 devices comply with the regulations / standards listed in Table 8.
Table 8: Environmental conditions
|Abbreviation|Regulation/ Standard|
|---|---|
||CE - 2014/30/EU|
|EMC|FCC - 47 CFR Part 15|
||UKCA - S.I. 2016 No. 1091 and S.I. 2012 No. 3032|
|RoHS|2011/65/EU with 2015/863/EU and 2017/2102/EU|
|REACh|1907/2006/EU and 207/2011/EU|
|WEEE|2012/19/EU|
> 4 The data retention time at temperature above 40°C is reduced. Swissbit can provide more data and support on request.
> 5 High Temperature storage without operation reduces the data retention, in operation the data will be refreshed, if data error issues were detected
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## _**4.4 Physical dimensions**_
## Table 9: Physical dimensions
|**_4.4 Physical dimensions_**<br>Table 9: Physical dimensions|||
|---|---|---|
|Outer Physical dimensions|Value|Unit|
|Length|32.00±0.1|mm|
|Width|24.00±0.1||
|Thickness|2.10±0.15||
|Weight (typ.)|2|g|
## _**4.5 Reliability**_
Data reliability with data retention at the beginning and end of life is provided in the table below.
Table 10: Reliability[6] Parameter Value[7] Data Retention at beginning @ 40°C 10 years Data Retention at life end @ 40°C 1 year ~~SSS~~
## _**4.6 Endurance**_
Endurance represented as TeraBytes Written (TBW) is provided in the following Table 11:
Table 11: Endurance[8,][9]
TeraBytes Written (TBW) TeraBytes Written (TBW) TeraBytes Written (TBW) Drive @ @ @ Capacity Seq. Write 1MB Random Write 128kB Random Write 4kB Operation Operation Operation 64 GBytes 140 3.5 0.8 128 GBytes 270 7.5 1.0 256 GBytes 475 20 2.6 512 GBytes 940 40 4.5 ~~————~~ **5. User density specification** Table 12: SD Memory Card capacity specification
|Capacity<br>Sectors<br>Total addressable Bytes<br>64 GBytes<br>121,634,816<br>62,277,025,792<br>128 GBytes<br>244,809,728<br>125,342,580,736<br>256 GBytes<br>492,077,056<br>251,943,452,672<br>512 GBytes<br>984,154,112<br>503,886,905,344<br>~~———~~||
|---|---|
|6NAND Flash data retention and endurance characteristics are defined according to JEDEC JESD47 and JESD22. The endurance limits of the|NAND Flash data retention and endurance characteristics are defined according to JEDEC JESD47 and JESD22. The endurance limits of the|
|storage shall be monitored by the life time information and simulated before field usage by the customer.||
> 7 After every power on the card reads the whole flash and performs a data refresh if necessary. Therefore, the data retention can be much longer in most use cases. 8 The specified TBW is valid, if the amount of data is spread evenly over at least 24 months. Higher daily data volume or frequent writing below 0°C reduces the specified TBW. The drive endurance limit, also called EOL or 0% remaining life, is defined as TBW or DWPD over the product’s limited lifetime warranty period. TBW calculations refer to the JEDEC JESD218A and JESD219A standard for SSD device life and endurance measurement techniques if not otherwise specified.
> 9 Sequential write 1MB simulates a continuous stream recording on a drive which has been preconditioned with a sequential write of the complete drive, Random Write 128KB or 4KB represent data logging applications with large or small block sizes.
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## **6. Card physical**
## _**6.1 Physical description**_
The SD Memory Card contains a single chip controller and Flash memory module(s). The controller interfaces with a host system allowing data to be written to and read from the Flash memory module(s).
Figure 1: Simplified mechanical dimensions SD Memory Card
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## **7. Electrical interface**
## _**7.1 Electrical description**_
Figure 2: SD Memory Card shape and Interface (bottom view)
– Table 13: Pad Assignment SD Mode
|Table 13: Pad Assignment|Table 13: Pad Assignment–SD Mode|Table 13: Pad Assignment–SD Mode|Table 13: Pad Assignment–SD Mode|
|---|---|---|---|
|Pin|SD Mode|||
||Name|Type10|Description|
|1|CD/DAT311|I/O/PP12|Card Detect/Data Line [Bit 3]|
|2|CMD|PP|Command/Response|
|3|VSS1|S|Supply voltage ground|
|4|VDD|S|Supply voltage|
|5|CLK|I|Clock|
|6|VSS2|S|Supply voltage ground|
|7|DAT0|I/O/PP|Data Line [Bit 0]|
|8|DAT113|I/O/PP|Data Line [Bit 1]|
|9|DAT214|I/O/PP|Data Line [Bit 2]|
> 10 S: power supply; I: input; O: output using push-pull drivers; PP: I/O using push-pull drivers
> 11 The extended DAT lines (DAT1-DAT3) are input on power up. They start to operate as DAT lines after SET_BUS_WIDTH command. The Host shall keep its own DAT1-DAT3 lines in input mode, as well, while they are not used.
> 12 At power up this line has a 50kOhm pull up enabled in the card. This resistor serves two functions Card detection and Mode Selection. For Mode Selection, the host can drive the line high or let it be pulled high to select SD mode. If the host wants to select SPI mode it should drive the line low. For Card detection, the host detects that the line is pulled high. This pull-up should be disconnected by the user, during regular data transfer, with SET_CLR_CARD_DETECT (ACMD42) command 13 DAT1 line may be used as Interrupt Output (from the Card) in SDIO mode during all the times that it is not in use for data transfer operations (refer to "SDIO Card Specification" for further details).
> 14 DAT2 line may be used as Read Wait signal in SDIO mode (refer to "SDIO Card Specification" for further details).
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– Table 14: Pad Assignment SPI Mode
|Pin|SPI Mode|SPI Mode|SPI Mode|
|---|---|---|---|
||Name|Type10|Description|
|1|CS|I12|Chip Select (neg true)|
|2|DI|I|Data In|
|3|VSS|S|Supply voltage ground|
|4|VDD|S|Supply voltage|
|5|SCLK|I|Clock|
|6|VSS2|S|Supply voltage ground|
|7|DO|O/PP|Data Out|
|8|RSV|||
|9|RSV|||
## _**7.2 Power up / Power down behavior and reset**_
## Power up
The host can start with communication 1ms after 2.7V is reached according the SDA specification. That should perform 74 clock cycles and start with the sequence CMD0, CMD8, ACMD41 until card is ready as described in the SD specification 6.10.
## Power down
When the power falls below 2.6V the controller stops the communication to the flash, but enables the flash to finish a started flash program operation (if voltage drop is not fast).
## Power drop
If the voltage drops below 2.6V and rises again, the card performs a reset. The card must be initialized like after a power on.
## _**7.3 DC characteristics**_
Measurements are not recommended operation conditions unless otherwise specified. Table 15: DC characteristics
|Symbol<br>~~_[Od~~|Parameter<br>~~[Od~~|Density<br>~~[Od~~<br>~~Od~~<br>~~a~~|Min<br>~~[Od~~<br>~~Od~~|Typ<br>~~[Od~~<br>~~Od~~<br>~~EE~~|Max<br>~~[Od~~<br>~~Od~~<br>~~EE~~|Unit<br>~~[Od~~<br>~~Od~~<br>~~EE~~|Notes<br>~~[Od~~<br>~~Od~~|
|---|---|---|---|---|---|---|---|
|IDD<br>~~PE~~|Operating Current Read<br>(UHS-I / HS)<br>~~PE~~|64GB<br>~~Od~~<br>~~PE~~<br>~~a~~|~~Od ~~<br>~~PE~~|110 / 50<br> ~~Od~~<br>~~PE~~<br>~~EE~~|140<br>~~Od~~<br>~~PE~~<br>~~EE~~|mA<br>~~Od~~<br>~~PE~~<br>~~EE~~|@ 25°C<br>~~Od~~<br>~~PE~~|
|||128/256/512GB<br>~~PE~~<br>~~a~~<br>~~a~~|~~PE~~|110 / 50<br>~~PE~~<br>~~EE~~<br>~~EE~~|140<br>~~PE~~<br>~~EE~~<br>~~EE~~|mA<br>~~PE~~<br>~~EE~~<br>~~EE~~|@ 25°C<br>~~PE~~|
|IDD<br>~~PE~~|Operating Current Write<br>(UHS-I / HS)<br>~~PE~~|64GB<br>~~a~~<br>~~PE~~<br>~~a~~|~~PE~~|115 / 55<br>~~EE~~<br>~~PE~~<br>~~EE~~|140<br>~~EE~~<br>~~PE~~<br>~~EE~~|mA<br>~~EE~~<br>~~PE~~<br>~~EE~~|@ 25°C<br>~~PE~~|
|||128/256/512GB<br>~~PE~~<br>~~a~~|~~PE~~|130 / 65<br>~~PE~~<br>~~EE~~|170<br>~~PE~~<br>~~EE~~|mA<br>~~PE~~<br>~~EE~~|@ 25°C<br>~~PE~~|
|IDD<br>~~[OO~~|Standby Current<br>~~[OO~~|~~a~~<br>~~[OO~~|~~[OO~~|0.3<br>~~EE~~<br>~~[OO~~|4<br>~~EE~~<br>~~[OO~~|mA<br>~~EE~~<br>~~[OO~~|@ 25°C<br>~~[OO~~|
|IDD<br>~~aee~~|Autoread Current (UHS-I / HS)<br>duringstandby<br>~~ee~~|~~ee~~|~~ee~~|90 / 45<br>~~ee~~|110<br>~~ee~~|mA<br>~~ee~~|@ 25°C<br>~~ee~~|
|IL3V3<br>~~aee~~<br>~~CO~~|Leakage Current (3.3V signaling)<br>~~ee~~<br>~~CO~~|~~ee~~<br>~~CO~~|-10<br>~~ee~~<br>~~CO~~|~~ee~~<br>~~CO~~|10<br>~~ee~~<br>~~CO~~|µA<br>~~ee~~<br>~~CO~~|without pull up R<br>~~ee~~<br>~~CO~~|
|IL1V8<br>~~CO~~<br>~~OCC~~|Leakage Current (1.8V signaling)<br>~~CO~~<br>~~OCC~~|~~CO~~<br>~~OCC~~|-2<br>~~CO~~<br>~~OCC~~|~~CO~~<br>~~OCC~~|2<br>~~CO~~<br>~~OCC~~|µA<br>~~CO~~<br>~~OCC~~|without pull up R<br>~~CO~~<br>~~OCC~~|
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## Table 16: SD Memory Card recommended operation conditions
|Symbol|Parameter|Parameter|Min|Typ|Max|Unit|
|---|---|---|---|---|---|---|
|VDD|Supply voltage|Normal operating status|2.7|3.3|3.6|V|
|-|Power Up Time (from 0V to VDD min)||||250|ms|
## _**7.4 Signal loading**_
According to SD specification
## _**7.5 AC characteristics**_
## Default speed mode (0-25MHz)
According to SD specification
## High speed mode (0-50MHz)
According to SD specification
## UHS modes
UHS modes were driven with a signal level of 1.8V. The cards support following UHS-I modes:
- Table 17: Supported UHS I modes
|Table 17: Supported UHS-I modes|||
|---|---|---|
|Mode|Max. Burst MB/s|Max. Clock frequency MHz|
|SDR12|12.5|25|
|SDR25|25|50|
|SDR50|50|100|
|SDR104|104|208|
|DDR50|50|50 (rising and falling edge)|
According to the SD specification
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## **8. Host access specification**
The following chapters summarize how the host accesses the card:
- Chapter 8.1 summarizes the SD and SPI buses.
- Chapter 8.2 summarizes the registers.
## _**8.1 SD and SPI Bus Modes**_
The card supports SD and the SPI Bus modes. Application can chose either one of the modes. Mode selection is transparent to the host. The card automatically detects the mode of the reset command and will expect all further communication to be in the same communication mode. The SD mode uses a 4-bit high performance data transfer, and the SPI mode provides compatible interface to MMC host systems with little redesign, but with a lower performance.
## SD Bus Mode Protocol
The SD Bus mode has a single master (host) and multiple slaves (cards) synchronous topology. Clock, power, and ground signals are common to all cards. After power up, the SD Bus mode uses DAT0 only; after initialization, the host can change the cards’ bus width from 1 bit (DAT0) to 4 bits (DAT0-DAT3). In high speed mode, only one card can be connected to the bus.
Communication over the SD bus is based on command and data bit streams which are initiated by a start bit and terminated by a stop bit.
- Command: a command is a token which starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line.
- Response: a response is a token which is sent from an addressed card, or (synchronously) from all connected cards, to the host as an answer to a previously received command. A response is transferred serially on the CMD line.
- Data: data can be transferred from the card to the host or vice versa. Data is transferred via the data lines.
## SPI Bus Mode Protocol
The Serial Peripheral Interface (SPI) Bus is a general purpose synchronous serial interface. The SPI mode consists of a secondary communication protocol. The interface is selected during the first reset command after power up (CMD0) and it cannot be changed once the card is powered on.
While the SD channel is based on command and data bit streams which are initiated by a start bit and terminated by a stop bit, the SPI channel is byte oriented. Every command or data block is built of 8-bit bytes and is byte aligned to the CS signal.
The card identification and addressing methods are replaced by a hardware Chip Select (CS) signal. There are no broadcast commands. For every command, a card (slave) is selected by asserting (active low) the CS signal. The CS signal must be continuously active for the duration of the SPI transaction (command, response and data). The only exception occurs during card programming, when the host can de-assert the CS signal without affecting the programming process.
The bidirectional CMD and DAT lines are replaced by unidirectional dataIn and dataOut signals.
Table 18: SPI Bus signals
|Table 18: SPI Bus signals||
|---|---|
|Signal|Description|
|/CS|Host to card chip select|
|CLK|Host to card clock signal|
|Data In|Host to card data signal|
|Data Out|Card to host data signal|
|Vdd, Vss|Power and ground|
## Mode Selection
The SD Memory Card wakes up in the SD mode. It will enter SPI mode if the CS signal is asserted (negative) during the reception of the reset command (CMD0) and the card is in idle_state. If the card recognizes that the SD mode is required it will not respond to the command and remain in the SD mode. If SPI mode is required the card will switch to SPI and respond with the SPI mode R1 response.
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The only way to return to the SD mode is by entering the power cycle. In SPI mode the SD Memory Card protocol state machine is not observed. All the SD Memory Card commands supported in SPI mode are always available. During the initialization sequence, if the host gets Illegal Command indication for ACMD41 sent to the card, it may assume that the card is Multimedia Card. In that case it should restart the card as Multimedia Card using CMD0 and CMD1.
## _**8.2 Card Registers**_
The SD Memory Card has the following registers.
Table 19: SD Memory Card registers
|Register name|Bit width|Description|Function|
|---|---|---|---|
|CID|128|Card Identification<br>information|This register contains the card identification information<br>used duringthe Card Identificationphase.|
|OCR|32|Operation Conditions<br>Registers|This register describes the operating voltage range and<br>contains the status bit in thepower supply.|
|CSD|128|Card specific information|This register provides information on how to access the<br>card content. Some fields of this register are writeable<br>byPROGRAM_CSD(CMD27).|
|SCR|64|SD Memory Card’s Special<br>features|This register provides information on special features.|
|RCA15|16|Relative Card Address|This register carries the card address is SD Card mode.|
|SSR|512|SD Status|information about the card proprietary features and<br>vendor specific life time information|
Table 20: CID register
|Table 20: CID register||||
|---|---|---|---|
|Register name|Bit width|Description|Function|
|MID|8|Manufacture ID|0x5d|
|OID|16|OEM/Application ID|0x5342|
|PNM|40|Product Name|e.g.“AELI0”|
|PRV|8|Product Revision|0xgg|
|PSN|32|Product Serial Number|xxxxxxxx|
|—|4|Reserved|0x0|
|MDT|12|Manufacture Date|0xyym|
|CRC|7|Check sum of CID contents|chksum|
|—|1|Not used; always=1|1|
> 15 RCA register is not available in SPI mode
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Table 21: OCR register
|OCR bit positon<br>VDD voltage<br>windows<br>Typ. value<br>OCR bit<br>position<br>VDD voltage window<br>Typ. value<br>0-3<br>Reserved<br>0<br>15<br>2.7-2.8<br>1<br>4<br>1.6-1.7<br>0<br>16<br>2.8-2.9<br>1<br>5<br>1.7-1.8<br>0<br>17<br>2.9-3.0<br>1<br>6<br>1.8-1.9<br>0<br>18<br>3.0-3.1<br>1<br>7<br>1.9-2.0<br>0<br>19<br>3.1-3.2<br>1<br>8<br>2.0-2.1<br>0<br>20<br>3.2-3.3<br>1<br>9<br>2.1-2.2<br>0<br>21<br>3.3-3.4<br>1<br>10<br>2.2-2.3<br>0<br>22<br>3.4-3.5<br>1<br>11<br>2.3-2.4<br>0<br>23<br>3.5-3.6<br>1<br>12<br>2.4-2.5<br>0<br>24<br>Switching to 1.8V<br>accepted<br>1<br>13<br>2.5-2.6<br>0<br>25-29<br>Reserved<br>14<br>2.6-2.7<br>0<br>30<br>Card Capacity Status (CCS)<br>*16<br>31<br>0=busy; 1=ready<br>*17<br>~~ee~~<br>~~es es~~<br>~~a~~<br>~~ee GO~~<br>~~a~~<br>~~ee GO~~<br>~~a~~<br>~~ee GO~~<br>~~a~~<br>~~ee GO~~<br>~~a~~<br>~~ee GO~~<br>~~a~~<br>~~ee GO~~<br>~~a~~<br>~~ee GO~~<br>~~a~~<br>~~ee GO~~<br>~~esGO~~<br>~~eeee~~<br>~~es~~<br>~~es~~<br>~~a GO~~|
|---|
|Table 22: CSD register<br>Register name<br>Bits<br>Bit width<br>Description<br>Typ. value<br>CSD_STRUCTURE<br>127:126<br>2<br>CSD structure<br>01<br>—<br>125:120<br>6<br>Reserved<br>00000<br>TAAC<br>119:112<br>8<br>Data read access time 1<br>00001110<br>NSAC<br>111:104<br>8<br>Data read access time 2 (CLK cycle)<br>00000000<br>TRAN_SPEED<br>103:96<br>8<br>Data transfer rate<br>00110010 Default speed<br>00101011 SDR 104<br>or other values<br>CCC<br>95:84<br>12<br>Card command classes<br>010110110101<br>READ_BL_LEN<br>83:80<br>4<br>Read data block length<br>1001<br>READ_BL_PARTIAL<br>79<br>1<br>Partial blocks for read allowed<br>0<br>WRITE_BLK_MISALIGN<br>78<br>1<br>Write block misalignment<br>0<br>READ_BLK_MISALIGN<br>77<br>1<br>Read block misalignment<br>0<br>DSR_IMP<br>76<br>1<br>DSR implemented<br>0<br>—<br>75:70<br>6<br>Reserved<br>000000<br>C_SIZE<br>69:48<br>22<br>Device size<br>xxx18<br>—<br>47<br>1<br>Reserved<br>0<br>ERASE_BLK_EN<br>46<br>1<br>Erase single block enable<br>1<br>SECTOR_SIZE<br>45:39<br>7<br>Erase sector size<br>1111111<br>WP_GRP_SIZE<br>38:32<br>7<br>Write protect group size<br>0000000<br>WP_GRP_ENABLE<br>31<br>1<br>Write protect group enable<br>0<br>—<br>30:29<br>2<br>Reserved<br>00<br>~~es ns A~~<br>~~es es Gn~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es es~~<br>~~a~~<br>~~ee ee~~<br>~~ee~~<br>~~ee~~<br>~~es es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es~~<br>~~es es~~<br>~~es es~~<br>~~es es~~<br>~~es~~<br>~~es~~|
- 16 This bit is valid only when the card power up status bit is set
- 17 This bit is set to LOW if the card has not finished the power up routine
- 18 Drive size and block sizes vary with card capacity
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|~~es es~~<br>~~es~~|~~es~~|||~~SWISSDIt~~|
|---|---|---|---|---|
|R2W_FACTOR<br>~~es es~~<br>~~es~~|28:26<br>~~es~~<br>~~es~~|3|Write speed factor|010<br>~~SWISSDIt~~|
|WRITE_BL_LEN<br>~~es es~~<br>~~es~~|25:22<br>~~es~~<br>~~es~~|4|Write data block length|100118<br>~~SWISSDIt~~|
|WRITE_BL_PARTIAL<br>~~es~~<br>~~es~~<br>~~oo~~|21<br>~~es~~<br>~~es~~<br>~~oo~~|1<br>~~oo~~|Partial blocks for write allowed<br>~~oo~~|0<br>~~oo~~|
|—<br>~~oo~~<br>~~oo~~|20:16<br>~~oo~~<br>~~oo~~|5<br>~~oo~~<br>~~oo~~|Reserved<br>~~oo~~<br>~~oo~~|00000<br>~~oo~~<br>~~oo~~|
|FILE_FORMAT_GRP<br>~~oo~~<br>~~oo~~|15<br>~~oo~~<br>~~oo~~|1<br>~~oo~~<br>~~oo~~|File format group<br>~~oo~~<br>~~oo~~|0 W(1)<br>~~oo~~<br>~~oo~~|
|COPY<br>~~oo~~<br>~~oo~~|14<br>~~oo~~<br>~~oo~~|1<br>~~oo~~<br>~~oo~~|Copy flag<br>~~oo~~<br>~~oo~~|0 W(1)<br>~~oo~~<br>~~oo~~|
|PERM_WRITE_PROTECT<br>~~oo~~<br>~~|~~<br>~~|~~|13<br>~~oo~~<br>|<br>~~|.~~|1<br>~~oo~~<br>|<br>~~|.|~~|Permanent write protection<br>~~oo~~<br>~~+i~~<br>~~|~~|0 W(1)<br>~~oo~~<br>~~+i~~|
|TMP_WRITE_PROTECT<br>~~|~~<br>~~|~~|12<br>~~|.~~<br>~~|.~~|1<br>~~|.|~~<br>~~|.|~~|Temporary write protection<br>~~|~~<br>~~«dS~~<br>~~|~~|0 W<br>~~«dS~~|
|FILE_FORMAT<br>~~|~~<br>~~|~~<br>~~|~~|11:10<br>~~|.~~<br>~~|.~~<br>~~|.~~|2<br>~~|. |~~<br>~~|.|~~<br>~~|.|~~|File format<br>~~|~~<br>~~|~~<br>~~«dS~~<br>~~|~~|00 W(1)<br>~~«dS~~|
|—<br>~~|~~<br>~~|~~<br>~~|~~|9:8<br>~~|.~~<br>~~|.~~<br>~~|.~~|2<br>~~|. |~~<br>~~|.|~~<br>~~|.|~~|Reserved<br>~~|~~<br>~~|~~<br>~~«dS~~<br>~~|~~|00 W<br>~~«dS~~|
|CRC<br>~~|~~<br>~~|~~<br>~~es~~|7:1<br>~~|.~~<br>~~|.~~<br>~~es~~|7<br>~~|. |~~<br>~~|.|~~|Checksum of CSD contents<br>~~|~~<br>~~|~~<br>~~«dS~~|xxxxxxx<br>~~«dS~~|
|—<br>~~|~~<br>~~es~~|0<br>~~|.~~<br>~~es~~|1<br>~~|. |~~|Always=1<br>~~|~~<br>~~«dS~~|1<br>~~«dS~~|
Memory capacity = (C_SIZE+1) * 512kByte
W value can be changed with CMD27 (PROGRAM_CSD) W(1) value can be changed ONCE with CMD27 (PROGRAM_CSD)
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Table 23: SCR register
|Table 23: SCR register||||SWISSDIt|
|---|---|---|---|---|
|Field<br>~~a~~|Bits|Bit width|Typ. value|Remark|
|SCR_STRUCTURE<br>~~a~~<br>~~a~~|63:60|4<br>~~OO~~|0000<br>~~OO~~|SCR 1.0|
|SD_SPEC<br>~~a~~<br>~~a~~|59:56|4<br>~~OO~~<br>~~OO~~|0010<br>~~OO~~<br>~~OO~~|SD 2.0 or higher|
|DATA_STAT_AFTER_ERASE<br>~~a~~<br>~~a~~|55|1<br>~~OO~~<br>~~OO~~|0<br>~~OO~~<br>~~OO~~|data are 0xFF after erase|
|SD_SECURITY<br>~~a~~<br>~~a~~|54:52|3<br>~~OO~~<br>~~OO~~|000<br>~~OO~~<br>~~OO~~|No security|
|SD_BUS_WIDTHS<br>~~a~~<br>~~a~~|51:48|4<br>~~OO~~<br>~~OO~~|0101<br>~~OO~~<br>~~OO~~|1 or 4 bit|
|SD_SPEC3<br>~~a~~<br>~~a~~|47|1<br>~~OO~~<br>~~OO~~|1<br>~~OO~~<br>~~OO~~|yes|
|EX_SECURITY<br>~~a~~<br>~~a~~|46:43|4<br>~~OO~~<br>~~OO~~|0000<br>~~OO~~<br>~~OO~~|no extended security|
|SD_SPEC4<br>~~a~~<br>~~a~~|42:42|1<br>~~OO~~<br>~~OO~~|1<br>~~OO~~<br>~~OO~~|yes|
|SD_SPECX<br>~~a~~<br>~~a~~|41:38|4<br>~~OO~~<br>~~OO~~|2<br>~~OO~~<br>~~OO~~|Version 6.xx|
|Reserved<br>~~a~~<br>~~a~~<br>~~a~~|37:36|9<br>~~OO~~<br>~~OO~~<br>~~OO~~|0<br>~~OO~~<br>~~OO~~<br>~~OO~~||
|CMD_SUPPORT<br>~~a~~<br>~~es~~<br>~~a~~|35:32<br>~~es~~|2<br>~~OO~~<br>~~es~~<br>~~OO~~|11<br>~~OO~~<br>~~es~~<br>~~OO~~|CMD23 and CMD20 supported<br>~~es~~|
|Reserved<br>~~es~~<br>~~a~~|31:0<br>~~es~~|32<br>~~es~~<br>~~OO~~|0<br>~~es~~<br>~~OO~~|~~es~~|
> 19 After initialization the card can change the RCA register
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Table 25: SSR register
**==> picture [488 x 471] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|Field|Bits|Bit width|Typ. value|Remark|
|es|
|Data bus width|511:510|2|0x2|[20]|4 bit width|
|od|
|Secured mode|509:509|1|0x0|not secured|
|od|
|Reserved for security|508:502|7|0x00|-|
|od|
|Reserved|501:496|6|0x00|-|
|od|
|SD card type|495:480|16|0x0000|Regular SD|
|od|
|Size protected area|479:448|32|0x0xxxxxxx|
|od|
|Speed class|447:440|8|0x04|Class 10|
|od|
|Move performance|439:432|8|0x00|Sequential write|
|od|
|Allocation unit size|431:428|4|0x9|4 MiB|
|od|
|Reserved|427:424|4|0x0|
|od|
|Erase unit size|423:408|16|0x8|8 AU|
|TT|_"Nn-v——|
|Erase unit timeout|407:402|6|0x04|4 seconds|
|rNnrna-nrn—————_|
|Erase unit offset|401:400|2|0x1|1 second|
|rNnrna-nrn—————_|
|UHS mode Speed Grade|399:396|4|0x1 / 0x3|UHS Grade 1 / 3|
|rNnrna-nrn—————_|
|Allocation unit size in UHS mode|395:392|4|0x9|4MB/s|
|rNnrna-nrn—————_|
|Video Speed Class|391:384|8|0x1e|Video Speed Class 30|
|rNnrna-nrn—————_|
|Reserved|383:378|6|0x0|
|rNnrna-nrn—————_|
|AU size for Video Speed Class|377:368|10|0x8|8 MiB|
|rNnrna-nrn—————_|
|Suspension Address|367:346|22|0x0|
|rNnrna-nrn—————_|
|Reserved|345:340|6|0x0|
|rNnrna-nrn—————_|
|Application Performance Class|339:336|4|1 / 2|Class A1 / A2|
|rNnrna-nrn—————_|
|Performance Enhancement|335:328|8|0x00 / 0xfc|
|Nn’|
|Reserved|327:314|14|0x0|
|es|GO|
|Discard support|313:313|1|0x0|Not supported|
|es|
|Full User Area Logical Erase|
|312:312|1|0x0|Not supported|
|es|Support|ee Gs Pe|
**----- End of picture text -----**<br>
> 20 Value change in operation
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## **9. Life Time Monitoring**
The products support life time monitoring with a vendor specific SD command CMD56 with argument 0x53420001 (read transfer). CMD56 follows the SD protocol specification and returns 512 bytes of data. All multi-byte values are in big endian order (most significant byte first).
|Field<br>~~—”™~—COC~~|Bytes<br>~~—”™~—COC~~<br>~~NCOs~~<br>~~ee~~|Byte width<br>~~—”™~—COC~~<br>~~NCOs~~|Remark<br>~~—”™~—COC~~<br>~~NS~~|
|---|---|---|---|
|Unique ID<br>~~ee~~|0:7<br>~~NCOs~~<br>~~ee~~<br>~~ee~~|8<br>~~NCOs ~~<br>~~ee~~|53 77 69 73 73 62 69 74<br>«Swissbit» in ASCII<br> ~~NS~~<br>~~ee~~|
|Reserved<br>~~GO~~|8:15<br>~~ee~~<br>~~GO~~|8<br>~~GO~~|All 0x00<br>~~GO~~|
|SD CID Register<br>~~GO~~|16:31<br>~~GO~~|16<br>~~GO~~|See chapter 8.2<br>~~GO~~|
|Firmware Revision<br>~~GO~~|32:47<br>~~GO~~|16<br>~~GO~~|ASCII Null-Terminated<br>~~GO~~|
|User Area Rated Cycles<br>~~GO~~|48:51<br>~~GO~~|4<br>~~GO~~|~~GO~~|
|User Area Max. Cycle Count<br>~~A~~|52:55<br>~~A~~|4<br>~~A~~|~~A~~|
|User Area Total Cycle Count<br>~~A~~<br>~~ene~~|56:59<br>~~A~~<br>~~ene~~|4<br>~~A~~<br>~~ene~~|~~A~~<br>~~ene~~|
|User Area Average Cycle Count<br>~~ene~~<br>~~a~~|60:63<br>~~ene~~|4<br>~~ene~~|~~ene~~|
|Reserved<br>~~a~~|64:67|4|All 0x00|
|System Area Max. Cycle Count<br>~~a~~|68:71|4||
|System Area Total Cycle Count<br>~~a~~|72:75|4||
|System Area Average Cycle Count<br>~~a~~|76:79<br>~~es es~~|4<br>~~es~~||
|Remaining Card Lifetime Percent (user<br>area)<br>~~es~~|80:80<br>~~es~~<br>~~es es~~|1<br>~~es~~<br>~~es~~|~~es~~|
|Reserved<br>~~es~~|81:85<br>~~es~~<br>~~es es~~|5<br>~~es~~<br>~~es~~|All 0x00<br>~~es~~|
|Current SD Card Speed Mode|86:86<br>~~ss~~|1<br>~~ss~~|0x00: Default Speed<br>0x01: High Speed<br>0x10: SDR12<br>0x11: SDR25<br>0x12: SDR50<br>0x14: DDR50<br>0x18: SDR104|
|Current SD Card Bus Width<br>~~es~~|87:87<br>~~es~~<br>~~ss~~|1<br>~~es~~<br>~~ss~~|0x00: 1 bit width<br>0x10: 4 bit width<br>~~es~~|
|Current Spare Blocks User Area<br>~~es~~<br>~~ene~~|88:91<br>~~es~~<br>~~ss~~<br>~~ene~~|4<br>~~es~~<br>~~ss~~<br>~~ene~~|~~es~~<br>~~ene~~|
|Current Spare Blocks System Area<br>~~ene~~<br>~~ene~~|92:95<br>~~ene~~<br>~~ene~~|4<br>~~ene~~<br>~~ene~~|~~ene~~<br>~~ene~~|
|Runtime Bad Blocks User Area<br>~~ene~~<br>~~ene~~|96:99<br>~~ene~~<br>~~ene~~|4<br>~~ene~~<br>~~ene~~|~~ene~~<br>~~ene~~|
|Runtime Bad Blocks System Area<br>~~ene~~<br>~~ene~~|100:103<br>~~ene~~<br>~~ene~~|4<br>~~ene~~<br>~~ene~~|~~ene~~<br>~~ene~~|
|Refresh Count User Area<br>~~ene~~<br>~~ene~~|104:107<br>~~ene~~<br>~~ene~~|4<br>~~ene~~<br>~~ene~~|~~ene~~<br>~~ene~~|
|Refresh Count System Area<br>~~ene~~<br>~~ene~~|108:111<br>~~ene~~<br>~~ene~~|4<br>~~ene~~<br>~~ene~~|~~ene~~<br>~~ene~~|
|Host Interface CRC count<br>~~ene~~<br>~~ene~~|112:115<br>~~ene~~<br>~~ene~~|4<br>~~ene~~<br>~~ene~~|~~ene~~<br>~~ene~~|
|Power Cycle Counter<br>~~ene~~<br>~~GO~~|116:119<br>~~ene~~<br>~~GO~~|4<br>~~ene~~<br>~~GO~~|~~ene~~<br>~~GO~~|
|Reserved<br>~~a~~|120:511|392||
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## **10. Part Number Decoder**
S F SD 512G L 1 A M 1 MT - I - 8 H - 211 - STD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Manuf. Option Memory Type. Configuration Product Type Manuf. Code: Flash Mode Density Manuf. Code: Flash Package Platform Temp. Option Product Generation Flash Vendor Code Memory Organization Number of Channels ~~ma"~~ Technology _**10.1 Manufacturer**_ Swissbit code S _**10.2 Memory Type**_
|Swissbit code||
|---|---|
|Swissbit code|S|
|||
|Flash|F|
## _**10.3 Product Type**_
## _**10.4 Density**_
## _**10.5 Platform**_
SD Memory Card SD 64 GBytes 064G 128 GBytes 128G 256 GBytes 256G 512 GBytes 512G ~~a~~ SD Memory Card L
## _**10.6 Product Generation**_
## _**10.7 Memory Organization**_
## _**10.8 Technology**_
## _**10.9 Channels**_
## _**10.10 Flash Code**_
|64 GBytesytestes<br>128 GBytesytestes<br>256 GBytesytestes<br>512 GBytesytestes<br>SD Memory Cardy CardCard<br>**_10.7 Memory Organization_**<br>~~a~~|~~a~~|064G<br>128G<br>256G<br>512G<br>L<br>~~a~~|
|---|---|---|
|x8||A|
||||
|SD MemoryCard controller|S-5x Platform|M|
||||
|1 Flash channel||1|
||||
|Micron||MT|
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_**10.11 Temperature Option**_
Extended Temp. Range: -25°C to 85°C E ~~ee~~ Industrial Temperature Range: -40 °C to 85 °C I
## _**10.12 Die Classification**_
|3D TLC MONO(single diepackage)|5|
|---|---|
|3D TLC DDP(dual diepackage)|6|
|3D TLCQDP(quad diepackage)|7|
|3D TLC ODP (oct diepackage)|8|
## _**10.13 Pin Mode**_
|Single nCE & R/nB|E|
|---|---|
|Dual nCE & R/nB|F|
|Quad nCE & R/nB|G|
|Octo nCE & R/nB|H|
## _**10.14 Drive configuration XYZ**_
X = Configuration Configuration X UHS-I 2 ~~ee~~ Y = Firmware Revision FW Revision Y ~~ee~~ High reliability series firmware 1 Z = Feature Feature Z Standard 1 ~~_~~
## _**10.15 Option**_
Swissbit / Standard STD ~~Po~~
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Page 21 of 23
## **11.Marking Specification**
## _**11.1 Top View**_
Figure 3: S-55 top view
## _**11.2 Back side marking**_
Figure 4: S-55 bottom view
Swissbit Part number Manufacturing date / Lot code Made in Germany CE / WEEE logo
Swissbit AG Industriestrasse 4 Switzerland
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## **12. Revision History**
Table 26: Document Revision History
|Date|Revision|Description|Revision Details|
|---|---|---|---|
|22-FEB-2022|1.00|Initial release version|Doc. req. no. 5250|
|25-MAR-2022|1.01|Updated MTBF value|Doc. req. no. 5322|
## Disclaimer:
No part of this document may be copied or reproduced in any form or by any means, or transferred to any third party, without the prior written consent of an authorized representative of Swissbit AG (“SWISSBIT”). The information in this document is subject to change without notice. SWISSBIT assumes no responsibility for any errors or omissions that may appear in this document and disclaims responsibility for any consequences resulting from the use of the information set forth herein. SWISSBIT makes no commitments to update or to keep current information contained in this document. The products listed in this document are not suitable for use in applications such as, but not limited to, aircraft control systems, aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. Moreover, SWISSBIT does not recommend or approve the use of any of its products in life support devices or systems or in any application where failure could result in injury or death. If a customer wishes to use SWISSBIT products in applications not intended by SWISSBIT, said customer must contact an authorized SWISSBIT representative to determine SWISSBIT willingness to support a given application. The information set forth in this document does not convey any license under the copyrights, patent rights, trademarks or other intellectual property rights claimed and owned by SWISSBIT. The information set forth in this document is considered to be “Proprietary” and “Confidential” property owned by SWISSBIT.
ALL PRODUCTS SOLD BY SWISSBIT ARE COVERED BY THE PROVISIONS APPEARING IN SWISSBIT’S TERMS AND CONDITIONS OF SALE ONLY, INCLUDING THE LIMITATIONS OF LIABILITY, WARRANTY AND INFRINGEMENT PROVISIONS. SWISSBIT MAKES NO WARRANTIES OF ANY KIND, EXPRESS, STATUTORY, IMPLIED OR OTHERWISE, REGARDING INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED PRODUCTS FROM INTELLECTUAL PROPERTY INFRINGEMENT AND EXPRESSLY DISCLAIMS ANY SUCH WARRANTIES INCLUDING WITHOUT LIMITATION ANY EXPRESS, STATUTORY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
© 2022 SWISSBIT AG All rights reserved.
Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Switzerland
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Pe TLP: Swissbit public Template: Doc-4991 no unauthorized distribution File:S-55-High-Reliability_data_sheet_SD-LxAM_STD_Rev101 www.swissbit.com/contact
Updated at June 3, 2026
Swissbit is a premier independent European manufacturer specializing in industrial-grade storage and embedded IoT solutions. Founded in 2001, the company is globally recognized for engineering highly reliable products designed to meet the rigorous demands of the industrial, automotive, telecommunications, and medical sectors. With manufacturing operations rooted in Germany, Swissbit delivers exceptional quality, long-term component availability, and custom optimization for mission-critical applications. The core of the company's offering centers on advanced semiconductor memory solutions, with a strong emphasis on high-performance flash memory cards. These robust storage options, which include industrial SD cards, microSD memory cards, and CompactFlash, are specifically engineered to provide secure, reliable data retention in extreme operating environments. Swissbit's flash memory products integrate sophisticated wear-leveling and error-correction technologies to guarantee maximum endurance and data integrity over extended product lifecycles. Beyond portable flash memory cards, Swissbit's comprehensive storage ecosystem encompasses managed NAND BGAs, USB flash drives, and a wide array of solid-state drives across multiple interfaces. By combining cutting-edge packaging expertise with hardware-based security features, Swissbit empowers design engineers to reliably store and protect sensitive data across the entire spectrum of modern connected devices.
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