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SFSD0512N1BM1TO-I-ME-221-STD
Flash Memory Card, MicroSD Card, 512 MB, Class 10, UHS-I U1
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: SWISSBIT
- Product type: Flash Memory Cards
- Blank Media Flash Memory Type:MicroSD Card, UHS-1, Class 10; Memory Capacity:512MB; Product Range:S-450u Series; SVHC:No SVHC (15-Jan-2019); Available until stocks are exhausted
- SVHC: No SVHC (15-Jan-2018)
- App Rating: -
- UHS Standard: UHS-I U1
- Product Range: S-450u Series
- Memory Capacity: 512MB
- Video Speed Class: -
- Supply Voltage Nom: 3.3V
- Standard Speed Class: Class 10
- Flash Memory Card Type: MicroSD Card
- Operating Temperature Max: 85°C
- Operating Temperature Min: -40°C
| Delivery and price | |
|---|---|
| Units per pack | 1 |
| Price | 27.25 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
Product Data Sheet
**Industrial SD / SDHC microSD Memory Card S-450u Series UHS-I Interface, SLC** Standard and Extended Temperature Grade
## **Contents**
**==> picture [487 x 505] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||
|---|---|---|
|1.|PRODUCT SUMMARY ............................................................................................................ 3|
|2.|ORDERING INFORMATION ...................................................................................................... 4|
|3.|PRODUCT DESCRIPTION ......................................................................................................... 5|
|3.1|PERFORMANCE SPECIFICATIONS ...................................................................................................... 5|
|3.2|ENVIRONMENTAL SPECIFICATIONS .................................................................................................... 5|
|3.3|PHYSICAL DIMENSIONS .............................................................................................................. 7|
|3.4|RELIABILITY ........................................................................................................................ 7|
|3.5|GEOMETRY SPECIFICATION .......................................................................................................... 7|
|4.|CARD PHYSICAL ................................................................................................................. 8|
|4.1|PHYSICAL DESCRIPTION ............................................................................................................. 8|
|5.|ELECTRICAL INTERFACE ......................................................................................................... 9|
|5.1|ELECTRICAL DESCRIPTION ............................................................................................................9|
|5.2|POWER UP /|POWER DOWN BEHAVIOR AND RESET ..................................................................................10|
|5.3|DC CHARACTERISTICS ...............................................................................................................10|
|5.4|SIGNAL LOADING ..................................................................................................................10|
|5.5|AC CHARACTERISTICS ............................................................................................................... 11|
|6.|HOST ACCESS SPECIFICATION .................................................................................................. 12|
|6.1|SD AND SPI|BUS MODES .......................................................................................................... 12|
|6.2|CARD REGISTERS ................................................................................................................... 13|
|7.|PART NUMBER DECODER ...................................................................................................... 18|
|7.1|MANUFACTURER ....................................................................................................................18|
|7.2|MEMORY TYPE .....................................................................................................................18|
|7.3|PRODUCT TYPE .....................................................................................................................18|
|7.4|DENSITY ...........................................................................................................................18|
|7.5|PLATFORM .........................................................................................................................18|
|7.6|PRODUCT GENERATION .............................................................................................................18|
|7.7|MEMORY ORGANIZATION ...........................................................................................................18|
|7.8|TECHNOLOGY ......................................................................................................................18|
|7.9|CHANNELS .........................................................................................................................18|
|7.10|FLASH CODE ...................................................................................................................... 19|
|7.11|TEMPERATURE OPTION ............................................................................................................. 19|
|7.12|DIE CLASSIFICATION ............................................................................................................... 19|
|7.13|PIN MODE ........................................................................................................................ 19|
|7.14|CONFIGURATION XYZ ............................................................................................................. 19|
|7.15|OPTION ........................................................................................................................... 19|
|8.|SWISSBIT MARKING SPECIFICATION .......................................................................................... 20|
|8.1|FRONT SIDE MARKING ............................................................................................................. 20|
|8.2|BACK SIDE MARKING ............................................................................................................. 20|
**----- End of picture text -----**<br>
9. REVISION HISTORY ............................................................................................................. 21
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## **S-450u Series (UHS-I, SLC) Industrial SD / SDHC microSD Memory Card – 512 MBytes up to 8 GBytes**
## **1. Product Summary**
- Fully compliant with SD Memory Card specification 2.0 and 3.0 and microSD Memory Card Addendum 4.00
- SD ultra high speed mode, speed class 1 (up to SDR104)
- SD high speed mode, up to speed class 10
- SD2.0 SDHC backward compliant, default speed and high speed mode
- `o` FAT16 / FAT32 preformatted
- High performance 3.0 specification
- SD burst up to 104MB/s
- SD Normal speed 0…25MHz clock rate
- SD High speed 0…50MHz clock rate
- SD UHS-I speed 0...50MHz (DDR) and 0…208MHz (SDR)
- Up to 24MByte/s sequential data rate
- Power Supply: (Low-power CMOS technology)
- 2.7…3.6V normal operating voltage
- Standard microSD Memory card form factor
- 15.0mm x 11.0mm x 0.7mm (1.0mm)
- Optimized FW algorithms especially for high read access and long data retention applications `o` Patented power-off reliability technology
- Wear Leveling technology Equal wear leveling of static and dynamic data. The wear leveling assures that dynamic data as well as static data is balanced evenly across the memory. With that the maximum write endurance of the device is guaranteed
- Write Endurance technology
- Due to intelligent wear leveling an even use of the entire flash is guaranteed, regardless how much “static” (OS) data is stored.
- Read Disturb Management
- The read commands are monitored and the content is refreshed when critical levels have occurred
- Data Care Management
- The interruptible background process maintain the user data for Read Disturb effects or Retention degradation due to high temperature effects
- Near miss ECC technology
- Minimize the risk of uncorrectable bit failure over the product life time. Each read command analyzes the ECC margin level and refresh data if necessary
- Diagnostic features with Life Time Monitoring tool support
- High reliability
- SLC Flash
- Designed for industrial market especially read intensive application like navigation, infotainment, POS/POI, Medical and general boot medium use case
- The product is optimized for long life cycle that requires good data retention because of high temperature mission profile.
- For less write and performance critical applications S-4x the more cost efficient S-4xu series MLC cards could be used
- Number of card insertions/removals up to 20,000
- Extended and Industrial Temperature range -25° up to 85°C and -40° up to 85°C, respectively
- SIP (System In Package) process for extreme dust, water and ESD proof
- `o` Selected AEC-Q100 qualification
- Controlled BOM & PCN process
- Manufactured in a TS 16949 certified factory
- Customized options like CID registers, CPRM keys, firmware incl. settings and marking by projects
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## **2. Ordering Information**
## Table 1: Standard Product List
|Capacity|Extended Temperature|Industrial Temperature|
|---|---|---|
||Part Number|Part Number|
|512 MBytes|SFSD0512NxBM1TO-E-ME-2y1-STD|SFSD0512NxBM1TO-I-ME-2y1-STD|
|1 GBytes|SFSD1024NxBM1TO-E-DF-2y1-STD|SFSD1024NxBM1TO-I-DF-2y1-STD|
|2 GBytes|SFSD2048NxBM1MT-E-ME-2y1-STD|SFSD2048NxBM1MT-I-ME-2y1-STD|
|4 GBytes|SFSD4096NxBM1MT-E-DF-2y1-STD|SFSD4096NxBM1MT-I-DF-2y1-STD|
|8 GBytes|SFSD8192NxBM1MT-E-QG-2y1-STD|SFSD8192NxBM1MT-I-QG-2y1-STD|
x = product generation and y = firmware revision
Table 2: Available Part Numbers, SLC NAND Flash 24nm/25nm
|Capacity|Extended Temperature|Industrial Temperature|
|---|---|---|
||Part Number|Part Number|
|512 MBytes|SFSD0512N1BM1TO-E-ME-221-STD|SFSD0512N1BM1TO-I-ME-221-STD|
|1 GBytes|SFSD1024N1BM1TO-E-DF-221-STD|SFSD1024N1BM1TO-I-DF-221-STD|
|2 GBytes|SFSD2048N1BM1MT-E-ME-221-STD|SFSD2048N1BM1MT-I-ME-221-STD|
|4 GBytes|SFSD4096N1BM1MT-E-DF-221-STD|SFSD4096N1BM1MT-I-DF-221-STD|
|8 GBytes|SFSD8192N1BM1MT-E-QG-221-STD|SFSD8192N1BM1MT-I-QG-221-STD|
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## **3. Product Description**
The microSD Memory Card is a small form factor non-volatile memory card which provides high capacity data storage. Its aim is to capture, retain and transport data, audio and images, facilitating the transfer of all types of digital information between a large variety of digital systems. The card operates in two basic modes:
- SD/SDHC and UHS-I card modes
- SPI mode
- The microSD Memory Card also supports SD Default and High Speed mode with up to 50MHz clock frequency
as well as UHS-I modes DDR50, SDR12/25/50 with up to 100MHz clock frequency.
The cards are compliant with
- SD Memory card Specification Part 1, Physical layer Specification V3.01
- SD Memory card Specification Part 2, File System Specification V3.00
- SD Memory card Specification Part 3, Security Specification V3.00
- MICRO SD Memory Card Addendum V4.00
Simplified specifications are available at https://www.sdcard.org/
The Card has an internal intelligent controller which manages interface protocols, data storage and retrieval as well as hardware BCH Error Correction Code (ECC), defect handling, diagnostics and clock control. The advanced wear leveling mechanism assures an equal usage of the Flash memory cells to extend the life time.
The hardware BCH-code ECC allows to detect and correct up to 40 defect bits per 1kByte.
The controller performs control read operations and checks the consistence of the data. If an error of some bits is detected, the card refreshes all data in the flash cells to prevent data retention problems.
The card has a power-loss management feature to prevent data corruption after power-down. The cards are RoHS compliant and lead-free.
## _**3.1 Performance Specifications**_
Table 3: Read/Write Performance
|System Performance|Typ1 2|Max1 3|Unit|
|---|---|---|---|
|Burst Data transfer Rate<br>(max SD clock 208MHz)||104|MB/s|
|Sustained Sequential Read|27|30|MB/s|
|Sustained Sequential Write|17-20|20-24|MB/s|
## _**3.2 Environmental Specifications**_
## 3.2.1 Recommended operating conditions
The recommended operating conditions for the S-450u microSD Memory Card are provided in Table 4 below.
Table 4: microSD Memory Card recommended operating conditions
|Parameter|Min|Typ|Max4|Unit|
|---|---|---|---|---|
|Extended Operating<br>Temperature|-25|25|85|°C|
|Industrial Operating<br>Temperature|-40|25|85|°C|
> 1 All values refer to Toshiba Flash 4Gb or Micron Flash 16Gb
> 2 Sustained Speed measured with USB-SD Memory Card reader with crystal disk test tool.
> 3 Target values
> 4 High Temperature storage without operation reduces the data retention, in operation the data will be refreshed, if data error issues were detected
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## 3.2.2 Recommended storage conditions
The recommended storage conditions are listed below in Table 5.
Table 5: microSD Memory Card recommended storage conditions
|Parameter|Min|Typ|Max5|Unit|
|---|---|---|---|---|
|Extended Storage Temperature|-25|25|100|°C|
|Industrial Operating<br>Temperature|-40|25|100|°C|
## 3.2.3 Humidity and EMC
The humidity and EMC conditions are listed below in Table 6.
Table 6: Humidity & EMC
|Table 6: Humidity & EMC||
|---|---|
|Parameter|Condition|
|Humidity (non-condensing)|85% RH @85°C 1000h|
|ESD|up to ±4 kV (contact discharge),<br>according to IEC61000-4-2 and SDA, Human Body Model 150pF/ 330Ohm,<br>on each contact pad, non-operating<br>up to ±15 kV, (air discharge),<br>according to IEC61000-4-2 and SDA, Human Body Model 150pF/ 330Ohm,<br>isolated contactpad area,non-operating|
## 3.2.4 Environmental conditions
The Environmental conditions are listed below in Table 7.
Table 7: Environmental conditions
|Parameter|Condition|
|---|---|
|UV light exposure|UV: 254nm, 15Ws/cm2 according to ISO7816-1|
|X-Ray|0.1 Gy 70keV to 140KeV (ISO7816-1) according SDA|
|Durability|20,000 mating cycles|
|Drop Test|1.5m free fall|
|Bending / Torque|10N / 0.15Nm ±2.5° max|
|Mechanical Shock|1500G, 0.5ms, half sine wave ±xyz-axis, 4 pulses each<br>non-operating,JESD22B110 Condition B|
|Vibration|50G, p-p, 20..2000Hz, sweep xyz-axis,<br>4pulses each, non-operating, MIL-STD-883 M2007.3 Condition B|
> 5 High Temperature storage without operation reduces the data retention, in operation the data will be refreshed, if data error issues were detected
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## _**3.3 Physical dimensions**_
The physical dimensions of the S-450u microSD Memory Card are listed in the following table.
Table 8: Physical dimensions
|Table 8: Physical dimensions|||
|---|---|---|
|Outer physical dimensions|Value|Unit|
|Length|15.0±0.1|mm|
|Width|11.0±0.1|mm|
|Thickness|0.7 (1.0)±0.1|mm|
|Weight (typ.)|0.4|g|
## _**3.4 Reliability**_
Table 9: Reliability
|**_3.4 Reliability_**<br>Table 9: Reliability||
|---|---|
|Parameter|Value6|
|Data Retention at beginning @ 40°C|10 years|
|Data Retention at life end (60k-100k PE cycles) @ 40°C|1 year|
## _**3.5 Geometry Specification**_
Table 10: microSD Memory Card capacity specification
|Capacity|Sector|Total Addressable Bytes|
|---|---|---|
|512MB|967,680|495,452,160|
|1GB|1,953,792|1,000,341,504|
|2GB|3,938,304|2,016,411,648|
|4GB|7,774,208|3,980,394,496|
|8GB|15,802,368|8,090,812,416|
> 6 After every power on the card reads the whole flash and performs a data refresh if necessary. So, the data retention can be much longer in most use cases.
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## **4. Card physical**
## _**4.1 Physical description**_
The microSD Memory Card contains a single chip controller and Flash memory module(s). The controller interfaces with a host system allowing data to be written to and read from the Flash memory module(s).
Figure 1: Simplified mechanical dimensions microSD Memory Card
The dimensions and tolerances are according to the SD specification.
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## **5. Electrical Interface**
## _**5.1 Electrical description**_
Figure 2: microSD Memory Card shape and Interface (Bottom view)
– Table 11: Pad Assignment SD Mode
|Pin|SD Mode|SD Mode|SD Mode|
|---|---|---|---|
||Name|Type7|Description|
|1|DAT28|I/O/PP|Data Line [Bit 2]|
|2|CD/DAT39|I/O/PP10|Card Detect/ Data Line [Bit 3]|
|3|CMD|PP|Command/Response|
|4|VDD|S|Supply voltage|
|5|CLK|I|Clock|
|6|VSS|S|Supply voltage ground|
|7|DAT0|I/O/PP|Data Line [Bit 0]|
|3|DAT111|I/O/PP|Data Line [Bit 1]|
– Table 12: Pad Assignment SPI Mode
|Pin|SPI Mode|SPI Mode|SPI Mode|
|---|---|---|---|
||Name|Type7|Description|
|1|RSV|||
|2|CS|I10|Chip Select (neg true)|
|3|DI|I|Data In|
|4|VDD|S|Supply voltage|
|5|SCLK|I|Clock|
|6|VSS|S|Supply voltage ground|
|7|DO|O/PP|Data Out|
|8|RSV|||
> 7 S: power supply; I: input; O: output using push-pull drivers; PP: I/O using push-pull drivers
> 8 DAT2 line may be used as Read Wait signal in SDIO mode (refer to "SDIO Card Specification" for further details).
> 9 The extended DAT lines (DAT1-DAT3) are input on power up. They start to operate as DAT lines after SET_BUS_WIDTH command. The Host shall keep its own DAT1-DAT3 lines in input mode, as well, while they are not used.
> 10 At power up this line has a 50kOhm pull up enabled in the card. This resistor serves two functions Card detection and Mode Selection. For Mode Selection, the host can drive the line high or let it be pulled high to select SD mode. If the host wants to select SPI mode it should drive the line low. For Card detection, the host detects that the line is pulled high. This pull-up should be disconnected by the user, during regular data transfer, with SET_CLR_CARD_DETECT (ACMD42) command.
> 11 DAT1 line may be used as Interrupt Output (from the Card) in SDIO mode during all the times that it is not in use for data transfer operations (refer to "SDIO Card Specification" for further details).
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## _**5.2 Power up / Power down behavior and reset**_
## 5.2.1 Power up
When the voltage is ramped up the controller is ready (internal reset pin released) if the voltage reaches 1.65V. The host can start with communication 1ms after 2.7V is reached according the SDA specification. That should perform 74 clock cycles and start with the sequence CMD0, CMD8, ACMD41 until card is ready as described in the SD specification 3.01.
## 5.2.2 Power down
When the power falls below 2.6V the controller stops the communication to the flash, but enables the flash to finish a started flash program operation (if voltage drop is not fast).
After next initialization the controller checks the last written data for consistency and refreshes the data. Either the new or the old data (if the write operation could not be finished) are available.
## 5.2.3 Power drop
If the voltage drops below 2.6V and rises again, the card preforms a reset. The card must be initialized like after a power on.
## 5.2.4 Operation below minimum voltage
If the card initialization is performed below the specified voltage of 2.7V, the card may be detected as 1MB card with no useful data. In this case the host should power off and on the card and start initialization above 2.7V.
## _**5.3 DC characteristics**_
Measurements are not recommended operation conditions unless otherwise specified.
|Symbol<br>~~WT~~|Parameter<br>~~WT~~|Min|Typ<br>~~LL~~|Max<br>~~LL~~|Unit|Notes|
|---|---|---|---|---|---|---|
|IDD<br>~~WT~~<br>~~TD~~<br>~~Tr~~|Operating Current Read<br>~~WT~~<br>~~TD~~<br>~~Tr~~|~~TD~~|50<br>~~TD~~<br>~~LL~~<br>~~LL~~|80<br>~~TD~~<br>~~LL~~<br>~~LL~~|mA<br>~~TD~~|@ 25°C<br>~~TD~~|
|IDD<br>~~TD~~<br>~~Tr~~|Operating Current Write<br>~~TD~~<br>~~Tr~~|~~TD~~|60<br>~~LL~~<br>~~TD~~<br>~~LL~~|80<br>~~LL~~<br>~~TD~~<br>~~LL~~|mA<br>~~TD~~|@ 25°C<br>~~TD~~|
|IDD<br>~~Tr~~|Background read and refresh12<br>~~Tr~~|~~LL~~|80<br>~~LL~~<br>~~LL~~|110<br>~~LL~~<br>~~LL~~|mA|@ 25°C|
|IDD<br>~~|~~|Pre-initialization Standby Current<br>~~|~~|~~|~~|5<br>~~|~~|15<br>~~|~~|mA<br>~~|~~|@ 25°C<br>~~|~~|
|IDD<br>~~|~~<br>~~or~~|Post-initialization StandbyCurrent13<br>~~|~~<br>~~or~~|~~|~~|2<br>~~|~~<br>~~|~~|10<br>~~|~~<br>~~|~~|mA<br>~~|~~<br>~~|~~|@ 25°C<br>~~|~~|
|IDD<br>~~or~~<br>~~or~~|Post-initialization StandbyCurrent13<br>~~or~~<br>~~or~~||5<br>~~|~~<br>~~|~~|15<br>~~|~~<br>~~|~~|mA<br>~~|~~<br>~~|~~|@ 85°C|
|ILI<br>~~or~~<br>~~a~~|Input Leakage Current<br>~~or~~<br>~~ee~~|-2<br>~~ee~~|~~|~~<br>~~ee~~|2<br>~~|~~<br>~~ee~~|µA<br>~~|~~|without pull<br>upR|
|ILO<br>~~aa~~|Output Leakage Current<br>~~ee~~|-2<br>~~ee~~|~~ee~~|2<br>~~ee~~|µA|without pull<br>upR|
## _**5.4 Signal loading**_
According to SD specification
> 12 The card can perform auto data read of the whole card to check for ECC errors and performs data refresh
> 13 Before auto read the idle current is larger than the typical idle current after auto read
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## _**5.5 AC characteristics**_
## 5.5.1 Default speed mode (0-25MHz)
According to SD specification
## 5.5.2 High speed mode (0-50MHz)
According to SD specification
## 5.5.3 UHS modes
UHS modes were driven with a signal level of 1.8V. The cards support following UHS-I modes:
- Table 15: Supported UHS I modes
|Table 15: Supported UHS-I modes|||
|---|---|---|
|Mode|Max. Burst MB/s|Max. Clock frequency MHz|
|SDR12|12.5|25|
|SDR25|25|50|
|SDR50|50|100|
|SDR10414|104|208|
|DDR50|50|50 (rising and falling edge)|
> 14 SDR104 is not available in standard microSD Memory Cards with Micron Flash (2…8GB)
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## **6. Host access specification**
The following chapters summarize how the host accesses the card:
- Chapter 6.1 summarizes the SD and SPI buses.
- Chapter 6.2 summarizes the registers.
## _**6.1 SD and SPI Bus Modes**_
The card supports SD and the SPI Bus modes. Application can chose either one of the modes. Mode selection is transparent to the host. The card automatically detects the mode of the reset command and will expect all further communication to be in the same communication mode. The SD mode uses a 4-bit high performance data transfer, and the SPI mode provides compatible interface to MMC host systems with little redesign, but with a lower performance.
## 6.1.1 SD Bus Mode Protocol
The SD Bus mode has a single master (host) and multiple slaves (cards) synchronous topology. Clock, power, and ground signals are common to all cards. After power up, the SD Bus mode uses DAT0 only; after initialization, the host can change the cards’ bus width from 1 bit (DAT0) to 4 bits (DAT0-DAT3). In high speed mode, only one card can be connected to the bus.
Communication over the SD bus is based on command and data bit streams which are initiated by a start bit and terminated by a stop bit.
- Command: a command is a token which starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line.
- Response: a response is a token which is sent from an addressed card, or (synchronously) from all connected cards, to the host as an answer to a previously received command. A response is transferred serially on the CMD line.
- Data: data can be transferred from the card to the host or vice versa. Data is transferred via the data lines.
## 6.1.2 SPI Bus Mode Protocol
The Serial Parallel Interface (SPI) Bus is a general purpose synchronous serial interface. The SPI mode consists of a secondary communication protocol. The interface is selected during the first reset command after power up (CMD0) and it cannot be changed once the card is powered on.
While the SD channel is based on command and data bit streams which are initiated by a start bit and terminated by a stop bit, the SPI channel is byte oriented. Every command or data block is built of 8-bit bytes and is byte aligned to the CS signal.
The card identification and addressing methods are replaced by a hardware Chip Select (CS) signal. There are no broadcast commands. For every command, a card (slave) is selected by asserting (active low) the CS signal.
The CS signal must be continuously active for the duration of the SPI transaction (command, response and data). The only exception occurs during card programming, when the host can de-assert the CS signal without affecting the programming process.
The bidirectional CMD and DAT lines are replaced by unidirectional dataIn and dataOut signals.
Table 16: SPI Bus signals
|Table 16: SPI Bus signals||
|---|---|
|Signal|Description|
|/CS|Host to card chip select|
|CLK|Host to card clock signal|
|Data In|Host to card data signal|
|Data Out|Card to host data signal|
|Vdd, Vss|Power and ground|
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## 6.1.3 Mode Selection
The microSD Memory Card wakes up in the SD mode. It will enter SPI mode if the CS signal is asserted (negative) during the reception of the reset command (CMD0) and the card is in idle_state. If the card recognizes that the SD mode is required it will not respond to the command and remain in the SD mode. If SPI mode is required the card will switch to SPI and respond with the SPI mode R1 response. The only way to return to the SD mode is by entering the power cycle. In SPI mode the SD Memory Card protocol state machine is not observed. All the SD Memory Card commands supported in SPI mode are always available.
During the initialization sequence, if the host gets Illegal Command indication for ACMD41 sent to the card, it may assume that the card is Multimedia Card. In that case it should restart the card as Multimedia Card using CMD0 and CMD1.
## _**6.2 Card registers**_
The microSD Memory Card has the following registers.
Table 17: microSD Memory Card registers
|Register name|Bit width|Description|Function|
|---|---|---|---|
|CID|128|Card Identification<br>information|This register contains the card identification information<br>used duringthe Card Identificationphase.|
|OCR|32|Operation Conditions<br>Registers|This register describes the operating voltage range and<br>contains the status bit in thepower supply.|
|CSD|128|Card specific information|This register provides information on how to access the<br>card content. Some fields of this register are writeable<br>byPROGRAM_CSD(CMD27).|
|SCR|64|SD Memory Card’s Special<br>features|This register provides information on special features.|
|RCA15|16|Relative Card Address|This register carries the card address is SD Card mode.|
|SSR|512|SD Status|information about the card proprietary features and<br>vendor specific life time information|
Table 18: CID register
|Table 18: CID register||||
|---|---|---|---|
|Register name|Bit width|Description|Function|
|MID|8|Manufacture ID|0x5d|
|OID|16|OEM/Application ID|0x5342|
|PNM|40|Product Name|(“NgBM1”)<br>g=generation|
|PRV|8|Product Revision|0xgg|
|PSN|32|Product Serial Number|xxxxxxxx|
|—|4|Reserved|0x0|
|MDT|12|Manufacture Date|0xyym|
|CRC|7|Check sum of CID contents|chksum|
|—|1|Not used; always=1|1|
> 15 RCA register is not available in SPI mode
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Table 19: OCR register
|~~a~~|~~ee~~|~~ee~~|~~ee~~|~~ee~~||
|---|---|---|---|---|---|
|OCR bit positon<br>~~a~~<br>~~es~~|VDD voltage<br>windows<br>~~ee~~<br>~~es~~|Typ. value<br>~~ee~~<br>~~i~~|OCR bit<br>position<br>~~ee~~<br>~~rs~~|VDD voltage window<br>~~ee~~|Typ. value|
|0-3<br>~~a~~<br>~~es~~<br>~~es~~|Reserved<br>~~ee~~<br>~~es~~<br>~~es~~|0<br>~~ee~~<br>~~i~~<br>~~i~~|15<br>~~ee~~<br>~~rs~~<br>~~rs~~|2.7-2.8<br>~~ee~~|1|
|4<br>~~es ~~<br>~~es~~|1.6-1.7<br> ~~es~~<br>~~es~~|0<br>~~i~~<br>~~i~~|16<br>~~rs~~<br>~~rs~~|2.8-2.9|1|
|5<br>~~es ~~<br>~~a~~|1.7-1.8<br> ~~es~~<br>~~Oa~~|0<br>~~i~~<br>~~Oa~~|17<br>~~rs~~|2.9-3.0|1|
|6<br>~~a~~<br>~~TT~~|1.8-1.9<br>~~Oa~~<br>~~TT~~|0<br>~~Oa~~<br>~~TT~~|18<br>~~TT~~|3.0-3.1<br>~~TT~~|1<br>~~TT~~|
|7<br>~~TT~~<br>~~TT~~|1.9-2.0<br>~~TT~~<br>~~TT~~|0<br>~~TT~~<br>~~TT~~|19<br>~~TT~~<br>~~TT~~|3.1-3.2<br>~~TT~~<br>~~TT~~|1<br>~~TT~~<br>~~TT~~|
|8<br>~~TT~~<br>~~TT~~|2.0-2.1<br>~~TT~~<br>~~TT~~|0<br>~~TT~~<br>~~TT~~|20<br>~~TT~~<br>~~TT~~|3.2-3.3<br>~~TT~~<br>~~TT~~|1<br>~~TT~~<br>~~TT~~|
|9<br>~~TT~~<br>~~TT~~|2.1-2.2<br>~~TT~~<br>~~TT~~|0<br>~~TT~~<br>~~TT~~|21<br>~~TT~~<br>~~TT~~|3.3-3.4<br>~~TT~~<br>~~TT~~|1<br>~~TT~~<br>~~TT~~|
|10<br>~~TT~~<br>~~TT~~|2.2-2.3<br>~~TT~~<br>~~TT~~|0<br>~~TT~~<br>~~TT~~|22<br>~~TT~~<br>~~TT~~|3.4-3.5<br>~~TT~~<br>~~TT~~|1<br>~~TT~~<br>~~TT~~|
|11<br>~~TT~~<br>~~OT~~<br>~~a~~|2.3-2.4<br>~~TT~~<br>~~OT~~<br>~~ee~~|0<br>~~TT~~<br>~~OT~~<br>~~ee~~|23<br>~~TT~~<br>~~OT~~<br>~~ee ee~~|3.5-3.6<br>~~TT~~<br>~~OT~~<br>~~ee~~|1<br>~~TT~~<br>~~OT~~|
|12<br>~~a~~<br>~~es~~|2.4-2.5<br>~~ee~~<br>~~ns~~|0<br>~~ee~~<br>~~Ms~~|24<br>~~ee ee~~<br>~~Ms~~|Switching to 1.8V<br>accepted<br>~~ee~~<br>~~Ms~~|1<br>~~Ms~~|
|13<br>~~a~~<br>~~es~~|2.5-2.6<br>~~ee~~<br>~~ns~~|0<br>~~ee~~<br>~~Ms~~|25-29<br>~~ee ee~~<br>~~Ms~~|Reserved<br>~~ee~~<br>~~Ms~~|~~Ms~~|
|14<br>~~es~~<br>~~Oa~~|2.6-2.7<br>~~ns~~<br>~~Oa~~|0<br>~~Ms~~<br>~~Oa~~|30<br>~~Ms~~<br>~~Oa~~|Card Capacity Status (CCS)<br>~~Ms~~<br>~~Oa~~|*16<br>~~Ms~~<br>~~Oa~~|
|~~Oa~~<br>~~a~~|~~Oa~~|~~Oa~~|31<br>~~Oa~~|0=busy; 1=ready<br>~~Oa~~|*17<br>~~Oa~~|
> 16 This bit is valid only when the card power up status bit is set
> 17 This bit is set to LOW if the card has not finished the power up routine
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Table 20: CSD register
|Table 20: CSD register|Table 20: CSD register|||||
|---|---|---|---|---|---|
|Register name<br>~~oT~~<br>~~To~~|Bits<br>~~oT~~<br>~~TI~~|Bit width<br>~~oT~~<br>~~TI~~|Description<br>~~oT~~<br>~~TI~~|Typ. value (max. 2GB)<br>~~oT~~<br>~~TI~~|Typ. value (>2GB)<br>~~oT~~<br>~~TI~~|
|CSD_STRUCTURE<br>~~oT~~<br>~~To~~|127:126<br>~~oT~~<br>~~TI~~|2<br>~~oT~~<br>~~TI~~|CSD structure<br>~~oT~~<br>~~TI~~|00<br>~~oT~~<br>~~TI~~|01<br>~~oT~~<br>~~TI~~|
|—<br>~~To ~~<br>~~oT~~<br>~~es~~|125:120<br> ~~TI~~<br>~~oT~~<br>~~ee~~|6<br>~~TI~~<br>~~oT~~|Reserved<br>~~TI~~<br>~~oT~~|00000<br>~~TI~~<br>~~oT~~|00000<br>~~TI~~<br>~~oT~~|
|TAAC<br>~~oT~~<br>~~es~~<br>~~es~~|119:112<br>~~oT~~<br>~~ee~~<br>~~ee~~|8<br>~~oT~~|Data read access time<br>1<br>~~oT~~|00001110<br>~~oT~~|00001110<br>~~oT~~|
|NSAC<br>~~es ~~<br>~~es~~<br>~~a~~|111:104<br> ~~ee~~<br>~~ee~~<br>~~ee~~|8<br>~~ee~~|Data read access time<br>2 (CLK cycle)<br>~~ee~~|00000000<br>~~ee~~|00000000<br>~~ee~~|
|TRAN_SPEED<br>~~es ~~<br>~~a~~|103:96<br> ~~ee~~<br>~~ee~~|8<br>~~ee~~|Data transfer rate<br>~~ee~~|00110010 Default speed<br>00101011 SDR 104<br>or other values<br>~~ee~~|00110010 Default speed<br>00101011 SDR 104<br>or other values<br>~~ee~~|
|CCC<br>~~a~~<br>~~oT~~<br>~~es~~|95:84<br>~~ee~~<br>~~oT~~<br>~~ee~~|12<br>~~ee ~~<br>~~oT~~|Card command classes<br> ~~ee~~<br>~~oT~~|010110110101<br>~~ee~~<br>~~oT~~|010110110101<br>~~ee~~<br>~~oT~~|
|READ_BL_LEN<br>~~oT~~<br>~~es~~<br>~~es~~|83:80<br>~~oT~~<br>~~ee~~<br>~~ee~~|4<br>~~oT~~|Read data block<br>length<br>~~oT~~|1001<br>~~oT~~|1001<br>~~oT~~|
|READ_BL_PARTIAL<br>~~es ~~<br>~~es~~<br>~~ee~~|79<br> ~~ee~~<br>~~ee~~<br>~~ee~~|1<br>~~ee~~|Partial blocks for read<br>allowed<br>~~ee~~|0|0|
|WRITE_BLK_MISALIGN<br>~~es ~~<br>~~ee~~<br>~~a~~|78<br> ~~ee~~<br>~~ee~~<br>~~a~~|1<br>~~ee~~<br>~~ee~~|Write block<br>misalignment<br>~~ee~~<br>~~ee~~|0|0|
|READ_BLK_MISALIGN<br>~~ee ~~<br>~~a~~|77<br> ~~ee ~~<br>~~a~~|1<br> ~~ee ~~<br>~~ee~~|Read block<br>misalignment<br> ~~ee~~<br>~~ee~~|0|0|
|DSR_IMP<br>~~a~~<br>~~J~~|76<br>~~a~~<br>~~J~~|1<br>~~ee ~~<br>~~J~~|DSR implemented<br> ~~ee~~<br>~~J~~|0<br>~~J~~|0<br>~~J~~|
|—<br>~~J~~<br>~~J~~|75:74<br>~~J~~<br>~~J~~|2<br>~~J~~<br>~~J~~|Reserved<br>~~J~~<br>~~J~~|00<br>~~J~~<br>~~J~~|-<br>~~J~~<br>~~J~~|
|C_SIZE<br>~~J~~<br>~~J~~<br>~~To~~|73:62<br>~~J~~<br>~~J~~<br>~~oT~~|12<br>~~J~~<br>~~J~~<br>~~oT~~|Device size<br>~~J~~<br>~~J~~<br>~~oT~~|xxx18<br>~~J~~<br>~~J~~<br>~~oT~~|-<br>~~J~~<br>~~J~~<br>~~oT~~|
|VDD_R_CURR_MIN<br>~~To~~<br>~~To~~|61:59<br>~~oT~~<br>~~oT~~|3<br>~~oT~~<br>~~oT~~|VDD min read current<br>~~oT~~<br>~~oT~~|110<br>~~oT~~<br>~~oT~~|-<br>~~oT~~<br>~~oT~~|
|VDD_R_CURR_MAX<br>~~To ~~<br>~~To~~<br>~~To~~|58:56<br> ~~oT~~<br>~~oT~~<br>~~oT~~|3<br>~~oT~~<br>~~oT~~<br>~~oT~~|VDD max read current<br>~~oT~~<br>~~oT~~<br>~~oT~~|110<br>~~oT~~<br>~~oT~~<br>~~oT~~|-<br>~~oT~~<br>~~oT~~<br>~~oT~~|
|VDD_W_CURR_MIN<br>~~To ~~<br>~~To~~<br>~~To~~|55:53<br> ~~oT~~<br>~~oT~~<br>~~oT~~|3<br>~~oT~~<br>~~oT~~<br>~~oT~~|VDD min write current<br>~~oT~~<br>~~oT~~<br>~~oT~~|110<br>~~oT~~<br>~~oT~~<br>~~oT~~|-<br>~~oT~~<br>~~oT~~<br>~~oT~~|
|VDD_W_CURR_MAX<br>~~To ~~<br>~~To~~<br>~~To~~|52:50<br> ~~oT~~<br>~~oT~~<br>~~oT~~|3<br>~~oT~~<br>~~oT~~<br>~~oT~~|VDD max write current<br>~~oT~~<br>~~oT~~<br>~~oT~~|110<br>~~oT~~<br>~~oT~~<br>~~oT~~|-<br>~~oT~~<br>~~oT~~<br>~~oT~~|
|C_SIZE_MULT<br>~~To ~~<br>~~To~~<br>~~ro~~|49:47<br> ~~oT~~<br>~~oT~~<br>~~J~~|3<br>~~oT~~<br>~~oT~~|Device size multiplier<br>~~oT~~<br>~~oT~~|11118<br>~~oT~~<br>~~oT~~|-<br>~~oT~~<br>~~oT~~|
|—<br>~~To ~~<br>~~ro~~|75:70<br> ~~oT~~<br>~~J~~|6<br>~~oT~~|Reserved<br>~~oT~~|-<br>~~oT~~|000000<br>~~oT~~|
|C_SIZE<br>~~ro~~<br>~~J~~<br>~~ro~~|69:48<br>~~J~~<br>~~J~~<br>~~J~~|22<br>~~J~~|Device size<br>~~J~~|-<br>~~J~~|xxx18<br>~~J~~|
|—<br>~~J~~<br>~~ro~~<br>~~ee~~|47<br>~~J~~<br>~~J~~<br>~~ee~~|1<br>~~J~~<br>~~ee~~|Reserved<br>~~J~~|-<br>~~J~~|0<br>~~J~~|
|ERASE_BLK_EN<br>~~ro~~<br>~~ee~~|46<br>~~J~~<br>~~ee~~|1<br>~~ee~~|Erase single block<br>enable|1|1|
|SECTOR_SIZE<br>~~ee ~~<br>~~oT~~<br>~~a~~|45:39<br> ~~ee~~<br>~~oT~~<br>~~ee~~|7<br>~~ee~~<br>~~oT~~|Erase sector size<br>~~oT~~|1111111<br>~~oT~~|1111111<br>~~oT~~|
|WP_GRP_SIZE<br>~~oT~~<br>~~a~~<br>~~ee~~|38:32<br>~~oT~~<br>~~ee~~<br>~~ee~~|7<br>~~oT~~|Write protect group<br>size<br>~~oT~~|0001111<br>~~oT~~|0000000<br>~~oT~~|
|WP_GRP_ENABLE<br>~~a~~<br>~~ee~~|31<br>~~ee~~<br>~~ee~~|1|Write protect group<br>enable|1|0|
|—<br>~~ee ~~<br>~~oT~~|30:29<br> ~~ee~~<br>~~oT~~|2<br>~~oT~~|Reserved<br>~~oT~~|00<br>~~oT~~|00<br>~~oT~~|
|R2W_FACTOR<br>~~oT~~|28:26<br>~~oT~~|3<br>~~oT~~|Write speed factor<br>~~oT~~|010<br>~~oT~~|010<br>~~oT~~|
|WRITE_BL_LEN<br>~~|~~<br>~~a~~|25:22<br>~~fe~~<br>~~ee~~|4<br>~~fe~~|Write data block<br>length|100118|100118|
|WRITE_BL_PARTIAL<br>~~|~~<br>~~a~~|21<br>~~fe~~<br>~~ee~~|1<br>~~fe~~|Partial blocks for write<br>allowed|0|0|
> 18 Drive size and block sizes vary with card capacity
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**==> picture [483 x 160] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||
|---|---|---|---|---|---|---|
|—|20:16|5|Reserved|00000|00000|
|FILE_FORMAT_GRP|15|1|File format group|0 W(1)|0 W(1)|
|ee|ee|rs|rs I|
|oT|COPY|14|1|Copy flag|0 W(1)|0 W(1)|
|Permanent write|
|PERM_WRITE_PROTECT|13|1|0 W(1)|0 W(1)|
|protection|
|es|ee|
|Temporary write|
|TMP_WRITE_PROTECT|12|1|0 W|0 W|
|protection|
|es|ee|
|oT|FILE_FORMAT|11:10|2|File format|00 W(1)|00 W(1)|
|oT|—|9:8|2|Reserved|00 W|00 W|
|Checksum of CSD|
|CRC|7:1|7|xxxxxxx W|xxxxxxx W|
|contents|
|es|ee|
|—|0|1|Always=1|1|1|
|ee|re|rs|rs|
**----- End of picture text -----**<br>
≤2GB memory capacity = BLOCKNR * BLOCK_LEN Where
BLOCKNR = (C_SIZE+1) * MULT MULT = 2[C_SIZE_MULT+2 ] (C_SIZE_MULT < 8) BLOCK_LEN = 2[READ_BL_LEN] , (READ_BL_LEN < 12)
>2GB memory capacity = (C_SIZE+1) * 512kByte
W value can be changed with CMD27 (PROGRAM_CSD) W(1) value can be changed ONCE with CMD27 (PROGRAM_CSD)
Table 21: SCR register
**==> picture [487 x 231] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||
|---|---|---|---|---|---|---|---|---|
|GG|Field|Bits|Bit width|Typ. value|Remark|
|TT|SCR_STRUCTURE|63:60|4|0000|SCR 1.01…2.00|
|TT|SD_SPEC|59:56|4|0010|SD 2.0 or 3.0|
|TT|DATA_STAT_AFTER_ERASE|55|1|1|data are 0xFF after erase|
|010|1.01 (SDSC)|
|SD_SECURITY|54:52|3|
|ee|011|2.00 (SDHC)|
|a|SD_BUS_WIDTHS|ee|51:48|ee|4|0101|ee|1 or 4 bit|
|GG|SD_SPEC3|47|1|1|yes||SD3.0|
|GG|EX_SECURITY|46:43|4|0000|no extended security|
|GG|Reserved|42:34|9|0|0|
|00|CMD23 / CMD20 not supported|
|CMD_SUPPORT|33:32|2|
|11|CMD23 / CMD20 supported|
|ee|eeee|
|Reserved|31:0|32|0|0|
|TT|
|Table 22: RCA register|
|Field|Bits|Bit width|
|RCA|16|0x0000|[19]|
**----- End of picture text -----**<br>
> 19 After initialization the card can change the RCA register
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Table 23: SSR register
|Table 23: SSR register||||SWISSbIt™|
|---|---|---|---|---|
|Field<br>~~a~~|Bits<br>~~a~~|Bit width<br>~~a~~|Typ. value<br>~~a~~|Remark<br>~~a~~|
|Data bus width<br>~~a~~<br>~~a~~|511:510<br>~~a~~<br>~~a~~|2<br>~~a~~<br>~~a~~|0x220<br>~~a~~<br>~~a~~|4 bit width<br>~~a~~<br>~~a~~|
|Secured mode<br>~~a~~<br>~~oT~~|509:509<br>~~a~~<br>~~oT~~|1<br>~~a~~<br>~~oT~~|0x0<br>~~a~~<br>~~oT~~|not secured<br>~~a~~<br>~~oT~~|
|Reserved for security<br>~~oT~~<br>~~oT~~|508:502<br>~~oT~~<br>~~oT~~|7<br>~~oT~~<br>~~oT~~|0x00<br>~~oT~~<br>~~oT~~|-<br>~~oT~~<br>~~oT~~|
|Reserved<br>~~oT~~<br>~~oT~~|501:496<br>~~oT~~<br>~~oT~~|6<br>~~oT~~<br>~~oT~~|0x00<br>~~oT~~<br>~~oT~~|-<br>~~oT~~<br>~~oT~~|
|SD card type<br>~~oT~~<br>~~oT~~|495:480<br>~~oT~~<br>~~oT~~|16<br>~~oT~~<br>~~oT~~|0x0000<br>~~oT~~<br>~~oT~~|Regular SD<br>~~oT~~<br>~~oT~~|
|Size protected area<br>~~oT~~<br>~~ee~~|479:448<br>~~oT~~<br>~~ee~~<br>~~rs~~|32<br>~~oT~~<br>~~ee~~<br>~~ns I~~|0x03000000<br>0x04000000<br>~~oT~~<br>~~ee~~<br>~~I~~|48MB<br>64MB<br>~~oT~~<br>~~ee~~|
|Speed class<br>~~rs~~|447:440<br>~~rs~~<br>~~rs~~<br>~~ee~~|8<br>~~rs~~<br>~~ns I~~<br>~~e~~|0x04<br>~~rs~~<br>~~I~~<br>~~es~~|Class 10<br>~~rs~~|
|Move performance<br>~~e~~|439:432<br>~~rs ~~<br>~~e~~<br>~~ee~~<br>~~rs~~|8<br> ~~ns I~~<br>~~e~~~~**e**~~<br>~~e~~<br>~~ns I~~|0x05<br>0x00<br>~~I~~<br>~~**e**~~<br>~~es~~<br>~~I~~|5 MB/s<br>sequential write<br>~~**e**~~|
|Allocation unit size<br>~~rs~~|431:428<br>~~ee~~<br>~~rs~~<br>~~rs~~|4<br>~~e~~<br>~~rs~~<br>~~ns I~~|0x8<br>~~es~~<br>~~rs~~<br>~~I~~|2 MiB<br>~~rs~~|
|Reserved<br>~~oT~~|427:424<br>~~rs ~~<br>~~oT~~|4<br> ~~ns I~~<br>~~oT~~|0x0<br>~~I~~<br>~~oT~~|~~oT~~|
|Erase unit size<br>~~oT~~<br>~~oT~~|423:408<br>~~oT~~<br>~~oT~~|16<br>~~oT~~<br>~~oT~~|0x0001<br>~~oT~~<br>~~oT~~|1 AU<br>~~oT~~<br>~~oT~~|
|Erase unit timeout<br>~~oT~~<br>~~oT~~|407:402<br>~~oT~~<br>~~oT~~|6<br>~~oT~~<br>~~oT~~|0x10<br>~~oT~~<br>~~oT~~|16 seconds<br>~~oT~~<br>~~oT~~|
|Erase unit offset<br>~~oT~~<br>~~a~~|401:400<br>~~oT~~<br>~~a~~|2<br>~~oT~~<br>~~a~~|0x1<br>~~oT~~<br>~~a~~|1 seconds<br>~~oT~~<br>~~a~~|
|UHS mode Speed Grade<br>~~a~~|399:396<br>~~a~~|4<br>~~a~~|0x0<br>~~a~~|(no UHS)<br>~~a~~|
|Allocation unit size in UHS mode<br>~~a~~|395:392<br>~~a~~|4<br>~~a~~|0x8<br>~~a~~|2 MiB<br>~~a~~|
|Reserved<br>~~a~~<br>~~a~~|391:312<br>~~a~~<br>~~ee~~|80<br>~~a~~<br>~~ee~~|~~a~~<br>~~ee~~|~~a~~|
|Data structure version identifier,<br>currently1<br>~~a~~<br>~~a~~<br>~~a~~<br>~~a~~|311:304<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~**ee**~~<br>|8<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~**ee**~~<br>|0x01<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~**ee**~~<br>|version 1<br>~~a~~<br>~~a~~<br>|
|Number of manufacturer marked<br>defect blocks<br>~~a~~<br>~~a~~<br>~~a~~|303:288<br>~~a~~<br>~~ee~~<br>~~**ee**~~<br>|16<br>~~a~~<br>~~ee~~<br>~~**ee**~~<br>|0x0008<br>~~a~~<br>~~ee~~<br>~~**ee**~~<br>|8 initial BB<br>~~a~~<br>|
|Number of initial spare blocks<br>(worst chip)<br>~~a~~<br>~~a~~|287:272<br>~~ee~~<br>~~**ee**~~<br><br>~~ee~~|16<br>~~ee~~<br>~~**ee**~~<br><br>~~ee~~|0x0074<br>~~ee~~<br>~~**ee**~~<br><br>~~ee~~|116 spare blocks<br>|
|Number of initial spare blocks<br>(sum over all chips)<br>~~aee~~|271:256<br>~~**ee**~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|16<br>~~**ee**~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|0x0074<br>~~**ee**~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|116 spare blocks<br>~~ee~~|
|Percentage of remaining spare<br>blocks(worst chip)<br>~~ee~~|255:248<br>~~ee~~<br>~~ee~~<br>~~ee~~|8<br>~~ee~~<br>~~ee~~<br>~~ee~~|0x6420<br>~~ee~~<br>~~ee~~<br>~~ee~~|100%<br>~~ee~~|
|Percentage of remaining spare<br>blocks(all chips)<br>~~ee~~|247:240<br>~~ee~~<br>~~ee~~|8<br>~~ee~~<br>~~ee~~<br>~~ee~~|0x6420<br>~~ee~~<br>~~ee~~<br>~~ee~~|100%<br>~~ee~~|
|Number of uncorrectable ECC<br>errors (not including ECC errors<br>duringstartup)<br>~~ee~~|239:224<br>~~ee~~|16<br>~~ee~~<br>~~ee~~<br>~~ee~~|0x000020<br>~~ee~~<br>~~ee~~<br>~~ee~~|0 uncorrectable errors<br>~~ee~~|
|Number of correctable ECC errors<br>(not including ECC errors during<br>startup)<br>~~ee~~|223:192<br>~~ee~~|32<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0x0045074b20<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ph~~|4523851 correctable ECC errors<br>~~ee~~<br>~~ph~~|
|Lowest wear level class<br>~~ee~~<br>~~sp~~|191:176<br>~~ee~~<br>~~sp~~|16<br>~~ee~~<br>~~ee ~~<br>~~sp~~|0x000020<br>~~ee~~<br> ~~ee~~<br>~~sp~~<br>~~ph~~|0<br>~~ee~~<br>~~sp~~<br>~~ph~~|
|Highest wear level class<br>~~sp~~|175:160<br>~~sp~~|16<br>~~sp~~|0x000020<br>~~sp~~<br>~~ph~~|0<br>~~sp~~<br>~~ph~~|
|Wear level threshold<br>~~sp~~<br>~~a~~|159:144<br>~~sp~~<br>~~a~~|16<br>~~sp~~<br>~~a~~|0x03ff<br>~~sp~~<br>~~ph~~<br>~~a~~|1024 block erases per WL class<br>~~sp~~<br>~~ph~~<br>~~a~~|
|Total number of block erases<br>~~a~~<br>~~a~~|143:96<br>~~a~~<br>~~a~~<br>~~ee~~|48<br>~~a~~<br>~~a~~<br>~~ee~~|0x00…1ff020<br>~~a~~<br>~~a~~<br>~~ee~~|8176 block erase commands<br>~~a~~<br>~~a~~|
|Number of flash blocks, in units<br>of 256 blocks<br>~~a~~<br>~~ee~~|95:80<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|16<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|0x0008<br>~~a~~<br>~~ee~~<br>~~ee~~|2048 flash blocks<br>~~a~~<br>~~ee~~|
|Maximum flash block erase count<br>target,in wear level class units<br>~~ee~~|79:64<br>~~ee~~<br>~~ee~~<br>~~ee~~|16<br>~~ee~~<br>~~ee~~<br>~~ee~~|0x003a<br>~~ee~~<br>~~ee~~|Flash endurance 58 WL classes<br>(59392 erases)<br>~~ee~~|
|Power on count<br>~~oT~~|63:32<br>~~ee~~<br>~~oT~~|32<br>~~ee~~<br>~~oT~~|0x0000000320<br>~~oT~~|3x power on<br>~~oT~~|
|Firmware version<br>~~a~~|31:0|32|0xYYMMDDXX|Firmware version|
Bit 311:0 are vendor specific, example values in the table
> 20 Value change in operation
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## **7. Part Number Decoder**
S F SD 032G L 3 B M 1 TO - I - L F - 2B1 - STD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Manuf. Option Memory Type. Configuration Product Type Manuf. Code: Flash Mode Density Manuf. Code: Flash Package Platform Temp. Option Product Generation Flash Vendor Code Memory Organization Channels ~~mma"~~ Technology _**7.1 Manufacturer**_ Swissbit code S _**7.2 Memory Type**_
|Swissbit code|S|
|---|---|
|||
|Flash|F|
## _**7.3 Product Type**_
|**_7.3 Product Type_**|**_7.3 Product Type_**||||
|---|---|---|---|---|
||||SATA Interface|SD|
|**_7.4 Density_**|**_7.4 Density_**||||
|||512 MByte<br>512<br>1 GByte<br>1024<br>2 GByte<br>2048<br>4 GByte<br>4096<br>8 GByte<br>8192<br>16 GByte<br>016G<br>~~=:~~|||
|**_7.5 Platform_**|**_7.5 Platform_**||||
||||microSD Memory Card|N|
|**_7.6 Product Generation_**|**_7.6 Product Generation_**||||
|**_7.7 Memory Organization_**|**_7.7 Memory Organization_**|Generation<br>1<br>2<br>3<br>**_7.7 Memory Organization_**<br>x8<br>B<br>~~=~~|||
|**_7.8 Technology_**|**_7.8 Technology_**||||
||||SD Memory Card controller (S-4xx platform)|M|
|**_7.9 Channels_**|**_7.9 Channels_**||||
||||1 Flash channel|1|
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## _**7.10 Flash Code**_
## _**7.11 Temperature Option**_
Toshiba TO Micron MT ~~———~~ ae Extended Temperature Range: -25 °C to 85°C E Industrial Temperature Range: -40 °C to 85 °C I ~~en~~
## _**7.12 Die Classification**_
## _**7.13 Pin Mode**_
## _**7.14 Configuration XYZ**_
S-4x S-4xx MLC SLC MONO (single die package) G M DDP (dual die package) L D QDP (quad die package) H Q ODP (octal die package) M N ~~—a~~ Single nCE and Single R/nB E Dual nCE and Dual R/nB F Quad nCE and Quad R/nB G ~~——~~ X = Configuration Configuration X Default, non UHS 1 UHS-I 2 ~~———~~ Y = Firmware Revision FW Revision Y Version 1 1 Version 2 2 Version 3 3 ~~—s~~ Z = Optional Optional Z Optional 1 ~~———~~
## _**7.15 Option**_
Swissbit/Standard STD
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## **8. Swissbit marking specification**
## _**8.1 Front side marking**_
Swissbit Density
Micro SDHC Memory Card logo
## _**8.2 Back side marking**_
SFSD8192N1BM1 MT-I-QG-221-STD
Part Number
Calendar week and year Lot code
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## **9. Revision History**
Table 24: Document Revision History
|Date|Revision|Description|Revision Details|
|---|---|---|---|
|March 10, 2015|0.90|Initial preliminary release||
|May 27, 2015|1.00|Update to first final revision|Doc. req. no. 0555|
|May 24, 2016|1.10|Standby currents, PE cycles corrected, updated chapter 4, 5,<br>6, SDR104 mode disabled in cards with MT flash and removed<br>CE declaration|Doc. req. no. 1157|
|November 11, 2016|1.11|Corrected typo in chapter Environmental Conditions and<br>updated specification layout|Doc. req. no. 1365|
|June 07, 2017|1.12|Formal layout changes|Doc. req. no. 1710|
|February 14, 2019|1.13|Formal changes and added preformat information|Doc. req. no. 2757|
## Disclaimer:
No part of this document may be copied or reproduced in any form or by any means, or transferred to any third party, without the prior written consent of an authorized representative of Swissbit AG (“SWISSBIT”). The information in this document is subject to change without notice. SWISSBIT assumes no responsibility for any errors or omissions that may appear in this document, and disclaims responsibility for any consequences resulting from the use of the information set forth herein. SWISSBIT makes no commitments to update or to keep current information contained in this document. The products listed in this document are not suitable for use in applications such as, but not limited to, aircraft control systems, aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. Moreover, SWISSBIT does not recommend or approve the use of any of its products in life support devices or systems or in any application where failure could result in injury or death. If a customer wishes to use SWISSBIT products in applications not intended by SWISSBIT, said customer must contact an authorized SWISSBIT representative to determine SWISSBIT willingness to support a given application. The information set forth in this document does not convey any license under the copyrights, patent rights, trademarks or other intellectual property rights claimed and owned by SWISSBIT. The information set forth in this document is considered to be “Proprietary” and “Confidential” property owned by SWISSBIT.
ALL PRODUCTS SOLD BY SWISSBIT ARE COVERED BY THE PROVISIONS APPEARING IN SWISSBIT’S TERMS AND CONDITIONS OF SALE ONLY, INCLUDING THE LIMITATIONS OF LIABILITY, WARRANTY AND INFRINGEMENT PROVISIONS. SWISSBIT MAKES NO WARRANTIES OF ANY KIND, EXPRESS, STATUTORY, IMPLIED OR OTHERWISE, REGARDING INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED PRODUCTS FROM INTELLECTUAL PROPERTY INFRINGEMENT, AND EXPRESSLY DISCLAIMS ANY SUCH WARRANTIES INCLUDING WITHOUT LIMITATION ANY EXPRESS, STATUTORY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
©2019 SWISSBIT AG All rights reserved.
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Updated at June 3, 2026
Swissbit is a premier independent European manufacturer specializing in industrial-grade storage and embedded IoT solutions. Founded in 2001, the company is globally recognized for engineering highly reliable products designed to meet the rigorous demands of the industrial, automotive, telecommunications, and medical sectors. With manufacturing operations rooted in Germany, Swissbit delivers exceptional quality, long-term component availability, and custom optimization for mission-critical applications. The core of the company's offering centers on advanced semiconductor memory solutions, with a strong emphasis on high-performance flash memory cards. These robust storage options, which include industrial SD cards, microSD memory cards, and CompactFlash, are specifically engineered to provide secure, reliable data retention in extreme operating environments. Swissbit's flash memory products integrate sophisticated wear-leveling and error-correction technologies to guarantee maximum endurance and data integrity over extended product lifecycles. Beyond portable flash memory cards, Swissbit's comprehensive storage ecosystem encompasses managed NAND BGAs, USB flash drives, and a wide array of solid-state drives across multiple interfaces. By combining cutting-edge packaging expertise with hardware-based security features, Swissbit empowers design engineers to reliably store and protect sensitive data across the entire spectrum of modern connected devices.
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