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SFCF32GBH2BU4TO-I-QT-527-STD
Flash Memory Card, Compact Flash Card, Type I, 32 GB, C-440 Series
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: SWISSBIT
- Product type: Flash Memory Cards
- Product Range: C-440 Series
- Memory Capacity: 32GB
- Blank Media Flash Memory Type: Compact Flash Card, Type I
| Delivery and price | |
|---|---|
| Units per pack | 5 |
| Price | 356.7 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
Swissbit AG Swissbit reserves the right to change products or specifications without notice. Revision: 1.23 Industriestrasse 4 CompactFlashCard CH-9552 Bronschhofen www.swissbit.com C-440_data_sheet_CF-HxBU_Rev123.doc Switzerland industrial@swissbit.com Page 1 of 106
## **C-440 Series – Industrial UDMA CompactFlash™ Card, 2GByte up to 64GByte, 3.3/5V Supply**
## **1 Main Features**
- Highly-integrated memory controller
- CompactFlash[TM] specification 4.1, compatible with specification 5.0
- PCMCIA specification 2.1 (chapter CF-ATA Registers) & PC Card ATA Interface Specification 8, 7, 6, and 5
- True IDE mode compatible, up to UDMA6 / MDMA4 / PIO6 supported
- Fix drive (IDE mode) & removable drive (PC card mode) as default in the same card
- Hot swappable in PC card modes
- Signal termination resistors to improve signal quality
- LBA48 address support (LBA28 limitation on request)
- Fix drive (IDE mode) & removable drive (PC card mode) as default configuration
- Small form factor
- CFC Type I: 36.4mm x 42.8mm x 3.3mm
- Low-power CMOS technology
- 3.3V or 5.0V power supply, card drives bus with 3.3V, inputs 5V compatible
- Power saving mode (with automatic wake-up)
- S.M.A.R.T. support and extended vendor information
- Wear Leveling: equal wear leveling of static and dynamic data The wear leveling assures that dynamic data as well as static data is balanced evenly across the memory. With that the maximum write endurance of the device is guaranteed.
- Data Retention: 10 year (JESD47)
- Patented power-off reliability
- No data loss of older sectors
- Max. 32 sectors data loss (old data kept)
- High reliability
- MTBF >3,000,000 hours
- Data reliability: < 1 non-recoverable error per 10[14] bits read
- Number of connector insertions/removals: >10,000
- 24bit per double sector ECC capability
- Near Miss ECC handling at read (refresh and correct data, if multiple correctable errors detected)
- `o` Read Disturb Management (RDM, refresh and correct data after a certain number of read commands per block)
- High performance
- Up to 133MB/s burst transfer rate in UDMA6
- Sustained Write performance: up to 40MB/s (UDMA6 untrimmed)
- Sustained Read Performance: up to 65MB/s (UDMA6)
- Trim command supported to increase random write performance
- Up to 300 IOPS with Trim Support (4k random write) and up to 32 IOPS untrimmed
- Available densities
- up to 64GBytes (SLC NAND Flash)
- Operating System support
- Standard Software Drivers operation CompactFlash[TM]
- 2 Temperature ranges
- Commercial Temperature range 0 … +70°C
- `o` Industrial Temperature range -40 … +85°C
- Life Cycle Management
- Controlled BOM
- RoHS compatible
Swissbit reserves the right to change products or specifications without notice.
Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Switzerland
Revision: 1.23
www.swissbit.com
C-440_data_sheet_CF-HxBU_Rev123.doc
Page 2 of 106
industrial@swissbit.com
## **2 Table of Contents**
|1<br>MAIN FEATURES**..................................................................................................................................................................... 2**|
|---|
|2<br>TABLE OF CONTENTS**............................................................................................................................................................... 3**|
|3<br>ORDER INFORMATION**............................................................................................................................................................. 6**|
|3.1 STANDARD PART NUMBERS............................................................................................................................................................... 6|
|3.2 SUPPORTEDFEATURES.................................................................................................................................................................... 6|
|3.3 OFFEREDOEMOPTIONS ON REQUEST................................................................................................................................................ 6|
|3.4 OFFEREDLBA28OPTIONS ON REQUEST............................................................................................................................................. 7|
|4<br>PRODUCT SPECIFICATION**........................................................................................................................................................ 8**|
|4.1 SYSTEMPERFORMANCE................................................................................................................................................................... 8|
|4.2 ENVIRONMENTALSPECIFICATIONS...................................................................................................................................................... 9|
|4.3 PHYSICALDIMENSIONS................................................................................................................................................................. 10|
|4.4 RELIABILITY............................................................................................................................................................................... 10|
|4.5 DRIVEGEOMETRY/ CHS PARAMETER............................................................................................................................................. 10|
|4.6 PHYSICAL DESCRIPTION................................................................................................................................................................ 11|
|5<br>ELECTRICAL INTERFACE**......................................................................................................................................................... 12**|
|5.1 ELECTRICAL DESCRIPTION............................................................................................................................................................... 12|
|5.2 ELECTRICALSPECIFICATION............................................................................................................................................................. 17|
|5.3 ADDITIONAL REQUIREMENTS FORCOMPACTFLASHTM ADVANCEDTIMING MODE.......................................................................................... 18|
|6<br>COMMAND INTERFACE**.......................................................................................................................................................... 19**|
|6.1 ATTRIBUTEMEMORYREAD ANDWRITE............................................................................................................................................ 19|
|6.2 COMMONMEMORYREAD ANDWRITE............................................................................................................................................. 20|
|6.3 I/O READ ANDWRITE.................................................................................................................................................................. 22|
|6.4 TRUEIDE MODE........................................................................................................................................................................ 23|
|6.5 ULTRADMA MODE.................................................................................................................................................................... 25|
|7<br>CARD CONFIGURATION**......................................................................................................................................................... 44**|
|7.1 CONFIGURATIONOPTIONREGISTER(200H INATTRIBUTEMEMORY)....................................................................................................... 44|
|7.2 COMPACTFLASHTM MEMORYCARDCONFIGURATIONS............................................................................................................................ 45|
|7.3 PINREPLACEMENTREGISTER(204H INATTRIBUTEMEMORY).............................................................................................................. 45|
|7.4 ATTRIBUTEMEMORYFUNCTION...................................................................................................................................................... 46|
|7.5 I/O TRANSFERFUNCTION.............................................................................................................................................................. 47|
|7.6 COMMONMEMORYTRANSFERFUNCTION.......................................................................................................................................... 47|
|7.7 TRUEIDE MODEI/O FUNCTION...................................................................................................................................................... 47|
|7.8 HOSTCONFIGURATIONREQUIREMENTS FORMASTER/SLAVE ORNEWTIMINGMODES................................................................................ 48|
|8<br>SOFTWARE INTERFACE**.......................................................................................................................................................... 49**|
|8.1 CF-ATA DRIVEREGISTERSETDEFINITION ANDPROTOCOL................................................................................................................... 49|
|8.2 MEMORYMAPPEDADDRESSING.................................................................................................................................................... 49|
|8.3 CONTIGUOUSI/O MAPPEDADDRESSING.......................................................................................................................................... 50|
|8.4 I/O PRIMARY ANDSECONDARYADDRESSCONFIGURATIONS................................................................................................................. 51|
|8.5 TRUEIDE MODEADDRESSING...................................................................................................................................................... 51|
|9<br>CF-ATA REGISTERS**............................................................................................................................................................... 52**|
|9.1 DATAREGISTER........................................................................................................................................................................... 52|
|9.2 ERRORREGISTER........................................................................................................................................................................ 52|
|9.3 FEATUREREGISTER...................................................................................................................................................................... 53|
|9.4 SECTORCOUNTREGISTER.............................................................................................................................................................. 53|
|9.5 SECTORNUMBER(LBA 7:0) REGISTER........................................................................................................................................... 53|
|9.6 CYLINDERLOW(LBA 15:8) REGISTER............................................................................................................................................ 53|
|9.7 CYLINDERHIGH(LBA 23:16) REGISTER......................................................................................................................................... 53|
|9.8 DRIVE/HEAD(LBA 27:24) REGISTER............................................................................................................................................. 54|
|9.9 STATUS& ALTERNATESTATUSREGISTERS........................................................................................................................................ 55|
|9.10 DEVICECONTROLREGISTER......................................................................................................................................................... 55|
|9.11 CARD(DRIVE) ADDRESSREGISTER................................................................................................................................................. 56|
|Swissbit AG<br>Swissbit reserves the right to change products or specifications without notice.<br>Revision: 1.23|
|Industriestrasse 4|
|CH-9552 Bronschhofen<br>www.swissbit.com<br>C-440_data_sheet_CF-HxBU_Rev123.doc|
|Switzerland<br>industrial@swissbit.com<br>Page3 of 106|
|10<br>CF-ATA COMMAND DESCRIPTION**......................................................................................................................................... 57**|
|---|
|10.1 CHECKPOWERMODE(98H ORE5H)............................................................................................................................................ 59|
|10.2 DATASETMANAGEMENT(06H) TRIM.......................................................................................................................................... 59|
|10.3 ERASESECTOR(S) (C0H)............................................................................................................................................................. 59|
|10.4 EXECUTEDRIVEDIAGNOSTIC(90H).............................................................................................................................................. 59|
|10.5 FLUSHCACHE(E7H).................................................................................................................................................................. 60|
|10.6 FLUSHCACHEEXT(EAH) 48BITLBA............................................................................................................................................ 60|
|10.7 FORMAT TRACK(50H)................................................................................................................................................................ 61|
|10.8 IDENTIFYDEVICE(ECH).............................................................................................................................................................. 61|
|10.9 IDLE(97H ORE3H)................................................................................................................................................................... 71|
|10.10 IDLEIMMEDIATE(95H ORE1H).................................................................................................................................................. 71|
|10.11 INITIALIZEDRIVEPARAMETERS(91H)........................................................................................................................................... 71|
|10.12 NOP (00H)........................................................................................................................................................................... 72|
|10.13 READBUFFER(E4H)................................................................................................................................................................ 72|
|10.14 READDMA (C8H)................................................................................................................................................................... 72|
|10.15 READDMA EXT(25H) 48BITLBA............................................................................................................................................. 73|
|10.16 READMULTIPLE(C4H)............................................................................................................................................................. 73|
|10.17 READMULTIPLEEXT(29H) 48BITLBA....................................................................................................................................... 74|
|10.18 READSECTOR(S) (20H OR21H).................................................................................................................................................. 75|
|10.19 READSECTORSEXT(24H) 48BITLBA......................................................................................................................................... 75|
|10.20 READVERIFYSECTOR(S) (40H).................................................................................................................................................. 75|
|10.21 READVERIFYEXT(42H) 48BITLBA........................................................................................................................................... 76|
|10.22 RECALIBRATE(1XH).................................................................................................................................................................. 76|
|10.23 REQUESTSENSE(03H)............................................................................................................................................................. 76|
|10.24 SEEK(7XH)............................................................................................................................................................................ 77|
|10.25 SECURITYDISABLEPASSWORD(F6H).......................................................................................................................................... 77|
|10.26 SECURITYERASEPREPARE(F3H)................................................................................................................................................ 78|
|10.27 SECURITYERASEUNIT(F4H)...................................................................................................................................................... 78|
|10.28 SECURITYFREEZELOCK(F5H).................................................................................................................................................... 78|
|10.29 SECURITYSETPASSWORD(F1H)................................................................................................................................................. 78|
|10.30 SECURITYUNLOCK(F2H).......................................................................................................................................................... 79|
|10.31 SETFEATURES(EFH)................................................................................................................................................................ 80|
|10.32 SETMULTIPLEMODE(C6H)...................................................................................................................................................... 81|
|10.33 SETSLEEPMODE(99H ORE6)................................................................................................................................................. 82|
|10.34 S.M.A.R.T. (B0H)................................................................................................................................................................ 82|
|10.35 STANDBY(96H ORE2)............................................................................................................................................................ 83|
|10.36 STANDBYIMMEDIATE(94H ORE0H).......................................................................................................................................... 83|
|10.37 TRANSLATESECTOR(87H).......................................................................................................................................................... 83|
|10.38 WRITEBUFFER(E8H)............................................................................................................................................................. 84|
|10.39 WRITEDMA (CAH)................................................................................................................................................................. 84|
|10.40 WRITEDMA EXT(35H) 48BITLBA.......................................................................................................................................... 84|
|10.41 WRITEMULTIPLECOMMAND(C5H)............................................................................................................................................. 85|
|10.42 WRITEMULTIPLEEXT(39H) 48BITLBA..................................................................................................................................... 85|
|10.43 WRITEMULTIPLE WITHOUTERASE(CDH)..................................................................................................................................... 86|
|10.44 WRITESECTOR(S) (30H OR31H)................................................................................................................................................ 86|
|10.45 WRITESECTOR(S) EXT(34H) 48BITLBA.................................................................................................................................... 87|
|10.46 WRITESECTOR(S)WITHOUTERASE(38H).................................................................................................................................... 87|
|10.47 WRITEVERIFY(3CH)................................................................................................................................................................ 87|
|11<br>S.M.A.R.T FUNCTIONALITY**................................................................................................................................................... 88**|
|11.1 S.M.A.R.T. ENABLE/ DISABLE OPERATIONS................................................................................................................................... 88|
|11.2 S.M.A.R.T. ENABLE/ DISABLEATTRIBUTEAUTOSAVE...................................................................................................................... 88|
|11.3 S.M.A.R.T. READ DATA............................................................................................................................................................. 88|
|11.4 S.M.A.R.T. READATTRIBUTETHRESHOLDS.................................................................................................................................... 93|
|11.5 S.M.A.R.T. RETURNSTATUS....................................................................................................................................................... 94|
|12<br>CIS INFORMATION (TYPICAL)**................................................................................................................................................. 95**|
|13<br>PACKAGE MECHANICAL**......................................................................................................................................................... 99**|
|14<br>DECLARATION OF CONFORMITY**........................................................................................................................................... 100**|
|15<br>ROHS AND WEEE UPDATE FROM SWISSBIT**........................................................................................................................ 101**|
|Swissbit AG<br>Swissbit reserves the right to change products or specifications without notice.<br>Revision: 1.23|
|Industriestrasse 4|
|CH-9552 Bronschhofen<br>www.swissbit.com<br>C-440_data_sheet_CF-HxBU_Rev123.doc|
|Switzerland<br>industrial@swissbit.com<br>Page4 of 106|
Revision: 1.23
C-440_data_sheet_CF-HxBU_Rev123.doc Page 4 of 106
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|16<br>PART NUMBER DECODER**.................................................................................................................................................... 103**|
|---|
|16.1 MANUFACTURER....................................................................................................................................................................... 103|
|16.2 MEMORYTYPE........................................................................................................................................................................ 103|
|16.3 PRODUCTTYPE........................................................................................................................................................................ 103|
|16.4 DENSITY................................................................................................................................................................................ 103|
|16.5 PLATFORM............................................................................................................................................................................. 103|
|16.6 PRODUCTGENERATION............................................................................................................................................................. 103|
|16.7 MEMORYORGANIZATION........................................................................................................................................................... 103|
|16.8 CONTROLLER TYPE.................................................................................................................................................................... 103|
|16.9 NUMBER OFFLASHCHIP.......................................................................................................................................................... 103|
|16.10 FLASHCODE......................................................................................................................................................................... 103|
|16.11 TEMP. OPTION....................................................................................................................................................................... 104|
|16.12 DIE CLASSIFICATION................................................................................................................................................................ 104|
|16.13 PIN MODE........................................................................................................................................................................... 104|
|16.14 COMPACTFLASHXYZ.............................................................................................................................................................. 104|
|16.15 OPTION................................................................................................................................................................................ 104|
|17<br>SWISSBIT CF LABEL SPECIFICATION**.................................................................................................................................... 105**|
|17.1 FRONT SIDE LABEL..................................................................................................................................................................... 105|
|17.2 BACK SIDE LABEL...................................................................................................................................................................... 105|
|18<br>REVISION HISTORY**.............................................................................................................................................................. 106**|
Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Switzerland
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.23
www.swissbit.com industrial@swissbit.com
C-440_data_sheet_CF-HxBU_Rev123.doc Page 5 of 106
## **3 Order Information**
## **3.1 Standard part numbers**
- - IDE FIX & PC card Removable / PIO, DMA & UDMA support
|Density|Part Number|
|---|---|
|2GB|SFCF2048HxBU2TO-t-MS-5y7-STD|
|4GB|SFCF4096HxBU4TO-t-MS-5y7-STD|
|8GB|SFCF8192HxBU2TO-t-QT-5y7-STD|
|16GB|SFCF16GBHxBU4TO-t-QT-5y7-STD|
|32GB|SFCF32GBHxBU4TO-t-QT-5y7-STD|
|64GB|SFCF64GBHxBU4TO-t-NU-5y7-STD|
Table 1: Product list for standard product variations
- X = depends on product generation;
- y = depends on latest FW revision
t = C: commercial temperature; I: industrial temperature
## **3.2 Supported Features**
- MDMA/UDMA also in PC card mode
- SMART Feature Set with additional life time information
- TRIM command
- 48bit Address Feature Set
- Security Mode Feature Set
- Power Management Feature Set
- Write Cache
- Write_Buffer Command
- Read_Buffer Command
- NOP_Command
- Flush_Cache_EXT
## **3.3 Offered OEM options on request**
- Write Protect switch
- Disabling MDMA and/or UDMA modes
- Customer specified card size and card geometry (C/H/S – cylinder/head/sector)
- Customer specified CIS and drive ATA-ID strings
- Preload service (also images with any file system)
- Customized label
- ROM mode (write protected with preloaded software)
- Special Firmware solutions for additional customer requirements
- …
Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Switzerland
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.23
www.swissbit.com industrial@swissbit.com
C-440_data_sheet_CF-HxBU_Rev123.doc Page 6 of 106
## **3.4 Offered LBA28 options on request**
To be compatible to dedicated host systems, cards with the part number suffix “-L28” only support LBA28 commands but don’t support LBA48 commands (extended) including the TRIM command are available on request.
## 3.4.1 Commands not supported in LBA28 cards
The following commands are not supported in “-L28” cards:
- Table 2: CF ATA Command Set (1)
|Class|Command|Code|FR(1)|SC(2)|SN(3)|CY(5:4)|DH(6)|LBA(5:3)|
|---|---|---|---|---|---|---|---|---|
|2|Data SetManagement|06h||YY|||D|YY|
|1|FlushcacheExt|EAh|||||D||
|1|ReadDMA Ext|25h||YY|YY|YY|D|YY|
|1|ReadMultipleExt|29h||YY|YY|YY|D|YY|
|1|Read Sector(s)Ext|24h||YY|YY|YY|D|YY|
|1|ReadVerify Sector(s)Ext|42h||YY|YY|YY|D|YY|
|2|WriteDMA Ext|35h||YY|YY|YY|D|YY|
|3|WriteMultipleExt|39h||YY|YY|YY|D|YY|
|2|Write Sector(s)Ext|34h||YY|YY|YY|D|YY|
1. FR = Features Register (1), SC = Sector Count Register (2), SN = Sector Number Register (3), CY = Cylinder Registers (5:4), DH = Card/Drive/Head Register (6), LBA = Logical Block Address Mode Supported (see command descriptions for use), Y – The register contains a valid parameter for this command. For the Drive/Head Register Y means both the CompactFlash[TM] Memory Card and head parameters are used.
- YY – registers must be written twice for 48bit LBA commands
- D – only the Compact Flash Memory Card parameter is valid and not the head parameter C – the register contains command specific data (see command descriptors for use).
Data Set Management is used for the TRIM command.
## 3.4.2 Differences in the ATAID
Following Information are different in the ATAID compared with standard cards: Table 3: Identify Device Information
|Word<br>Address|STD<br>Value|L28<br>Value|Total<br>Bytes|Data Field Type Information|
|---|---|---|---|---|
|27-46|aaaa*<br>-STD|aaaa*<br>-L28|40|Model number in ASCII (right justified) Big Endian Byte Order in Word<br>(“SFCFxxxxHxBUxTO-x-xx-xxx-xxx”)|
|83|7405h*|5005h*|2|Features/command sets supported<br>Bit10 48bit address feature set supported<br>Bit13 48bit address feature set incl Flush Cache EXT supported|
|86|3405h*|1005h*|2|Features/command sets enabled<br>Bit10 48bit address feature set enabled<br>Bit13 48bit address feature set incl Flush Cache EXT enabled|
|105|0001h|0000h|2|Number of sectorsper Data Set Management command|
|169|0001h|0000h|2|Trim bit in Data Set Management not supported|
* Standard values for full functionality, depending on configuration XXXX Depending on card capacity and drive geometry
Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Switzerland
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## **4 Product Specification**
The CompactFlash[TM] is a small form factor non-volatile memory card which provides high capacity data storage. Its aim is to capture, retain and transport data, audio and images, facilitating the transfer of all types of digital information between a large variety of digital systems.
The Card operates in three basic modes:
- PC card ATA I/O mode
- PC card ATA memory mode
- True IDE mode
The CompactFlash[TM] also supports Advanced Timing modes. Advanced Timing modes are ATA I/O modes that are 100ns or faster, ATA Memory modes that are 100ns or 80ns.
Standard cards are shipped as max. UDMA6 (30ns) and PIO6/MDMA4 (80ns).
If the cards should be used in extended speed modes, they should be qualified on the target system and the system should fulfill the requirements listed below.
It conforms to the PCMCIA Card Specification 2.1 when operating in the ATA I/O mode, and in the ATA Memory mode (Personal Computer Memory Card International Association standard, JEIDA in Japan), and to the ATA specification when operating in True IDE Mode. CompactFlash[TM] Cards can be used with passive adapters in a PC-Card Type I, II, or Type III socket.
The Card has an internal intelligent controller which manages interface protocols, data storage and retrieval as well as hardware BCH-code Error Correction Code (ECC) , defect handling, diagnostics and clock control . The wear leveling mechanism assures an equal usage of the Flash memory cells to extend the life time. Once the Card has been configured by the host, it behaves as a standard ATA (IDE) disk drive. The hardware ECC mechanism allows to detect and correct 6 bit per sector or 24 bit per double sector, depending on the flash . The Card has a voltage detector and a powerful power-loss management feature to prevent data corruption after power-down.
The specification has been realized and approved by the CompactFlash[TM] Association (CFA).
This non-proprietary specification enables users to develop CF products that function correctly and are compatible with future CF design. The system highlights are shown in Table 4 … Table 10.
## Related Documentation
- CF+ and CompactFlash[TM] Specification Revision 4.1, 5.0
- AT Attachment Interface Document, American National Standards Institute, ATA-7, 2005
- PCMCIA PC Card Standard, 1995
- PCMCIA PC Card ATA Specification 7
- ATA Command Set 2 (ACS-2) for TRIM command
## **4.1 System Performance**
Table 4: System Performance
|**4.1 System Performance**<br>Table 4: System Performance|**4.1 System Performance**<br>Table 4: System Performance|**4.1 System Performance**<br>Table 4: System Performance||||
|---|---|---|---|---|---|
|System Performance|||Typ.|Max.|Unit|
|Sleep to write||||5|ms|
|Sleep to read||||5||
|Power up to Ready|||<500|1000||
|Reset to Ready (PC card/IDE Master )|||200|500||
|Data transfer Rate (UDMA6 burst)<br>~~(1, 3)~~<br>~~ss~~|||~~ss~~|133<br>~~ss~~|MB/s<br>~~ss~~|
|SustainedRead (measured)<br>~~ss~~<br>~~—_—_—~~|2 channel 4k~~(1, 3)~~<br>~~(1, 3)~~<br>~~ss~~<br>~~—_—_—~~|2GB-16GB<br>~~ss~~<br>|59<br>~~ss~~<br>|65<br>~~ss~~<br>|MB/s<br>~~ss~~<br>|
|Sustained Write (measured)<br>~~ss~~<br>~~—_—_—~~|2 channel 4k~~(1, 3)~~<br>~~(1, 3)~~<br>~~ss~~<br>~~—_—_—~~|2GB-16GB<br>~~ss~~<br>|31<br>~~ss~~<br>|35<br>~~ss~~<br>||
|SustainedRead (measured)<br>~~ss~~<br>~~—_—_—~~|2channel8k~~(1, 3)~~<br>~~(1, 3)~~<br>~~ss~~<br>~~—_—_—se~~|32GB-64GB<br>~~ss~~<br>~~se~~|58<br>~~ss~~<br>~~se~~|65<br>~~ss~~<br>~~se~~|MB/s<br>~~ss~~<br>~~se~~|
|SustainedWrite (measured)<br>~~—_—_—~~|2 channel 8k~~(1, 3)~~<br>~~—_—_—se~~|32GB-64GB<br>~~se~~|31<br>~~se~~|35<br>~~se~~||
|Random Write 4k(measured)<br>~~—_—_—~~<br>~~a~~|2 channel 4k(1, 2)<br>~~—_—_—~~<br>~~a~~|2GB-16GB<br><br>~~a~~|32<br><br>~~a~~|170 (300)<br><br>~~a~~|IOPS<br>(input/output per second)<br><br>~~a~~<br>~~re~~|
|Random Write 4k(measured)<br>~~a~~<br>~~———~~|2 channel 8k(1, 2)<br>~~a~~<br>~~re~~|32GB-64GB<br>~~a~~<br>~~re~~|27<br>~~a~~<br>~~re~~|160 (300)<br>~~a~~<br>~~re~~||
|~~C~~ommand to DRQ<br>~~———~~|Read<br>~~re~~||100<br>~~re~~|250000<br>~~re~~|µs<br>~~re~~|
||Write<br>~~re~~||30<br>~~re~~|500<br>~~re~~||
|Access Time<br>~~———~~|Read<br>~~re~~||0.22<br>~~re~~|~~re~~|ms<br>~~re~~|
3. CompactFlash[TM] Card in UDMA mode 6, cycle time 30ns in True-IDE mode with Sequential write/read test. The number of flash is decoded in the part number; also the flash page size is depicted in this table. Sustained Speed depends on flash type and number, file size, and burst speed.
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## Requirements for using extended speed (PIO 5, 6/ MDMA 3, 4)
(CompactFlash[TM] Specification 5.0; section 4.3.7)
The CF Advanced Timing modes include PCMCIA I/O and Memory modes that are 100ns or faster and True IDE PIO Modes 5, 6 and Multiword DMA Modes 3, 4.
- When operating in CF Advanced timing modes, the host shall conform to the following requirements: 1. Only one CF device shall be attached to the CF Bus.
2. The host shall not present a load of more than 40pF to the device for all signals, including any cabling.
3. The maximum cable length is 0.05 m (2 in). The cable length is measured from the card connector to the host controller. 0.46 m (18 in) cables are not supported .
4. The –WAIT and IORDY signals shall be ignored by the host.
Devices supporting CF Advanced timing modes shall also support slower timing modes, to ensure operability with systems that do not support CF Advanced timing modes.
## Ultra DMA Electrical Requirements
(CompactFlash[TM] Specification 5.0; section 4.3.8)
Operation in Ultra DMA mode requires careful attention to cabling, printed circuit board (PCB) trace routing and termination for reliable operation. These requirements are described in the following sections.
Host and Card signal capacitance limits for Ultra DMA operation
The host interface signal capacitance at the host connector shall be a maximum of 25pF for each signal as measured at 1 MHz.
The card interface signal capacitance at the card connector shall be a maximum of 20pF for each signal as measured at 1 MHz.
Series termination required for Ultra DMA operation
Series termination resistors are required at both the host and the card for operation in any of the Ultra DMA modes. The CF specification describes typical values for series termination at the host and the device. C-400 cards have the specified serial resistances in IDE bus.
## **4.2 Environmental Specifications**
## 4.2.1 Recommended Operating Conditions
## Table 5: CF Card Recommended Operating Conditions
|Parameter|Value|
|---|---|
|Commercial Operating Temperature|0°C to 70°C|
|Industrial Operating Temperature|-40°C to 85°C|
|Power Supply VCC Voltage (5V)|5.0V ±10% (4.5V to 5.5V)*)|
|Power Supply VCC Voltage (3.3V)|3.3V ±10% (2.97V to 3.63V)*)|
*) Voltage could be between 2.95V and 5.5V
Table 6: Current consumption (1)
|Table 6: Current consumption (1)||||
|---|---|---|---|
|Current Consumption(typ)|3.3V|5V|Unit|
|Read (UDMA6/max)|110 / 140|110 / 140|mA|
|Write (UDMA6/max)|90 / 110|85 / 110||
|Sleep/Idle Mode (typ/max)|3 / 5|3 / 5||
1. All values are typical at 25° C and nominal supply voltage and refer to 8Gbyte CompactFlash[TM] Card. Max values are for 32GB cards in UDMA6 mode in IDE mode. The card goes to Sleep/idle mode 20ms (default) after last host command. The sleep current at 5V depends on the signal level at the CF-Bus
## 4.2.2 Recommended Storage Conditions
Table 7: CF Card Recommended Storage Conditions Parameter Value Storage Temperature -50°C to 100°C ~~ooo dYA JH] 7~~ High temperature storage decreases the data retention.
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4.2.3 Shock, Vibration, and Humidity Table 8: Shock, Vibration, and Humidity Parameter Value Humidity (non-condensing) 85% RH 85°C, 1000 hrs (JEDEC JESD22, method A101-B) Vibration 20 G peak, 20-2000Hz, 4 per direction (JEDEC JESD22, method B103) 5.35G RMS, 15 min per plane (IEC 68-2-6) Shock 1.5k G peak, 0.5ms 5 times (JEDEC JESD22, method B110) ~~ae~~ 30 G, 11ms 1 time (IEC 68-2-27)
**4.3 Physical Dimensions** Table 9: Physical Dimensions Parameter Value Unit Width 42.8 Height 36.4 mm Thickness 3.3 ~~SSS~~ Weight (typ.) 10 g **4.4 Reliability** Table 10: System Reliability and Maintenance
Parameter Value MTBF (at 40°C) > 3,000,000 hours (1) Insertions/Removals > 10,000 Data Reliability < 1 Non-Recoverable Error per 10 ~~[14]~~ bits Read (1) Data Retention 10 years (JESD47) ~~SSS~~ (1) Dependent on final system qualification data. ~~SSS~~ **4.5 Drive Geometry / CHS Parameter** Table 11: CF capacity specification
|Capacity|Cylinders|Heads|Sectors / track|Sectors|Total addressable capacity (Byte)|
|---|---|---|---|---|---|
|2GB|3,970|16|63|4,001,760|2,048,901,120|
|4GB|7,964|16|63|8,027,712|4,110,188,544|
|8GB|15,880<br>~~(1)~~|16|63|16,007,040|8,195,604,480|
|16GB|16,383~~(1)~~<br>~~(1)~~|16|63|31,717,728|16,239,476,736|
|32GB|16,383~~(1)~~<br>~~(1)~~|16|63|64,028,160|32,782,417,920|
|64GB|16,383~~(1)~~|16|63|125,313,024|64,160,268,288|
(1) The CHS addressing is limited to about 8GB. Larger drives should be used in LBA mode.
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## **4.6 Physical description**
The CompactFlash[TM] Memory Card contains a single chip controller and Flash memory module(s). The controller interfaces with a host system allowing data to be written to and read from the Flash memory module(s). Figure 1 shows the Block Diagram of the CompactFlash[TM] Memory Card.
The Card is offered in a Type I package with a 50-pin connector consisting of two rows of 25 female contacts on 50 mil (1.27mm) centers. Figure 21 shows Type I Card Dimensions.
Figure 1: CompactFlash[TM] Memory Card Block Diagram
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## **5 Electrical interface**
## **5.1 Electrical description**
The CompactFlash[TM] Memory Card operates in three basic modes:
- PC Card ATA using I/O Mode
- PC Card ATA using Memory Mode
- True IDE Mode with MWDMA and UDMA, which is compatible with most disk drives
- The signal/pin assignments are listed in Table 12 Low active signals have a ‘-’ prefix. Pin types are Input, Output or Input/Output.
The configuration of the Card is controlled using the standard PC card configuration registers starting at address 200h in the Attribute Memory space of the memory card. Table 13 describes the I/O signals. Inputs are signals sourced from the host while Outputs are signals sourced from the Card. The signals are described for each of the three operating modes.
All outputs from the Card are totem pole except the data bus signals that are bi-directional tri-state. Refer to the section titled “Electrical Specifications” for definitions of Input and Output type.
|Pin Num<br>~~|Popp~~|PC Card MemoryMode<br>~~Popp~~|PC Card MemoryMode<br>~~Popp~~|PC Card MemoryMode<br>~~Popp~~|PC Card I/O Mode<br>~~ppp~~|PC Card I/O Mode<br>~~ppp~~|PC Card I/O Mode<br>~~ppp~~|TrueIDE Mode~~(4)~~<br>~~ppp~~|TrueIDE Mode~~(4)~~<br>~~ppp~~|TrueIDE Mode~~(4)~~<br>~~ppp~~|
|---|---|---|---|---|---|---|---|---|---|
||Signal<br>Name<br>~~Popp~~|Pin<br>Type<br>~~Popp~~|In, Out<br>Type<br>~~Popp~~|Signal<br>Name<br>~~ppp~~|Pin<br>Type<br>~~ppp~~|In, Out<br>Type<br>~~ppp~~|Signal<br>Name<br>~~ppp~~|Pin<br>Type<br>~~ppp~~|In, Out<br>Type<br>~~ppp~~|
|1<br>~~| Popp~~<br>~~ee ee~~<br>~~ee~~|GND<br>~~Popp~~<br>~~ee~~<br>~~ee~~|~~Popp~~<br>~~es~~<br>~~es~~|Ground<br>~~Popp ~~<br>~~es~~<br>~~es~~|GND<br> ~~ppp~~<br>~~ss~~<br>~~rs~~|~~ppp~~<br>~~ss~~<br>~~rs~~|Ground<br>~~ppp~~<br>~~ns~~|GND<br>~~ppp~~<br>~~(~~<br>~~ss~~|~~ppp~~<br>~~ss~~|Ground<br>~~ppp~~|
|2<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|D3<br>~~ee ~~<br>~~ee~~<br>~~er~~|I/O<br> ~~es~~<br>~~es~~<br>~~er es~~|I1Z,OZ3<br>~~es~~<br>~~es~~<br>~~es~~|D3<br>~~ss~~<br>~~rs~~<br>~~sts~~|I/O<br>~~ss~~<br>~~rs~~<br>~~sts~~|I1Z,OZ3<br>~~ns~~<br>~~ns~~|D3<br>~~(~~<br>~~ss~~<br>~~(OO~~|I/O<br>~~ss~~<br>~~(OO~~|I1Z,OZ3|
|3<br>~~ee~~<br>~~ee~~<br>~~ee~~|D4<br>~~ee~~<br>~~er~~<br>~~er~~|I/O<br>~~es ~~<br>~~er es~~<br>~~er es~~|I1Z,OZ3<br> ~~es ~~<br>~~es~~<br>~~es~~|D4<br> ~~rs~~<br>~~sts~~<br>~~rs~~|I/O<br>~~rs~~<br>~~sts~~<br>~~tts~~|I1Z,OZ3<br>~~ns~~<br>~~ns~~|D4<br>~~ss~~<br>~~(OO~~<br>~~(OO~~|I/O<br>~~ss~~<br>~~(OO~~<br>~~(OO~~|I1Z,OZ3|
|4<br>~~ee~~<br>~~ee~~<br>~~ee~~|D5<br>~~er~~<br>~~er~~<br>~~rr~~|I/O<br>~~er es~~<br>~~er es~~<br>~~rr es~~|I1Z,OZ3<br>~~es~~<br>~~es~~<br>~~es~~|D5<br>~~sts~~<br>~~rs~~<br>~~ers~~|I/O<br>~~sts~~<br>~~tts~~<br>~~rs~~|I1Z,OZ3<br>~~ns~~<br>~~ns~~<br>~~ns~~|D5<br>~~(OO~~<br>~~(OO~~<br>~~I~~|I/O<br>~~(OO~~<br>~~(OO~~<br>~~(OD~~|I1Z,OZ3|
|5<br>~~ee~~<br>~~ee~~<br>~~ee~~|D6<br>~~er~~<br>~~rr~~<br>~~ee~~|I/O<br>~~er es~~<br>~~rr es~~<br>~~es~~|I1Z,OZ3<br>~~es~~<br>~~es~~<br>~~es~~|D6<br>~~rs~~<br>~~ers~~<br>~~rs~~|I/O<br>~~tts ~~<br>~~rs~~<br>~~rs~~|I1Z,OZ3<br> ~~ns~~<br>~~ns~~|D6<br>~~(OO~~<br>~~I~~<br>~~ss~~|I/O<br>~~(OO~~<br>~~(OD~~<br>~~ss~~|I1Z,OZ3|
|6<br>~~ee~~<br>~~ee~~<br>~~ee~~|D7<br>~~rr~~<br>~~ee~~<br>~~er~~|I/O<br>~~rr es~~<br>~~es~~<br>~~er es~~|I1Z,OZ3<br>~~es ~~<br>~~es~~<br>~~es~~|D7<br> ~~ers ~~<br>~~rs~~<br>~~sts~~|I/O<br> ~~rs~~<br>~~rs~~<br>~~sts~~|I1Z,OZ3<br>~~ns ~~<br>~~ns~~|D7<br> ~~I ~~<br>~~ss~~<br>~~(OO~~|I/O<br> ~~(OD~~<br>~~ss~~<br>~~(OO~~|I1Z,OZ3|
|7<br>~~ee~~<br>~~ee~~<br>~~ee~~|-CE1<br>~~ee~~<br>~~er~~<br>~~er~~|I<br>~~es ~~<br>~~er es~~<br>~~er es~~|I3U<br> ~~es ~~<br>~~es~~<br>~~es~~|-CE1<br> ~~rs~~<br>~~sts~~<br>~~rs~~|I<br>~~rs~~<br>~~sts~~<br>~~tts~~|I3U<br>~~ns~~<br>~~ns~~|-CS0<br>~~ss~~<br>~~(OO~~<br>~~(OO~~|I<br>~~ss~~<br>~~(OO~~<br>~~(OO~~|I3Z|
|8<br>~~ee~~<br>~~ee~~<br>~~ee~~|A10<br>~~er~~<br>~~er~~<br>~~re~~|I<br>~~er es~~<br>~~er es~~<br>~~re~~|I1Z<br>~~es~~<br>~~es~~<br>~~rs~~|A10<br>~~sts~~<br>~~rs~~<br>~~rs~~|I<br>~~sts~~<br>~~tts~~<br>~~rs~~|I1Z<br>~~ns~~<br>~~ns~~<br>~~rs~~|A10(2)<br>~~(OO~~<br>~~(OO~~<br>~~I (~~|I<br>~~(OO~~<br>~~(OO~~<br>~~(~~|I1Z|
|9(1)<br>~~ee~~<br>~~ee~~<br>~~ee~~|-OE<br>~~er~~<br>~~re~~<br>~~es~~|I<br>~~er es~~<br>~~re~~<br>~~es ns~~|I3U<br>~~es~~<br>~~rs~~<br>~~ns~~|-OE<br>~~rs~~<br>~~rs~~<br>~~ts~~|I<br>~~tts ~~<br>~~rs~~|I3U<br> ~~ns~~<br>~~rs~~|-ATASEL<br>~~(OO~~<br>~~I (~~|I<br>~~(OO~~<br>~~(~~|I3U|
|10<br>~~ee~~<br>~~ee~~<br>~~re~~|A9<br>~~re~~<br>~~es~~<br>~~rr~~|I<br>~~re ~~<br>~~es ns~~<br>~~rr es~~|I1Z<br> ~~rs ~~<br>~~ns~~<br>~~es~~|A9<br> ~~rs~~<br>~~ts~~<br>~~rs~~|I<br>~~rs ~~<br>~~Gs~~|I1Z<br> ~~rs ~~|A9(2)<br> ~~I (~~<br>~~(Os~~|I<br>~~(~~<br>~~(Os~~|I1Z|
|11<br>~~ee~~<br>~~re~~<br>~~ee~~|A8<br>~~es~~<br>~~rr~~<br>~~re~~|I<br>~~es ns~~<br>~~rr es~~<br>~~re es~~|I1Z<br>~~ns~~<br>~~es~~<br>~~es~~|A8<br>~~ts~~<br>~~rs~~<br>~~rs~~|I<br>~~Gs~~<br>~~rs~~|I1Z<br>~~rs~~|A8(2)<br>~~(Os~~<br>~~(Os~~|I<br>~~(Os~~<br>~~(Os~~|I1Z|
|12<br>~~re~~<br>~~ee~~<br>~~ee~~|A7<br>~~rr~~<br>~~re~~<br>~~er~~|I<br>~~rr es~~<br>~~re es~~<br>~~er~~|I1Z<br>~~es ~~<br>~~es~~<br>~~rs~~|A7<br> ~~rs~~<br>~~rs~~<br>~~rs~~|I<br>~~Gs~~<br>~~rs~~<br>~~nD~~|I1Z<br>~~rs~~<br>~~rs~~|A7(2)<br>~~(Os~~<br>~~(Os~~<br>~~I~~|I<br>~~(Os~~<br>~~(Os~~|I1Z|
|13<br>~~ee~~<br>~~ee~~<br>~~ee~~|Vcc<br>~~re~~<br>~~er~~<br>~~rs~~|~~re es~~<br>~~er~~<br>~~rs~~|Power<br>~~es ~~<br>~~rs~~<br>~~rs~~|Vcc<br> ~~rs ~~<br>~~rs~~<br>~~ts~~|~~rs ~~<br>~~nD~~<br>~~ns~~|Power<br> ~~rs~~<br>~~rs~~<br>~~ns~~|Vcc<br>~~(Os~~<br>~~I~~<br>~~ns~~|~~(Os~~|Power|
|14<br>~~ee~~<br>~~ee~~<br>~~re~~|A6<br>~~er~~<br>~~rs~~<br>~~rr~~|I<br>~~er~~<br>~~rs~~<br>~~rr es~~|I1Z<br>~~rs ~~<br>~~rs~~<br>~~es~~|A6<br> ~~rs~~<br>~~ts~~<br>~~rs~~|I<br>~~nD~~<br>~~ns~~<br>~~Gs~~|I1Z<br>~~rs ~~<br>~~ns~~|A6(2)<br> ~~I~~<br>~~ns~~<br>~~(Os~~|I<br>~~(Os~~|I1Z|
|15<br>~~ee~~<br>~~re~~<br>~~ee~~|A5<br>~~rs~~<br>~~rr~~<br>~~re~~|I<br>~~rs~~<br>~~rr es~~<br>~~re es~~|I1Z<br>~~rs~~<br>~~es~~<br>~~es~~|A5<br>~~ts ~~<br>~~rs~~<br>~~rs~~|I<br> ~~ns~~<br>~~Gs~~<br>~~rs~~|I1Z<br>~~ns~~<br>~~rs~~|A5(2)<br>~~ns~~<br>~~(Os~~<br>~~(Os~~|I<br>~~(Os~~<br>~~(Os~~|I1Z|
|16<br>~~re~~<br>~~ee~~<br>~~ee~~|A4<br>~~rr~~<br>~~re~~<br>~~er~~|I<br>~~rr es~~<br>~~re es~~<br>~~er~~|I1Z<br>~~es ~~<br>~~es~~<br>~~rs~~|A4<br> ~~rs~~<br>~~rs~~<br>~~rs~~|I<br>~~Gs~~<br>~~rs~~<br>~~nD~~|I1Z<br>~~rs~~<br>~~rs~~|A4(2)<br>~~(Os~~<br>~~(Os~~<br>~~I~~|I<br>~~(Os~~<br>~~(Os~~|I1Z|
|17<br>~~ee~~<br>~~ee~~<br>~~ee~~|A3<br>~~re~~<br>~~er~~<br>~~rs~~|I<br>~~re es~~<br>~~er~~<br>~~rs~~|I1Z<br>~~es ~~<br>~~rs~~<br>~~rs~~|A3<br> ~~rs ~~<br>~~rs~~<br>~~ts~~|I<br> ~~rs ~~<br>~~nD~~<br>~~ns~~|I1Z<br> ~~rs~~<br>~~rs~~<br>~~ns~~|A3(2)<br>~~(Os~~<br>~~I~~<br>~~ns~~|I<br>~~(Os~~|I1Z|
|18<br>~~ee~~<br>~~ee~~<br>~~re~~|A2<br>~~er~~<br>~~rs~~<br>~~rr~~|I<br>~~er~~<br>~~rs~~<br>~~rr es~~|I1Z<br>~~rs ~~<br>~~rs~~<br>~~es~~|A2<br> ~~rs~~<br>~~ts~~<br>~~rs~~|I<br>~~nD~~<br>~~ns~~<br>~~Gs~~|I1Z<br>~~rs ~~<br>~~ns~~|A2<br> ~~I~~<br>~~ns~~<br>~~(Os~~|I<br>~~(Os~~|I1Z|
|19<br>~~ee~~<br>~~re~~<br>~~ee~~|A1<br>~~rs~~<br>~~rr~~<br>~~re~~|I<br>~~rs~~<br>~~rr es~~<br>~~re es~~|I1Z<br>~~rs~~<br>~~es~~<br>~~es~~|A1<br>~~ts ~~<br>~~rs~~<br>~~rs~~|I<br> ~~ns~~<br>~~Gs~~<br>~~rs~~|I1Z<br>~~ns~~<br>~~rs~~|A1<br>~~ns~~<br>~~(Os~~<br>~~(Os~~|I<br>~~(Os~~<br>~~(Os~~|I1Z|
|20<br>~~re~~<br>~~ee~~<br>~~ee~~|A0(11)<br>~~rr~~<br>~~re~~<br>~~er~~|I<br>~~rr es~~<br>~~re es~~<br>~~er~~|I1Z<br>~~es ~~<br>~~es~~<br>~~rs~~|A0(11)<br> ~~rs~~<br>~~rs~~<br>~~rs~~|I<br>~~Gs~~<br>~~rs~~<br>~~nD~~|I1Z<br>~~rs~~<br>~~rs~~|A0<br>~~(Os~~<br>~~(Os~~<br>~~I~~|I<br>~~(Os~~<br>~~(Os~~|I1Z|
|21<br>~~ee~~<br>~~ee~~<br>~~ee~~|D0<br>~~re~~<br>~~er~~<br>~~ee es~~|I/O<br>~~re es~~<br>~~er~~<br>~~es~~|I1Z,OZ3<br>~~es ~~<br>~~rs~~<br>~~rs~~|D0<br> ~~rs ~~<br>~~rs~~<br>~~res~~|I/O<br> ~~rs ~~<br>~~nD~~<br>~~rs~~|I1Z,OZ3<br> ~~rs~~<br>~~rs~~|D0<br>~~(Os~~<br>~~I~~<br>~~Ss~~|I/O<br>~~(Os~~<br>~~Ss~~|I1Z,OZ3|
|22<br>~~ee~~<br>~~ee~~<br>~~re~~|D1<br>~~er~~<br>~~ee es~~<br>~~es~~|I/O<br>~~er~~<br>~~es~~<br>~~es~~|I1Z,OZ3<br>~~rs ~~<br>~~rs~~<br>~~es~~|D1<br> ~~rs~~<br>~~res~~<br>~~rs~~|I/O<br>~~nD~~<br>~~rs~~<br>~~rs~~|I1Z,OZ3<br>~~rs ~~<br>~~es~~|D1<br> ~~I~~<br>~~Ss~~<br>~~I~~|I/O<br>~~Ss~~<br>~~(Os~~|I1Z,OZ3|
|23<br>~~ee~~<br>~~re~~<br>~~ee~~|D2<br>~~ee es~~<br>~~es~~<br>~~re~~|I/O<br>~~es~~<br>~~es~~<br>~~re~~|I1Z,OZ3<br>~~rs ~~<br>~~es~~<br>~~rs~~|D2<br> ~~res ~~<br>~~rs~~<br>~~rs~~|I/O<br> ~~rs~~<br>~~rs~~<br>~~rs~~|I1Z,OZ3<br>~~es~~<br>~~rs~~|D2<br>~~Ss~~<br>~~I~~<br>~~(I~~|I/O<br>~~Ss~~<br>~~(Os~~<br>~~(OU~~|I1Z,OZ3|
|24<br>~~re~~<br>~~ee~~<br>~~ee~~|WP<br>~~es~~<br>~~re~~|O<br>~~es~~<br>~~re~~<br>~~rs~~|OT3<br>~~es ~~<br>~~rs~~<br>~~rs~~|-IOIS16(10)<br> ~~rs ~~<br>~~rs~~<br>~~rs~~|O<br> ~~rs ~~<br>~~rs~~<br>~~GD~~|OT3<br> ~~es ~~<br>~~rs~~<br>~~ns~~|-IOIS16<br> ~~I ~~<br>~~(I~~<br>~~(~~|O<br> ~~(Os~~<br>~~(OU~~<br>~~(~~|ON3|
|25<br>~~ee~~<br>~~ee~~<br>~~ee~~|-CD2<br>~~re~~<br>~~ee es~~|O<br>~~re~~<br>~~rs~~<br>~~es ns~~|Ground<br>~~rs ~~<br>~~rs~~<br>~~ns~~|-CD2<br> ~~rs ~~<br>~~rs~~<br>~~rr~~|O<br> ~~rs~~<br>~~GD~~<br>~~nt~~|Ground<br>~~rs~~<br>~~ns~~<br>~~nD~~|-CD2<br>~~(I ~~<br>~~(~~<br>~~nD~~|O<br> ~~(OU~~<br>~~(~~|Ground|
|26<br>~~ee~~<br>~~ee~~<br>~~re~~|-CD1<br>~~ee es~~<br>~~es~~|O<br>~~rs~~<br>~~es ns~~<br>~~es~~|Ground<br>~~rs~~<br>~~ns~~<br>~~es~~|-CD1<br>~~rs~~<br>~~rr~~<br>~~rs~~|O<br>~~GD~~<br>~~nt~~<br>~~rs~~|Ground<br>~~ns~~<br>~~nD~~<br>~~es~~|-CD1<br>~~(~~<br>~~nD~~<br>~~I~~|O<br>~~(~~<br>~~(Os~~|Ground|
|27<br>~~ee ~~<br>~~re~~<br>~~ee~~|D11(1)<br> ~~ee es~~<br>~~es~~<br>~~ts~~|I/O<br>~~es ns~~<br>~~es~~<br>~~ts~~|I1Z,OZ3<br>~~ns ~~<br>~~es~~<br>~~ts~~|D11(1)<br> ~~rr~~<br>~~rs~~<br>~~rs~~|I/O<br>~~nt ~~<br>~~rs~~<br>~~rs~~|I1Z,OZ3<br> ~~nD~~<br>~~es~~<br>~~ns~~|D11(1)<br>~~nD~~<br>~~I~~<br>~~I (~~|I/O<br>~~(Os~~<br>~~(~~|I1Z,OZ3|
|28<br>~~re~~<br>~~ee~~<br>~~ee~~|D12(1)<br>~~es~~<br>~~ts~~<br>~~rs~~|I/O<br>~~es~~<br>~~ts~~<br>~~rs~~|I1Z,OZ3<br>~~es ~~<br>~~ts~~<br>~~rs~~|D12(1)<br> ~~rs ~~<br>~~rs~~<br>~~rs~~|I/O<br> ~~rs ~~<br>~~rs~~<br>~~Gs~~|I1Z,OZ3<br> ~~es ~~<br>~~ns~~<br>~~ns~~|D12(1)<br> ~~I ~~<br>~~I (~~<br>~~(GOD~~|I/O<br> ~~(Os~~<br>~~(~~<br>~~(GOD~~|I1Z,OZ3|
|29<br>~~ee~~<br>~~ee~~<br>~~ee~~|D13(1)<br>~~ts~~<br>~~rs~~<br>~~ee es~~|I/O<br>~~ts~~<br>~~rs~~<br>~~es~~|I1Z,OZ3<br>~~ts ~~<br>~~rs~~<br>~~rs~~|D13(1)<br> ~~rs ~~<br>~~rs~~<br>~~rs~~|I/O<br> ~~rs~~<br>~~Gs~~<br>~~rs~~|I1Z,OZ3<br>~~ns ~~<br>~~ns~~<br>~~nD~~|D13(1)<br> ~~I (~~<br>~~(GOD~~<br>~~nD~~|I/O<br>~~(~~<br>~~(GOD~~|I1Z,OZ3|
|30<br>~~ee~~<br>~~ee~~|D14(1)<br>~~rs~~<br>~~ee es~~|I/O<br>~~rs~~<br>~~es~~|I1Z,OZ3<br>~~rs ~~<br>~~rs~~|D14(1)<br> ~~rs~~<br>~~rs~~|I/O<br>~~Gs~~<br>~~rs~~|I1Z,OZ3<br>~~ns~~<br>~~nD~~|D14(1)<br>~~(GOD~~<br>~~nD~~|I/O<br>~~(GOD~~|I1Z,OZ3|
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.23
Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Switzerland
www.swissbit.com
C-440_data_sheet_CF-HxBU_Rev123.doc Page 12 of 106
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|Pin Num<br>~~|Pop~~|PC CardMemoryMode<br>~~Pop po~~|PC CardMemoryMode<br>~~Pop po~~|PC CardMemoryMode<br>~~Pop po~~|PC CardI/OMode<br>~~ppp~~|PC CardI/OMode<br>~~ppp~~|PC CardI/OMode<br>~~ppp~~|True IDE Mode~~(4)~~<br>~~ppp~~|True IDE Mode~~(4)~~<br>~~ppp~~|True IDE Mode~~(4)~~<br>~~ppp~~|
|---|---|---|---|---|---|---|---|---|---|
||Signal<br>Name<br>~~Pop~~|Pin<br>Type<br>~~Pop po~~|In, Out<br>Type<br>~~po~~|Signal<br>Name<br>~~ppp~~|Pin<br>Type<br>~~ppp~~|In, Out<br>Type<br>~~ppp~~|Signal<br>Name<br>~~ppp~~|Pin<br>Type<br>~~ppp~~|In, Out<br>Type<br>~~ppp~~|
|31<br>~~| Pop~~<br>~~ee~~<br>~~ee~~|D15(1)<br>~~Pop~~<br>~~es~~|I/O<br>~~Pop po~~<br>~~es~~<br>~~rs~~|I1Z,OZ3<br>~~po~~<br>~~es~~<br>~~rs~~|D15(1)<br>~~ppp~~<br>~~ns~~<br>~~rs~~|I/O<br>~~ppp~~<br>~~ns~~<br>~~rs~~|I1Z,OZ3<br>~~ppp~~<br>~~ns~~<br>~~rs~~|D15(1)<br>~~ppp~~<br>~~(OO~~<br>~~I~~|I/O<br>~~ppp~~<br>~~(OO~~<br>~~(Os~~|I1Z,OZ3<br>~~ppp~~|
|32<br>~~ee~~<br>~~ee~~<br>~~ee~~|-CE2(1)<br>~~es~~<br>~~ee~~|I<br>~~es~~<br>~~rs~~<br>~~ee~~|I3U<br>~~es~~<br>~~rs~~<br>~~rs~~|-CE2(1)<br>~~ns~~<br>~~rs~~<br>~~eres~~|I<br>~~ns~~<br>~~rs~~<br>~~rs~~|I3U<br>~~ns~~<br>~~rs~~<br>~~rs~~|-CS1(1)<br>~~(OO~~<br>~~I~~<br>~~(Os~~|I<br>~~(OO~~<br>~~(Os~~<br>~~(Os~~|I3Z|
|33<br>~~ee~~<br>~~ee~~|-VS1<br>~~ee~~|O<br>~~rs~~<br>~~ee~~|Ground<br>~~rs ~~<br>~~rs~~|-VS1<br> ~~rs~~<br>~~eres~~|O<br>~~rs~~<br>~~rs~~|Ground<br>~~rs ~~<br>~~rs~~|-VS1<br>~~(7)~~<br> ~~I~~<br>~~(Os~~|O<br>~~(Os~~<br>~~(Os~~|Ground|
|34<br>~~ee~~|-IORD<br>~~ee~~|I<br>~~ee~~|I3U<br>~~rs ~~|-IORD<br> ~~eres ~~|I<br> ~~rs~~|I3U<br>~~rs~~|-IORD~~(7)~~<br>~~(8)~~<br>~~(Os~~|I<br>~~(Os~~|I3Z|
||||||||HSTROBE~~(8)~~<br>~~(9)~~|||
||||||||-HDMARDY~~(9)~~<br>~~(7)~~|||
|35<br>~~ee~~<br>~~es~~<br>~~ee~~|-IOWR<br>~~ee~~<br>~~ee~~|I<br>~~ee~~<br>~~es~~|I3U<br>~~ee~~<br>~~nes~~|-IOWR<br>~~ee~~<br>~~Rs~~|I<br>~~ee~~<br>~~rt~~|I3U<br>~~ee ~~<br>~~(RD~~|-IOWR~~(7)~~<br>~~(8)(9)~~<br>~~—~~<br>~~Ee~~<br>|I<br>~~Ee~~|I3Z<br>~~Ee~~|
||||||||STOP~~(8)(9)~~<br>~~—~~<br> ~~Ee~~<br>~~OU~~|||
|36<br><br>~~es~~<br>~~ee~~<br>~~ee~~|-WE<br><br>~~ee~~<br>~~ne ns~~|I<br><br>~~es~~<br>~~ne ns~~|I3U<br><br>~~nes~~<br>~~ne ns~~|-WE<br><br>~~Rs~~<br>~~rs~~|I<br><br>~~rt~~<br>~~Gs~~|I3U<br> <br>~~(RD~~<br>~~ts~~|-WE(3)<br> ~~Ee~~<br>~~OU~~<br>~~(I~~|I<br>~~Ee~~<br>~~(OU~~|I3U<br>~~Ee~~|
|37<br><br>~~es ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|READY<br><br> ~~ee~~<br>~~ne ns~~|O<br><br>~~es~~<br>~~ne ns~~<br>~~rs~~|OT1<br><br>~~nes~~<br>~~ne ns~~<br>~~rs~~|-IREQ<br><br>~~Rs~~<br>~~rs~~<br>~~rs~~|O<br><br>~~rt~~<br>~~Gs~~<br>~~rs~~|OT1<br> <br>~~(RD~~<br>~~ts~~<br>~~rs~~|INTRQ<br> ~~Ee~~<br>~~OU~~<br>~~(I~~<br>~~I~~|O<br>~~Ee~~<br>~~(OU~~<br>~~(Os~~|OZ1<br>~~Ee~~|
|38<br> <br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~es~~|Vcc<br> ~~ee ~~<br>~~ne ns~~<br>~~ee~~<br>|~~es ~~<br>~~ne ns~~<br>~~rs~~<br>~~ee~~<br>|Power<br> ~~nes ~~<br>~~ne ns~~<br>~~rs~~<br>~~rs~~<br>|Vcc<br> ~~Rs ~~<br>~~rs~~<br>~~rs~~<br>~~eres~~<br>|~~rt ~~<br>~~Gs~~<br>~~rs~~<br>~~rs~~<br>|Power<br> ~~(RD ~~<br>~~ts~~<br>~~rs~~<br>~~rs~~<br>|Vcc<br> ~~OU~~<br>~~(I~~<br>~~I~~<br>~~(Os~~<br>|~~(OU~~<br>~~(Os~~<br>~~(Os~~|Power|
|39<br>~~ee~~<br>~~ee~~<br>~~es~~<br>~~ee~~|-CSEL(5)<br>~~ne ns~~<br>~~ee~~<br>~~ee~~<br>|I<br>~~ne ns~~<br>~~rs~~<br>~~ee~~<br>~~es~~<br>|I2Z<br>~~ne ns ~~<br>~~rs~~<br>~~rs~~<br>~~nes~~<br>|-CSEL(5)<br> ~~rs~~<br>~~rs~~<br>~~eres~~<br>~~rs~~<br>|I<br>~~Gs ~~<br>~~rs~~<br>~~rs~~<br>~~ts~~<br>|I2Z<br> ~~ts~~<br>~~rs~~<br>~~rs~~<br>~~(Us~~<br>|-CSEL<br>~~(I~~<br>~~I~~<br>~~(Os~~<br>~~UU~~<br>|I<br>~~(OU~~<br>~~(Os~~<br>~~(Os~~<br>|I2U|
|40<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~|~~|-VS2<br>~~ee~~<br>~~ee~~<br>~~er~~|O<br>~~rs~~<br>~~ee~~<br>~~es~~<br>~~er~~|OPEN<br>~~rs ~~<br>~~rs~~<br>~~nes~~<br>~~ns~~|-VS2<br> ~~rs ~~<br>~~eres~~<br>~~rs~~<br>~~ns~~|O<br> ~~rs ~~<br>~~rs~~<br>~~ts~~<br>~~Gs~~|OPEN<br> ~~rs ~~<br>~~rs~~<br>~~(Us~~<br>~~ns~~|-VS2<br> ~~I ~~<br>~~(Os~~<br>~~UU~~<br>~~(Os~~|O<br> ~~(Os~~<br>~~(Os~~<br>~~(Os~~|OPEN|
|41<br>~~es~~<br>~~ee~~<br>~~|~~<br>~~ee~~|RESET<br>~~ee~~<br>~~ee~~<br>~~er~~<br>~~ff~~|I<br>~~ee ~~<br>~~es~~<br>~~er~~<br>~~ff~~|I2U<br> ~~rs ~~<br>~~nes~~<br>~~ns~~<br>~~ffot~~|RESET<br> ~~eres ~~<br>~~rs~~<br>~~ns~~<br>~~otEt~~|I<br> ~~rs ~~<br>~~ts~~<br>~~Gs~~<br>~~Et~~|I2U<br> ~~rs~~<br>~~(Us~~<br>~~ns~~<br>~~Etce~~|-RESET<br>~~(7)~~<br>~~(Os~~<br>~~UU~~<br>~~(Os~~<br>~~ce~~|I<br>~~(Os~~<br>~~(Os~~|I2U|
|42<br><br>~~ee ~~<br>~~|~~<br>~~ee~~<br>~~ee~~|-WAIT<br>~~ee ~~<br> ~~er~~<br>~~ff~~<br>~~er~~<br>|O<br> ~~es ~~<br>~~er~~<br>~~ff~~<br>~~er es~~<br>|OT1<br> ~~nes ~~<br>~~ns~~<br>~~ffot~~<br>~~es~~<br>|-WAIT<br> ~~rs ~~<br>~~ns~~<br>~~otEt~~<br>~~sts~~<br>|O<br> ~~ts~~<br>~~Gs~~<br>~~Et~~<br>~~sts~~<br>|OT1<br>~~(Us ~~<br>~~ns~~<br>~~Etce~~<br>~~ns~~<br>|IORDY~~(7)~~<br>~~(8)~~<br> ~~UU~~<br>~~(Os~~<br>~~ce~~|O<br>~~(Os~~<br>~~(OO~~|ON1|
||||||||-DDMARDY~~(8)~~<br>~~(9)~~<br>~~(Os~~<br>~~ce~~|||
||||||||DSTROBE~~(9)~~<br>~~(Os~~<br>~~ce~~<br>~~(OO~~|||
|43<br> <br>~~|~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|-INPACK<br> ~~er~~<br>~~ff~~<br>~~er~~<br>~~er~~|O<br>~~er ~~<br>~~ff~~<br>~~er es~~<br>~~er es~~|OT1<br> ~~ns ~~<br>~~ffot~~<br>~~es~~<br>~~es~~|-INPACK<br> ~~ns~~<br>~~otEt~~<br>~~sts~~<br>~~rs~~|O<br>~~Gs ~~<br>~~Et~~<br>~~sts~~<br>~~tts~~|OT1<br> ~~ns ~~<br>~~Etce~~<br>~~ns~~<br>~~ns~~|DMARQ<br> ~~(Os~~<br>~~ce~~<br>~~(OO~~<br>~~(OO~~|O<br>~~(Os~~<br>~~(OO~~<br>~~(OO~~|OZ1|
|44<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|-REG<br>~~ff~~<br>~~er~~<br>~~er~~<br>~~rr~~<br>|I<br>~~ff~~<br>~~er es~~<br>~~er es~~<br>~~rr es~~<br>|I3U<br>~~ff ot~~<br>~~es~~<br>~~es~~<br>~~es~~<br>|-REG<br>~~ot Et~~<br>~~sts~~<br>~~rs~~<br>~~ers~~<br>|I<br>~~Et~~<br>~~sts~~<br>~~tts~~<br>~~rs~~<br>|I3U<br>~~Et ce~~<br>~~ns~~<br>~~ns~~<br>~~ns~~|-DMACK(6)<br>~~ce~~<br>~~(OO~~<br>~~(OO~~<br>~~I~~|I<br>~~(OO~~<br>~~(OO~~<br>~~(OD~~|I3U|
|45<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|BVD2<br>~~er~~<br> ~~er~~<br>~~rr~~<br>~~ee~~|I/O<br>~~er es~~<br>~~er es~~<br>~~rr es~~<br>~~es~~|I1U,OT1<br>~~es ~~<br>~~es~~<br>~~es~~<br>~~es~~|-SPKR<br> ~~sts~~<br>~~rs~~<br>~~ers~~<br>~~rs~~|I/O<br>~~sts~~<br>~~tts~~<br>~~rs~~<br>~~rs~~|I1U,OT1<br>~~ns~~<br>~~ns~~<br>~~ns~~|-DASP<br>~~(OO~~<br>~~(OO~~<br>~~I~~<br>~~ss~~|I/O<br>~~(OO~~<br>~~(OO~~<br>~~(OD~~<br>~~ss~~|I1U,ON1|
|46<br> <br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|BVD1<br> ~~er~~<br>~~rr~~<br>~~ee~~<br>~~er~~<br>|I/O<br>~~er es~~<br>~~rr es~~<br>~~es~~<br>~~er es~~<br>|I1U,OT1<br>~~es ~~<br>~~es~~<br>~~es~~<br>~~es~~<br>|-STSCHG<br> ~~rs ~~<br>~~ers~~<br>~~rs~~<br>~~sts~~<br>|I/O<br> ~~tts ~~<br>~~rs~~<br>~~rs~~<br>~~sts~~<br>|I1U,OT1<br> ~~ns~~<br>~~ns~~<br>~~ns~~<br>|-PDIAG<br>~~(OO~~<br>~~I~~<br>~~ss~~<br>~~(OO~~|I/O<br>~~(OO~~<br>~~(OD~~<br>~~ss~~<br>~~(OO~~|I1U,ON1|
|47<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|D8(1)<br>~~rr~~<br> ~~ee~~<br>~~er~~<br>~~er~~|I/O<br>~~rr es~~<br>~~es~~<br>~~er es~~<br>~~er es~~|I1Z,OZ3<br>~~es ~~<br>~~es~~<br>~~es~~<br>~~es~~|D8(1)<br> ~~ers ~~<br>~~rs~~<br>~~sts~~<br>~~rs~~|I/O<br> ~~rs ~~<br>~~rs~~<br>~~sts~~<br>~~tts~~|I1Z,OZ3<br> ~~ns ~~<br>~~ns~~<br>~~ns~~|D8(1)<br> ~~I ~~<br>~~ss~~<br>~~(OO~~<br>~~(OO~~|I/O<br> ~~(OD~~<br>~~ss~~<br>~~(OO~~<br>~~(OO~~|I1Z,OZ3|
|48<br> <br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|D9(1)<br> ~~ee ~~<br>~~er~~<br>~~er~~<br>~~rr~~|I/O<br> ~~es ~~<br>~~er es~~<br>~~er es~~<br>~~rr e~~|I1Z,OZ3<br> ~~es ~~<br>~~es~~<br>~~es~~<br>~~e~~~~**s**~~|D9(1)<br> ~~rs ~~<br>~~sts~~<br>~~rs~~<br>~~ers~~|I/O<br> ~~rs~~<br>~~sts~~<br>~~tts~~<br>~~rs~~|I1Z,OZ3<br>~~ns~~<br>~~ns~~<br>~~ns~~|D9(1)<br>~~ss~~<br>~~(OO~~<br>~~(OO~~<br>~~I~~|I/O<br>~~ss~~<br>~~(OO~~<br>~~(OO~~<br>~~(OD~~|I1Z,OZ3|
|49<br>~~ee ~~<br>~~ee~~<br>~~ee~~|D10(1)<br>~~er~~<br> ~~er~~<br>~~rr~~<br>~~es~~|I/O<br>~~er es~~<br>~~er es~~<br>~~rr e~~<br>~~es n~~|I1Z,OZ3<br>~~es ~~<br>~~es~~<br>~~e~~~~**s**~~<br>~~n~~|D10(1)<br> ~~sts~~<br>~~rs~~<br>~~ers~~<br>~~rs~~|I/O<br>~~sts~~<br>~~tts~~<br>~~rs~~<br>~~nd~~|I1Z,OZ3<br>~~ns~~<br>~~ns~~<br>~~ns~~<br>~~nn~~|D10(1)<br>~~(OO~~<br>~~(OO~~<br>~~I~~|I/O<br>~~(OO~~<br>~~(OO~~<br>~~(OD~~|I1Z,OZ3|
|50<br> <br>~~ee~~<br>~~ee~~|GND<br> ~~er~~<br>~~rr~~<br>~~es~~|~~er es~~<br>~~rr e~~<br>~~es n~~|Ground<br>~~es ~~<br>~~e~~~~**s**~~<br>~~n~~|GND<br> ~~rs ~~<br>~~ers~~<br>~~rs~~|~~tts ~~<br>~~rs~~<br>~~nd~~|Ground<br> ~~ns~~<br>~~ns~~<br>~~nn~~|GND<br>~~(OO~~<br>~~I~~|~~(OO~~<br>~~(OD~~|Ground|
2. The signal should be grounded by the host.
3. The signal should be tied to VCC by the host.
4. The mode is required for CompactFlash[TM] Storage Cards.
5. The –CSEL signal is ignored by the card in PC Card modes. However, because it is not pulled up on the card in these modes, it should not be left floating by the host in PC Card modes. In these modes, the pin should be connected by the host to PC Card A25 or grounded by the host.
6. If DMA operations are not used, the signal must be held high or tied to VCC by the host, also for read registers.
7. Signal usage in True IDE Mode except when Ultra DMA mode protocol is active.
8. Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Write is active.
9. Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Read is active. The signal should be grounded by the host.
10. In PC-Card mode, the IOIS16 signal does not work as fully specified. If a host uses this signal, this may result in 16 bit accesses being changed to two 8 bit accesses. Depending on the address, this may result in an incompatibility with the host controller.
11. In PC-Card mode (memory and I/O), 16 bit ATA register file accesses (i.e. both -CE1 and -CE2 asserted) do not work as fully specified if A0 is high.
If you have host-card incompatibilities please contact Swissbit.
Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Switzerland
Swissbit reserves the right to change products or specifications without notice.
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C-440_data_sheet_CF-HxBU_Rev123.doc Page 13 of 106
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Table 13: Signal Description
|Signal Name|Dir.|Pin|Description|
|---|---|---|---|
|A10 to A0<br>(PC Card Memory Mode)|I|8,10,11,12,<br>14,15,16,17,<br>18,19,20|14,15,16,17,<br>These address lines along with the –REG signal are used to select the following:<br>The I/O port address registers within the CompactFlashTMStorage Card, the<br>memory mapped port address registers within the CompactFlashTMStorage Card,<br>a byte in the card’s information structure and its configuration control and<br>status registers.<br>In PC-Card mode, 16 bit ATA register file accesses (i.e. both -CE1 and -CE2 low)<br>do not work if A0 is high. A simple test will show the C-400 compatibility to a<br>certain host. If the C-400 cards can be recognized (Identify Device and MBR<br>data is read out successfully), then this PC card issue will likely not affect the<br>operation in this host. (1)|
|A10 to A0<br>(PC Card I/O Mode)|||This signal is the same as the PC Card Memory Mode signal.|
|A2 to A0<br>(True IDE Mode)<br>~~|~~|||In True IDE Mode, only A[2:0] are used to select the one of eight registers in the<br>Task File, the remaining address lines should be grounded by the host.|
|BVD1<br>(PC Card Memory Mode)<br>~~|~~|I/O<br>~~i~~<br>~~|~~|46<br>~~i~~<br>~~|~~|This signal is asserted high, as BVD1 is not supported.<br>~~i~~|
|–STSCHG<br>(PC Card I/O Mode)<br>~~|~~|||This signal is asserted low to alert the host to changes in the READY and Write<br>Protect states, while the I/O interface is configured. Its use is controlled by the<br>Card Config and Status Register.<br>~~i~~|
|–PDIAG<br>(True IDE Mode)<br><br>~~|~~|||In the True IDE Mode, this input / output is the Pass Diagnostic signal in the<br>Master / Slave handshake protocol.<br>~~i~~|
|BVD2<br>(PC Card Memory Mode)<br>~~—~~<br>~~**|**~~|I/O<br>~~—|~~<br>~~—S_~~|45<br>~~—|~~<br>~~|~~|This signal is asserted high, as BVD2 is not supported.<br>~~———~~|
|–SPKR<br>(PC Card I/O Mode)<br><br>~~**|**~~|||This line is the Binary Audio output from the card. If the Card does not support<br>the Binary Audio function, this line should be held negated.<br>~~———~~|
|–DASP<br>(True IDE Mode)<br><br>~~**|**~~<br>~~—S_~~|||In the True IDE Mode, this input/output is the Disk Active/Slave Present signal in<br>the Master/Slave handshake protocol.<br>~~———~~|
|D15-D0 (PC Card Memory<br>Mode)<br>~~—S_~~|I/O<br>~~—S_~~|31, 30, 29,<br>28, 27, 49,<br>48, 47, 6,<br>5, 4, 3, 2,<br>23, 22, 21<br>~~|~~|28, 27, 49,<br>These lines carry the Data, Commands and Status information between the host<br>and the controller. D0 is the LSB of the Even Byte of the Word. D8 is the LSB of<br>the Odd Byte of the Word.|
|D15-D0 (PC Card I/O Mode)<br>~~—S_~~|||This signal is the same as the PC Card Memory Mode signal.|
|D15-D0 (True IDE Mode)<br>~~—S_~~<br>~~|~~|||In True IDE Mode, all Task File operations occur in byte mode on the low order<br>bus D[7:0] while all data transfers are 16 bit using D[15:0].|
|GND<br>(PC Card Memory Mode)<br>~~—S_~~<br>~~|~~|~~—S_ ~~|1, 50<br> ~~|~~|Ground.|
|GND<br>(PC Card I/O Mode)<br>~~|~~|||Same for all modes.|
|GND<br>(True IDE Mode)<br>~~|~~<br>~~|~~|||Same for all modes.|
|–INPACK<br>(PC Card Memory Mode)<br>~~|~~|O<br>||43<br>||This signal is not used in this mode.|
|–INPACK<br>(PC Card I/O Mode)|||The Input Acknowledge signal is asserted by the CompactFlashTMStorage Card<br>when the card is selected and responding to an I/O read cycle at the address<br>that is on the address bus. This signal is used by the host to control the enable<br>of any input data buffers between the CompactFlashTMStorage Card and the<br>CPU.|
|DMARQ<br>(True IDE Mode)|||This signal is a DMA Request that is used for DMA data transfers between host<br>and device. It shall be asserted by the device when it is ready to transfer data<br>to or from the host. For Multiword DMA transfers, the direction of data transfer<br>is controlled by –IORD and –IOWR. This signal is used in a handshake manner<br>with –DMACK, i.e., the device shall wait until the host asserts –DMACK before<br>negating DMARQ, and reasserting DMARQ if there is more data to transfer.<br>DMARQ shall not be driven when the device is not selected.<br>While a DMA operation is in progress, -CS0 and –CS1 shall be held negated and<br>the width of the transfers shall be 16 bits.<br>If there is no hardware support for DMA mode in the host, this output signal is<br>not used and should not be connected at the host. In this case, the BIOS must<br>report that DMA mode is not supported by the host so that device drivers will<br>not attempt DMA mode.<br>A host that does not support DMA mode and implements both PC card and<br>True-IDE modes of operation need not alter the PC card mode connections<br>while in True-IDE mode as long as this does not prevent proper operation in<br>any mode.|
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|~~a~~||||
|---|---|---|---|
|Signal Name<br>~~a~~|Dir.|Pin|Description|
|–IORD<br>(PC Card Memory Mode)<br>~~a~~<br>~~ee~~|I<br> <br> <br>~~|~~|34<br> <br> <br>~~|~~|This signal is not used in this mode.<br>~~ee~~|
|–IORD<br>(PC Card I/O Mode)<br>~~ee~~<br>~~ee~~|||This is an I/O Read strobe generated by the host. This signal gates I/O data onto<br>the bus from the CompactFlashTMStorage Card when the card is configured to<br>use the I/O interface.<br>~~ee~~<br>~~a~~|
|–IORD<br>(True IDE Mode)<br>~~ee ~~<br>~~ee~~|||In True IDE Mode, while Ultra DMA mode is not active, this signal has the same<br>function as in PC Card I/O Mode.<br> ~~ee~~<br>~~a~~|
|-HDMARDY<br>(True IDE Mode – In Ultra<br>DMA Protocol DMA Read)<br>~~ee ~~|||In True IDE Mode when Ultra DMA mode DMA Read is active, this signal is<br>asserted by the host to indicate that the host is read to receive Ultra DMA data-<br>in bursts. The host may negate-HDMARDY to pause an Ultra DMA transfer.<br> ~~a~~|
|HSTROBE<br>(True IDE Mode – In Ultra<br>DMA Protocol DMA<br>Write)|||In True IDE Mode when Ultra DMA mode DMA Write is active, this signal is the<br>data out strobe generated by the host. Both the rising and falling edge of<br>HSTROBE cause data to be latched by the device. The host may stop generating<br>HSTROBE edges to pause an Ultra DMA data-out burst.|
|–CD1,–CD2<br>(PC Card Memory Mode)<br>~~=~~<br>~~ee~~|O<br>~~|~~<br>~~|__~~<br>|26, 25<br>~~|~~<br>~~|__~~<br>|These Card Detect pins are connected to ground on the CompactFlashTMStorage<br>Card. They are used by the host to determine that the CompactFlashTMStorage<br>Card or is fully inserted into its socket.<br>~~|__~~<br>~~a~~|
|–CD1,–CD2<br>(PC Card I/O Mode)<br>~~=~~<br>~~ee~~|||This signal is the same for all modes.<br>~~|__~~<br>~~a~~|
|–CD1,–CD2<br>(True IDE Mode)<br>~~=~~<br>~~ee ~~|||This signal is the same for all modes.<br>~~|__~~<br> ~~a~~|
|–CE1,–CE2<br>(PC Card Memory Mode)<br>~~ty~~|I<br>~~ty~~<br>|7, 32<br>~~ty~~<br>|These input signals are used both to select the card and to indicate to the card<br>whether a byte or a word operation is being performed. –CE2 always accesses<br>the odd byte of the word.<br>-CE1 accesses the even byte or the Odd byte of the word depending on A0 and<br>–CE2. A multiplexing scheme based on A0, -CE1, -CE2 allows 8 bit hosts to<br>access all data on D0-D7. SeeTable 33,Table 40,Table 41,Table 42, and<br>Table 43.<br>~~ty~~|
|–CE1,–CE2<br>(PC Card I/O Mode)|||This signal is the same as the PC Card Memory Mode signal.|
|–CS0,–CS1<br>(True IDE Mode)<br>~~ee~~|||In the True IDE Mode, -CS0 is the chip select for the task file registers while –CS1<br>is used to select the Alternate Status Register and the Device Control Register.<br>While –DMACK is asserted, -CS0 and –CS1 shall be held negated and the width<br>of the transfers shall be 16 bits.<br>|
|–CSEL<br>(PC Card Memory Mode)<br>~~eeS|~~|I<br>~~S|~~|39<br>~~S|~~|This signal is not used for this mode, but should be connected by the host to PC<br>Card A25 or grounded by the host.<br>~~S|~~|
|–CSEL<br>(PC Card I/O Mode)<br>~~eeS|~~|||This signal is not used for this mode, but should be connected by the host to PC<br>Card A25 or grounded by the host.<br>~~S|~~|
|–CSEL<br>(True IDE Mode)<br>~~S|~~|||This internally pulled up signal is used to configure this device as a Master or a<br>Slave when configured in the True IDE Mode.<br>When this pin is grounded, this device is configured as a Master.<br>When the pin is open, this device is configured as a Slave.<br>~~S|~~|
|–IOWR<br>(PC Card Memory Mode)<br>~~ee a~~|I<br> <br>~~|~~<br>~~a~~<br>~~——~~|35<br> <br>~~|~~<br>~~a~~<br>~~———~~|This signal is not used in this mode.<br>~~a~~|
|–IOWR<br>(PC Card I/O Mode)<br>~~a ~~<br>~~ee a~~|||The I/O Write strobe pulse is used to clock I/O data on the Card Data bus into the<br>CompactFlashTMStorage Card controller registers when the CompactFlashTM<br>Storage Card is configured to use the I/O interface.<br>The clocking shall occur on the negative to positive edge of the signal (trailing<br>edge).<br> ~~ee~~<br>~~a~~|
|-IOWR<br>(True IDE Mode – Except<br>Ultra DMA Protocol<br>Active)<br>~~ee a~~|||In True IDE Mode, while Ultra DMA mode protocol is not active, this signal has<br>the same function as in PC Card I/O Mode.<br>When Ultra DMA mode protocol is supported, this signal must be negated<br>before entering Ultra DMA mode protocol.<br>~~a~~|
|STOP<br>(True IDE Mode – Ultra<br>DMA Protocol Active)<br>~~ee a~~<br>~~——~~|||In True IDE Mode, while Ultra DMA mode protocol is active, the assertion of this<br>signal causes the termination of the Ultra DMA burst.<br>~~a~~<br>~~———~~|
|–OE<br>(PC Card Memory Mode)<br>~~ee a~~<br>~~——~~<br>~~ee~~|I<br>~~|~~<br>~~a~~<br>~~——~~<br> <br>|9<br>~~|~~<br>~~a~~<br>~~———~~<br> <br>|This is an Output Enable strobe generated by the host interface.<br>It is used to read data from the CompactFlashTMStorage in Memory Mode and to<br>read the CIS and configuration registers.<br>~~a~~<br>~~———~~<br>~~a~~|
|–OE<br>(PC Card I/O Mode)<br>~~——~~<br>~~ee~~<br>~~ee~~|||In PC Card I/O Mode, this signal is used to read the CIS and configuration<br>registers.<br>~~———~~<br>~~a~~<br>~~a~~|
|–ATASEL<br>(True IDE Mode)<br>~~——~~<br>~~ee ~~<br>~~ee~~|||To enable True IDE Mode this input should be grounded by the host.<br>~~———~~<br> ~~a~~<br>~~a~~|
||||SWISSbIt”|
|---|---|---|---|
|Signal Name|Dir.|Pin|Description|
|READY<br>(PC Card Memory Mode)<br>~~ee~~|O<br>~~i~~<br>|37<br>~~il~~<br>|In Memory Mode, this signal is set high when the CompactFlashTMStorage Card<br>is ready to accept a new data transfer operation and is held low when the card<br>is busy.<br>At power up and at Reset, the READY signal is held low (busy) until the<br>CompactFlashTMStorage Card has completed its power up or reset function. No<br>access of any type should be made to the CompactFlashTMStorage Card during<br>this time.<br>Note, however, that when a card is powered up and used with RESET<br>continuously disconnected or asserted, the Reset function of the RESET pin is<br>disabled. Consequently, the continuous assertion of RESET from the application<br>of power shall not cause the READY signal to remain continuously in the busy<br>state.<br>|
|–IREQ<br>(PC Card I/O Mode)<br>~~ee~~|||I/O Operation – After the CompactFlashTMStorage Card has been configured for<br>I/O operation, this signal is used as -Interrupt Request. This line is strobed low<br>to generate a pulse mode interrupt or held low for a level mode interrupt.<br>|
|INTRQ<br>(True IDE Mode)<br>~~ee~~|||In True IDE Mode signal is the active high Interrupt Request to the host.<br>|
|–REG<br>(PC Card Memory Mode)<br>~~ee~~|I<br>~~i~~<br>~~|~~<br>~~_~~|44<br>~~il~~<br>~~|~~<br>~~_~~|This signal is used during Memory Cycles to distinguish between Common<br>Memory and Register (Attribute) Memory accesses. High for Common Memory,<br>Low for Attribute Memory.<br>~~|~~|
|–REG<br>(PC Card I/O Mode)<br>|||The signal shall also be active (low) during I/O Cycles when the<br>I/O address is on the Bus.<br>~~|~~|
|–DMACK<br>(True IDE Mode)<br><br>~~_~~|||This is a DMA Acknowledge signal that is asserted by the host in response to<br>DMARQ to initiate DMA transfers.<br>The –DMACK signal must be high except during the execution of DMA<br>commands. (1)<br>If DMA operation is not supported by a True IDE Mode only host, this signal<br>should be driven high or connected to VCC by the host.<br>A host that does not support DMA mode and implements both<br>PC card and True-IDE modes of operation need not alter the<br>PC card mode connections while in True-IDE mode as long as this does not<br>prevent proper operation all modes.<br>~~|~~<br>|
|RESET<br>(PC Card Memory Mode)<br>|I<br>~~f~~<br><br>~~|~~|41<br>~~f~~<br><br>~~|~~|The CompactFlashTMStorage Card is Reset when the RESET pin is high with the<br>following important exception:<br>The host may leave the RESET pin open or keep it continually high from the<br>application of power without causing a continuous Reset of the card. Under<br>either of these conditions, the card shall emerge from power-up having<br>completed an initial Reset.<br>The CompactFlashTMCard is also Reset when the Soft Reset bit in the Card<br>Configuration Option Register is set.<br>~~f~~|
|RESET<br>(PC CardI/OMode)<br><br>~~ee~~|||This signal is the same as the PC Card Memory Mode signal.<br>~~f~~<br>~~|~~|
|–RESET<br>(True IDE Mode)<br><br>~~ee~~<br>~~—S~~|||In the True IDE Mode, this input pin is theactive lowhardware reset from the<br>host.<br>~~f~~<br>~~|~~<br>~~————~~|
|Vcc<br>(PC CardMemoryMode)<br>~~ee ~~<br>~~—S~~<br>~~ee~~|<br>~~|~~<br>|13, 38<br> <br>~~|~~<br>|+5V, +3.3V power.<br> ~~|~~<br>~~————~~|
|Vcc<br>(PC Card I/O Mode)<br>~~—S~~<br>~~ee~~<br>~~ee~~|||Same for all modes.<br>~~————~~|
|Vcc<br>(TrueIDE Mode)<br>~~—S~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|||Same for all modes.<br>~~————~~<br>~~a~~|
|–VS1,–VS2<br>(PC Card Memory Mode)<br>~~—S ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|O<br> ~~|~~<br> <br> <br>|33, 40<br>~~|~~<br> <br> <br>|Voltage Sense Signals. –VS1 is grounded on the Card and sensed by the Host so<br>that the CompactFlashTMStorage Card CIS can be read at 3.3 volts and –VS2 is<br>reserved by PCMCIA for a secondary voltage and is not connected on the Card.<br>~~————~~<br>~~a~~<br>~~a~~|
|–VS1,–VS2<br>(PC Card I/O Mode)<br>~~ee ~~<br>~~ee~~|||This signal is the same for all modes.<br> ~~a~~<br>~~a~~|
|–VS1,–VS2<br>(True IDE Mode)<br>~~ee ~~<br>~~|~~|||This signal is the same for all modes.<br> ~~a~~|
|–WAIT<br>(PC Card Memory Mode)<br><br>~~|~~|O<br>~~i~~<br> <br>~~ee~~|42<br>~~i~~<br> <br>|The –WAIT signal is driven low by the CompactFlashTMStorage<br>Card to signal the host to delay completion of a memory or I/O cycle that is in<br>progress.<br>~~|~~|
|–WAIT<br>(PC Card I/O Mode)<br><br>~~|~~<br>~~ee~~|||This signal is the same as the PC Card Memory Mode signal.<br>~~|~~<br>~~ee~~|
|IORDY<br>(True IDE Mode – Except<br>Ultra DMA Mode)<br><br>~~| ~~<br>~~ee~~|||In True IDE Mode, except in Ultra DMA modes, this output signal may be used as<br>IORDY.<br> ~~|~~<br>~~ee~~|
||||SWISSDIt™|
|---|---|---|---|
|Signal Name|Dir.|Pin|Description|
|-DDMARDY<br>(True IDE Mode – Ultra<br>DMA Write Mode)|||In True IDE Mode, when Ultra DMA mode DMA Write is active, this signal is<br>asserted by the host to indicate that the device is read to receive Ultra DMA<br>data-in bursts. The device may negate –DDMARDY to pause an Ultra DMA<br>transfer.|
|DSTROBE<br>(True IDE Mode – Ultra<br>DMA Read Mode)|||In True IDE Mode, when Ultra DMA mode DMA Write is active, this signal is the<br>data out strobe generated by the device. Both the rising and falling edge of<br>DSTROBE cause data to be latched by the host. The device may stop generating<br>DSTROBE edges to pause an Ultra DMA data-out burst.|
|–WE<br>(PC Card Memory Mode)|I|36|This is a signal driven by the host and used for strobing memory write data to<br>the registers of the CompactFlashTMStorage when the card is configured in the<br>memory interface mode. It is also used for writing the configuration registers.|
|–WE<br>(PC Card I/O Mode)|||In PC Card I/O Mode, this signal is used for writing the configuration registers.|
|–WE<br>(True IDE Mode)|||In True IDE Mode, this input signal is not used and should be connected to VCC<br>by the host.|
|WP<br>(PC Card Memory Mode)|O|24|Memory Mode – The CompactFlashTMStorage Card does not have a write protect<br>switch. This signal is held low after the completion of the reset initialization<br>sequence.|
|–IOIS16<br>(PC Card I/O Mode)|||I/O Operation – When the CompactFlashTMStorage Card is configured for I/O<br>Operation Pin 24 is used for the –I/O Selected is 16 Bit Port (-IOIS16) function. A<br>Low signal indicates that a 16 bit or odd byte only operation can be performed<br>at the addressed port.<br>In PC-Card mode, the IOIS16 signal does not work correctly. If a host uses this<br>signal, this may result in 16 bit accesses being changed to two 8 bit accesses.<br>Depending on the address, this may fail. A simple test will show the C-400<br>compatibility to a certain host. If the C-400 cards can be recognized (Identify<br>Device and MBR data is read out successfully), then this PC card issue will likely<br>not affect the operation in this host. (1)|
|–IOCS16<br>(TrueIDE Mode)|||In True IDE Mode this output signal is asserted low when this device is<br>expecting aword data transfercycle.|
- 1) If you have host-card incompatibilities please contact Swissbit.
## **5.2 Electrical Specification**
Table 14 defines the DC Characteristics for the CompactFlash[TM] Memory Card. Unless otherwise stated, conditions are:
- Vcc = 5V ± 10%
- Vcc = 3.3V ± 10%
- 0 °C to +85 °C
- The card interface is driven with 3.3V. The input pins are 5V tolerant.
The High-Speed IDE lines are terminated with serial resistors as specified in the ATA specification to improve the signal quality.
Table 14 shows that the Card operates correctly in both the voltage ranges and that the current requirements must not exceed the maximum limit shown.
The current is measured by connecting an amp meter in series with the Vcc supply. The meter should be set to the 2A scale range, and have a fast current probe with an RC filter with a time constant of 0.1ms. Current measurements are taken while looping on a data transfer command with a sector count of 128. Current consumption values for both read and write commands are not to exceed the Maximum Average RMS Current specified in Table 14.
Table 15 shows the Input Leakage Current, Table 16 the Input Characteristics, Table 17 the Output Drive Type and Table 18 the Output Drive Characteristics.
Table 14: Absolute Maximum Conditions
|Table 14: Absolute Maximum Conditions|Table 14: Absolute Maximum Conditions|Table 14: Absolute Maximum Conditions|Table 14: Absolute Maximum Conditions|Table 14: Absolute Maximum Conditions|||||||
|---|---|---|---|---|---|---|---|---|---|---|
|Parameter<br>Symbol<br>Input Power<br>VCC<br>Voltage on any pin except VCC with respect to GND<br>V<br>~~a~~|||||mbol|||Conditions<br>-0.3V to 6.5V<br>-0.5V to 6.5V|||
|Table 15: Input Leakage current (1)|||||||||||
|Type<br>Parameter|Symbol|Conditions|||Min.||Typ.|Max.||Units|
|IxZ<br>Input Leakage Current<br>(if notpulled upor down)|IL|VIH =Vcc<br>VIL =GND|||-10|||10||µA|
|IxU<br>Pull Up Resistor|RPU1|Vcc=5.0V|||50|||500||kOhm|
|IxD<br>Pull Down Resistor|RPD1|Vcc=5.0V|||50|||500||kOhm|
Swissbit reserves the right to change products or specifications without notice.
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industrial@swissbit.com
1. x refers to the characteristics described in Table 16 For example, I1U indicates a pull up resistor with a type 1 input characteristic.
Table 16: Input characteristics
|1.<br>x refers to the characteristics described in Table 16Table 16 For example, I1U indicates a pull up resistor with a type 1 input<br>characteristic.<br>Table 16: Input characteristics|1.<br>x refers to the characteristics described in Table 16Table 16 For example, I1U indicates a pull up resistor with a type 1 input<br>characteristic.<br>Table 16: Input characteristics|1.<br>x refers to the characteristics described in Table 16Table 16 For example, I1U indicates a pull up resistor with a type 1 input<br>characteristic.<br>Table 16: Input characteristics|1.<br>x refers to the characteristics described in Table 16Table 16 For example, I1U indicates a pull up resistor with a type 1 input<br>characteristic.<br>Table 16: Input characteristics|1.<br>x refers to the characteristics described in Table 16Table 16 For example, I1U indicates a pull up resistor with a type 1 input<br>characteristic.<br>Table 16: Input characteristics||
|---|---|---|---|---|---|
|Type<br>Parameter<br>Symbol<br>Min.<br>Typ.<br>Max.<br>Min.<br>Typ.<br>Max.<br>Units<br>Vcc=3.3V<br>Vcc=5.0V<br>~~PR Ht ee~~||||||
|1<br>Input Voltage CMOS<br>VIH<br>2.0<br>5.5<br>2.0<br>5.5<br>V<br>VIL<br>-0.3<br>0.8<br>-0.3<br>0.8<br>~~Ff EE~~||||||
|2<br>Input Voltage CMOS<br>VIH<br>2.0<br>5.5<br>2.0<br>5.5<br>VIL<br>-0.3<br>0.8<br>-0.3<br>0.8<br>3<br>Input Voltage CMOS Schmitt<br>Trigger<br>VTH<br>2.0<br>5.5<br>2.0<br>5.5<br>VTL<br>-0.3<br>0.8<br>-0.3<br>0.8<br>~~Pf~~<br>~~ee~~<br>~~cee~~<br>~~en ee~~|||V<br>V|||
|Table 17: Output Drive Type (1)||||||
|Type<br>Output Type|Valid Conditions|||||
|Otx<br>Totempole|IOH& IOL|||||
|Ozx<br>Tri-State N-P Channel|IOH& IOL|||||
|Opx<br>P-Channel Only|IOHonly|||||
|Onx<br>N-Channel Only|IOLonly|||||
|1.<br>x refers to the characteristics described inTable 16For example, OT3 refers to totem pole output with a type 3 output drive||For example, OT3 refers to totem pole output with a type 3 output drive||||
|characteristic.||||||
|Table 18: Output Drive Characteristics||||||
|Type<br>Parameter<br>Symbol<br>Conditions|Min.<br>Max.||Units|||
|1<br>Output Voltage<br>VOH<br>IOH= -1mA<br>2.4<br>V<br>VOL<br>IOL=4mA<br>0.45<br>2<br>Output Voltage<br>VOH<br>IOH= -1mA<br>2.4<br>V<br>VOL<br>IOL=4mA<br>0.45<br>3<br>Output Voltage<br>VOH<br>IOH= -1mA<br>2.4<br>V<br>VOL<br>IOL=4mA<br>0.45<br>Tri-State<br>IOZ<br>VOL=GND<br>-10<br>10<br>µA<br>X<br>Leakage Current<br>VOH =Vcc<br>**5.3 Additional requirements for CompactFlashTM Advanced Timing mode**<br>~~pfSC~~<br>~~Oe~~<br>~~$$~~<br>~~J~~<br>~~FJ~~||||||
|When operating in a CompactFlashTMAdvanced timing mode (PIO5, 6 or MDMA 3, 4), the following conditions must|Advanced timing mode (PIO5, 6 or MDMA 3, 4), the following conditions must|||||
|be respected:||||||
- Only one CompactFlash[TM] Card must be connected to the CompactFlash[TM] bus.
- The load capacitance (cable included) for all signals must be lower than 40pF.
- The cable length must be lower than 0.15m (6 inches). The cable length is measured from the Card connector to the host controller. 0.46m (18 inches) cables are not supported .
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## **6 Command Interface**
There are two types of bus cycles and timing sequences that occur in the PC card type interface, direct mapped I/O transfer and memory access. Two types of bus cycles are also available in True IDE interface type: PIO transfer and Multi-Word DMA transfer.
Table 19, Table 20, Table 21, Table 22, Table 23, Table 24, Table 25, and Table 26 show the read and write timing parameters. Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, and Figure 8 and Figure 9 show the read and write timing diagrams.
In order to set the card mode, the –OE (-ATASEL) signal must be set and kept stable before applying VCC until the reset phase is completed. To place the card in Memory mode or I/O mode, -OE (-ATASEL) must be driven High, while it must be driven Low to place the card in True IDE mode.
## **6.1 Attribute Memory Read and Write**
Figure 2: Attribute Memory Read waveforms
Table 19: Attribute Memory Read timing
|Table 19: Attribute Memory Read timing|Table 19: Attribute Memory Read timing|Table 19: Attribute Memory Read timing|||
|---|---|---|---|---|
|Speed version|||300ns||
|Item|Symbol|IEEEE Symbol|Min.(ns)|Max.(ns)|
|Read Cycle Time|tcI|tAVAV|250||
|Address Access Time|ta(A)|tAVQV||250|
|Card Enable Access Time|ta(CE)|tELQV||250|
|Output Enable Access Time|ta(OE)|tGLQV||125|
|Output Disable Time from CE|tdis(CE)|tEHQZ||100|
|Output Disable Time from OE|tdis(OE)|tGHQZ||100|
|Output Enable Time from CE|ten(CE)|tELQNZ|5||
|Output Enable Time from OE|ten(OE)|tGLQNZ|5||
|Data Valid from Address Change|tv(A)|tAXQX|0||
|Address Setup Time|tsu(A)|tAVWL|30||
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Figure 3: Configuration Register (Attribute Memory) Write waveforms
- 1 DIN signifies data provided by the system to the CompactFlash[TM] Card.
Table 20: Configuration Register (Attribute Memory) Write timing
|Speed Version|Speed Version|Speed Version|250ns|250ns|
|---|---|---|---|---|
|Item|Symbol|IEEEE Symbol|Min. (ns)|Max. (ns)|
|Write Cycle Time|tc(W)|tAVAV|250||
|Write Pulse Width|tw(WE)|tWLWH|150||
|Address Setup Time|tsu(A)|tAVWL|30||
|Data Setup Time for WE|tsu(D-WEH)|tDVWH|80||
|Data Hold Time|th(D)|tWMDX|30||
|Write Recovery Time|trec(WE)|tWMAX|30||
## **6.2 Common Memory Read and Write**
Figure 4: Common Memory Read waveforms
1 DOUT means data provided by the CompactFlash[TM] Memory Card to the system.
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Table 21: Common Memory Read timing (1)
|Table 21: Common Memory Read timing (1)|Table 21: Common Memory Read timing (1)|Table 21: Common Memory Read timing (1)|||||||||
|---|---|---|---|---|---|---|---|---|---|---|
|Cycle Time Mode<br>~~nD~~|||250ns<br>~~nD~~||120ns<br>~~nD~~||100ns<br>~~nD~~||80ns<br>~~nD~~||
|Item<br>~~nD~~|Symbol<br>~~nD~~|IEEEE<br>Symbol<br>~~nD~~|Min<br>(ns)<br>~~nD~~|Max<br>(ns)<br>~~nD~~|Min<br>(ns)<br>~~nD~~|Max<br>(ns)<br>~~nD~~|Min<br>(ns)<br>~~nD~~|Max<br>(ns)<br>~~nD~~|Min<br>(ns)<br>~~nD~~|Max<br>(ns)<br>~~nD~~|
|Output Enable Access Time<br>~~a~~|ta(OE)<br>~~eG~~|tGLQV<br>~~eG~~<br>~~GG~~|~~eG~~<br>~~GG~~|125<br>~~eG~~<br>~~GG~~|~~GO~~<br>~~GG~~|60<br>~~GO~~<br>~~GG~~|~~GO~~<br>~~GG~~|50<br>~~GG~~||45|
|Output Disable Time from OE<br>~~ss~~|tdis(OE)<br>~~ss~~|tGHQZ<br>~~ss~~<br>~~GG~~<br>~~GG~~|~~ss~~<br>~~GG~~<br>~~GG~~|100<br>~~ss~~<br>~~GG~~<br>~~GG~~|~~ss~~<br>~~GG~~|60<br>~~ss~~<br>~~GG~~|~~ss~~<br>~~GG~~|50<br>~~ss~~<br>~~GG~~|~~ss~~|45<br>~~ss~~|
|Address Setup Time<br>~~ss~~<br>~~ss~~<br>~~a~~|tsu(A)<br>~~ss~~<br>~~ss~~|tAVGL<br>~~ss~~<br>~~GG~~<br>~~ss~~<br>~~GG~~<br>~~DG~~|30<br>~~ss~~<br>~~GG~~<br>~~ss~~<br>~~GG~~<br>~~DG~~|~~ss~~<br>~~GG~~<br>~~ss~~<br>~~GG~~<br>~~DG~~|15<br>~~ss~~<br>~~GG~~<br>~~ss~~<br>~~GO~~|~~ss~~<br>~~GG~~<br>~~ss~~<br>~~GO~~|10<br>~~ss~~<br>~~GG~~<br>~~ss~~<br>~~GO~~|~~ss~~<br>~~GG~~<br>~~ss~~|10<br>~~ss~~<br>~~ss~~|~~ss~~<br>~~ss~~|
|Address Hold Time<br>~~ss~~<br>~~se~~<br>~~a~~|th(A)<br>~~ss~~<br>~~se~~<br>~~Gs~~|tGHAX<br>~~ss~~<br>~~GG~~<br>~~se~~<br>~~DG~~<br>~~Gs~~|20<br>~~ss~~<br>~~GG~~<br>~~se~~<br>~~DG~~<br>~~GsGD~~|~~ss~~<br>~~GG~~<br>~~se~~<br>~~DG~~<br>~~GD(OO~~|15<br>~~ss~~<br>~~se~~<br>~~GO~~<br>~~(OO~~|~~ss~~<br>~~se~~<br>~~GO~~<br>~~(OO~~|15<br>~~ss~~<br>~~se~~<br>~~GO~~<br>~~I~~|~~ss~~<br>~~se~~<br>~~I~~|10<br>~~ss~~<br>~~se~~<br>~~I~~|~~ss~~<br>~~se~~|
|CE Setup before OE<br>~~a~~|tsu(CE)<br>~~Gs~~|tELGL<br>~~DG~~<br>~~Gs~~|0<br>~~DG~~<br>~~GsGD~~|~~DG~~<br>~~GD(OO~~|0<br>~~GO~~<br>~~(OO~~|~~GO~~<br>~~(OO~~|0<br>~~GO~~<br>~~I~~|~~I~~|0<br>~~I~~||
|CE Hold following OE<br>~~po~~|th(CE)<br>~~Gs~~<br>~~po~~|tGHEH<br>~~Gs~~<br>~~po~~|20<br>~~GsGD~~<br>~~po~~|~~GD(OO~~<br>~~po~~|15<br>~~(OO~~<br>~~po~~|~~(OO~~<br>~~po~~|15<br>~~I~~<br>~~po~~|~~I~~<br>~~po~~|10<br>~~I~~<br>~~po~~|~~po~~|
Figure 5: Common Memory Write Waveforms
Table 22: Common Memory Write Timing(1)
|Table 22: Common Memory Write Timing(1)|Table 22: Common Memory Write Timing(1)|Table 22: Common Memory Write Timing(1)|||||||||
|---|---|---|---|---|---|---|---|---|---|---|
|Cycle Time Mode<br>~~GO~~|||250ns<br>~~GO~~||120ns<br>~~GO~~||100ns<br>~~GO~~||80ns<br>~~GO~~||
|Item|Symbol|IEEEE<br>Symbol|Min<br>(ns)|Max<br>(ns)|Min<br>(ns)|Max<br>(ns)|Min<br>(ns)|Max<br>(ns)|Min<br>(ns)|Max<br>(ns)|
|Data Setup before WE<br>~~as~~|tsu(D-WEH)<br>~~se~~|tDVWH<br>~~se~~|80<br>~~se~~|~~QO~~|50<br>~~QO~~|~~OO~~<br>~~GO~~|40<br>~~OO~~<br>~~GO~~|~~OO~~<br>~~GO~~|30||
|Data Hold following WE<br>~~as~~<br>~~GG~~|th(D)<br>~~se~~<br>~~GG~~|tIWMDX<br>~~se~~<br>~~GG~~<br>~~fs~~|30<br>~~se~~<br>~~GG~~<br>~~fs~~|~~QO~~<br>~~GG~~<br>~~fs~~|15<br>~~QO~~<br>~~GG~~<br>~~fsGO~~|~~OO~~<br>~~GG~~<br>~~GO~~<br>~~GO~~|10<br>~~OO~~<br>~~GG~~<br>~~GO~~<br>~~GO~~|~~OO~~<br>~~GG~~<br>~~GO~~|10<br>~~GG~~|~~GG~~|
|WE Pulse Width<br>~~GG~~<br>~~ee~~|tw(WE)<br>~~GG~~<br>~~ee~~|tWLWH<br>~~GG~~<br>~~ee~~<br>~~fs~~|150<br>~~GG~~<br>~~ee~~<br>~~fs~~|~~GG~~<br>~~ee~~<br>~~fs~~|70<br>~~GG~~<br>~~ee~~<br>~~fsGO~~<br>~~G~~|~~GG~~<br>~~GO~~<br>~~ee~~<br>~~GO~~<br>~~(~~|60<br>~~GG~~<br>~~GO~~<br>~~ee~~<br>~~GO~~<br>~~(~~|~~GG~~<br>~~GO~~<br>~~ee~~|55<br>~~GG~~<br>~~ee~~|~~GG~~<br>~~ee~~|
|Address Setup Time<br>~~OO~~<br>~~se~~|tsu(A)<br>~~OO~~<br>~~se~~|tAVWL<br>~~fs~~<br>~~OO~~<br>~~se~~|30<br>~~fs~~<br>~~OO~~|~~fs~~<br>~~OO~~|15<br>~~fsGO~~<br>~~OO~~<br>~~G~~|~~GO~~<br>~~OO~~<br>~~(~~<br>~~GO~~|10<br>~~GO~~<br>~~OO~~<br>~~(~~<br>~~GO~~|~~OO~~<br>~~GO~~|10<br>~~OO~~|~~OO~~|
|CE Setup before WE<br>~~GG~~<br>~~se~~|tsu(CE)<br>~~GG~~<br>~~se~~|tELWL<br>~~GG~~<br>~~se~~|0<br>~~GG~~|~~GG~~|0<br>~~G~~<br>~~GG~~|~~(~~<br>~~GG~~<br>~~GO~~|0<br>~~(~~<br>~~GG~~<br>~~GO~~|~~GG~~<br>~~GO~~|0<br>~~GG~~|~~GG~~|
|Write Recovery Time<br>~~GG~~<br>~~se~~|trec(WE)<br>~~GG~~<br>~~se~~|tWMAX<br>~~GG~~<br>~~se~~<br>~~fs~~|30<br>~~GG~~<br>~~QQ~~<br>~~fs~~|~~GG~~<br>~~QQ~~<br>~~fs~~|15<br>~~GG~~<br>~~QQ~~<br>~~fsGO~~|~~GG~~<br>~~GO~~<br>~~QQ~~<br>~~GO~~|15<br>~~GG~~<br>~~GO~~<br>~~QQ~~<br>~~GO~~|~~GG~~<br>~~GO~~|15<br>~~GG~~|~~GG~~|
|Address Hold Time<br>~~se~~<br>~~ee~~|th(A)<br>~~se~~<br>~~ee~~|tGHAX<br>~~se~~<br>~~ee~~<br>~~fs~~|20<br>~~QQ~~<br>~~ee~~<br>~~fs~~|~~QQ~~<br>~~ee~~<br>~~fs~~|15<br>~~QQ~~<br>~~ee~~<br>~~fsGO~~|~~GO~~<br>~~QQ~~<br>~~ee~~<br>~~GO~~|15<br>~~GO~~<br>~~QQ~~<br>~~ee~~<br>~~GO~~<br>~~DO~~|~~GO~~<br>~~ee~~<br>~~DO~~|10<br>~~ee~~|~~ee~~|
|CE Hold following WE<br>~~PO~~|th(CE)<br>~~PO~~|tGHEH<br>~~fs~~<br>~~PO~~|20<br>~~fs~~<br>~~PO~~|~~fs~~<br>~~PO~~|15<br>~~fsGO~~<br>~~PO~~|~~GO~~<br>~~PO~~|15<br>~~GO~~<br>~~PO~~<br>~~DO~~|~~PO~~<br>~~DO~~|10<br>~~PO~~|~~PO~~|
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## **6.3 I/O Read and Write**
Figure 6: I/O Read waveforms
1 DOUT signifies data provided by the CompactFlash[TM] Memory Card or to the system.
## Table 23: I/O Read timing(1)
|Table 23: I/O Read timing(1)|Table 23: I/O Read timing(1)|Table 23: I/O Read timing(1)|||||||||
|---|---|---|---|---|---|---|---|---|---|---|
|Cycle Time Mode<br>~~DG~~|||250ns<br>~~DG~~||120ns<br>~~DG~~||100ns<br>~~DG~~||80ns<br>~~DG~~||
|Item<br>~~DG~~|Symbol<br>~~DG~~|IEEEE<br>Symbol<br>~~DG~~|Min<br>(ns)<br>~~DG~~|Max<br>(ns)<br>~~DG~~|Min<br>(ns)<br>~~DG~~<br>~~GG~~|Max<br>(ns)<br>~~DG~~<br>~~GG~~|Min<br>(ns)<br>~~DG~~<br>~~GG~~|Max<br>(ns)<br>~~DG~~<br>~~GG~~|Min<br>(ns)<br>~~DG~~|Max<br>(ns)<br>~~DG~~|
|Data Delay after IORD<br>~~GG~~|td(IORD)<br>~~GG~~|tIGLQV<br>~~GG~~|~~GG~~|100<br>~~GG~~|~~GG~~<br>~~GG~~|50<br>~~GG~~<br>~~GG~~|~~GG~~<br>~~GG~~|50<br>~~GG~~<br>~~GG~~|~~GG~~|45<br>~~GG~~|
|Data Hold following IORD<br>~~GG~~<br>~~pf~~|th(IORD)<br>~~GG~~<br>~~pf~~|tIGHQX<br>~~GG~~<br>~~pf~~|0<br>~~GG~~<br>~~pf~~|~~GG~~<br>~~pf~~|5<br>~~GG~~<br>~~GG~~<br>~~pf~~|~~GG~~<br>~~GG~~<br>~~pf~~|5<br>~~GG~~<br>~~GG~~<br>~~pf~~|~~GG~~<br>~~GG~~<br>~~pf~~|5<br>~~GG~~<br>~~pf~~|~~GG~~<br>~~pf~~|
|IORD Width Time<br>~~pf~~|tw(IORD)<br>~~pf~~|tIGLIGH<br>~~pf~~|165<br>~~pf~~|~~pf~~|70<br>~~pf~~|~~pf~~|65<br>~~pf~~|~~pf~~|55<br>~~pf~~|~~pf~~|
|Address Setup before IORD<br>~~GG~~|tsuA(IORD)<br>~~GG~~|tAVIGL<br>~~GG~~|70<br>~~GG~~|~~GG~~|25<br>~~GG~~|~~GG~~|25<br>~~GG~~|~~GG~~|15<br>~~GG~~|~~GG~~|
|Address Hold following IORD<br>~~GG~~<br>~~pe~~|thA(IORD)<br>~~GG~~<br>~~pe~~|tIGHAX<br>~~GG~~<br>~~pe~~|20<br>~~GG~~<br>~~pe~~|~~GG~~<br>~~pe~~|10<br>~~GG~~<br>~~pe~~|~~GG~~<br>~~pe~~|10<br>~~GG~~<br>~~pe~~|~~GG~~<br>~~pe~~|10<br>~~GG~~<br>~~pe~~|~~GG~~<br>~~pe~~|
|CE setup before IORD<br>~~pf~~|tsuCE(IORD)<br>~~pf~~|tELIGL<br>~~pf~~|5<br>~~pf~~|~~pf~~|5<br>~~pf~~|~~pf~~|5<br>~~pf~~|~~pf~~|5<br>~~pf~~|~~pf~~|
|CE Hold following IORD<br>~~GG~~|thCE(IORD)<br>~~GG~~|tIGHEH<br>~~GG~~|20<br>~~GG~~|~~GG~~<br>~~GOO~~|10<br>~~GG~~<br>~~GOO~~|~~GG~~<br>~~GOO~~|10<br>~~GG~~<br>~~GO~~|~~GG~~<br>~~GO~~|10<br>~~GG~~<br>~~GO~~|~~GG~~|
|REG setup before IORD<br>~~GG~~<br>~~CGO~~|tsuREG(IORD)<br>~~GG~~<br>~~CGO~~|tRGLIGL<br>~~GG~~<br>~~CGO~~|5<br>~~GG~~<br>~~CGO~~|~~GG~~<br>~~CGO~~<br>~~GOO~~|5<br>~~GG~~<br>~~CGO~~<br>~~GOO~~|~~GG~~<br>~~CGO~~<br>~~GOO~~|5<br>~~GG~~<br>~~CGO~~<br>~~GO~~|~~GG~~<br>~~CGO~~<br>~~GO~~|5<br>~~GG~~<br>~~CGO~~<br>~~GO~~|~~GG~~<br>~~CGO~~|
|REG Hold following IORD<br>~~CGO~~<br>~~pe~~|thREG(IORD)<br>~~CGO~~<br>~~pe~~|tIGHRGH<br>~~CGO~~<br>~~pe~~|0<br>~~CGO~~<br>~~pe~~|~~CGO~~<br>~~GOO~~<br>~~pe~~|0<br>~~CGO~~<br>~~GOO~~<br>~~pe~~|~~CGO~~<br>~~GOO~~<br>~~pe~~|0<br>~~CGO~~<br>~~GO~~<br>~~pe~~|~~CGO~~<br>~~GO~~<br>~~pe~~|0<br>~~CGO~~<br>~~GO~~<br>~~pe~~|~~CGO~~<br>~~pe~~|
|INPACK Delay Falling from<br>IORD|tdfINPACK(IORD)|tIGLIAL|0|45|0|NA(2)|0|NA(2)|0|NA(2)|
|NPACK Delay Rising from IORD<br>~~pe~~|tdrINPACK(IORD)<br>~~pe~~|tIGHIAH<br>~~pe~~|~~pe~~|45<br>~~pe~~|~~pe~~|NA(2)<br>~~pe~~|~~pe~~|NA(2)<br>~~pe~~|~~pe~~|NA(2)<br>~~pe~~|
|IOIS16 Delay Falling from<br>Address|tdfIOIS16(ADR)|tAVISL||35|||||||
|IOIS16 Delay Rising from<br>Address|tdrIOIS16(ADR)|tAVISH||35|||||||
1. This Swissbit CF card does not assert the WAIT signal.
2. –IOIS16 is not supported in this mode.
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Page 22 of 106
Figure 7: I/O Write waveforms
Table 24: I/O write timing
**==> picture [500 x 174] intentionally omitted <==**
**----- Start of picture text -----**<br>
GO Cycle Time Mode 250ns 120ns 100ns 80ns<br>Item Symbol IEEEE Min Max Min Max Min Max Min Max<br>Symbol (ns) (ns) (ns) (ns) (ns) (ns) (ns) (ns)<br>GG Data Setup before IOWR tsu(IOWR) tDVIWH 60 OO 20 20 15<br>dG Data Hold following IOWR th(IOWR) QQ tIWHDX 30 CQO 10 5 5<br>RG IOWR Width Time tw(IOWR) QQ tIWLIWH 165 QO 70 65 55<br>dG Address Setup before IOWR tsuA(IOWR) QQ tAVIWL 70 CQO 25 25 15<br>RG Address Hold following IOWR thA(IOWR) QQ tIWHAX 20 QO 20 10 10<br>dG CE setup before IOWR tsuCE(IOWR) QQ tELIWL 5 CQO 5 5 5<br>RG CE Hold following IOWR thCE(IOWR) QQ tIWHEH 20 GG 20 10 10<br>DG REG setup before IOWR tsuREG(IOWR) QQ tRGLIWL 5 QQ 5 5 5<br>RG REG Hold following IOWR thREG(IOWR) QQ tIWHRGH 0 GG 0 0 0<br>Rd IOIS16 Delay Falling from Addr. tdfIOIS16(ADR) GQ tAVISL 35 QO NA [(2)] GO NA [(2)] NA [(2)]<br>Pf IOIS16 Delay Rising from Addr. tdrIOIS16(ADR) tAVISH 35 NA [(2)] NA [(2)] NA [(2)]<br>1. DIN signifies data provided by the system to the CompactFlash [TM] Memory Card.<br>2. –IOIS16 and –INPACK are not supported in this mode.<br>**----- End of picture text -----**<br>
## **6.4 True IDE Mode**
The timing waveforms for True IDE mode and True IDE DMA mode of operation in this section are drawn using the conventions in the ATA-4 specification, which are different than the conventions used in the PCMCIA specification and earlier versions of this specification. Signals are shown with their asserted state as High regardless of whether the signal is actually negative or positive true. Consequently, the –IORD, the
-IOWR and the –IOCS16 signals are shown in the waveforms inverted from their electrical states on the bus.
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Figure 8: True IDE PIO mode Read/Write waveforms
1. The device addresses consists of –CS0, −CS1, and A2-A0. 2. The Data I/O consist of D15-D0 (16-bit) or D7-D0 (8 bit). 3. –IOCS16 is shown for PIO modes 0, 1 and 2. For other modes, this signal is ignored.
Table 25: True IDE PIO mode Read/Write timing (1)
|Parameter|Symbol|Mode 0<br>(ns)|1<br>(ns)|2<br>(ns)|3<br>(ns)|4<br>(ns)|5(5)<br>(ns)|6(5)<br>(ns)|
|---|---|---|---|---|---|---|---|---|
|Cycle time(min)<br>~~a~~|t0<br>(2)<br>~~GG~~|600<br>~~GG~~|383<br>~~GG~~|240|180<br>~~OO~~|120<br>~~OO~~|100|80|
|Address Valid to –IORD/-IOWR setup (min)<br>~~pf~~|t1<br>~~pf~~|70<br>~~pf~~|50<br>~~pf~~|30<br>~~pf~~|30<br>~~pf~~|25<br>~~pf~~|15<br>~~pf~~|10<br>~~pf~~|
|-IORD/-IOWR(min)<br>~~I~~|t2<br>(2)<br>~~I~~|165<br>~~I~~<br>~~GG~~|125<br>~~I~~<br>~~GG~~|100<br>~~I~~<br>~~QO~~|80<br>~~I~~<br>~~QO~~|70<br>~~I~~<br>~~QO~~|65<br>~~I~~|55<br>~~I~~|
|-IORD/-IOWR(min)Register(8 bit)<br>~~I~~<br>~~DG~~|t2<br>(2)<br>~~I~~<br>~~DG~~|290<br>~~I~~<br>~~DG~~<br>~~GG~~<br>~~GG~~|290<br>~~I~~<br>~~DG~~<br>~~GG~~<br>~~GG~~|290<br>~~I~~<br>~~DG~~<br>~~QO~~<br>~~OO~~|80<br>~~I~~<br>~~DG~~<br>~~QO~~|70<br>~~I~~<br>~~DG~~<br>~~QO~~|65<br>~~I~~<br>~~DG~~|55<br>~~I~~<br>~~DG~~|
|-IORD/-IOWR recoverytime(min)<br>~~DG~~<br>~~Ge~~|t2i<br>(2)<br>~~DG~~<br>~~Ge~~|-<br>~~DG~~<br>~~GG~~<br>~~Ge~~<br>~~GG~~|-<br>~~DG~~<br>~~GG ~~<br>~~Ge~~<br>~~GG~~|-<br>~~DG~~<br> ~~QO~~<br>~~Ge~~<br>~~OO~~|70<br>~~DG~~<br>~~QO~~<br>~~Ge~~|25<br>~~DG~~<br>~~QO~~<br>~~Ge~~|25<br>~~DG~~<br>~~Ge~~|20<br>~~DG~~<br>~~Ge~~|
|-IOWR data setup (min)<br>~~I~~|t3<br>~~I~~|60<br>~~GG~~<br>~~I~~<br>~~OO~~|45<br>~~GG~~<br>~~I~~<br>~~OO~~|30<br>~~OO~~<br>~~I~~<br>~~OO~~|30<br>~~I~~<br>~~OO~~|20<br>~~I~~<br>~~OO~~|20<br>~~I~~|15<br>~~I~~|
|-IOWR data hold(min)<br>~~I~~<br>~~DO~~|t4<br>~~I~~<br>~~DO~~|30<br>~~I~~<br>~~DO~~<br>~~OO~~<br>~~GG~~|20<br>~~I~~<br>~~DO~~<br>~~OO~~<br>~~GG~~|15<br>~~I~~<br>~~DO~~<br>~~OO~~<br>~~OO~~|10<br>~~I~~<br>~~DO~~<br>~~OO~~|10<br>~~I~~<br>~~DO~~<br>~~OO~~|5<br>~~I~~<br>~~DO~~|5<br>~~I~~<br>~~DO~~|
|-IORD data setup (min)<br>~~DO~~<br>~~Ge~~|t5<br>~~DO~~<br>~~Ge~~|50<br>~~DO~~<br>~~OO~~<br>~~Ge~~<br>~~GG~~|35<br>~~DO~~<br>~~OO~~<br>~~Ge~~<br>~~GG~~|20<br>~~DO~~<br>~~OO~~<br>~~Ge~~<br>~~OO~~|20<br>~~DO~~<br>~~OO~~<br>~~Ge~~|20<br>~~DO~~<br>~~OO~~<br>~~Ge~~|15<br>~~DO~~<br>~~Ge~~|10<br>~~DO~~<br>~~Ge~~|
|-IORD data hold(min)<br>~~pf~~|t6z<br>(3)<br>~~pf~~|5<br>~~GG~~<br>~~pf~~|5<br>~~GG~~<br>~~pf~~|5<br>~~OO~~<br>~~pf~~|5<br>~~pf~~|5<br>~~pf~~|5<br>~~pf~~|5<br>~~pf~~|
|-IORD data tri-state(max)<br>~~I~~|t7<br>(4)<br>~~I~~|30<br>~~I~~<br>~~GG~~|30<br>~~I~~<br>~~GG~~|30<br>~~I~~<br>~~OO~~|30<br>~~I~~|30<br>~~I~~|20<br>~~I~~|20<br>~~I~~|
|Address valid to –IOCS16 assertion(max)<br>~~I~~<br>~~Ge~~|t8<br>(4)<br>~~I~~<br>~~Ge~~|90<br>~~I~~<br>~~Ge~~<br>~~GG~~|50<br>~~I~~<br>~~Ge~~<br>~~GG~~|40<br>~~I~~<br>~~Ge~~<br>~~OO~~|NA<br>~~I~~<br>~~Ge~~|NA<br>~~I~~<br>~~Ge~~|NA<br>~~I~~<br>~~Ge~~|NA<br>~~I~~<br>~~Ge~~|
|Address valid to –IOCS16 released(max)<br>~~pf~~|t7<br>~~pf~~|60<br>~~GG~~<br>~~pf~~|45<br>~~GG~~<br>~~pf~~|30<br>~~OO~~<br>~~pf~~|NA<br>~~pf~~<br>~~OO~~|NA<br>~~pf~~<br>~~OO~~|NA<br>~~pf~~<br>~~OO~~|NA<br>~~pf~~|
|-IORD/-IOWR to address valid hold<br>~~GD~~|t9<br>~~GD~~|20<br>~~GD~~|15<br>~~GD~~|10<br>~~GD~~|10<br>~~GD~~<br>~~OO~~|10<br>~~GD~~<br>~~OO~~|10<br>~~GD~~<br>~~OO~~|10<br>~~GD~~|
3. This parameter specifies the time from the falling edge of –IORD to the moment when the CompactFlash[TM] Memory Card (tri-state). 4. t7 and t8 apply only to modes 0, 1 and 2. The –IOCS16 signal is not valid for other modes.
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Figure 9: True IDE Multi-Word DMA Mode Read/Write waveforms
**–DMARQ –DMACK**
- Table 26: True IDE Multi Word DMA Mode Read/Write timing
**==> picture [519 x 265] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||
|---|---|---|---|---|---|---|---|---|
|Parameter|Symbol|Mode 0|1|2|3|4|
|(ns)|(ns)|(ns)|(ns)|(ns)|
|a|Cycle time (min)|t0(1)|480|150|120|100|80|
|a|-IORD / -IOWR asserted width (min)|tD|(1)|215|80|70|65|55|
|a|-IORD data access (max)|tE|150|60|50|50|45|
|a|-IORD data hold (min)|tF|5|5|5|5|5|
|a|-IORD/-IOWR data setup|(min)|tG|100|30|20|15|10|
|a|-IOWR data hold (min)|tH|20|15|10|5|5|
|CG|DMACK to –IORD/-IOWR setup|(min)|tI|0|0|0|0|0|
|CG|-IORD / -IOWR to –DMACK hold (min)|tJ|20|5|5|5|5|
|CG|-IORD Low width (min)|tKR|(1)|50|50|25|25|20|
|CG|-IOWR Low width (min)|tKW|(1)|215|50|25|25|20|
|CG|-IORD to DMARQ delay|(max)|tLR|120|40|35|35|35|
|CG|-IOWR to DMARQ delay|(max)|tLW|40|40|35|35|35|
|CG|CS(1:0) valid to –IORD / -IOWR (min)|tM|50|30|25|10|5|
|CG|CS(1:0) hold (min)|tN|15|10|10|10|10|
|GG|-DMACK (max)|tZ|20|25|25|25|25|
|1.|t0|is the minimum total cycle time.|TD|is the minimum command active time.|TKR|and|tKW|are the minimum command recovery time|
|or command inactive time for input and output cycles, respectively. The actual cycle time is the sum of the actual command active|
|time and the actual command inactive time. The timing requirements of|t0, tD, tKR|, and|tKW|must be respected.|T0|is higher than|tD +|
|tKR|or|tD + tKW|, for input and output cycles respectively. This means the host can lengthen either tD or|tKR/tKW|, or both, to ensure|
|that t0 is equal to or higher than the value reported in the devices identify device data. A CompactFlash|[TM]|Storage Card|
|implementation shall support any legal host implementation.|
**----- End of picture text -----**<br>
## **6.5 Ultra DMA Mode**
## 6.5.1 Ultra DMA Overview
Ultra DMA is an optional data transfer protocol used with the READ DMA, and WRITE DMA, commands. When this protocol is enabled, the Ultra DMA protocol shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. When this protocol is used there are no changes to other elements of the ATA protocol (e.g., Command Block Register access). Ultra DMA operations can take place in any of the three basic interface modes: PC Card Memory mode, PC Card I/O mode, and True IDE (the original mode to support UDMA). The usage of signals in each of the modes is shown in Table 27.
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Table 27: Ultra DMA Signal Usage in Each Interface Mode
|UDMA Signal<br>~~ee~~|Type<br>~~ee~~|Pin # (Non UDMA<br>MEM MODE)<br>~~ee~~|PC CARD MEM<br>MODE UDMA<br>~~ee~~|PC CARD IO<br>MODE UDMA<br>~~ee~~|TRUE IDE MODE<br>UDMA<br>~~ee~~|
|---|---|---|---|---|---|
|DMARQ<br>~~ee~~|Output 43 (<br>~~ee~~|Output 43 (-INPACK)<br>~~ee~~|-DMARQ<br>~~ee~~|-DMARQ<br>~~ee~~|DMARQ<br>~~ee~~|
|DMACK<br>~~ee~~|Input<br>~~ee~~|44 (-REG)<br>~~ee~~|-DMACK<br>~~1~~<br>~~ee~~|DMACK<br>~~1~~<br>~~ee~~|-DMACK<br>~~1~~<br>~~ee~~|
|STOP|Input|35 (-IOWR)|STOP ~~1~~<br>~~1, 2~~|STOP ~~1~~<br>~~1, 2~~|STOP ~~1~~<br>~~1, 2~~|
|HDMARDYI<br>HSTROBE(W)|Input|34 (-IORD)|-HDMARDYI~~1, 2~~<br>HSTROBE(W)1, 3, 4<br>~~1, 3~~|-HDMARDYI~~1, 2~~<br>HSTROBE(W)1, 3, 4<br>~~1, 3~~|-HDMARDYI~~1, 2~~<br>HSTROBE(W)1, 3, 4<br>~~1, 3~~|
|DDMARDY(W)<br>DSTROBEI<br>~~i~~|Output <br>~~i~~|42 (-WAIT)<br>~~i~~|-DDMARDY(W)~~1, 3~~<br>DSTROBEI1. 2. 4<br>~~i~~|-DDMARDY(W)~~1, 3~~<br>DSTROBEI1. 2. 4<br>~~i~~|-DDMARDY(W)~~1, 3~~<br>DSTROBEI1. 2. 4<br>~~i~~|
|DATA<br>~~i~~|Bidir<br>~~i~~|(D[15:0])<br>~~i~~|D[15:0]<br>~~i~~|D[15:0]<br>~~i~~|D[15:0]<br>~~5~~<br>~~i~~|
|ADDRESS<br>~~i~~|Input<br>~~i~~|(A[10:0])<br>~~i~~|A[10:0]<br>~~i~~|A[10:0]<br>~~i~~|A[02:0] ~~5~~<br>~~i~~|
|CSEL<br>~~a~~|Input<br>~~a~~|39 (-CSEL)<br>~~a~~|-CSEL<br>~~a~~|-CSEL<br>~~a~~|-CSEL<br>~~a~~|
|INTRQ<br>~~a~~|Output 37 (READY)<br>~~a~~|Output 37 (READY)<br>~~a~~|READY<br>~~a~~|-INTRQ<br>~~a~~|INTRQ<br>~~a~~|
|Card Select<br>~~a~~|Input<br>~~a~~|7 (-CE1)<br>31 (-CE2)<br>~~a~~|-CE1<br>-CE2<br>~~a~~|-CE1<br>-CE2<br>~~a~~|-CS0<br>-CS1<br>~~a~~|
3. The UDMA interpretation of this signal is valid only during an Ultra DMA data burst during a DMA Write command.
4. The HSTROBE and DSTROBE signals are active on both the rising and the falling edge.
5. Address lines 03 through 10 are not used in True IDE mode.
Several signal lines are redefined to provide different functions during an Ultra DMA burst. These lines assume these definitions when:
1. an Ultra DMA mode is selected, and
2. a host issues a READ DMA, or a WRITE DMA command requiring data transfer, and
3. the device asserts (-)DMARQ, and
4. the host asserts –DMACK.
These signal lines revert back to the definitions used for non-Ultra DMA transfers upon the negation of –DMACK by the host at the termination of an Ultra DMA burst.
With the Ultra DMA protocol, the STROBE signal that latches data from D[15:0] is generated by the same agent (either host or device) that drives the data onto the bus. Ownership of D[15:0] and this data strobe signal are given either to the device during an Ultra DMA data-in burst or to the host for an Ultra DMA data-out burst. During an Ultra DMA burst a sender shall always drive data onto the bus, and, after a sufficient time to allow for propagation delay, cable settling, and setup time, the sender shall generate a STROBE edge to latch the data. Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data.
Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA modes the device is capable of supporting. The Set transfer mode subcommand in the SET FEATURES command shall be used by a host to select the Ultra DMA mode at which the system operates. The Ultra DMA mode selected by a host shall be less than or equal to the fastest mode of which the device is capable. Only one Ultra DMA mode shall be selected at any given time. All timing requirements for a selected Ultra DMA mode shall be satisfied. Devices supporting any Ultra DMA mode shall also support all slower Ultra DMA modes.
An Ultra DMA capable device shall retain the previously selected Ultra DMA mode after executing a software reset sequence or the sequence caused by receipt of a DEVICE RESET command if a SET FEATURES disable reverting to defaults command has been issued. The device may revert to a Multiword DMA mode if a SET FEATURES enable reverting to default has been issued. An Ultra DMA capable device shall clear any previously selected Ultra DMA mode and revert to the default non-Ultra DMA modes after executing a power-on or hardware reset.
Both the host and device perform a CRC function during an Ultra DMA burst. At the end of an Ultra DMA burst the host sends its CRC data to the device. The device compares its CRC data to the data sent from the host. If the two values do not match, the device reports an error in the error register. If an error occurs during one or more Ultra DMA bursts for any one command, the device shall report the first error that occurred. If the device detects that a CRC error has occurred before data transfer for the command is complete, the device may complete the transfer and report the error or abort the command and report the error.
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NOTE – If a data transfer is terminated before completion, the assertion of INTRQ should be passed through to the host software driver regardless of whether all data requested by the command has been transferred.
## 6.5.2 Restrictions and Considerations during Ultra DMA Commands
There are number of important restrictions and considerations for the implementation and use of Ultra DMA commands in CompactFlash[TM] devices. These are highlighted in the subsections below. Additional restrictions on specific modes of operation are given in sections 5.3 and 6.5.3
## 6.5.2.1 System Restrictions for Ultra DMA modes 3 and above
Ultra DMA modes 3 and above are valid only for systems that meet the requirements of section 5.3
## 6.5.2.2 UDMA Address and Card Enable Signals
The Card Enable signals (-CE1 / -CS0 and –CE2 / -CS1) shall remain negated during Ultra DMA data bursts. The Address bus (A[10:0]) shall not transition unnecessarily during the UDMA command and shall remain fixed during an Ultra DMA data burst. In True IDE mode, the address lines (A[2:0]) shall be held to all zeros. This will reduce unnecessary noise during the UDMA command.
## 6.5.2.3 Task File registers shall not be written during an Ultra DMA command
The task file registers shall not be written after an Ultra DMA command is issued by the host and before the command completes. Writing to the device control register is permitted between bursts, but is expected to occur only to reset the card after an unrecoverable protocol error.
## 6.5.2.4 Ultra DMA transfers shall be 16 bits wide
All transfers during an Ultra DMA data burst are 16 bit wide transfers. The Set Features command that controls the bus width for PIO transfers does not affect the width of Ultra DMA transfers.
## 6.5.2.5 No Access to Memory or I/O Space during an Ultra DMA Data Burst
No access to common or attribute memory or to I/O space on the device is permitted during an Ultra DMA data burst.
## 6.5.3 Specific rules for PC Card Memory Mode Ultra DMA
In addition to the general restrictions for all Ultra DMA operations, these additional considerations exist for PC Card Memory Mode Ultra DMA operations.
## 6.5.3.1 No Access to Attribute Memory during PC Card Memory Mode DMA Commands
The host shall not attempt to access Attribute Memory space during a PC Card Memory Mode DMA command either before, between or within Ultra DMA data bursts.
## 6.5.3.2 READY signal handling during DMA commands in PC Card Memory Mode
In PC Card Memory Mode, the READY signal shall be negated (made BUSY) by the device upon receipt of a DMA command and shall remain negated until the command has completed at which time it shall be re-asserted. This treatment allows the host to receive a single interrupt at the end of the command and avoids the extra overhead that would be associated with processing busy to ready transitions for each sector transferred as is the case when the READY toggles at the end of every sector of PIO Memory Mode transfers.
The BSY bit in the status register is permitted to be negated in the status register at any time that the DRQ bit in the status register is asserted. The only restriction is that either DRQ or BSY or both must remain asserted while the command is in progress.
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## 6.5.4 Ultra DMA Phases of Operation
An Ultra DMA data transfer is accomplished through a series of Ultra DMA data-in or data-out bursts. Each Ultra DMA burst has three mandatory phases of operation: the initiation phase, the data transfer phase, and the Ultra DMA burst termination phase. In addition, an Ultra DMA burst may be paused during the data transfer phase (see: 6.5.4.4 , for the detailed protocol descriptions for each of these phases. Table 28: Ultra DMA Data Burst Timing Requirements and Table 29: Ultra DMA Data Burst Timing Descriptions define the specific timing requirements). In the following rules –DMARDY is used in cases that could apply to either –DDMARDY or –HDMARDY, and STROBE is used in cases that could apply to either DSTROBE or HSTROBE. The following are general Ultra DMA rules.
1. An Ultra DMA burst is defined as the period from an assertion of –DMACK by the host to the subsequent negation of –DMACK.
2. When operating in Ultra DMA modes 2, 1, or 0 a recipient shall be prepared to receive up to two data words whenever an Ultra DMA burst is paused. When operating in Ultra DMA modes 6, 5, 4, or 3 a recipient shall be prepared to receive up to three data words whenever an Ultra DMA burst is paused.
## 6.5.4.1 Ultra DMA Burst Initiation Phase Rules
1. An Ultra DMA burst initiation phase begins with the assertion of DMARQ by a device and ends when the sender generates a STROBE edge to transfer the first data word.
2. An Ultra DMA burst shall always be requested by a device asserting DMARQ.
3. When ready to initiate the requested Ultra DMA burst, the host shall respond by asserting –DMACK.
4. A host shall never assert –DMACK without first detecting that DMARQ is asserted.
5. For Ultra DMA data-in bursts: a device may begin driving D[15:00] after detecting that –DMACK is asserted, STOP negated, and –HDMARDY is asserted.
6. After asserting DMARQ or asserting –DDMARDY for an Ultra DMA data-out burst, a device shall not negate either signal until the first STROBE edge is generated.
7. After negating STOP or asserting –HDMARDY for an Ultra DMA data-in burst, a host shall not change the state of either signal until the first STROBE edge is generated.
## 6.5.4.2 Ultra DMA Data transfer phase rules
1. The data transfer phase is in effect from after Ultra DMA burst initiation until Ultra DMA burst termination.
2. A recipient pauses an Ultra DMA burst by negating –DMARDY and resumes an Ultra DMA burst by reasserting –DMARDY.
3. A sender pauses an Ultra DMA burst by not generating STROBE edges and resumes by generating STROBE edges.
4. A recipient shall not signal a termination request immediately when the sender stops generating STROBE edges. In the absence of a termination from the sender the recipient shall always negate –DMARDY and wait the required period before signaling a termination request.
5. A sender may generate STROBE edges at greater than the minimum period specified by the enabled Ultra DMA mode. The sender shall not generate STROBE edges at less than the minimum period specified by the enabled Ultra DMA mode. A recipient shall be able to receive data at the minimum period specified by the enabled Ultra DMA mode.
## 6.5.4.3 Ultra DMA Burst Termination Phase Rules
1. Either a sender or a recipient may terminate an Ultra DMA burst.
2. Ultra DMA burst termination is not the same as command completion. If an Ultra DMA burst termination occurs before command completion, the command shall be completed by initiation of a new Ultra DMA burst at some later time or aborted by the host issuing a hardware or software reset or DEVICE RESET command if implemented by the device.
3. An Ultra DMA burst shall be paused before a recipient requests a termination.
4. A host requests a termination by asserting STOP. A device acknowledges a termination request by negating DMARQ.
5. A device requests a termination by negating DMARQ. A host acknowledges a termination request by asserting STOP.
6. Once a sender requests a termination, the sender shall not change the state of STROBE until the recipient acknowledges the request. Then, if STROBE is not in the asserted state, the sender shall return STROBE to the asserted state. No data shall be transferred on this transition of STROBE.
7. A sender shall return STROBE to the asserted state whenever the sender detects a termination request from the recipient. No data shall be transferred nor CRC calculated on this edge of DSTROBE.
8. Once a recipient requests a termination, the responder shall not change DMARDY from the negated state for the remainder of an Ultra DMA burst.
9. A recipient shall ignore a STROBE edge when DMARQ is negated or STOP is asserted.
Swissbit reserves the right to change products or specifications without notice.
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## 6.5.4.4 Ultra DMA Data Transfers Timing
Table 28 and Table 29 define the timings associated with all phases of Ultra DMA bursts.
Table 28: Ultra DMA Data Burst Timing Requirements
|Name<br>~~p~~<br>~~{|~~|UDMA<br>Mode 0<br>(ns)<br>~~{||~~|UDMA<br>Mode 0<br>(ns)<br>~~{||~~|UDMA<br>Mode 1<br>(ns)<br>~~||~~|UDMA<br>Mode 1<br>(ns)<br>~~||~~|UDMA<br>Mode 2<br>(ns)<br>~~||~~|UDMA<br>Mode 2<br>(ns)<br>~~||~~|UDMA<br>Mode 3<br>(ns)<br>~~||~~|UDMA<br>Mode 3<br>(ns)<br>~~||~~|UDMA<br>Mode 4<br>(ns)<br>~~|ft~~|UDMA<br>Mode 4<br>(ns)<br>~~|ft~~|UDMA<br>Mode 5<br>(ns)<br>~~ft~~<br>~~ft~~|UDMA<br>Mode 5<br>(ns)<br>~~ft~~<br>~~ft~~|UDMA<br>Mode 6<br>(ns)<br>~~ft|~~|UDMA<br>Mode 6<br>(ns)<br>~~ft|~~|Measurement<br>location<br>(See Note 2)<br>~~|~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||Min Max Min Max Min Max Min Max Min Max Min Max Min Max<br>~~{|~~|Min Max Min Max Min Max Min Max Min Max Min Max Min Max<br>~~|~~|Min Max Min Max Min Max Min Max Min Max Min Max Min Max<br>~~|~~|Min Max Min Max Min Max Min Max Min Max Min Max Min Max<br>~~|~~|Min Max Min Max Min Max Min Max Min Max Min Max Min Max<br>~~|~~|Min Max Min Max Min Max Min Max Min Max Min Max Min Max<br>~~|~~|Min Max Min Max Min Max Min Max Min Max Min Max Min Max<br>~~|~~|Min Max Min Max Min Max Min Max Min Max Min Max Min Max<br>~~|~~|Min Max Min Max Min Max Min Max Min Max Min Max Min Max<br>~~|~~|Min Max Min Max Min Max Min Max Min Max Min Max Min Max<br>~~ft~~|Min Max Min Max Min Max Min Max Min Max Min Max Min Max<br>~~ft~~|Min Max Min Max Min Max Min Max Min Max Min Max Min Max<br>~~ft~~|Min Max Min Max Min Max Min Max Min Max Min Max Min Max<br>~~ft~~|Min Max Min Max Min Max Min Max Min Max Min Max Min Max<br>~~|~~|Min Max Min Max Min Max Min Max Min Max Min Max Min Max<br>~~|~~|
|t2CYCTYP<br>~~p~~<br>~~{|~~<br>~~ee~~<br>~~PEE~~|240<br>~~{| ~~<br>~~rs~~<br>~~PEE~~|~~|~~<br>~~ns~~<br>~~PEE~~|160<br>~~| ~~<br>~~ee~~|~~|~~<br>~~ns~~|120<br>~~| ~~<br>~~GO~~|~~|~~<br>~~GO~~|90<br>~~| ~~|~~|~~<br>~~GO~~|60<br>~~| ~~<br>~~GO~~|~~ft~~<br>~~OO~~|40<br>~~ft~~<br>~~GO~~|~~ft~~<br>~~GO~~|24<br>~~ft ~~<br>~~OO~~|~~|~~<br>~~GO~~|Sender<br>~~|~~|
|tCYC<br>~~ee~~<br>~~PEE~~<br>~~PEE~~|112<br>~~rs ~~<br>~~PEE~~<br>~~PEE~~|~~ns~~<br>~~PEE~~<br>~~PEE~~|73<br>~~ee~~|~~ns ~~|54<br> ~~GO~~|~~GO~~|39|~~GO~~|25<br>~~GO~~|~~OO~~|16.8<br>~~GO~~|~~GO~~|13<br>~~OO~~|~~GO~~|Note 3|
|t2CYC<br>~~PEE~~<br>~~PEE~~<br>~~PEE~~|230<br>~~PEE~~<br>~~PEE~~<br>~~PEE~~|~~PEE~~<br>~~PEE~~<br>~~PEE~~|153||115||86||57||38||29||Sender|
|tDS<br>~~PEE~~<br>~~PEE~~<br>~~PEE~~|15.0<br>~~PEE~~<br>~~PEE~~<br>~~PEE~~|~~PEE~~<br>~~PEE~~<br>~~PEE~~|10.0||7.0||7.0||5.0||4.0||2.6||Recipient|
|tDH<br>~~PEE~~<br>~~PEE~~<br>~~PEE~~|5.0<br>~~PEE~~<br>~~PEE~~<br>~~PEE~~|~~PEE~~<br>~~PEE~~<br>~~PEE~~|5.0||5.0||5.0||5.0||4.6||3.5||Recipient|
|tDVS<br>~~PEE~~<br>~~PEE~~<br>~~PEE~~|70.0<br>~~PEE~~<br>~~PEE~~<br>~~PEE~~|~~PEE~~<br>~~PEE~~<br>~~PEE~~|48.0||31.0||20.0||6.7||4.8||4.0||Sender|
|tDVH<br>~~PEE~~<br>~~PEE~~<br>~~PEE~~|6.2<br>~~PEE~~<br>~~PEE~~<br>~~PEE~~|~~PEE~~<br>~~PEE~~<br>~~PEE~~|6.2||6.2||6.2||6.2||4.8||4.0||Sender|
|tCS<br>~~PEE~~<br>~~PEE~~<br>~~es~~|15.0<br>~~PEE~~<br>~~PEE~~<br>~~es ns~~|~~PEE~~<br>~~PEE~~<br>~~ns~~|10.0<br>~~rs~~|~~nn~~|7.0<br>~~RU~~|~~(I~~|7.0<br>~~(I~~|~~(I~~|5.0<br>~~(RO~~|~~OO~~|5.0<br>~~ON~~|~~GO~~|5.0<br>~~OOS~~||Device|
|tCH<br>~~PEE~~<br>~~es~~<br>~~Re~~|5.0<br>~~PEE~~<br>~~es ns~~<br>~~ns~~|~~PEE~~<br>~~ns~~<br>~~ns~~|5.0<br>~~rs~~<br>~~ns~~|~~nn~~<br>~~Gnd~~|5.0<br>~~RU~~<br>~~rs~~|~~(I~~<br>~~(I~~|5.0<br>~~(I~~<br>~~ID~~|~~(I~~<br>~~(RRID~~|5.0<br>~~(RO~~<br>~~(OD~~|~~OO~~<br>~~(I~~|5.0<br>~~ON~~<br>~~OOD~~|~~GO~~<br>~~(OO~~|5.0<br>~~OOS~~<br>~~(OO~~|~~(OO~~|Device|
|tCVS<br>~~es~~<br>~~Re~~<br>~~ee~~|70.0<br>~~es ns~~<br>~~ns~~<br>~~ns~~|~~ns~~<br>~~ns~~<br>~~ns~~|48.0<br>~~rs ~~<br>~~ns~~<br>~~nsGs~~|~~nn ~~<br>~~Gnd~~<br>~~nsGs~~|31.0<br> ~~RU ~~<br>~~rs~~<br>~~Is~~|~~(I~~<br>~~(I~~<br>~~(I~~|20.0<br>~~(I~~<br>~~ID~~<br>~~UD~~|~~(I ~~<br>~~(RRID~~<br>~~(RD~~|6.7<br> ~~(RO~~<br>~~(OD~~<br>~~(OD~~|~~OO ~~<br>~~(I~~<br>~~(I~~|10.0<br> ~~ON ~~<br>~~OOD~~<br>~~OOO~~|~~GO~~<br>~~(OO~~<br>~~(I~~|10.0<br>~~OOS~~<br>~~(OO~~<br>~~(I~~|~~(OO~~<br>~~(OO~~|Host|
|tCVH<br>~~Re~~<br>~~ee~~<br>~~ee~~|6.2<br>~~ns~~<br>~~ns~~<br>~~ns~~|~~ns~~<br>~~ns~~<br>~~ns~~|6.2<br>~~ns ~~<br>~~nsGs~~<br>~~nsGs~~|~~Gnd~~<br>~~nsGs~~<br>~~nsGs~~|6.2<br>~~rs ~~<br>~~Is~~<br>~~Is~~|~~(I~~<br>~~(I~~<br>~~(I~~|6.2<br>~~ID ~~<br>~~UD~~<br>~~UD~~|~~(RRID ~~<br>~~(RD~~<br>~~(RD~~|6.2<br> ~~(OD~~<br>~~(OD~~<br>~~(OD~~|~~(I ~~<br>~~(I~~<br>~~(I~~|10.0<br> ~~OOD ~~<br>~~OOO~~<br>~~OOO~~|~~(OO~~<br>~~(I~~<br>~~(I~~|10.0<br>~~(OO~~<br>~~(I~~<br>~~(I~~|~~(OO~~<br>~~(OO~~<br>~~(OO~~|Host|
|tZFS<br>~~ee~~<br>~~ee~~<br>~~ee~~|0<br>~~ns~~<br>~~ns~~<br>~~ns~~|~~ns ~~<br>~~ns~~<br>~~ns~~|0<br> ~~nsGs~~<br>~~nsGs~~<br>~~nsGs~~|~~nsGs ~~<br>~~nsGs~~<br>~~nsGs~~|0<br> ~~Is ~~<br>~~Is~~<br>~~Is~~|~~(I ~~<br>~~(I~~<br>~~(I~~|0<br> ~~UD ~~<br>~~UD~~<br>~~UD~~|~~(RD ~~<br>~~(RD~~<br>~~(RD~~|0<br> ~~(OD~~<br>~~(OD~~<br>~~(OD~~|~~(I ~~<br>~~(I~~<br>~~(I~~|35<br> ~~OOO ~~<br>~~OOO~~<br>~~OOO~~|~~(I~~<br>~~(I~~<br>~~(I~~|25<br>~~(I ~~<br>~~(I~~<br>~~(I~~|~~(OO~~<br>~~(OO~~<br>~~(OO~~|Device|
|tDZFS<br>~~ee~~<br>~~ee~~<br>~~ee~~|70.0<br>~~ns~~<br>~~ns~~<br>~~ns~~|~~ns ~~<br>~~ns~~<br>~~ns~~|48.0<br> ~~nsGs~~<br>~~nsGs~~<br>~~nsGs~~|~~nsGs ~~<br>~~nsGs~~<br>~~nsGs~~|31.0<br> ~~Is ~~<br>~~Is~~<br>~~Is~~|~~(I ~~<br>~~(I~~<br>~~(I~~|20.0<br> ~~UD ~~<br>~~UD~~<br>~~UD~~|~~(RD ~~<br>~~(RD~~<br>~~(RD~~|6.7<br> ~~(OD~~<br>~~(OD~~<br>~~(OD~~|~~(I ~~<br>~~(I~~<br>~~(I~~|25.0<br> ~~OOO ~~<br>~~OOO~~<br>~~OOO~~|~~(I~~<br>~~(I~~<br>~~(I~~|17.5<br>~~(I ~~<br>~~(I~~<br>~~(I~~|~~(OO~~<br>~~(OO~~<br>~~(OO~~|Sender|
|tFS<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~ns~~<br>~~ns~~<br>~~ns~~|230<br>~~ns ~~<br>~~ns~~<br>~~ns~~|~~nsGs~~<br>~~nsGs~~<br>~~nsGs~~|200<br>~~nsGs ~~<br>~~nsGs~~<br>~~nsGs~~|~~Is ~~<br>~~Is~~<br>~~Is~~|170<br> ~~(I ~~<br>~~(I~~<br>~~(I~~|~~UD ~~<br>~~UD~~<br>~~UD~~|130<br> ~~(RD ~~<br>~~(RD~~<br>~~(RD~~|~~(OD~~<br>~~(OD~~<br>~~(OD~~|120<br>~~(I ~~<br>~~(I~~<br>~~(I~~|~~OOO ~~<br>~~OOO~~<br>~~OOO~~|90<br> ~~(I~~<br>~~(I~~<br>~~(I~~|~~(I ~~<br>~~(I~~<br>~~(I~~|80 Device<br> ~~(OO~~<br>~~(OO~~<br>~~(OO~~|80 Device|
|tLI<br>~~ee~~<br>~~ee~~<br>~~ee~~|0<br>~~ns~~<br>~~ns~~<br>~~ns~~|150<br>~~ns ~~<br>~~ns~~<br>~~ns~~|0<br> ~~nsGs~~<br>~~nsGs~~<br>~~nsGs~~|150<br>~~nsGs ~~<br>~~nsGs~~<br>~~nsGs~~|0<br> ~~Is ~~<br>~~Is~~<br>~~Is~~|150<br> ~~(I ~~<br>~~(I~~<br>~~(I~~|0<br> ~~UD ~~<br>~~UD~~<br>~~UD~~|100<br> ~~(RD ~~<br>~~(RD~~<br>~~(RD~~|0<br> ~~(OD~~<br>~~(OD~~<br>~~(OD~~|100<br>~~(I ~~<br>~~(I~~<br>~~(I~~|0<br> ~~OOO ~~<br>~~OOO~~<br>~~OOO~~|75<br> ~~(I~~<br>~~(I~~<br>~~(I~~|0<br>~~(I ~~<br>~~(I~~<br>~~(I~~|60 Note 4<br> ~~(OO~~<br>~~(OO~~<br>~~(OO~~|60 Note 4|
|tMLI<br>~~ee~~<br>~~ee~~<br>~~ee~~|20<br>~~ns~~<br>~~ns~~<br>~~ns~~|~~ns ~~<br>~~ns~~<br>~~ns~~|20<br> ~~nsGs~~<br>~~nsGs~~<br>~~nsGs~~|~~nsGs ~~<br>~~nsGs~~<br>~~nsGs~~|20<br> ~~Is ~~<br>~~Is~~<br>~~Is~~|~~(I ~~<br>~~(I~~<br>~~(I~~|20<br> ~~UD ~~<br>~~UD~~<br>~~UD~~|~~(RD ~~<br>~~(RD~~<br>~~(RD~~|20<br> ~~(OD~~<br>~~(OD~~<br>~~(OD~~|~~(I ~~<br>~~(I~~<br>~~(I~~|20<br> ~~OOO ~~<br>~~OOO~~<br>~~OOO~~|~~(I~~<br>~~(I~~<br>~~(I~~|20<br>~~(I ~~<br>~~(I~~<br>~~(I~~|~~(OO~~<br>~~(OO~~<br>~~(OO~~|Host|
|tUI<br>~~ee~~<br>~~ee~~<br>~~ee~~|0<br>~~ns~~<br>~~ns~~<br>~~ns~~|~~ns ~~<br>~~ns~~<br>~~ns~~|0<br> ~~nsGs~~<br>~~nsGs~~<br>~~nsGs~~|~~nsGs ~~<br>~~nsGs~~<br>~~nsGs~~|0<br> ~~Is ~~<br>~~Is~~<br>~~Is~~|~~(I ~~<br>~~(I~~<br>~~(I~~|0<br> ~~UD ~~<br>~~UD~~<br>~~UD~~|~~(RD ~~<br>~~(RD~~<br>~~(RD~~|0<br> ~~(OD~~<br>~~(OD~~<br>~~(OD~~|~~(I ~~<br>~~(I~~<br>~~(I~~|0<br> ~~OOO ~~<br>~~OOO~~<br>~~OOO~~|~~(I~~<br>~~(I~~<br>~~(I~~|0<br>~~(I ~~<br>~~(I~~<br>~~(I~~|~~(OO~~<br>~~(OO~~<br>~~(OO~~|Host|
|tAZ<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~ns~~<br>~~ns~~<br>~~ns~~|10<br>~~ns ~~<br>~~ns~~<br>~~ns~~|~~nsGs~~<br>~~nsGs~~<br>~~nsGs~~|10<br>~~nsGs ~~<br>~~nsGs~~<br>~~nsGs~~|~~Is ~~<br>~~Is~~<br>~~Is~~|10<br> ~~(I ~~<br>~~(I~~<br>~~(I~~|~~UD ~~<br>~~UD~~<br>~~UD~~|10<br> ~~(RD ~~<br>~~(RD~~<br>~~(RD~~|~~(OD~~<br>~~(OD~~<br>~~(OD~~|10<br>~~(I ~~<br>~~(I~~<br>~~(I~~|~~OOO ~~<br>~~OOO~~<br>~~OOO~~|10<br> ~~(I~~<br>~~(I~~<br>~~(I~~|~~(I ~~<br>~~(I~~<br>~~(I~~|10 Note 5<br> ~~(OO~~<br>~~(OO~~<br>~~(OO~~|10 Note 5|
|tZAH<br>~~ee~~<br>~~ee~~<br>~~ee~~|20<br>~~ns~~<br>~~ns~~<br>~~ns~~|~~ns ~~<br>~~ns~~<br>~~ns~~|20<br> ~~nsGs~~<br>~~nsGs~~<br>~~nsGs~~|~~nsGs ~~<br>~~nsGs~~<br>~~nsGs~~|20<br> ~~Is ~~<br>~~Is~~<br>~~Is~~|~~(I ~~<br>~~(I~~<br>~~(I~~|20<br> ~~UD ~~<br>~~UD~~<br>~~UD~~|~~(RD ~~<br>~~(RD~~<br>~~(RD~~|20<br> ~~(OD~~<br>~~(OD~~<br>~~(OD~~|~~(I ~~<br>~~(I~~<br>~~(I~~|20<br> ~~OOO ~~<br>~~OOO~~<br>~~OOO~~|~~(I~~<br>~~(I~~<br>~~(I~~|20<br>~~(I ~~<br>~~(I~~<br>~~(I~~|~~(OO~~<br>~~(OO~~<br>~~(OO~~|Host|
|tZAD<br>~~ee~~<br>~~ee~~<br>~~ee~~|0<br>~~ns~~<br>~~ns~~<br>~~ns~~|~~ns ~~<br>~~ns~~<br>~~ns~~|0<br> ~~nsGs~~<br>~~nsGs~~<br>~~nsGs~~|~~nsGs ~~<br>~~nsGs~~<br>~~nsGs~~|0<br> ~~Is ~~<br>~~Is~~<br>~~Is~~|~~(I ~~<br>~~(I~~<br>~~(I~~|0<br> ~~UD ~~<br>~~UD~~<br>~~UD~~|~~(RD ~~<br>~~(RD~~<br>~~(RD~~|0<br> ~~(OD~~<br>~~(OD~~<br>~~(OD~~|~~(I ~~<br>~~(I~~<br>~~(I~~|0<br> ~~OOO ~~<br>~~OOO~~<br>~~OOO~~|~~(I~~<br>~~(I~~<br>~~(I~~|0<br>~~(I ~~<br>~~(I~~<br>~~(I~~|~~(OO~~<br>~~(OO~~<br>~~(OO~~|Device|
|tENV<br>~~ee~~<br>~~ee~~<br>~~ee~~|20<br>~~ns~~<br>~~ns~~<br>~~ns~~|70<br>~~ns ~~<br>~~ns~~<br>~~ns~~|20<br> ~~nsGs~~<br>~~nsGs~~<br>~~nsGs~~|70<br>~~nsGs ~~<br>~~nsGs~~<br>~~nsGs~~|20<br> ~~Is ~~<br>~~Is~~<br>~~Is~~|70<br> ~~(I ~~<br>~~(I~~<br>~~(I~~|20<br> ~~UD ~~<br>~~UD~~<br>~~UD~~|55<br> ~~(RD ~~<br>~~(RD~~<br>~~(RD~~|20<br> ~~(OD~~<br>~~(OD~~<br>~~(OD~~|55<br>~~(I ~~<br>~~(I~~<br>~~(I~~|20<br> ~~OOO ~~<br>~~OOO~~<br>~~OOO~~|50<br> ~~(I~~<br>~~(I~~<br>~~(I~~|20<br>~~(I ~~<br>~~(I~~<br>~~(I~~|50 Host<br> ~~(OO~~<br>~~(OO~~<br>~~(OO~~|50 Host|
|tRFS<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~ns~~<br>~~ns~~<br>~~ns~~|75<br>~~ns ~~<br>~~ns~~<br>~~ns~~|~~nsGs~~<br>~~nsGs~~<br>~~nsGs~~|70<br>~~nsGs ~~<br>~~nsGs~~<br>~~nsGs~~|~~Is ~~<br>~~Is~~<br>~~Is~~|60<br> ~~(I ~~<br>~~(I~~<br>~~(I~~|~~UD ~~<br>~~UD~~<br>~~UD~~|60<br> ~~(RD ~~<br>~~(RD~~<br>~~(RD~~|~~(OD~~<br>~~(OD~~<br>~~(OD~~|60<br>~~(I ~~<br>~~(I~~<br>~~(I~~|~~OOO ~~<br>~~OOO~~<br>~~OOO~~|50<br> ~~(I~~<br>~~(I~~<br>~~(I~~|~~(I ~~<br>~~(I~~<br>~~(I~~|50 Sender<br> ~~(OO~~<br>~~(OO~~<br>~~(OO~~|50 Sender|
|tRP<br>~~ee~~<br>~~ee~~<br>~~ee~~|160<br>~~ns~~<br>~~ns~~<br>~~ns~~|~~ns ~~<br>~~ns~~<br>~~ns~~|125<br> ~~nsGs~~<br>~~nsGs~~<br>~~nsGs~~|~~nsGs ~~<br>~~nsGs~~<br>~~nsGs~~|100<br> ~~Is ~~<br>~~Is~~<br>~~Is~~|~~(I ~~<br>~~(I~~<br>~~(I~~|100<br> ~~UD ~~<br>~~UD~~<br>~~UD~~|~~(RD ~~<br>~~(RD~~<br>~~(RD~~|100<br> ~~(OD~~<br>~~(OD~~<br>~~(OD~~|~~(I ~~<br>~~(I~~<br>~~(I~~|85<br> ~~OOO ~~<br>~~OOO~~<br>~~OOO~~|~~(I~~<br>~~(I~~<br>~~(I~~|85<br>~~(I ~~<br>~~(I~~<br>~~(I~~|~~(OO~~<br>~~(OO~~<br>~~(OO~~|Recipient|
|tIORDYZ<br>~~ee~~<br>~~ee~~<br>~~ee~~|~~ns~~<br>~~ns~~<br>~~ns~~|20<br>~~ns ~~<br>~~ns~~<br>~~ns~~|~~nsGs~~<br>~~nsGs~~<br>~~nsGs~~|20<br>~~nsGs ~~<br>~~nsGs~~<br>~~nsGs~~|~~Is ~~<br>~~Is~~<br>~~Is~~|20<br> ~~(I ~~<br>~~(I~~<br>~~(I~~|~~UD ~~<br>~~UD~~<br>~~UD~~|20<br> ~~(RD ~~<br>~~(RD~~<br>~~(RD~~|~~(OD~~<br>~~(OD~~<br>~~(OD~~|20<br>~~(I ~~<br>~~(I~~<br>~~(I~~|~~OOO ~~<br>~~OOO~~<br>~~OOO~~|20<br> ~~(I~~<br>~~(I~~<br>~~(I~~|~~(I ~~<br>~~(I~~<br>~~(I~~|20 Device<br> ~~(OO~~<br>~~(OO~~<br>~~(OO~~|20 Device|
|tZIORDY<br>~~ee~~<br>~~ee~~|0<br>~~ns~~<br>~~ns~~|~~ns ~~<br>~~ns~~|0<br> ~~nsGs~~<br>~~nsGs~~|~~nsGs ~~<br>~~nsGs~~|0<br> ~~Is ~~<br>~~Is~~|~~(I ~~<br>~~(I~~|0<br> ~~UD ~~<br>~~UD~~|~~(RD ~~<br>~~(RD~~|0<br> ~~(OD~~<br>~~(OD~~|~~(I ~~<br>~~(I~~|0<br> ~~OOO ~~<br>~~OOO~~|~~(I~~<br>~~(I~~|0<br>~~(I ~~<br>~~(I~~|~~(OO~~<br>~~(OO~~|Device|
|tACK<br>~~ee~~<br>~~PoE~~|20<br>~~ns~~<br>~~PoE~~|~~ns ~~<br>~~PoE~~|20<br> ~~nsGs~~<br>~~PoE~~|~~nsGs ~~<br>~~PoE~~|20<br> ~~Is ~~<br>~~PoE~~|~~(I ~~<br>~~PoE~~|20<br> ~~UD ~~<br>~~PoE~~|~~(RD ~~<br>~~PoE~~|20<br> ~~(OD~~<br>~~PoE~~|~~(I ~~<br>~~PoE~~|20<br> ~~OOO ~~<br>~~PoE~~|~~(I~~<br>~~PoE~~|20<br>~~(I ~~<br>~~PoE~~|~~(OO~~<br>~~PoE~~|Host<br>~~PoE~~|
|tSS<br>~~PoE~~<br>~~PE~~|50<br>~~PoE~~<br>~~PE~~|~~PoE~~|50<br>~~PoE~~|~~PoE~~|50<br>~~PoE~~|~~PoE~~|50<br>~~PoE~~|~~PoE~~|50<br>~~PoE~~|~~PoE~~|50<br>~~PoE~~|~~PoE~~|50<br>~~PoE~~|~~PoE~~|Sender<br>~~PoE~~|
Notes:
1. All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V.
2. All signal transitions for a timing parameter shall be measured at the connector specified in the measurement location column. For example, in the case of tRFS, both STROBE and –DMARDY transitions are measured at the sender connector.
3. The parameter tCYC shall be measured at the recipient’s connector farthest from the sender.
4. The parameter tLI shall be measured at the connector of the sender or recipient that is responding to an incoming transition from the recipient or sender respectively. Both the incoming signal and the outgoing response shall be measured at the same connector.
5. The parameter tAZ shall be measured at the connector of the sender or recipient that is driving the bus but must release the bus the allow for a bus turnaround.
6. See the AC Timing requirements in Table 29: Ultra DMA Data Burst Timing Descriptions.
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## Table 29: Ultra DMA Data Burst Timing Descriptions
|Name Comment<br>~~a~~|Name Comment<br>~~a~~|Notes|
|---|---|---|
|t2CYCTYPT<br>~~a~~|Typicalsustained average two cycle time<br>~~a~~||
|tCYC<br>~~a~~|Cycle time allowingfor asymmetryand clock variations(from STROBE edge to STROBE edge)<br>~~a~~||
|t2CYC<br>~~ee~~|Two cycle time allowing for clock variations (from rising edge to next rising edge or from<br>falling edge tonextfalling edge ofSTROBE)<br>~~ee~~|~~ee~~|
|tDS<br>~~ee~~|Data setup time at recipient (from data valid until STROBE edge)<br>~~ee~~|2, 5<br>~~ee~~|
|tDH<br>~~ee~~|Data hold time at recipient (from STROBE edge until data may become invalid)<br>~~ee~~|2, 5<br>~~ee~~|
|tDVS|Data valid setup time at sender (from data valid until STROBE edge)|3|
|tDVH|Data valid hold time at sender (from STROBE edge until data may become invalid)|3|
|tCS|CRCword setup time at device|2|
|tCH|CRC word hold time device|2|
|tCVS|CRCwordvalid setup time athost (fromCRCvalid until –DMACK negation)|3|
|tCVH|CRC word valid hold time at sender (from–DMACK negation until CRC may become invalid)|3|
|tZFS|Time from STROBE output released-to-driving until the first transition of critical timing.||
|TDZFS<br>~~—~~|Time from data output released-to-driving until the first transition of critical timing.||
|TFS<br>~~—~~|First STROBE time (for device to first negate DSTROBE from STOP during a data in burst)||
|tLI<br>~~—~~|Limitedinterlocktime|1|
|tMLI<br>~~—~~|Interlock time with minimum|1|
|tUI<br>~~—~~<br>~~_____———————————————~~|Unlimited interlock time<br>~~_____———————————————~~|1|
|tAZ<br>~~_____———————————————~~|Maximum time allowed for output drivers to release (from asserted or negated)<br>~~_____———————————————~~||
|tZAH<br>~~_____———————————————~~|Minimum delay time required for output<br>~~_____———————————————~~||
|tZAD<br>~~_____———————————————~~|drivers to assert or negate (from released)<br>~~_____———————————————~~||
|tENV<br>~~_____———————————————~~<br>~~a~~|Envelope time (from –DMACK to STOP and –HDMARDY during data in burst initiation and<br>from DMACKto STOPduring data out burstinitiation)<br>~~_____———————————————~~<br>||
|tRFS<br>~~——~~|Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of<br>-DMARDY)<br>~~——~~|~~——~~|
|tRP<br>~~——~~|Ready-to-pause time (that recipient shall wait to pause after negating–DMARDY)<br>~~——~~|~~——~~|
|tIORDYZ<br>~~——~~|Maximumtime beforereleasingIORDY<br>~~——~~|~~——~~|
|tZIORDY<br>~~Pe~~|Minimum time before driving IORDY<br>~~Pe~~|4<br>~~Pe~~|
|tACK<br>~~Pe~~|Setup and hold times for–DMACK (before assertion or negation)<br>~~Pe~~|~~Pe~~|
|tSS<br>~~Pe~~|Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates<br>a burst)<br>~~Pe~~|~~Pe~~|
2. 80-conductor cabling shall be required in order to meet setup (tDS, tCS) and hold (tDH, tCH) times in modes greater than 2.
3. Timing for tDVS, tDVH, tCVS and tCVH shall be met for lumped capacitive loads of 15 and 40 pF at the connector where the Data and STROBE signals have the same capacitive load value. Due to reflections on the cable, these timing measurements are not valid in a normally functioning system.
4. For all modes the parameter tZIORDY may be greater than tENV due to the fact that the host has a pull-up on IORDY- giving it a known state when released.
5. The parameters tDS, and tDH for mode 5 are defined for a recipient at the end of the cable only in a configuration with a single device located at the end of the cable. This could result in the minimum values for tDS and tDH for mode 5 at the middle connector being 3.0 and 3.9 ns respectively.
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Table 30: Ultra DMA Sender and Recipient IC Timing Requirements
|Name Comments<br>~~pf~~|Name Comments<br>~~pf~~<br>~~EE~~|UDMA<br>Mode 0<br>(ns)<br>~~EE~~|UDMA<br>Mode 1<br>(ns)<br>~~EEET~~|UDMA<br>Mode 2<br>(ns)<br>~~ET~~|UDMA<br>Mode 3<br>(ns)<br>~~ET~~|UDMA<br>Mode4<br>(ns)|UDMA<br>Mode 5<br>(ns)|UDMA<br>Mode6<br>(ns)|
|---|---|---|---|---|---|---|---|---|
|||Min<br>~~EE~~|Min<br>~~EEET~~|Min<br>~~ET~~|Min<br>~~ET~~|Min|Min|Min|
|tDSIC<br>~~pf~~<br>~~Ppee~~|Recipient IC data setup time (from<br>data valid until STROBE edge)<br>(see note 2)<br>~~pf~~<br>~~EE~~<br>~~pee~~|14.7<br>~~EE~~|9.7<br>~~EE ET~~<br>~~eee~~|6.8<br>~~ET~~<br>~~eee~~|6.8<br>~~ET~~<br>~~eee~~|4.8<br>~~eee~~|2.3<br>~~eee~~|2.3<br>~~eee~~|
|tDHIC<br>~~Ppee~~|Recipient IC data hold time (from<br>STROBE edge until data may<br>become invalid) (see note 2)<br>~~pee~~|4.8|4.8<br>~~eee~~|4.8<br>~~eee~~|4.8<br>~~eee~~|4.8<br>~~eee~~|2.8<br>~~eee~~|2.8<br>~~eee~~|
|tDVSIC<br>~~ee~~<br>~~pp~~|Sender IC data valid setup time<br>(from data valid until STROBE<br>edge) (see note 3)<br>~~ee~~<br>~~pp~~|72.9<br>~~pp~~<br>~~ee~~|50.9<br>~~eee~~<br>~~pp~~<br>~~ee~~|33.9<br>~~eee~~<br>~~pp~~<br>~~ee~~|22.6<br>~~eee~~<br>~~pp~~<br>~~ee~~|9.5<br>~~eee~~<br>~~pp~~<br>~~ee~~|6.0<br>~~eee~~<br>~~pp~~<br>~~ee~~|5.2<br>~~eee~~<br>~~pp~~<br>~~ee~~|
|tDVHIC<br>~~ee~~|Sender IC data valid hold time<br>(from STROBE edge until data<br>may become invalid) (see note 3)<br>~~ee~~|9.0<br>~~ee~~<br>~~ee~~|9.0<br>~~ee~~<br>~~ee~~|9.0<br>~~ee~~<br>~~ee~~|9.0<br>~~ee~~<br>~~ee~~|9.0<br>~~ee~~<br>~~ee~~|6.0<br>~~ee~~<br>~~ee~~|5.2<br>~~ee~~<br>~~ee~~|
3. The parameters tDVSIC and tDVHIC shall be met for lumped capacitive loads of 15 and 40 pF at the IC where all signals have the same capacitive load value. Noise that may couple onto the output signals from external sources has not been included in these values.
Table 31: Ultra DMA AC Signal Requirements
|Table 31: Ultra DMA AC Signal Requirements|Table 31: Ultra DMA AC Signal Requirements||||
|---|---|---|---|---|
|Name|Comment|Min<br>[V/ns]|Max<br>[V/ns]|Notes|
|SRISE|Rising Edge Slew Rate for any signal||1.25|1|
|SFALL|Falling Edge Slew Rate for any signal||1.25|1|
1. The sender shall be tested while driving an 18 inch long, 80 conductor cable with PVC insulation material. The signal under test shall be cut at a test point so that it has not trace, cable or recipient loading after the test point. All other signals should remain connected through to the recipient. The test point may be located at any point between the sender’s series termination resistor and one half inch or less of conductor exiting the connector. If the test point is on a cable conductor rather than the PCB, an adjacent ground conductor shall also be cut within one half inch of the connector.
The test load and test points should then be soldered directly to the exposed source side connectors. The test loads consist of a 15 pF or a 40 pF, 5%, 0.08 inch by 0.05 inch surface mount or smaller size capacitor from the test point to ground. Slew rates shall be met for both capacitor values.
Measurements shall be taken at the test point using a <1 pF, >100 kOhm, 1 GHz or faster probe and a 500 MHz or faster oscilloscope. The average rate shall be measured from 20% to 80% of the settled VOH level with data transitions at least 120 ns apart. The settled VOH level shall be measured as the average output high level under the defined testing conditions from 100 nsec after 80% of a rising edge until 20% of the subsequent falling edge.
## 6.5.4.4.1 Initiating an Ultra DMA Data-In Burst
- a) An Ultra DMA Data-In burst is initiated by following the steps lettered below. The timing diagram is shown in Figure 10: Ultra DMA Data-In Burst Initiation Timing. The associated timing parameters are specified in Table 28: Ultra DMA Data Burst Timing Requirements and are described in Table 29: Ultra DMA Data Burst Timing Descriptions.
- b) The following steps shall occur in the order they are listed unless otherwise specifically allowed:
- c) The host shall keep –DMACK in the negated state before an Ultra DMA burst is initiated.
- d) The device shall assert DMARQ to initiate an Ultra DMA burst. After assertion of DMARQ the device shall not negate DMARQ until after the first negation of DSTROBE.
- e) Steps I, (d), and (e) may occur in any order or at the same time. The host shall assert STOP.
- f) The host shall negate –HDMARDY.
- g) The host shall negate –CS0, -CS1, A2, A1, and A0. The host shall keep –CS0, -CS1, A2, A1, and A0 negated until after negating –DMACK at the end of the burst.
- h) Steps I, (d), and (e) shall have occurred at least tACK before the host asserts –DMACK. The host shall keep – DMACK asserted until the end of an Ultra DMA burst.
- i) The host shall release D[15:0] within tAZ after asserting –DMACK.
- j) The device may assert DSTROBE tZIORDY after the host has asserted –DMACK. Once the device has driven DSTROBE the device shall not release DSTROBE until after the host has negated –DMACK at the end of an Ultra DMA burst.
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- k) The host shall negate STOP and assert –HDMARDY within tENV after asserting –DMACK. After negating STOP and asserting –HDMARDY, the host shall not change the state of either signal until after receiving the first transition of DSTROBE from the device (i.e., after the first data word has been received).
- l) The device shall drive D[15:00] no sooner than tZAD after the host has asserted –DMACK, negated STOP, and asserted –HDMARDY.
- m) The device shall drive the first word of the data transfer onto D[15:0]. This step may occur when the device first drives D[15:0] in step (j).
- n) To transfer the first word of data the device shall negate DSTROBE within tFS after the host has negated STOP and asserted –HDMARDY. The device shall negate DSTROBE no sooner than tDVS after driving the first word of data onto D[15:0].
Figure 10: Ultra DMA Data-In Burst Initiation Timing
Notes: The definitions for the IORDY:-DDMARDY:DSTROBE, -IORD: -HDMARDY:HSTROBE, and –IOWR:STOP signal lines are not in effect until DMARQ and –DMACK are asserted.
## 6.5.4.4.2 Sustaining an Ultra DMA Data-In Burst
An Ultra DMA Data-In burst is sustained by following the steps lettered below. The timing diagram is shown in Figure 11: Sustained Ultra DMA Data-In Burst Timing. The timing parameters are specified in Table 28: Ultra DMA Data Burst Timing Requirements and are described in Table 29: Ultra DMA Data Burst Timing Descriptions.
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The following steps shall occur in the order they are listed unless otherwise specifically allowed:
- a) The device shall drive a data word onto D[15:0].
- b) The device shall generate a DSTROBE edge to latch the new word no sooner than tDVS after changing the state of D[15:0]. The device shall generate a DSTROBE edge no more frequently than tCYC for the selected Ultra DMA mode. The device shall not generate two rising or two falling DSTROBE edges more frequently than 2tcyc for the selected Ultra DMA mode.
- c) The device shall not change the state of D[15:0] until at least tDVH after generating a DSTROBE edge to latch the data.
- d) The device shall repeat steps (a), (b), and (c) until the data transfer is complete or an Ultra DMA burst is paused, whichever occurs first.
Figure 11: Sustained Ultra DMA Data-In Burst Timing
Notes: D[15:0] and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device.
## 6.5.4.4.3 Host Pausing an Ultra DMA Data-In Burst
The host pauses a Data-In burst by following the steps lettered below. A timing diagram is shown in Figure 12: Ultra DMA Data-In Burst Host Pause Timing. The timing parameters are specified in Table 28: Ultra DMA Data Burst Timing Requirements and are described in Table 29: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
- a) The host shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred.
- b) The host shall pause an Ultra DMA burst by negating –HDMARDY.
- c) The device shall stop generating DSTROBE edges within tRFS of the host negating –HDMARDY.
- d) If the host negates –HDMARDY within tSR after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero or one additional data words. If the host negates –HDMARDY greater than tSR after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and tRFS timing for the device.
- e) The host shall resume an Ultra DMA burst by asserting –HDMARDY.
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Figure 12: Ultra DMA Data-In Burst Host Pause Timing
Notes:
1. The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after –HDMARDY is negated.
2. After negating –HDMARDY, the host may receive zero, one, two, or three more data words from the device.
## 6.5.4.4.4 Device Terminating an Ultra DMA Data-In Burst
The device terminates an Ultra DMA Data-In burst by following the steps lettered below. The timing diagram is shown in Figure 13: Ultra DMA Data-In Burst Device Termination Timing. The timing parameters are specified in Table 28: Ultra DMA Data Burst Timing Requirements and are described in Table 29: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
- a) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra
- b) The device shall pause an Ultra DMA burst by not generating DSTROBE edges.
- c) NOTE – The host shall not immediately assert STOP to initiate Ultra DMA burst termination when the device stops generating STROBE edges. If the device does not negate DMARQ, in order to initiate ULTRA DMA burst termination, the host shall negate
- d) The device shall resume an Ultra DMA burst by generating a DSTROBE edge.
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Figure 13: Ultra DMA Data-In Burst Device Termination Timing
Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.
## 6.5.4.4.5 Host Terminating an Ultra DMA Data-In Burst
The host terminates an Ultra DMA Data-In burst by following the steps lettered below. The timing diagram is shown in Figure 14: Ultra DMA Data-In Burst Host Termination Timing. The timing parameters are specified in Table 28: Ultra DMA Data Burst Timing Requirements and are described in Table 29: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
- a) The host shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred.
- b) The host shall initiate Ultra DMA burst termination by negating –HDMARDY. The host shall continue to negate –HDMARDY until the Ultra DMA burst is terminated.
- c) The device shall stop generating DSTROBE edges within tRFS of the host negating –HDMARDY
- d) If the host negates –HDMARDY within tSR after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero or one additional data words. If the host negates HDMARDYgreater than tSR after the device has generated a DSTROBE edge, then the host shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and tRFS timing for the device.
- e) The host shall assert STOP no sooner than tRP after negating –HDMARDY. The host shall not negate STOP again until after the Ultra DMA burst is terminated.
- f) The device shall negate DMARQ within tLI after the host has asserted STOP. The device shall not assert DMARQ again until after the Ultra DMA burst is terminated.
- g) If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted STOP. No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE. DSTROBE shall remain asserted until the Ultra DMA burst is terminated.
- h) The device shall release D[15:0] no later than tAZ after negating DMARQ.
- i) The host shall drive DD D[15:0] no sooner than tZAH after the device has negated DMARQ. For this step, the host may first drive D[15:0] with the result of its CRC calculation (see 6.5.4.5 ).
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- j) If the host has not placed the result of its CRC calculation on D[15:0] since first driving D[15:0] during (9), the host shall place the result of its CRC calculation on D[15:0] (see 6.5.4.5 ).
- k) The host shall negate –DMACK no sooner than tMLI after the device has asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated –HDMARDY, and no sooner than tDVS after the host places the result of its CRC calculation on D[15:0].
- l) The device shall latch the host’s CRC data from D[15:0] on the negating edge of –DMACK.
- m) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA burst for any one command, at the end of the command, the device shall report the first error that occurred (see 6.5.4.5 ).
- n) The device shall release DSTROBE within tIORDYZ after the host negates –DMACK.
- o) The host shall neither negate STOP nor assert –HDMARDY until at least tACK after the host has negated – DMACK.
- p) The host shall not assert –IORD, -CS0, -CS1, A2, A1, or A0 until at least tACK after negating DMACK.
Figure 14: Ultra DMA Data-In Burst Host Termination Timing
Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.
## 6.5.4.4.6 Initiating an Ultra DMA Data-Out Burst
An Ultra DMA Data-out burst is initiated by following the steps lettered below. The timing diagram is shown in Figure 15: Ultra DMA Data-Out Burst Initiation Timing. The timing parameters are specified in Table 28: Ultra DMA Data Burst Timing Requirements and are described in Table 29: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
- a) The host shall keep –DMACK in the negated state before an Ultra DMA burst is initiated.
- b) The device shall assert DMARQ to initiate an Ultra DMA burst.
- c) Steps I, (d), and (e) may occur in any order or at the same time. The host shall assert STOP. d) The host shall assert HSTROBE.
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- e) The host shall negate –CS0, -CS1, A2, A1, and A0. The host shall keep –CS0, -CS1, A2, A1, and A0 negated until after negating –DMACK at the end of the burst.
- f) Steps I, (d), and (e) shall have occurred at least tACK before the host asserts –DMACK. The host shall keep – DMACK asserted until the end of an Ultra DMA burst.
- g) The device may negate –DDMARDY tZIORDY after the host has asserted –DMACK. Once the device has negated –DDMARDY, the device shall not release –DDMARDY until after the host has negated DMACK at the end of an Ultra DMA burst.
- h) The host shall negate STOP within tENV after asserting –DMACK. The host shall not assert STOP until after the first negation of HSTROBE.
- i) The device shall assert –DDMARDY within tLI after the host has negated STOP. After asserting DMARQ and – DDMARDY the device shall not negate either signal until after the first negation of HSTROBE by the host.
- j) The host shall drive the first word of the data transfer onto D[15:0]. This step may occur any time during Ultra DMA burst initiation.
- k) To transfer the first word of data: the host shall negate HSTROBE no sooner than tUI after the device has asserted –DDMARDY. The host shall negate HSTROBE no sooner than tDVS after the driving the first word of data onto D[15:0].
Figure 15: Ultra DMA Data-Out Burst Initiation Timing
Note: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted.
## 6.5.4.4.7 Sustaining an Ultra DMA Data-Out Burst
An Ultra DMA Data-Out burst is sustained by following the steps lettered below. The timing diagram is shown in Figure 16: Sustained Ultra DMA Data-Out Burst Timing. The associated timing parameters are specified in Table 28: Ultra DMA Data Burst Timing Requirements and are described in Table 29: Ultra DMA Data Burst Timing Descriptions.
- The following steps shall occur in the order they are listed unless otherwise specifically allowed: a) The host shall drive a data word onto D[15:0].
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- b) The host shall generate an HSTROBE edge to latch the new word no sooner than tDVS after changing the state of D[15:0]. The host shall generate an HSTROBE edge no more frequently than tCYC for the selected Ultra DMA mode. The host shall not generate two rising or falling HSTROBE edges more frequently than 2tcyc for the selected Ultra DMA mode.
- c) The host shall not change the state of D[15:0] until at least tDVH after generating an HSTROBE edge to latch the data.
- d) The host shall repeat steps (a), (b), and (c) until the data transfer is complete or an Ultra DMA burst is paused, whichever occurs first.
Figure 16: Sustained Ultra DMA Data-Out Burst Timing
Note: Data (D15:D0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host.
## 6.5.4.4.8 Device Pausing an Ultra DMA Data-Out Burst
The device pauses an Ultra DMA Data-Out burst by following the steps lettered below. The timing diagram is shown in Figure 17: Ultra DMA Data-Out Burst Device Pause Timing. The timing parameters are specified in Table 28: Ultra DMA Data Burst Timing Requirements and are described in Table 29: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
- a) The device shall not pause an Ultra DMA burst until at least one data word of an Ultra DMA burst has been transferred.
- b) The device shall pause an Ultra DMA burst by negating –DDMARDY.
- c) The host shall stop generating HSTROBE edges within tRFS of the device negating –DDMARDY.
- d) If the device negates –DDMARDY within tSR after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero or one additional data words. If the device negates –DDMARDY greater than tSR after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and tRFS timing for the host.
- e) The device shall resume an Ultra DMA burst by asserting –DDMARDY.
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Figure 17: Ultra DMA Data-Out Burst Device Pause Timing
Notes:
1. The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after -DDMARDY is negated.
2. After negating –DDMARDY, the device may receive zero, one, two, or three more data words from the host.
## 6.5.4.4.9 Device Terminating an Ultra DMA Data-Out Burst
The device terminates an Ultra DMA Data-Out burst by following the steps lettered below. The timing diagram for the operation is shown in Figure 18: Ultra DMA Data-Out Burst Device Termination Timing. The timing parameters are specified in Table 28: Ultra DMA Data Burst Timing Requirements and are described in Table 29: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
- a) The device shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA burst has been transferred.
- b) The device shall initiate Ultra DMA burst termination by negating –DDMARDY.
- c) The host shall stop generating an HSTROBE edges within tRFS of the device negating –DDMARDY.
- d) If the device negates –DDMARDY within tSR after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero or one additional data words. If the device negates –DDMARDY greater than tSR after the host has generated an HSTROBE edge, then the device shall be prepared to receive zero, one or two additional data words. The additional data words are a result of cable round trip delay and tRFS timing for the host.
- e) The device shall negate DMARQ no sooner than tRP after negating –DDMARDY. The device shall not assert DMARQ again until after the Ultra DMA burst is terminated.
- f) The host shall assert STOP within tLI after the device has negated DMARQ. The host shall not negate STOP again until after the Ultra DMA burst is terminated.
- g) If HSTROBE is negated, the host shall assert HSTROBE within tLI after the device has negated DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition of HSTROBE. HSTROBE shall remain asserted until the Ultra DMA burst is terminated.
- h) The host shall place the result of its CRC calculation on D[15:0] (see 6.5.4.5 ).
- i) The host shall negate –DMACK no sooner than tMLI after the host has asserted HSTROBE and STOP and the device has negated DMARQ and –DDMARDY, and no sooner than tDVS after placing the result of its CRC calculation on D[15:00].
- j) The device shall latch the host’s CRC data from D[15:00] on the negating edge of –DMACK.
- k) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command.
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Figure 18: Ultra DMA Data-Out Burst Device Termination Timing
Note: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.
## 6.5.4.4.10 Host Terminating an Ultra DMA Data-Out Burst
Termination of an Ultra DMA Data-Out burst by the host is shown in Figure 19: Ultra DMA Data-Out Burst Host Termination Timing while timing parameters are specified in Table 28: Ultra DMA Data Burst Timing Requirements and timing parameters are described in Table 29: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
- a) The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges.
- b) The host shall assert STOP no sooner than tSS after it last generated an HSTROBE edge. The host shall not negate STOP again until after the Ultra DMA burst is terminated.
- c) The device shall negate DMARQ within tLI after the host asserts STOP. The device shall not assert DMARQ again until after the Ultra DMA burst is terminated.
- d) The device shall negate –DDMARDY within tLI after the host has negated STOP. The device shall not assert – DDMARDY again until after the Ultra DMA burst termination is complete.
- e) If HSTROBE is negated, the host shall assert HSTROBE within tLI after the device has negated DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition on HSTROBE. HSTROBE shall remain asserted until the Ultra DMA burst is terminated.
- f) The host shall place the result of its CRC calculation on D[15:0] (see 6.5.4.5 ).
- g) The host shall negate –DMACK no sooner than tMLI after the host has asserted HSTROBE and STOP and the device has negated DMARQ and –DDMARDY, and no sooner than tDVS after placing the result of its CRC calculation on D[15:0].
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- h) The device shall latch the host’s CRC data from D[15:0] on the negating edge of –DMACK.
- i) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred (see 6.5.4.5 ).
- j) The device shall release –DDMARDY within tIORDYZ after the host has negated –DMACK.
- k) The host shall neither negate STOP nor negate HSTROBE until at least tACK after negating –DMACK.
- l) The host shall not assert –IOWR, -CS0, -CS1, A2, A1, or A0 until at least tACK after negating -DMACK.
Figure 19: Ultra DMA Data-Out Burst Host Termination Timing
Notes: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated.
## 6.5.4.5 Ultra DMA CRC Calculation
The following is a list of rules for calculating CRC, determining if a CRC error has occurred during an Ultra DMA burst, and reporting any error that occurs at the end of a command.
1. Both the host and the device shall have a 16-bit CRC calculation function.
2. Both the host and the device shall calculate a CRC value for each Ultra DMA burst.
3. The CRC function in the host and the device shall be initialized with a seed of 4ABAh at the beginning of an Ultra DMA burst before any data is transferred.
4. For each STROBE transition used for data transfer, both the host and the device shall calculate a new CRC value by applying the CRC polynomial to the current value of their individual CRC functions and the word being transferred. CRC is not calculated for the return of STROBE to the asserted state after the Ultra DMA burst termination request has been acknowledged.
5. At the end of any Ultra DMA burst the host shall send the results of its CRC calculation function to the device on D[15:0] with the negation of –DMACK.
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6. The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function. If the two values do not match, the device shall save the error and report it at the end of the command. A subsequent Ultra DMA burst for the same command that does not have a CRC error shall not clear an error saved from a previous Ultra DMA burst in the same command. If a miscompare error occurs during one or more Ultra DMA bursts for any one command, at the end of the command, the device shall report the first error that occurred.
7. For READ DMA, WRITE DMA, READ DMA QUEUED, or WRITE DMA QUEUED commands:
- When a CRC error is detected, it shall be reported by setting both ICRC and ABRT (bit 7 and bit 2 in the Error register) to one. ICRC is defined as the “Interface CRC Error” bit. The host shall respond to this error by reissuing the command.
8. For a REQUEST SENSE packet command (see SPC T10/955D for definition of the REQUEST SENSE command): When a CRC error is detected during transmission of sense data the device shall complete the command and set CHK to one. The device shall report a Sense key of 0Bh (ABORTED COMMAND). The device shall preserve the original sense data that was being returned when the CRC error occurred. The device shall not report any additional sense data specific to the CRC error. The host device driver may retry the REQUEST SENSE command or may consider this an unrecoverable error and retry the command that caused the Check Condition.
9. For any packet command except a REQUEST SENSE command: If a CRC error is detected, the device shall complete the command with CHK set to one. The device shall report a Sense key of 04h (HARDWARE ERROR). The sense data supplied via a subsequent REQUEST SENSE command shall report an ASC/ASCQ value of 08h/03h (LOGICAL UNIT COMMUNICATION CRC ERROR). Host drivers should retry the command that resulted in a HARDWARE ERROR.
- NOTE – If excessive CRC errors are encountered while operating in Ultra mode 2 or 1, the host should select a slower Ultra mode. Caution: CRC errors are detected and reported only while operating in an Ultra mode.
10. A host may send extra data words on the last Ultra DMA burst of a data out command. If a device determines that all data has been transferred for a command, the device shall terminate the burst. A device may have already received more data words than were required for the command. These extra words are used by both the host and the device to calculate the CRC, but, on an Ultra DMA data out burst, the extra words shall be discarded by the device.
11. 11. The CRC generator polynomial is: G(X) = X16 + X12 + X5 + 1. Table 32 describes the equations for 16-bit parallel generation of the resulting polynomial (based on a word boundary). NOTE – Since no bit clock is available, the recommended approach for calculating CRC is to use a word clock derived from the bus strobe. The combinational logic is then equivalent to shifting sixteen bits serially through the generator polynomial where D0 is shifted in first and D15 is shifted in last.
Table 32: Equations for parallel generation of an Ultra DMA CRC
|CRCIN0=f16|CRCIN8=f8 XOR f13|
|---|---|
|CRCIN1=f15|CRCIN9=f7 XOR f12|
|CRCIN2=f14|CRCIN10=f6 XOR f11|
|CRCIN3=f13|CRCIN11=f5 XOR f10|
|CRCIN4=f12|CRCIN12=f4 XOR f9 XOR f16|
|CRCIN5=f11 XOR f16|CRCIN13=f3 XOR f8 XOR f15|
|CRCIN6=f10 XOR f15|CRCIN14=f2 XOR f7 XOR f14|
|CRCIN7=f9 XOR f14|CRCIN15=f1 XOR f6 XOR f13|
|f1=D0 XOR CRCOUT15|f9=D8 XOR CRCOUT7 XOR f5|
|f2=D1 XOR CRCOUT14|f10=D9 XOR CRCOUT6 XOR f6|
|f3=D2 XOR CRCOUT13|f11=D10 XOR CRCOUT5 XOR f7|
|f4=D3 XOR CRCOUT12|f12=D11 XOR CRCOUT4 XOR f1 XOR f8|
|f5=D4 XOR CRCOUT11 XOR f1|f13=D12 XOR CRCOUT3 XOR f2 XOR f9|
|f6=D5 XOR CRCOUT10 XOR f2|f14=D13 XOR CRCOUT2 XOR f3 XOR f10|
|f7=D6 XOR CRCOUT9 XOR f3|f15=D14 XOR CRCOUT1 XOR f4 XOR f11|
|f8=D7 XOR CRCOUT8 XOR f4|f16=D15 XOR CRCOUT0 XOR f5 XOR f12|
Notes:
1. f=feedback
2. D[15:0] = Data to or from the bus
3. CRCOUT = 16-bit edge triggered result (current CRC)
4. CRCOUT[15:0] are sent on matching order bits of D[15:0]
An example of a CRC generator implementation is provided below in Figure 20: Ultra DMA Parallel CRC Generator Example.
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Figure 20: Ultra DMA Parallel CRC Generator Example
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## **7 Card Configuration**
The CompactFlash[TM] Memory Card is identified by information in the Card Information Structure (CIS). The Card has four configuration registers (Table 33 and Table 34).
- Configuration Option Register
- Pin Replacement Register
- Card Configuration and Status Register
They are used to coordinate the I/O spaces and the Interrupt level of cards that are located in the system. In addition, in I/O Card mode these registers provide a method for accessing status information that would normally appear on dedicated pins in Memory Card mode.
The base address of the card configuration registers is 200h in the Attribute Memory space.
No write operation should be performed to the attribute memory area except for the configuration register addresses. All other attribute memory locations are reserved. See 7.4 Attribute Memory Function.
## Table 33: CompactFlash[TM] Memory Card Registers and Memory Space Decoding
|-CE2|-CE1|-REG|-OE|-WE|A10 A|A10 A9|A8-A4|A3|A2|A1|A0 Selected S|A0 Selected Space|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|1|1|X|X|X|X|X|XX|X|X|X|X|Standby|
|X|0|0|0|1|X|1|XX|X|X|X|0|Configuration Register Read|
|1|0|1|0|1|X|X|XX|X|X|X|X|Common Memory Read (8 bit–D7 to D0)|
|0|1|1|0|1|X|X|XX|X|X|X|X|Common Memory Read (8 bit–D15 to D8)|
|0|0|1|0|1|X|X|XX|X|X|X|0|Common Memory Read (16 bit–D15 to D0)|
|X|0|0|1|0|X|1|XX|X|X|X|0|Configuration Register Write|
|1|0|1|1|0|X|X|XX|X|X|X|X|Common Memory Write (8 bit–D7 to D0)|
|0|1|1|1|0|X|X|XX|X|X|X|X|Common Memory Write (8 bit–D15 to D8)|
|0|0|1|1|0|X|X|XX|X|X|X|0|Common Memory Write (16 bit–D15 to D0)|
|X|0|0|0|1|0|0|XX|X|X|X|0|Card Information Structure Read|
|1|0|0|1|0|0|0|XX|X|X|X|0|Invalid Access (CIS Write)|
|1|0|0|0|1|X|X|XX|X|X|X|1|Invalid Access (CIS Odd Byte Read)|
|1|0|0|1|0|X|X|XX|X|X|X|1|Invalid Access (CIS Odd Byte Write)|
|0|1|0|0|1|X|X|XX|X|X|X|X|Invalid Access (CIS Odd Byte Read)|
|0|1|0|1|0|X|X|XX|X|X|X|X|Invalid Access (CIS Odd Byte Write)|
## Table 34: CompactFlash[TM] Memory Card Configuration Registers Decoding
|-CE2|-CE1|-REG|-OE|-WE|A10 A|A10 A9A8~A|A8~A4A|A3|A2|A1|A0 Selected S|A0 Selected Space|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|X|0|0|0|1|0|1|00|0|0|0|0|Configuration Option Register Read(200h)|
|X|0|0|1|0|0|1|00|0|0|0|0|Configuration Option Register Write(200h)|
|X|0|0|0|1|0|1|00|0|0|1|0|Card Status Register Read (202h)|
|X|0|0|1|0|0|1|00|0|0|1|0|Card Status Register Write (202h)|
|X|0|0|0|1|0|1|00|0|1|0|0|Pin Replacement Register Read (204h)|
|X|0|0|1|0|0|1|00|0|1|0|0|Pin Replacement Register Write (204h)|
Note: The location of the Card Configuration Registers should always be read from the CIS since these locations may vary in future products. No Writes should be performed to the Card Attribute Memory except to the Card Configuration Register Addresses. All other attribute memory locations are reserved.
## **7.1 Configuration Option Register (200h in Attribute Memory)**
The Configuration Option Register is used to configure the Card’s interface, address decoding and interrupt to the Card (see Table 35).
## 7.1.1 SRESET
Setting the SRESET bit to ‘1’ and returning the bit ‘0’ places the CompactFlash[TM] Storage Card in the Reset state. Setting this bit to ‘1’ is equivalent to asserting the RESET signal except that the SRESET bit is not cleared. Returning the SRESET bit to ‘0’ leaves the CompactFlash[TM] Storage Card in the same un-configured Reset state as after a power-up and hardware reset.
This bit is set to ‘0’ at power-up and taking the Card through a hardware reset.
## 7.1.2 LevlREQ
This bit is set to one (1) when Level Mode Interrupt is selected, and zero (0) when Pulse Mode is selected. Set to zero (0) after Power Up.
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## 7.1.3 Conf5 – Conf0 (Configuration Index)
These bits are used to select the operation mode of the Card as shown in Table 36. This bit is set to ‘0’ after Power Up.
Table 35: Configuration Option Register (default value: 00h)
|Operation<br>D7<br>D6<br>D5<br>D4<br>D3<br>D2<br>D1<br>D0<br>R/W<br>SRESET<br>LevlREQ<br>Conf5<br>Conf4<br>Conf3<br>Conf2<br>Conf1<br>Conf0<br>~~a~~|Operation<br>D7<br>D6<br>D5<br>D4<br>D3<br>D2<br>D1<br>D0<br>R/W<br>SRESET<br>LevlREQ<br>Conf5<br>Conf4<br>Conf3<br>Conf2<br>Conf1<br>Conf0<br>~~a~~|Operation<br>D7<br>D6<br>D5<br>D4<br>D3<br>D2<br>D1<br>D0<br>R/W<br>SRESET<br>LevlREQ<br>Conf5<br>Conf4<br>Conf3<br>Conf2<br>Conf1<br>Conf0<br>~~a~~|Operation<br>D7<br>D6<br>D5<br>D4<br>D3<br>D2<br>D1<br>D0<br>R/W<br>SRESET<br>LevlREQ<br>Conf5<br>Conf4<br>Conf3<br>Conf2<br>Conf1<br>Conf0<br>~~a~~|Operation<br>D7<br>D6<br>D5<br>D4<br>D3<br>D2<br>D1<br>D0<br>R/W<br>SRESET<br>LevlREQ<br>Conf5<br>Conf4<br>Conf3<br>Conf2<br>Conf1<br>Conf0<br>~~a~~|Operation<br>D7<br>D6<br>D5<br>D4<br>D3<br>D2<br>D1<br>D0<br>R/W<br>SRESET<br>LevlREQ<br>Conf5<br>Conf4<br>Conf3<br>Conf2<br>Conf1<br>Conf0<br>~~a~~|Operation<br>D7<br>D6<br>D5<br>D4<br>D3<br>D2<br>D1<br>D0<br>R/W<br>SRESET<br>LevlREQ<br>Conf5<br>Conf4<br>Conf3<br>Conf2<br>Conf1<br>Conf0<br>~~a~~|Operation<br>D7<br>D6<br>D5<br>D4<br>D3<br>D2<br>D1<br>D0<br>R/W<br>SRESET<br>LevlREQ<br>Conf5<br>Conf4<br>Conf3<br>Conf2<br>Conf1<br>Conf0<br>~~a~~|Operation<br>D7<br>D6<br>D5<br>D4<br>D3<br>D2<br>D1<br>D0<br>R/W<br>SRESET<br>LevlREQ<br>Conf5<br>Conf4<br>Conf3<br>Conf2<br>Conf1<br>Conf0<br>~~a~~|Operation<br>D7<br>D6<br>D5<br>D4<br>D3<br>D2<br>D1<br>D0<br>R/W<br>SRESET<br>LevlREQ<br>Conf5<br>Conf4<br>Conf3<br>Conf2<br>Conf1<br>Conf0<br>~~a~~|Operation<br>D7<br>D6<br>D5<br>D4<br>D3<br>D2<br>D1<br>D0<br>R/W<br>SRESET<br>LevlREQ<br>Conf5<br>Conf4<br>Conf3<br>Conf2<br>Conf1<br>Conf0<br>~~a~~|Operation<br>D7<br>D6<br>D5<br>D4<br>D3<br>D2<br>D1<br>D0<br>R/W<br>SRESET<br>LevlREQ<br>Conf5<br>Conf4<br>Conf3<br>Conf2<br>Conf1<br>Conf0<br>~~a~~|
|---|---|---|---|---|---|---|---|---|---|---|---|
||Table 36: CompactFlashTMMemory Card Configurations|||||||||||
||Conf5|Conf4|Conf3|Conf2|Conf1<br>Conf0|Mapping Mode|Card<br>Mode||Task File Register Address|||
||0|0|0|0|0<br>0|Memory|Memory||Memory<br>0h–Fh, 400h–7FFh||7FFh|
||0|0|0|0|0<br>1|Contiguous I/O|I/O||xx0h–xxFh|||
||0|0|0|0|1<br>0|Primary I/O|I/O||1F0h–1F7h, 3F6h–3F7h|||
||0|0|0|0|1<br>1|Secondary I/O|I/O||170h–177h, 376h–377h|||
## **7.2 CompactFlash[TM] Memory Card Configurations**
The Card Configuration and Status Register contains information about the Card’s status (see Table 37).
## 7.2.1 Changed
Indicates that one or both of the Pin Replacement register (CRDY, or CWProt) bits are set to ‘1’. When the Changed bit is set, -STSCHG (Pin 46) is held Low and if the SigChg bit is ‘1’ the Card is configured for the I/O interface.
## 7.2.2 SigChg
This bit is set and reset by the host to enable and disable a state-change signal from the Status Register (issued on Status Changed pin 46). If no state change signal is desired, this bit should be set ‘0’ and pin 46 (-STSCHG) will be held High while the Card is configured for I/O.
## 7.2.3 Iois8
The host sets this bit to ‘1’ if the Card is to be configured in 8 bit I/O Mode. The Card is always configured for both 8 and 16 bit I/O, so this bit is ignored.
## 7.2.4 PwrDwn
This bit indicates whether the Card is in the power saving mode or active mode. When the PwrDwn bit is set to ‘1’, the Card enters power down mode. When set to ‘0’, the Card enters active mode. The READY value on Pin Replacement Register becomes BUSY when this bit is changed. READY will not become Ready until the power state requested has been entered. The Card automatically powers down when it is idle and powers back up when it receives a command.
## 7.2.5 Int
This bit represents the internal state of the interrupt request. It is available whether or not the I/O interface has been configured. It remains valid until the condition which caused the interrupt request has been serviced. If interrupts are disabled by the –IEN bit in the Device Control Register, this bit is ‘0’.
Table 37: Card Configuration and Status Register (default value: 00h)
|Table 37: Card Configuration and Status Register (default value: 00h)<br>~~———~~|Table 37: Card Configuration and Status Register (default value: 00h)|Table 37: Card Configuration and Status Register (default value: 00h)|Table 37: Card Configuration and Status Register (default value: 00h)|Table 37: Card Configuration and Status Register (default value: 00h)|||||
|---|---|---|---|---|---|---|---|---|
|Operation<br>~~———~~|D7|D6|D5|D4|D3|D2|D1|D0|
|Read<br>~~———~~|Changed|SigChg|IOIS8|0|0|PwrDwn|Int|0|
|Write<br>~~———~~|0|SigChg|IOIS8|0|0|PwrDwn|0|0|
## **7.3 Pin Replacement Register (204h in Attribute Memory)**
This register contains information on the state of the READY signal when configured in memory mode and the IREQ signal in I/O mode. See Table 38 and Table 39.
## 7.3.1 Cready
This bit is set to ‘1’ when the bit Rready changes state. This bit can also be written by the host.
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## 7.3.2 CWProt
This bit is set to ‘1’ when the bit RWProt changes state. This bit can also be written by the host.
## 7.3.3 Rready
This bit is used to determine the internal state of the Ready signal. In I/O mode it is used as an interrupt request. When written, this bit acts as a mask (Mready) for writing the corresponding bit Cready.
## 7.3.4 Wprot
This bit is always ‘0’ since the CompactFlash[TM] Memory Card does not have a Write Protect switch. When written, this bit acts as a mask for writing the corresponding CWProt bit.
## 7.3.5 Mready
This bit acts as a mask for writing the corresponding Cready bit.
## 7.3.6 MWProt
This bit when written acts as a mask for writing the corresponding CWProt bit.
Table 38: Pin Replacement Register (default value: 0Ch)
|Operation|D7|D6|D6|D5||D4|||D3|D3|D2|D2|D1|D0|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|Read|0||0|Cready||CWProt|||1|1|1||Rready|Wprot|
|Write|0||0|Cready||CWProt|||0|0|0||Rready|MWProt|
|Table 39: Pin Replacement Changed Bit/Mask Bit Values|Table 39: Pin Replacement Changed Bit/Mask Bit Values|||Table 39: Pin Replacement Changed Bit/Mask Bit Values|||||||||||
|Initial Value of ‘C’ Status|Written by Host<br>‘C’ Bit<br>‘M’ Bit|||||Final ‘C’ Bit|Final ‘C’ Bit|||||Comments|||
|0|X|||0|||0|||||Unchanged|||
|1|X|||0|||1|||||Unchanged|||
|X|0|||1|||0|||||Cleared by Host|||
|X|1|||1|||1|||||Set by Host|||
## **7.4 Attribute Memory Function**
Attribute memory is a space where identification and configuration information are stored. Only 8 bit wide accesses at even addresses can be performed in this area. The Card configuration registers are also located in the Attribute Memory area, at base address 200h. Attribute memory is not accessible in True IDE mode of operation. For the Attribute Memory Read function, signals –REG and –OE must be active and –WE inactive during the cycle. As in the Main Memory Read functions, the signals –CE1 and –CE2 control the even and odd Byte address, but only the even Byte data is valid during the Attribute Memory access. Refer to Table 40 for signal states and bus validity.
Table 40: Attribute Memory Function
|Function Mode|-REG|-CE2**(1)**|-CE1**(1)**|A10|A9|A0|-OE**(1)**|-WE**(1)**|D15to D8|D7to D0|
|---|---|---|---|---|---|---|---|---|---|---|
|Standby|X|H|H|X|X|X|X|X|High-Z|High-Z|
|Read Byte Access CIS (8 bits)|L|H<br>~~ee~~|L<br>~~es~~|L|L<br>~~Gd~~|L<br>~~Gd~~|L<br>~~Gd~~|H<br>~~Gd~~|High-Z<br>~~Gd~~|Even Byte|
|Write Byte Access CIS (8 bits)<br>Invalid<br>~~es~~|L<br>~~es~~|H<br>~~es~~<br>~~ee~~<br>~~ee~~|L<br>~~es~~<br>~~es~~<br>~~es~~|L<br>~~es~~|L<br>~~es~~<br>~~Gd~~<br>~~Gd~~|L<br>~~es~~<br>~~Gd~~<br>~~Gd~~|H<br>~~es~~<br>~~Gd~~<br>~~Gd~~|L<br>~~es~~<br>~~Gd~~<br>~~Gd~~|Don’t Care<br>~~es~~<br>~~Gd~~<br>~~Gd~~|Even Byte<br>~~es~~|
|Read Byte Access<br>Configuration (8 bits)<br>~~es~~<br>~~es~~|L<br>~~es~~<br>~~es~~|H<br>~~es~~<br>~~ee ~~<br>~~es~~<br>~~ee~~<br>~~es~~|L<br>~~es~~<br> ~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|L<br>~~es~~<br>~~es~~|H<br>~~es~~<br>~~Gd~~<br>~~es~~<br>~~Gd~~<br>~~Gd~~|L<br>~~es~~<br>~~Gd~~<br>~~es~~<br>~~Gd~~<br>~~Gd~~|L<br>~~es~~<br>~~Gd~~<br>~~es~~<br>~~Gd~~<br>~~Gd~~|H<br>~~es~~<br>~~Gd~~<br>~~es~~<br>~~Gd~~|High-Z<br>~~es~~<br>~~Gd~~<br>~~es~~<br>~~Gd~~|Even Byte<br>~~es~~<br>~~es~~|
|Write Byte Access<br>Configuration (8 bits)<br>~~es~~<br>~~ed~~|L<br>~~es~~<br>~~ed~~|H<br>~~es~~<br>~~ee ~~<br>~~ed~~<br>~~es~~<br>~~es~~|L<br>~~es~~<br> ~~es~~<br>~~ed~~<br>~~es~~<br>~~ne~~|L<br>~~es~~<br>~~ed~~|H<br>~~es~~<br>~~Gd~~<br>~~ed~~<br>~~Gd~~|L<br>~~es~~<br>~~Gd~~<br>~~ed~~<br>~~Gd~~|H<br>~~es~~<br>~~Gd~~<br>~~ed~~<br>~~Gd~~|L<br>~~es~~<br>~~Gd~~<br>~~ed~~|Don’t Care<br>~~es~~<br>~~Gd~~<br>~~ed~~|Even Byte<br>~~es~~<br>~~ed~~|
|Read Byte Access<br>Configuration CF+(8 bits)<br>~~ed~~<br>~~ed~~|L<br>~~ed~~<br>~~ed~~|H<br>~~ed~~<br>~~es ~~<br>~~ed~~<br>~~es~~<br>~~ne~~|L<br>~~ed~~<br> ~~es~~<br>~~ed~~<br>~~ne~~<br>~~es~~|X<br>~~ed~~<br>~~ed~~|X<br>~~ed~~<br>~~Gd~~<br>~~ed~~<br>~~Gd~~|L<br>~~ed~~<br>~~Gd~~<br>~~ed~~<br>~~Gd~~|L<br>~~ed~~<br>~~Gd~~<br>~~ed~~<br>~~Gd~~|H<br>~~ed~~<br>~~ed~~|High-Z<br>~~ed~~<br>~~ed~~|Even Byte<br>~~ed~~<br>~~ed~~|
|Read Word Access CIS (16<br>bits)<br>~~es~~|L<br>~~es~~|L<br>~~es ~~<br>~~es~~<br>~~ne~~<br>~~ne~~|L<br> ~~ne~~<br>~~es~~<br>~~es~~<br>~~es~~|L<br>~~es~~|L<br>~~es~~<br>~~Gd~~<br>~~Gd~~|L*<br>~~es~~<br>~~Gd~~<br>~~Gd~~|L<br>~~es~~<br>~~Gd~~<br>~~Gd~~|H<br>~~es~~|Not Valid<br>~~es~~|Even Byte<br>~~es~~|
|Write Word Access CIS (16<br>bits) Invalid<br>~~es~~|L<br>~~es~~|L<br>~~ne ~~<br>~~es~~<br>~~ne~~<br>~~ne~~|L<br> ~~es~~<br>~~es~~<br>~~es~~<br>~~es~~|L<br>~~es~~|L<br>~~Gd~~<br>~~es~~<br>~~Gd~~<br>~~Gd~~|L*<br>~~Gd~~<br>~~es~~<br>~~Gd~~<br>~~Gd~~|H<br>~~Gd~~<br>~~es~~<br>~~Gd~~<br>~~Gd~~|L<br>~~es~~|Don’t Care<br>~~es~~|Even Byte<br>~~es~~|
|Read Word Access<br>Configuration (16 bits)<br>~~es~~|L<br>~~es~~|L<br>~~ne ~~<br>~~es~~<br>~~ne~~<br>~~es~~|L<br> ~~es~~<br>~~es~~<br>~~es~~<br>~~ee~~|L<br>~~es~~|H<br>~~Gd~~<br>~~es~~<br>~~Gd~~<br>~~Gd~~|L*<br>~~Gd~~<br>~~es~~<br>~~Gd~~<br>~~Gd~~|L<br>~~Gd~~<br>~~es~~<br>~~Gd~~<br>~~Gd~~|H<br>~~es~~|Not Valid<br>~~es~~|Even Byte<br>~~es~~|
|Write Word Access<br>Configuration (16 bits)<br>~~es~~|L<br>~~es~~|L<br>~~ne ~~<br>~~es~~<br>~~es~~|L<br> ~~es~~<br>~~es~~<br>~~ee~~|L<br>~~es~~|H<br>~~Gd~~<br>~~es~~<br>~~Gd~~|L*<br>~~Gd~~<br>~~es~~<br>~~Gd~~|H<br>~~Gd~~<br>~~es~~<br>~~Gd~~|L<br>~~es~~|Don’t Care<br>~~es~~|Even Byte<br>~~es~~|
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* Address A0 must be low for all word accesses.
## **7.5 I/O Transfer Function**
The I/O transfer to or from the Card can be either 8 or 16 bits. When a 16 bit accessible port is addressed, the – IOIS16 signal is asserted by the Card, otherwise it is de-asserted. When a 16 bit transfer is attempted, and the – IOIS16 signal is not asserted, the system must generate a pair of 8 bit references to access the Word’s even and odd Bytes. The Card permits both 8 and 16 bit accesses to all of its I/O addresses, so –IOIS16 is asserted for all addresses (see Table 41).
Table 41: I/O Function
|Table 41: I/O Function|||||||||
|---|---|---|---|---|---|---|---|---|
|Function Code|-REG|-CE2|-CE1|A0|-IORD|-IOWR|D15to D8|D7to D0|
|Standby Mode<br>~~LLL~~|X<br>~~LLL~~|H<br>~~LLL~~|H<br>~~LLL~~|X<br>~~LLL~~|X<br>~~LLL~~|X<br>~~LLL~~|High Z<br>~~LLL~~|High Z<br>~~LLL~~|
|Byte Input Access<br>(8 bits)<br>~~LLL~~|L<br>L<br>~~LLL~~|H<br>H<br>~~LLL~~|L<br>L<br>~~LLL~~|L<br>H<br>~~LLL~~|L<br>L<br>~~LLL~~|H<br>H<br>~~LLL~~|High Z<br>High Z<br>~~LLL~~|Even Byte<br>Odd Byte<br>~~LLL~~|
|Byte Output Access<br>(8 bits)<br>~~LLL~~<br>~~EEE~~|L<br>L<br>~~LLL~~<br>~~EEE~~|H<br>H<br>~~LLL~~<br>~~EEE~~|L<br>L<br>~~LLL~~<br>~~EEE~~|L<br>H<br>~~LLL~~<br>~~EEE~~|H<br>H<br>~~LLL~~<br>~~EEE~~|L<br>L<br>~~LLL~~<br>~~EEE~~|Don’t Care<br>Don’t Care<br>~~LLL~~<br>~~EEE~~|Even Byte<br>Odd Byte<br>~~LLL~~<br>~~EEE~~|
|Word Input Access (16 bits)<br>~~EEE~~|L<br>~~EEE~~|L<br>~~EEE~~|L<br>~~EEE~~|L*<br>~~EEE~~|L<br>~~EEE~~|H<br>~~EEE~~|Odd Byte<br>~~EEE~~|Even Byte<br>~~EEE~~|
|Word Output Access (16 bits)|L|L|L|L*|H|L|Odd Byte|Even Byte|
|I/O Read Inhibit|H|X|X|X|L|H|Don’t Care|Don’t Care|
|I/O Write Inhibit|H|X|X|X|H|L|High Z|High Z|
|High Byte Input Only (8 bits)|L|L|H|X|L|H|Odd Byte|High Z|
|High Byte Output Only (8 bits)|L|L|H|X|H|L|Odd Byte|Don’t Care|
* Address A0 must be low for all word accesses.
## **7.6 Common Memory Transfer Function**
The Common Memory transfer to or from the Card permits both 8 or 16 bit access to all of the Common Memory addresses (see Table 42).
Table 42: Common Memory Function
|Function Code|-REG|-CE2|-CE1|A0|-OE|-WE|D15to D8|D7to D0|
|---|---|---|---|---|---|---|---|---|
|Standby Mode<br>~~TLE~~|X<br>~~TLE~~|H<br>~~TLE~~|H<br>~~TLE~~|X<br>~~TLE~~|X<br>~~TLE~~|X<br>~~TLE~~|High Z<br>~~TLE~~|High Z<br>~~TLE~~|
|Byte Read Access<br>(8 bits)<br>~~TLE~~|H<br>H<br>~~TLE~~|H<br>H<br>~~TLE~~|L<br>L<br>~~TLE~~|L<br>H<br>~~TLE~~|L<br>L<br>~~TLE~~|H<br>H<br>~~TLE~~|High Z<br>High Z<br>~~TLE~~|Even Byte<br>Odd Byte<br>~~TLE~~|
|Byte Write Access<br>(8 bits)<br>~~TLE~~<br>~~pt~~|H<br>H<br>~~TLE~~<br>~~pt~~|H<br>H<br>~~TLE~~<br>~~pt~~|L<br>L<br>~~TLE~~<br>~~pt~~|L<br>H<br>~~TLE~~<br>~~pt~~|H<br>H<br>~~TLE~~<br>~~pt~~|L<br>L<br>~~TLE~~<br>~~pt~~|Don’t Care<br>Don’t Care<br>~~TLE~~<br>~~pt~~|Even Byte<br>Odd Byte<br>~~TLE~~<br>~~pt~~|
|Word Read Access (16 bits)<br>~~pt~~|H<br>~~pt~~|L<br>~~pt~~|L<br>~~pt~~|L*<br>~~pt~~|L<br>~~pt~~|H<br>~~pt~~|Odd Byte<br>~~pt~~|Even Byte<br>~~pt~~|
|Word Write Access (16 bits)<br>~~pt~~|H<br>~~pt~~|L<br>~~pt~~|L<br>~~pt~~|L*<br>~~pt~~|H<br>~~pt~~|L<br>~~pt~~|Odd Byte<br>~~pt~~|Even Byte<br>~~pt~~|
|Odd Byte Read Only (8 bits)|H|L|H|X|L|H|Odd Byte|High Z|
|Odd Byte Write Only (8 bits)|H|L|H|X|H|L|Odd Byte|Don’t Care|
* Address A0 must be low for all word accesses.
## **7.7 True IDE Mode I/O Function**
The Card can be configured in a True IDE Mode of operation. It is configured in this mode only when the –OE signal is grounded by the host during the power off to power on cycle. In this True IDE Mode the PC card protocol and configuration are disabled and only I/O operations to the Task File and Data Register are allowed. No Memory or Attribute Registers are accessible to the host. The Set Feature Command can be used to put the device in 8 bit Mode (see Table 43).
Removing and reinserting the Card while the host computer’s power is on will reconfigure the Card to PC Card ATA mode.
Table 43: True IDE Mode I/O Function
|Function Code|-CS1|-CS0|A2 to A0|-DMACK|-IORD|-IOWR|D15to D8|D7to D0|
|---|---|---|---|---|---|---|---|---|
|Invalid Mode|L|L|X|X|X|X|Undefined<br>In/Out|Undefined In/Out|
||L|X|X|L|L|X|Undefined Out|Undefined Out|
||L|X|X|L|X|L|Undefined In|Undefined In|
||X|L|X|L|L|X|Undefined Out|Undefined Out|
||X|L|X|L|X|L|Undefined In|Undefined In|
|Standby Mode|H|H|X|H|X|X|High Z|High Z|
|Task File Write|H|L|1h-7h|H|H|L|Don’t Care|Data In|
|Task File Read|H|L|1h-7h|H|L|H|High Z|Data Out|
|PIO Data Register Write|H|L|0|H|H|L|Odd-Byte In|Even-Byte In|
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|DMA Data Register Write|H|L|X|L|H|L|Odd-Byte In|Even-Byte In|
|---|---|---|---|---|---|---|---|---|
|PIO Data Register Read|H|L|0|H|L|H|Odd-Byte Out|Even-Byte Out|
|DMA Data Register Read|H|H|X|L|L|H|Odd-Byte Out|Even-Byte Out|
|Control Register Write|L|H|6h|H|H|L|Don’t Care|Control In|
|Alternate Status Read|L|H|6h|H|L|H|High Z|Status Out|
|Drive Address|L|H|7h|H|L|H|High Z|Data Out|
## **7.8 Host Configuration Requirements for Master/Slave or New Timing Modes**
The CF Advanced Timing modes include PCMCIA PC Card style I/O modes that are faster than the original 250 ns cycle time. These modes are not supported by the PCMCIA PC Card specification nor CF by cards based on revisions of the CF specification before Revision 3.0. Hosts shall ensure that all cards accessed through a common electrical interface are capable of operation at the desired, faster than 250 ns, I/O mode before configuring the interface for that I/O mode.
Advanced Timing modes are PCMCIA PC Card style I/O modes that are 100 ns or faster, PC Card Memory modes that are 100ns or faster, True IDE PIO Modes 5, 6 and Multiword DMA Modes 3, 4. These modes are permitted to be used only when a single card is present and the host and card are connected directly, without a cable exceeding 0.15m in length. Consequently, the host shall not configure a card into an Advanced Timing Mode if two cards are sharing I/O lines, as in Master/Slave operation, nor if it is constructed such that a cable exceeding 0.15 meters is required to connect the host to the card.
The load presented to the Host by cards supporting Ultra DMA is more controlled than that presented by other CompactFlash[TM] cards. Therefore, the use of a card that does not support Ultra DMA in a Master/Slave arrangement with an Ultra DMA card can affect the critical timing of the Ultra DMA transfers. The host shall not configure a card into Ultra DMA mode when a card not supporting Ultra DMA is also present on the same interface
When the use of two cards on an interface is otherwise permitted, the host may use any mode that is supported by both cards, but to achieve maximum performance it should use its highest performance mode that is also supported by both cards.
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## **8 Software interface**
## **8.1 CF-ATA Drive Register Set Definition and Protocol**
The CompactFlash[TM] Memory Card can be configured as a high performance I/O device through:
- Standard PC-AT disk I/O address spaces
- 1F0h-1F7h, 3F6h-3F7h (primary);
- 170h-177h, 376h-377h (secondary) with IRQ 14 (or other available IRQ).
- Any system decoded 16 Byte I/O block using any available IRQ.
- Memory space.
Communication to or from the Card is done using the Task File registers which provide all the necessary registers for control and status information. The PCMCIA interface connects peripherals to the host using four-register mapping methods. Table 44: I/O Configurations is a detailed description of these methods:
Table 44: I/O Configurations
|Table 44: I/O Configurations|Table 44: I/O Configurations|Table 44: I/O Configurations|Table 44: I/O Configurations|
|---|---|---|---|
|Standards Configurations||||
|ConfigIndex|I/O or Memory|Address|Description|
|0|Memory|0h-Fh, 400h-7FFh|Memory Mapped|
|1|I/O|xx0h-xxFh|I/O Mapped 16 Continuous Registers|
|2|I/O|1F0-1F7h, 3F6h-3F7h|Primary I/O Mapped|
|3|I/O|170-177h, 376h-377h|Secondary I/O Mapped|
## **8.2 Memory Mapped Addressing**
When the Card registers are accessed via memory references, the registers appear in the common memory space window: 0-2Kbytes as shown in Table 45: Memory Mapped Decoding. This window accesses the Data Register FIFO. It does not allow random access to the data buffer within the Card.
Register 0 is accessed with –CE1 and –CE2 Low, as a Word register on the combined Odd and Even Data Bus (D15 to D0). Address A0 must be low for all word accesses. It can also be accessed with –CE1 Low and –CE2 High, by a pair of Byte accesses to offset 0. The address space of this Word register overlaps the address space of the Error and Feature Byte-wide registers at offset 1. When accessed twice as Byte register with –CE1 Low, the first Byte is the even Byte of the Word and the second is the odd Byte. A Byte access to address 0 with –CE1 High and –CE2 Low accesses the Error (read) or Feature (write) register.
Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is equivalent to register 0, while register 9 accesses the odd Byte. Therefore, if the registers are Byte accessed in the order 9 then 8 the data will be transferred odd Byte then even Byte. Repeated Byte accesses to register 8 or 0 will access consecutive (even then odd) Bytes from the data buffer. Repeated Word accesses to register 8, 9 or 0 will access consecutive Words from the data buffer, however repeated Byte accesses to register 9 are not supported. Repeated alternating Byte accesses to registers 8 then 9 will access consecutive (even then odd) Bytes from the data buffer.
Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd addresses between 400h and 7FFh access register 9. This 1 kByte memory window to the data register is provided so that hosts can perform memory-to-memory block moves to the data register when the register lies in memory space. Some hosts, such as the X86 processors, must increment both the source and destination addresses when executing the memoryto-memory block move instruction. Some PCMCIA socket adapters also have embedded auto incrementing address logic.
A Word access to address at offset 8 will provide even data on the least significant Byte of the data bus, along with odd data at offset 9 on the most significant Byte of the data bus.
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Table 45: Memory Mapped Decoding
|-REG|A10 A|A10 A9to A4|A3|A2 A1 A0 Offset|A2 A1 A0 Offset|A2 A1 A0 Offset|A2 A1 A0 Offset|-OE=0|-WE=0|
|---|---|---|---|---|---|---|---|---|---|
|1|0|X|0|0|0|0|0h|Even Data Register|Even Data Register|
|1|0|X|0|0|0|1|1h|Error Register|Feature Register|
|1|0|X|0|0|1|0|2h|Sector Count Register|Sector Count Register|
|1|0|X|0|0|1|1|3h|Sector Number Register|Sector Number Register|
|1|0|X|0|1|0|0|4h|Cylinder Low Register|Cylinder Low Register|
|1|0|X|0|1|0|1|5h|Cylinder High Register|Cylinder High Register|
|1|0|X|0|1|1|0|6h|Select Card/Head Register|Select Card/Head Register|
|1|0|X|0|1|1|1|7h|Status Register|Command Register|
|1|0|X|1|0|0|0|8h|Dup. Even Data Register|Dup. Even Data Register|
|1|0|X|1|0|0|1|9h|Dup. Odd Data Register|Dup. Odd Data Register|
|1|0|X|1|1|0|1|Dh|Dup. Error Register|Dup. Feature Register|
|1|0|X|1|1|1|0|Eh|Alternate Status Register|Device Control Register|
|1|0|X|1|1|1|1|Fh|Drive Address Register|Reserved|
|1|1|X|X|X|X|0|8h|Even Data Register|Even Data Register|
|1|1|X|X|X|X|1|9h|Odd Data Register|Odd Data Register|
## **8.3 Contiguous I/O Mapped Addressing**
When the system decodes a contiguous block of I/O registers to select the Card, the registers are accessed in the block of I/O space decoded by the system as shown in Table 46.
Address A0 must be low for all word accesses. As for the Memory Mapped Addressing, register 0 is accessed with – CE1 Low and –CE2 Low ( A0 must be 0 ) as a Word register on the combined Odd and Even Data Bus (D15 to D0). This register may also be accessed with –CE1 Low and –CE2 High, by a pair of Byte accesses to offset 0. The address space of this Word register overlaps the address space of the Error and Feature Byte-wide registers at offset 1. When accessed twice as Byte register with –CE1 Low, the first Byte is the even Byte of the Word and the second is the odd Byte. A Byte access to register 0 with –CE1 High and –CE2 Low accesses the error (read) or feature (write) register.
Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is equivalent to register 0, while register 9 accesses the odd Byte. Therefore, if the registers are Byte accessed in the order 9 then 8 the data will be transferred odd Byte then even Byte. Repeated Byte accesses to register 8 or 0 will access consecutive (even than odd) Bytes from the data buffer. Repeated Word accesses to register 8, 9 or 0 will access consecutive Words from the data buffer, however repeated Byte accesses to register 9 are not supported. Repeated alternating Byte accesses to registers 8 then 9 will access consecutive (even then odd) Bytes from the data buffer.
Table 46: Contiguous I/O Decoding
|-REG|A10 to A4A|A3|A2|A1|A0|Offset|-IORD=0|-IOWR=0|
|---|---|---|---|---|---|---|---|---|
|0|X|0|0|0|0|0h|Even Data Register|Even Data Register|
|0|X|0|0|0|1|1h|Error Register|Feature Register|
|0|X|0|0|1|0|2h|Sector Count Register|Sector Count Register|
|0|X|0|0|1|1|3h|Sector Number Register|Sector Number Register|
|0|X|0|1|0|0|4h|Cylinder Low Register|Cylinder Low Register|
|0|X|0|1|0|1|5h|Cylinder High Register|Cylinder High Register|
|0|X|0|1|1|0|6h|Select Card/Head Register|Select Card/Head Register|
|0|X|0|1|1|1|7h|Status Register|Command Register|
|0|X|1|0|0|0|8h|Dup. Even Data Register|Dup. Even Data Register|
|0|X|1|0|0|1|9h|Dup. Odd Data Register|Dup. Odd Data Register|
|0|X|1|1|0|1|Dh|Dup. Error Register|Dup. Feature Register|
|0|X|1|1|1|0|Eh|Alternate Status Register|Device Control Register|
|0|X|1|1|1|1|Fh|Drive Address Register|Reserved|
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## **8.4 I/O Primary and Secondary Address Configurations**
When the system decodes the Primary and Secondary Address Configurations, the registers are accessed in the block of I/O space as shown in Table 47.
Address A0 must be low for all word accesses. As for the Memory Mapped Addressing, register 0 is accessed with – CE1 Low and –CE2 Low ( A0 must be 0 ) as a Word register on the combined Odd and Even Data Bus (D15 to D0). This register may also be accessed with –CE1 Low and –CE2 High, by a pair of Byte accesses to offset 0. The address space of this Word register overlaps the address space of the Error and Feature Byte-wide registers at offset 1. When accessed twice as Byte register with –CE1 Low, the first Byte is the even Byte of the Word and the second is the odd Byte. A Byte access to register 0 with –CE1 High and –CE2 Low accesses the error (read) or feature (write) register.
Table 47: Primary and Secondary I/O Decoding
|-REG|A9to A4|A3|A2|A1|A0|-IORD=0|-IOWR=0|
|---|---|---|---|---|---|---|---|
|0|1F(17)h|0|0|0|0|Even Data Register|Even Data Register|
|0|1F(17)h|0|0|0|1|Error Register|Feature Register|
|0|1F(17)h|0|0|1|0|Sector Count Register|Sector Count Register|
|0|1F(17)h|0|0|1|1|Sector Number Register|Sector Number Register|
|0|1F(17)h|0|1|0|0|Cylinder Low Register|Cylinder Low Register|
|0|1F(17)h|0|1|0|1|Cylinder High Register|Cylinder High Register|
|0|1F(17)h|0|1|1|0|Select Card/Head Register|Select Card/Head Register|
|0|1F(17)h|0|1|1|1|Status Register|Command Register|
|0|3F(37)h|0|1|1|0|Alternate Status Register|Device Control Register|
|0|3F(37)h|0|1|1|1|Drive Address Register|Reserved|
## **8.5 True IDE Mode Addressing**
When the Card is configured in the True IDE Mode, the I/O decoding is as shown in Table 48.
## Table 48: True IDE Mode I/O Decoding
|-CS1|-CS0|A2|A1|A0|-DMACK|-IORD=0|-IOWR=0|
|---|---|---|---|---|---|---|---|
|1|0|0|0|0|1|PIO RD Data|PIO WR Data|
|1|1|X|X|X|0|DMA RD Data|DMA WR Data|
|1|0|0|0|1|1|Error Register|Features|
|1|0|0|1|0|1|Sector Count|Sector Count|
|1|0|0|1|1|1|Sector No.|Sector No.|
|1|0|1|0|0|1|Cylinder Low|Cylinder Low|
|1|0|1|0|1|1|Cylinder High|Cylinder High|
|1|0|1|1|0|1|Select Card/Head|Select Card/Head|
|1|0|1|1|1|1|Status|Command|
|0|1|1|1|0|1|Alt Status|Control Register|
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## **9 CF-ATA Registers**
The following section describes the hardware registers used by the host software to issue commands to the Card. These registers are collectively referred to as the ‘task file’.
In accordance with the PCMCIA specification, each register that is located at an odd offset address can be accessed in the PC Card Memory or PC Card I/O modes. The register can be addressed in two ways:
- Using the normal register address.
- Using the corresponding even address (normal address -1) when –CE1 is High and –CE2 Low, unless –IOIS16 is High (not asserted by the card) and an I/O cycle is in progress. Register data are input or output on data bus lines D15-D8.
In True IDE mode, the size of the transfer is based solely on the register being addressed. All registers are 8-bit only except for the Data Register, which is normally 16 bits. However, they can be configured to be accessed in 8- bit mode for non-DMA operations, by using a Set Features command (see Section 10.25 ).
There are situations possible where the C-440 CompactFlash Card is not compatible to certain PC-Card (PCMCIA) host systems. PC-Card mode, 16 bit ATA register file accesses (i.e. both -CE1 and -CE2 low) aren’t working if A0 is high (odd addresses). The IOIS16 signal might also not work correctly. If a host uses this signal, this may result in 16 bit accesses being changed to two 8 bit accesses. Depending on the address, this may fail.
A simple test will show the C-400 compatibility to a certain host. If the C-400 cards can be recognized (Identify Device and MBR data is read out successfully), then this PC card issue will likely not affect the operation in this host. Host systems with IDE/ATA interface are not affected by the issue, described above.
## **9.1 Data Register**
The Data register is located at address 1F0h [170h], offset 0h, 8h, and 9h.
The Data Register is a 16 bit register used to transfer data blocks between the Card data buffer and the Host. This register overlaps the Error Register. Table 49 and Table 50 describe the combinations of Data register access and explain the overlapped Data and Error/Feature Registers. Because of the overlapped registers, access to the 1F1h, 171h or offset 1 are not defined for Word (-CE2 and –CE1 set to ‘0’) operations, and are treated as accesses to the Word Data Register. The duplicated registers at offsets 8, 9 and Dh have no restrictions on the operations that can be performed.
Table 49: Data Register Access (Memory and I/O mode)
|Table 49: Data Register Access (Memory and I/O mode)|Table 49: Data Register Access (Memory and I/O mode)|Table 49: Data Register Access (Memory and I/O mode)||~~(1)~~|||
|---|---|---|---|---|---|---|
|Data Register|-CE2|-CE1|A0|-REG~~(1)~~|Offset|Data Bus|
|WordDataRegister|0|0|0**(2)**|-|0h, 8h, 9h|D15 toD0|
|Even Data Register|1|0|0|-|0h, 8h|D7 to D0|
|Odd Data Register|1|0|1|-|9h|D7 to D0|
|Odd Data Register|0|1|X|-|8h, 9h|D15 to D8|
|Error/Feature Register|1|0|1|-|1h, Dh|D7 to D0|
|Error/Feature Register|0|1|X<br>~~**(2)**~~|-|1h|D15 to D8|
|Error/FeatureRegister|0|0|0~~**(2)**~~|-|Dh|D15 toD8|
1 –REG signal is mode dependent. It must be Low when the Card operates in I/O Mode and High when it operates in Memory Mode.
2 In current C-400 cards A0 must be 0 for all word accesses (if –CE2 and –CE1 are 0).
Table 50: Data Register Access (True IDE mode)
|Data Register|-CS1|-CS0|A0|-DMACK|Offset|Data Bus|
|---|---|---|---|---|---|---|
|PIO Word Data Register|1|0|0|1|0h|D15 to D0|
|DMA Word Data Register|1|1|X|0|X|D15 to D0|
|PIO Byte Data Register (Selected Using Set<br>Features Command)|1|0|0|1|0h|D7 to D0|
## **9.2 Error Register**
The Error register is a read-only register, located at address 1F1h [171h], offset 1h, 0Dh.
This read only register contains additional information about the source of an error when an error is indicated in bit 0 of the Status register. The bits are defined in Table 51 This register is accessed on data bits D15 to D8 during a write operation to offset 0 with –CE2 Low and –CE1 High.
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## 9.2.1 Bit 7 (BBK)
This bit is set when a Bad Block is detected.
## 9.2.2 Bit 6 (UNC)
This bit is set when an Uncorrectable Error is encountered.
## 9.2.3 Bit 5
This bit is ‘0’.
## 9.2.4 Bit 4 (IDNF)
This bit is set if the requested sector ID is in error or cannot be found.
## 9.2.5 Bit 3
This bit is ‘0’.
## 9.2.6 Bit 2 (Abort)
This bit is set if the command has been aborted because of a Card status condition (Not Ready, Write Fault, etc.) or when an invalid command has been issued.
## 9.2.7 Bit 1
This bit is ‘0’.
## 9.2.8 Bit 0 (AMNF)
This bit is set when there is a general error.
## Table 51: Error Register
|D7<br>~~Ee~~|D6<br>~~Ee~~|D5|D4|D3|D2|D1|D0|
|---|---|---|---|---|---|---|---|
|BBK<br>~~Ee~~|UNC<br>~~Ee~~|0|IDNF|0|ABRT|0|AMNF|
## **9.3 Feature Register**
The Feature register is a write-only register, located at address 1F1h [171h], offset 1h, Dh. This write-only register provides information on features that the host can utilize. It is accessed on data bits D15 to D8 during a write operation to Offset 0 with –CE2 Low and –CE1 High.
## **9.4 Sector Count Register**
The Sector Count register is located at address 1F2h [172h], offset 2h.
This register contains the number of sectors of data to be transferred on a read or write operation between the host and Card. If the value in this register is zero, a count of 256 sectors is specified. If the command was successful, this register is zero at completion. If not successfully completed, the register contains the number of sectors that need to be transferred in order to complete the request. The default value is 01h.
## **9.5 Sector Number (LBA 7:0) Register**
The Sector Number register is located at address 1F3h [173h], offset 3h.
This register contains the starting sector number or bits 7 to 0 of the Logical Block Address (LBA), for any data access for the subsequent sector transfer command.
## **9.6 Cylinder Low (LBA 15:8) Register**
The Cylinder Low register is located at address 1F4h [174h], offset 4h.
This register contains the least significant 8 bits of the starting cylinder address or bits 15 to 8 of the Logical Block Address.
## **9.7 Cylinder High (LBA 23:16) Register**
The Cylinder High register is located at address 1F5h [175h], offset 5h.
This register contains the most significant bits of the starting cylinder address or bits 23 to 16 of the Logical Block Address.
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## **9.8 Drive/Head (LBA 27:24) Register**
The Driver/Head register is located at address 1F6h [176h], offset 6h. The Drive/Head register is used to select the drive and head. It is also used to select LBA addressing instead of cylinder/head/sector addressing. The bits are defined in Table 52.
## 9.8.1 Bit 7
This bit is set to ‘1’.
## 9.8.2 Bit 6 (LBA)
LBA is a flag to select either Cylinder/Head/Sector (CHS) or Logical Block Address Mode (LBA). When LBA is set to ‘0’, Cylinder/Head/Sector mode is selected. When LBA is set to’1’, Logical Block Address is selected. In Logical Block Mode, the Logical Block Address is interpreted as follows:
- LBA7-LBA0: Sector Number Register D7 to D0
- LBA15-LBA8: Cylinder Low Register D7 to D0
- LBA23-LBA16: Cylinder High Register D7 to D0
- LBA27-LBA24: Drive/Head Register bits HS3 to HS0
## 9.8.3 Bit 5
This bit is set to ‘1’.
## 9.8.4 Bit 4 (DRV)
DRV is the drive number. When DRV is ‘0’, drive/card 0 is selected (Master). When DRV is ‘1’, drive/card 1 is selected (Slave).
## 9.8.5 Bit 3 (HS3)
When operating in the Cylinder, Head, Sector mode, this is bit 3 of the head number. It is bit 27 in the Logical Block Address mode.
## 9.8.6 Bit 2 (HS2)
When operating in the Cylinder, Head, Sector mode, this is bit 2 of the head number. It is bit 26 in the Logical Block Address mode.
## 9.8.7 Bit 1 (HS1)
When operating in the Cylinder, Head, Sector mode, this is bit 1 of the head number. It is Bit 25 in the Logical Block Address mode.
## 9.8.8 Bit 0 (HS0)
When operating in the Cylinder, Head, Sector mode, this is bit 0 of the head number. It is Bit 24 in the Logical Block Address mode.
|Table 52: Drive/Head Register<br>D7<br>D6<br>D5<br>1<br>LBA<br>1<br>~~a~~|D4<br>DRV|D3<br>HS3|D2<br>HS2|D1<br>HS1|D0<br>HS0|
|---|---|---|---|---|---|
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## **9.9 Status & Alternate Status Registers**
The Status & Alternate Status registers are located at addresses 1F7h [177h] and 3F6h [376h], respectively. Offsets are 7h and Eh.
These registers return the Card status when read by the host.
Reading the Status Register clears a pending interrupt. Reading the Auxiliary Status Register does not clear a pending interrupt.
The Status Register should be accessed in Byte mode; in Word mode it is recommended that Alternate Status Register is used. The status bits are described as follows
## 9.9.1 Bit 7 (BUSY)
The busy bit is set when only the Card can access the command register and buffer, The host is denied access. No other bits in this register are valid when this bit is set to ‘1’.
## 9.9.2 Bit 6 (RDY)
This bit indicates whether the device is capable of performing CompactFlash[TM] Memory Card operations. This bit is cleared at power up and remains cleared until the Card is ready to accept a command.
## 9.9.3 Bit 5 (DWF)
When set this bit indicates a Write Fault has occurred.
## 9.9.4 Bit 4 (DSC)
This bit is set when the Card is ready.
## 9.9.5 Bit 3 (DRQ)
The Data Request is set when the Card requires information be transferred either to or from the host through the Data register. The bit is cleared by the next command.
## 9.9.6 Bit 2 (CORR)
This bit is set when a Correctable data error has been encountered and the data has been corrected. This condition does not terminate a multi-sector read operation.
## 9.9.7 Bit 1 (IDX)
This bit is always set to ‘0’.
## 9.9.8 Bit 0 (ERR)
This bit is set when the previous command has ended in some type of error. The bits in the Error register contain additional information describing the error. In case of read or write access commands that end with an error, the address of the first sector with an error is in the command block registers. This bit is cleared by the next command.
Table 53: Status & Alternate Status Register
D7 D6 D5 D4 D3 D2 D1 D0 ~~A~~ BUSY RDY DWF DSC DRQ CORR 0 ERR **9.10 Device Control Register**
The Device Control register is located at address 3F6h [376h], offset Eh.
This Write-only register is used to control the CompactFlash[TM] Memory Card interrupt request and to issue an ATA soft reset to the Card. This register can be written even if the device is BUSY. The bits are defined as follows:
## 9.10.1 Bit 7 to 3
Don’t care. The host should reset this bit to ‘0’.
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## 9.10.2 Bit 2 (SW Rst)
This bit is set to 1 in order to force the CompactFlash[TM] Storage Card to perform an AT Disk controller Soft Reset operation. This clears Status Register and writes Diagnostic Code in Error register after a Write or Read Sector error. The Card remains in Reset until this bit is reset to ‘0.’
## 9.10.3 Bit 1 (-Ien)
When the Interrupt Enable bit is set to ‘0’, -IREQ interrupts are enabled. When the bit is set to ‘1’, interrupts from the Card are disabled. This bit also controls the Int bit in the Card Configuration and Status Register. It is set to ‘0’ at Power On.
## 9.10.4 Bit 0
This bit is set to ‘0’.
Table 54: Device Control Register
D7 D6 D5 D4 D3 D2 D1 D0 ~~A~~ X(0) X(0) X(0) X(0) X(0) SW Rst -Ien 0 **9.11 Card (Drive) Address Register**
The Card (Drive) Address register is located at address 3F7h [377h], offset Fh. This read-only register is provided for compatibility with the AT disk drive interface and can be used for confirming the drive status. It is recommended that this register is not mapped into the host’s I/O space because of potential conflicts on Bit 7. The bits are defined as follows:
## 9.11.1 Bit 7
This bit is don’t care.
## 9.11.2 Bit 6 (-WTG)
This bit is ‘0’ when a write operation is in progress; otherwise, it is ‘1’.
## 9.11.3 Bit 5 (-HS3)
This bit is the negation of bit 3 in the Drive/Head register.
## 9.11.4 Bit 4 (-HS2)
This bit is the negation of bit 2 in the Drive/Head register.
## 9.11.5 Bit 3 (-HS1)
This bit is the negation of bit 1 in the Drive/Head register.
## 9.11.6 Bit 2 (-HS0)
This bit is the negation of bit 0 in the Drive/Head register.
## 9.11.7 Bit 1 (-nDS1)
This bit is ‘0’ when drive 1 is active and selected.
## 9.11.8 Bit 0 (-nDS0)
This bit is ‘0’ when the drive 0 is active and selected.
|Table 55: Card (Drive) Address Register<br>D7<br>D6<br>D5<br>X<br>-WTG<br>-HS3<br>~~Ce~~|D4<br>-HS2|D3<br>-HS1|D2<br>-HS0|D1<br>-nDS1|D0<br>-nDS0|
|---|---|---|---|---|---|
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## **10 CF-ATA command description**
This section defines the software requirements and the format of the commands the Host sends to the Card. Commands are issued to the Card by loading the required registers in the command block with the supplied parameters, and then writing the command code to the Command Register. There are three classes of command acceptance, all dependent on the host not issuing commands unless the Card is not busy (BSY is ‘0’).
- Class 1: Upon receipt of a Class 1 command, the Card sets BSY within 400ns.
- Class 2: Upon receipt of a Class 2 command, the Card sets BSY within 400ns, sets up the sector buffer for a
- write operation, sets DRQ within 700µs, and clears BSY within 400ns of setting DRQ.
- Class 3: Upon receipt of a Class 3 command, the Card sets BSY within 400ns, sets up the sector buffer for a
- write operation, sets DRQ within 20ms (assuming no re-assignments), and clears BSY within 400ns of setting DRQ.
For reasons of backward compatibility some commands are implemented as ‘no operation’ NOP. Table 56 summarizes the CF-ATA command set with the paragraphs that follow describing the individual commands and the task file for each.
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- Table 56: CF ATA Command Set (1)
|Class|Command|Code|FR(1)|SC(2)|SN(3)|CY(5:4)|DH(6)|LBA(5:3)|
|---|---|---|---|---|---|---|---|---|
|1|Check Power Mode|E5h or98h|||||D||
|2|Data SetManagement|06h||YY|||D|YY|
|1|Erase Sector(s)|C0h||Y|Y|Y|Y|Y|
|1|ExecuteDriveDiagnostic|90h|||||D||
|1|Flushcache|E7h|||||D||
|1|Flush cache Ext|EAh|||||D||
|2|Format track|50h||Y||Y|Y|Y|
|1|IdentifyDrive|ECh|||||D||
|1|Idle|E3hor97h||Y|||D||
|1|IdleImmediate|E1hor95h|||||D||
|1|Initialize Drive Parameters|91h||Y|||Y||
|1|MediaLock|DEh|||||D||
|1|Media Unlock|DFh|||||D||
|1|NOP|00h|||||D||
|1<br>~~=~~|ReadBuffer<br>~~=~~|E4h|~~SSSSE=~~|~~SSSSE=~~|~~SSSSE=~~|~~SSSSE=~~|D<br>~~SSSSE=~~|~~SSSSE=~~|
|1<br>~~=~~|Read DMA<br>~~=~~|C8h|~~SSSSE=~~|Y<br>~~SSSSE=~~|Y<br>~~SSSSE=~~|Y<br>~~SSSSE=~~|Y<br>~~SSSSE=~~|Y<br>~~SSSSE=~~|
|1<br>~~=~~|ReadDMA Ext<br>~~=~~|25h|~~SSSSE=~~|YY<br>~~SSSSE=~~|YY<br>~~SSSSE=~~|YY<br>~~SSSSE=~~|D<br>~~SSSSE=~~|YY<br>~~SSSSE=~~|
|1<br>~~=~~|Read Multiple<br>~~=~~|C4h|~~SSSSE=~~|Y<br>~~SSSSE=~~|Y<br>~~SSSSE=~~|Y<br>~~SSSSE=~~|Y<br>~~SSSSE=~~|Y<br>~~SSSSE=~~|
|1<br>~~=~~|ReadMultipleExt<br>~~=~~|29h|~~SSSSE=~~|YY<br>~~SSSSE=~~|YY<br>~~SSSSE=~~|YY<br>~~SSSSE=~~|D<br>~~SSSSE=~~|YY<br>~~SSSSE=~~|
|1<br>~~=~~<br>~~=~~|Read Sector(s)<br>~~=~~<br>~~=~~|20hor 21h|~~SSSSE=~~<br>~~SSSSE=~~|Y<br>~~SSSSE=~~<br>~~SSSSE=~~|Y<br>~~SSSSE=~~<br>~~SSSSE=~~|Y<br>~~SSSSE=~~<br>~~SSSSE=~~|Y<br>~~SSSSE=~~<br>~~SSSSE=~~|Y<br>~~SSSSE=~~<br>~~SSSSE=~~|
|1<br>~~=~~|Read Sector(s)Ext<br>~~=~~|24h|~~SSSSE=~~|YY<br>~~SSSSE=~~|YY<br>~~SSSSE=~~|YY<br>~~SSSSE=~~|D<br>~~SSSSE=~~|YY<br>~~SSSSE=~~|
|1<br>~~=~~|ReadVerify Sector(s)<br>~~=~~|40h|~~SSSSE=~~|Y<br>~~SSSSE=~~|Y<br>~~SSSSE=~~|Y<br>~~SSSSE=~~|Y<br>~~SSSSE=~~|Y<br>~~SSSSE=~~|
|1<br>~~=~~|Read VerifySector(s)Ext<br>~~=~~|42h|~~SSSSE=~~|YY<br>~~SSSSE=~~|YY<br>~~SSSSE=~~|YY<br>~~SSSSE=~~|D<br>~~SSSSE=~~|YY<br>~~SSSSE=~~|
|1<br>~~=~~|Recalibrate<br>~~=~~|1Xh|~~SSSSE=~~|~~SSSSE=~~|~~SSSSE=~~|~~SSSSE=~~|D<br>~~SSSSE=~~|~~SSSSE=~~|
|1<br>~~=~~<br>~~=~~|Request Sense<br>~~=~~<br>~~=~~|03h|~~SSSSE=~~<br>~~SSSSE=~~|~~SSSSE=~~<br>~~SSSSE=~~|~~SSSSE=~~<br>~~SSSSE=~~|~~SSSSE=~~<br>~~SSSSE=~~|D<br>~~SSSSE=~~<br>~~SSSSE=~~|~~SSSSE=~~<br>~~SSSSE=~~|
|1<br>~~=~~|SecurityDisablePassword<br>~~=~~|F6h|~~SSSSE=~~|~~SSSSE=~~|~~SSSSE=~~|~~SSSSE=~~|D<br>~~SSSSE=~~|~~SSSSE=~~|
|1<br>~~=~~|SecurityErasePrepare<br>~~=~~|F3h|~~SSSSE=~~|~~SSSSE=~~|~~SSSSE=~~|~~SSSSE=~~|D<br>~~SSSSE=~~|~~SSSSE=~~|
|1<br>~~=~~|SecurityErase Unit<br>~~=~~|F4h|~~SSSSE=~~|~~SSSSE=~~|~~SSSSE=~~|~~SSSSE=~~|D<br>~~SSSSE=~~|~~SSSSE=~~|
|1<br>~~=~~|SecurityFreezeLock<br>~~=~~|F5h|~~SSSSE=~~|~~SSSSE=~~|~~SSSSE=~~|~~SSSSE=~~|D<br>~~SSSSE=~~|~~SSSSE=~~|
|1<br>~~=~~<br>~~=~~|Security SetPassword<br>~~=~~<br>~~=~~|F1h<br>~~=~~|~~SSSSE=~~<br>~~=~~|~~SSSSE=~~<br>~~=~~|~~SSSSE=~~<br>~~=~~|~~SSSSE=~~<br>~~=~~|D<br>~~SSSSE=~~<br>~~=~~|~~SSSSE=~~<br>~~=~~|
|1<br>~~=~~|Security Unlock<br>~~=~~|F2h<br>~~=~~|~~=~~|~~=~~|~~=~~|~~=~~|D<br>~~=~~|~~=~~|
|1<br>~~=~~|Seek<br>~~=~~|7Xh<br>~~=~~|~~=~~|~~=~~|Y<br>~~=~~|Y<br>~~=~~|Y<br>~~=~~|Y<br>~~=~~|
|1<br>~~=~~|Set Features<br>~~=~~|EFh<br>~~=~~|Y<br>~~=~~|~~=~~|~~=~~|~~=~~|D<br>~~=~~|~~=~~|
|1<br>~~=~~|SetMultipleMode<br>~~=~~|C6h<br>~~=~~|~~=~~|Y<br>~~=~~|~~=~~|~~=~~|D<br>~~=~~|~~=~~|
|1<br>~~=~~<br>~~———~~|Set SleepMode<br>~~=~~<br>~~———~~|E6hor99h<br>~~=~~<br>~~———~~|~~=~~<br>~~———~~|~~=~~<br>~~———~~|~~=~~<br>~~———~~|~~=~~<br>~~———~~|D<br>~~=~~<br>~~———~~|~~=~~<br>~~———~~|
|1<br>~~———~~|S.M.A.R.T.<br>~~———~~|B0h<br>~~———~~|Y<br>~~———~~|Y<br>~~———~~|~~———~~|Y<br>~~———~~|D<br>~~———~~|~~———~~|
|1<br>~~———~~|StandBy<br>~~———~~|E2hor96h<br>~~———~~|~~———~~|~~———~~|~~———~~|~~———~~|D<br>~~———~~|~~———~~|
|1<br>~~———~~|Stand ByImmediate<br>~~———~~|E0h or94h<br>~~———~~|~~———~~|~~———~~|~~———~~|~~———~~|D<br>~~———~~|~~———~~|
|1<br>~~———~~|Translate Sector<br>~~———~~|87h<br>~~———~~|~~———~~|Y<br>~~———~~|Y<br>~~———~~|Y<br>~~———~~|Y<br>~~———~~|Y<br>~~———~~|
|2<br>~~———~~<br>~~———~~|Write Buffer<br>~~———~~<br>~~———~~|E8h<br>~~———~~<br>~~———~~|~~———~~<br>~~———~~|~~———~~<br>~~———~~|~~———~~<br>~~———~~|~~———~~<br>~~———~~|D<br>~~———~~<br>~~———~~|~~———~~<br>~~———~~|
|2<br>~~———~~|WriteDMA<br>~~———~~|CAh<br>~~———~~|~~———~~|Y<br>~~———~~|Y<br>~~———~~|Y<br>~~———~~|Y<br>~~———~~|Y<br>~~———~~|
|2<br>~~———~~|WriteDMA Ext<br>~~———~~|35h<br>~~———~~|~~———~~|YY<br>~~———~~|YY<br>~~———~~|YY<br>~~———~~|D<br>~~———~~|YY<br>~~———~~|
|3<br>~~———~~|WriteMultiple<br>~~———~~|C5h<br>~~———~~|~~———~~|Y<br>~~———~~|Y<br>~~———~~|Y<br>~~———~~|Y<br>~~———~~|Y<br>~~———~~|
|3<br>~~———~~|WriteMultipleExt<br>~~———~~|39h<br>~~———~~|~~———~~|YY<br>~~———~~|YY<br>~~———~~|YY<br>~~———~~|D<br>~~———~~|YY<br>~~———~~|
|3<br>~~———~~<br>~~=e~~|Write Multiple w/o Erase<br>~~———~~<br>~~=e~~|CDh<br>~~———~~<br>~~=e~~|~~———~~<br>~~=e~~|Y<br>~~———~~<br>~~=e~~|Y<br>~~———~~<br>~~=e~~|Y<br>~~———~~<br>~~=e~~|Y<br>~~———~~<br>~~=e~~|Y<br>~~———~~<br>~~=e~~|
|2<br>~~=e~~|Write Sector(s)<br>~~=e~~|30hor31h<br>~~=e~~|~~=e~~|Y<br>~~=e~~|Y<br>~~=e~~|Y<br>~~=e~~|Y<br>~~=e~~|Y<br>~~=e~~|
|2<br>~~=e~~|Write Sector(s)Ext<br>~~=e~~|34h<br>~~=e~~|~~=e~~|YY<br>~~=e~~|YY<br>~~=e~~|YY<br>~~=e~~|D<br>~~=e~~|YY<br>~~=e~~|
|2<br>~~=e~~|Write Sector(s)w/oErase<br>~~=e~~|38h<br>~~=e~~|~~=e~~|Y<br>~~=e~~|Y<br>~~=e~~|Y<br>~~=e~~|Y<br>~~=e~~|Y<br>~~=e~~|
|3<br>~~=e~~|WriteVerify<br>~~=e~~|3Ch<br>~~=e~~|~~=e~~|Y<br>~~=e~~|Y<br>~~=e~~|Y<br>~~=e~~|Y<br>~~=e~~|Y<br>~~=e~~|
YY – registers must be written twice for 48bit LBA commands
D – only the Compact Flash Memory Card parameter is valid and not the head parameter C – the register contains command specific data (see command descriptors for use).
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## **10.1 Check Power Mode (98h or E5h)**
This command checks the power mode.
Issuing the command while the Card is in Standby mode, is about to enter Standby, or is exiting Standby, the command will set BSY, set the Sector Count Register to 00h, clear BSY and generate an interrupt. Issuing the command when the Card is in Idle mode will set BSY, set the Sector Count Register to FFh, clear BSY and generate an interrupt.
Table 57 defines the Byte sequence of the Check Power Mode command.
Table 57: Check Power Mode
|Task File Register<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>COMMAND<br>E5h (or Legacy 98h)<br>DRIVE/HEAD<br>nu<br>nu<br>nu<br>D<br>nu<br>CYLINDER HI<br>nu<br>CYLINDER LOW<br>nu<br>SECTOR NUM<br>nu<br>SECTOR COUNT<br>nu<br>FEATURES<br>nu<br>~~——=S====~~||
|---|---|
|**10.2 Data Set Management (06h) TRIM**||
|This 48-bit command is optional for ATA devices. The DATA SETMANAGEMENT command is not part of any feature||
|set.||
|The DATA SET MANAGEMENT command provides information for device optimization (e.g., file system information).||
|See Table 58 for the DATA SET MANAGEMENT command inputs.||
|Table 58: Data Set Management||
|register write<br>previous<br>current<br>Task File Register<br>15:8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>COMMAND<br>nu<br>06h<br>DRIVE/HEAD<br>nu<br>nu<br>L<br>nu<br>Transport<br>dependent<br>Reserved<br>LBA High<br>Reserved<br>LBA Mid<br>Reserved<br>LBA Low<br>Reserved<br>SECTOR COUNT<br>15:8<br>7:0 Number of 512-byte blocks to be transferred; the value of zero is reserved.<br>FEATURES<br>Reserved<br>TRIM<br>~~a~~||
|Currently this command is specified only for the TRIM command.||
|Currently only one 512-byte block can be transferred with one command (see Identify Device word 169).||
|Detailed information about the TRIM command is available in the ATA/ATAPI Command Set-2 (ACS-2) at||
|www.t13.org||
## **10.3 Erase Sector(s) (C0h)**
This command is used to pre-erase and condition data sectors prior to a Write Sector without Erase command or a Write Multiple Without Erase command. There is no data transfer associated with this command but a Write Fault error status can occur. Table 59 defines the Byte sequence of the Erase Sector command.
Table 59: Erase Sector(s) Task File Register 7 6 5 4 3 2 1 0 COMMAND C0h DRIVE/HEAD nu L nu D H[3:0] or LBA[27:24] of the starting sector/LBA CYLINDER HI Cylinder[15:8] or LBA[23:16] of the first sector/LBA to erase CYLINDER LOW Cylinder[7:0] or LBA[15:8] of the first sector/LBA to erase SECTOR NUM Sector[7:0] or LBA[7:0] of the first sector/LBA to erase SECTOR COUNT The number of sectors/logical blocks to erase ~~SS~~ FEATURES nu **10.4 Execute Drive Diagnostic (90h)** This command performs the internal diagnostic tests implemented by the Card.
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In PCMCIA configuration, this command only runs on the Card which is addressed by the Drive/Head register when the command is issued. This is because PCMCIA Card interface does not allow for direct inter-drive communication.
In True IDE Mode, the Drive bit is ignored and the diagnostic command is executed by both the Master and the Slave with the Master responding with the status for both devices.
Table 60 defines the Execute Drive Diagnostic command Byte sequence. The Diagnostic codes shown in Table 61 are returned in the Error Register at the end of the command.
Table 60: Execute Drive Diagnostic
Task File Register 7 6 5 4 3 2 1 0 COMMAND 90h DRIVE/HEAD nu nu nu D nu CYLINDER HI nu CYLINDER LOW nu SECTOR NUM nu SECTOR COUNT nu ~~===~~ FEATURES nu Table 61: Diagnostic Codes Code Error Type 01h No Error Detected 02h Formatter Device Error 03h Sector Buffer Error 04h ECC Circuitry Error 05h Controlling Microprocessor Error ~~———~~ 8Xh Slave Error in True IDE Mode **10.5 Flush Cache (E7h)** This command causes the card to complete writing data from its cache. The card returns status with RDY=1 and DSC=1 after the data in the write cache buffer is written to the media. If the Compact Flash Storage Card does not support the Flush Cache command, the Compact Flash Storage Card shall return command aborted. Table 62: Flush Cache Task File Register 7 6 5 4 3 2 1 0 COMMAND E7h DRIVE/HEAD nu nu nu D nu CYLINDER HI nu CYLINDER LOW nu SECTOR NUM nu SECTOR COUNT nu ~~=~~ FEATURES nu **10.6 Flush Cache Ext (EAh) 48bit LBA** This command causes the card to complete writing data from its volatile cache into non-volatile memory. The BSY bit shall remain set to one until all data has been successfully written or an error occurs. The card returns status with RDY=1 and DSC=1 after the data in the write cache buffer is written to the media. If the Compact Flash Storage Card does not support the Flush Cache Ext command, the Compact Flash Storage Card shall return command aborted. See Table 63 for the DATA SET MANAGEMENT command inputs.
Table 63: Flush cache Ext
|register write|previous|current|current|current|current|current|current|current|current|
|---|---|---|---|---|---|---|---|---|---|
|Task File Register|15:8|7|6|5|4|3|2|1|0|
|COMMAND|-|EAh||||||||
|DRIVE/HEAD|-|1|1|1|Drive|Reserved||||
|LBA High|nu|nu||||||||
|LBA Mid|nu|nu||||||||
|LBA Low|nu|nu||||||||
|SECTOR COUNT|nu|nu||||||||
|FEATURES|nu|nu||||||||
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An unrecoverable error encountered while writing data results in aborting the command and the Command Block registers contain the 48 –bit sector address of the sector where the first unrecoverable error occurred. Subsequent FLUSH CACHE EXT commands continue the process of flushing the cache starting with the first sector after the sector in error.
This command is used by the host to request the device to flush the write cache. If there is data in the write cache, that data shall be written to the media. The BSY bit shall remain set to one until all data has been successfully written or an error occurs.
## **10.7 Format track (50h)**
This command writes the desired head and cylinder of the selected drive with a vendor unique data pattern (typically FFh or 00h). To remain host backward compatible, the CompactFlash[TM] Storage Card expects a sector buffer of data from the host to follow the command with the same protocol as the Write Sector(s) command although the information in the buffer is not used by the CompactFlash[TM] Storage Card. If LBA=1 then the number of sectors to format is taken from the Sec Cnt register (0=256). The use of this command is not recommended.
Table 64: Format track
|Table 64: Format track|||||||||
|---|---|---|---|---|---|---|---|---|
|Task File Register|7|6|5|4|3|2|1|0|
|COMMAND|50h||||||||
|DRIVE/HEAD|nu|L|nu|D|H[3:0] or LBA[27:24] of the starting<br>sector/LBA||||
|CYLINDER HI|Cylinder[15:8] or LBA[23:16] of the first sector/LBA||||||||
|CYLINDER LOW|Cylinder[7:0] or LBA[15:8] of the first sector/LBA||||||||
|SECTOR NUM|nu||||||||
|SECTOR COUNT|Sector Count (LBA only)||||||||
|FEATURES|nu||||||||
## **10.8 Identify Device (ECh)**
The Identify Device command enables the host to receive parameter information from the Card. This command has the same protocol as the Read Sector(s) command. Table 65 defines the Identify Device command Byte sequence. All reserved bits or Words are zero.
Identify Device table shows the definition of each field in the Identify Drive Information.
Table 65: Identify Device
|Table 65: Identify Device|||||||||
|---|---|---|---|---|---|---|---|---|
|Task File Register|7|6|5|4|3|2|1|0|
|COMMAND|ECh||||||||
|DRIVE/HEAD|nu|nu|nu|D|nu||||
|CYLINDER HI|nu||||||||
|CYLINDER LOW|nu||||||||
|SECTOR NUM|nu||||||||
|SECTOR COUNT|nu||||||||
|FEATURES|nu||||||||
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Table 66: Identify Device Information
|Table 66: Identify Device Information<br>~~es~~|Table 66: Identify Device Information<br>|Table 66: Identify Device Information<br>|Table 66: Identify Device Information<br>|
|---|---|---|---|
|Word<br>Address<br>~~es~~|Default<br>Value<br>|Total<br>Bytes<br>|Data Field Type Information<br>|
|0<br>~~es———~~<br>~~pf~~|848Ah*<br>~~———~~|2<br>~~———~~|General Configuration (REMOVABLE, signature of the CompactFlashTMMemory Card) In<br>PC card mode the HxBU cards have normally the value 848Ah<br>but other configurations are possible<br>~~———~~|
||045Ah*<br>~~———~~<br>~~pf~~|2<br>~~———~~|Alternate Configuration FIX,<br>In IDE mode the HxBU cards have normally the value 045Ah<br>but other configurations are possible<br>~~———~~|
|1<br>~~pf~~|XXXXh<br>~~pf~~|2|Default number of cylinders|
|2<br>~~pf~~|0000h<br>~~pf~~|2|Reserved|
|3|00XXh|2|Default number of heads|
|4|0000h|2|Obsolete|
|5|0200h|2|Obsolete|
|6|XXXXh|2|Default number of sectors per track|
|7-8|XXXXh|4|Number of sectors per Card (Word 7=MSW, Word 8=LSW)|
|9|0000h|2|Obsolete|
|10-19|aaaa|20|Serial number in ASCII (right justified)|
|20|0002h|2|Buffer type|
|21|0001h|2|Buffer size|
|22|0004h|2|Reserved|
|23-26|aaaa*|8|Firmware revision in ASCII. Big Endian Byte Order in Word|
|27-46<br>~~a~~|aaaa*<br>~~a~~|40|Model number in ASCII (right justified) Big Endian Byte Order in Word<br>(“SFCFxxxxHxBUxTO-x-xx-xxx-xxx”)|
|47<br>~~a~~|8001h<br>~~a~~|2|Maximum number of sectors on Read/Write Multiple command|
|48<br>~~a~~|0000h<br>~~a~~|2|Reserved|
|49<br>~~a~~|0F00h*<br>0E00h*<br>~~aa~~|2|Capabilities with DMA<br>without DMA|
|50<br>~~a~~|4001h<br>~~aa~~|2|Capabilities: device specific standby timer minimum|
|51|0200h|2|PIO data transfer cycle timing mode|
|52|0000h|2|Obsolete|
|53|0007h*|2|Field validity|
|54|XXXXh|2|Current numbers of cylinders|
|55|XXXXh|2|Current numbers of heads|
|56|XXXXh|2|Current sectors per track|
|57-58|XXXXh|4|Current capacity in sectors (cylinders*heads*sectors)(Word 57=LSW, Word 58=MSW)|
|59|010Xh|2|Multiple sector setting is valid|
|60-61|XXXXh|4|Total number of sectors addressable in LBA Mode|
|62<br>~~a~~|0000h<br>~~a~~|2<br>~~a~~|Single-Word DMA not implemented|
|63<br>~~a~~|0007h*<br>0000h*<br>~~a~~|2<br>~~a~~|Multi-Word DMA transfer Mode 0, 1, 2<br>for In PC card mode, this value is‘0000h’.|
|64<br>~~a ~~<br>~~es~~|0003h<br> ~~a~~<br>~~ee~~|2<br>~~a~~|Advanced PIO modes supported|
|65<br>~~es~~<br>~~pf~~|0078h*<br>0000h*<br>~~ee~~<br>~~pf~~|2<br>|Minimum Multi-Word DMA transfer cycle time per Word.<br>|
|66<br>~~es ~~<br>~~pf~~|0078h*<br>0000h*<br> ~~ee~~<br>~~pfff~~|2<br>~~ff~~|Recommended Multi-Word DMA transfer cycle time.<br>~~ff~~|
|67<br>~~pf~~|0078h*<br>~~pfff~~|2<br>~~ff~~|Minimum PIO transfer cycle time without flow control<br>~~ff~~|
|68<br>~~pf~~<br>~~a~~|0078h*<br>~~pf~~|2<br>|Minimum PIO transfer cycle time with IORDY flow control<br>|
|69-79<br>~~a~~<br>~~es~~|0000h|22|Reserved|
|80-81<br>~~a~~<br>~~es~~|01E0h<br>0000h|4|ATA version 5,6,7,8|
|82 -84<br>~~es~~<br>~~a~~<br>~~pf}~~|702Bh*<br>7405h*<br>4020h*<br>~~pf}ff~~|6<br>~~ff~~<br>~~|~~|Features/command sets supported|
|85-87<br>~~a~~<br>~~pf}~~|7009h*<br>3405h*<br>4000h*<br>~~pf}ff~~|6<br>~~ff~~<br>~~|~~|Features/command sets enabled|
|88<br>~~pf}~~|207Fh*<br>~~pf}ff~~|2<br>~~ff~~<br>~~|~~|Ultra DMA Mode 0,1,2,3,4,5,6 Supported and Selected(changes in operation)|
|89<br>~~pf}~~<br>~~a~~|0000h<br>~~pf} ff~~<br>~~a~~|2<br>~~ff~~<br>~~|~~<br>~~a~~|Time required for Securityerase unit completion<br>~~a~~|
|90<br>~~a~~|0000h<br>~~a~~|2<br>~~a~~|Time required for Enhanced securityerase unit completion<br>~~a~~|
|91<br>~~a~~|0000h<br>~~a~~|2<br>~~a~~|Current Advancedpower mana9ementvalue<br>~~a~~|
|92<br>~~a~~|FFFEh*<br>~~a~~|2<br>~~a~~|Master Password Revision Code<br>~~a~~|
|93<br>~~ss~~|XXXXh*<br>0000h<br>~~ss~~|2<br>|Hardware reset result, 0000h in PC card mode<br>|
|94-99<br>~~a~~|0000h<br>~~a~~|12<br>~~a~~|Reserved<br>~~a~~|
|100-103<br>~~a~~|XXXXh<br>~~a~~|8<br>~~a~~|Total number of sectors addressable in LBA48 mode<br>~~a~~|
|~~ae~~|~~ee~~|||
|---|---|---|---|
|Word<br>Address<br>~~ae~~<br>~~ee~~|Default<br>Value<br>~~ee~~<br>~~ee~~|Total<br>Bytes|Data Field Type Information|
|104<br>~~ae~~<br>~~ee~~|0000h<br>~~ee~~<br>~~ee~~|2|Reserved|
|105<br>~~ee ~~<br>~~es~~<br>~~ee Ps~~|0001h<br> ~~ee~~<br>~~es~~<br>~~Ps~~|2|Number of sectorsper Data Set Management command|
|106-107<br>~~es~~<br>~~ee Ps~~<br>~~ee~~|0000h<br>~~es~~<br>~~Ps~~<br>~~ns Gn~~|4<br>~~Gn~~|Reserved|
|108-111<br>~~ee Ps~~<br>~~ee~~<br>~~ee~~|0000h*<br>~~Ps~~<br>~~ns Gn~~<br>~~ns Gn~~|8<br>~~Gn~~<br>~~Gn~~|World Wide Name|
|112-127<br>~~ee~~<br>~~ee~~<br>~~ee~~|0000h*<br>~~ns Gn~~<br>~~ns Gn~~<br>~~ns Gn~~|36<br>~~Gn~~<br>~~Gn~~<br>~~Gn~~|Reserved|
|128<br>~~ee~~<br>~~ee~~<br>~~ee~~|0XXXh*<br>~~ns Gn~~<br>~~ns Gn~~<br>~~ns Gn~~|2<br>~~Gn~~<br>~~Gn~~<br>~~Gn~~|Securitystatus|
|129<br>~~ee~~<br>~~ee~~<br>~~ee~~|XX00h<br>~~ns Gn~~<br>~~ns Gn~~<br>~~ns Gn~~|2<br>~~Gn~~<br>~~Gn~~<br>~~Gn~~|Write Protect Status|
|130-159<br>~~ee~~<br>~~ee~~<br>~~ee~~|0000h<br>~~ns Gn~~<br>~~ns Gn~~<br>~~ns Gn~~|60<br>~~Gn~~<br>~~Gn~~<br>~~Gn~~|vendor unique bytes|
|160<br>~~ee~~<br>~~ee~~<br>~~ee~~|A064h*<br>~~ns Gn~~<br>~~ns Gn~~<br>~~ns Gn~~|2<br>~~Gn~~<br>~~Gn~~<br>~~Gn~~|Power requirement description(100mA)*|
|161<br>~~ee~~<br>~~ee~~<br>~~ee~~|0000h<br>~~ns Gn~~<br>~~ns Gn~~<br>~~ns Gn~~|2<br>~~Gn~~<br>~~Gn~~<br>~~Gn~~|Reserved for assignment bythe CFA|
|162<br>~~ee~~<br>~~ee~~<br>~~ee~~|0000h<br>~~ns Gn~~<br>~~ns Gn~~<br>~~ns Gn~~|2<br>~~Gn~~<br>~~Gn~~<br>~~Gn~~|Keymanagement schemes not supported|
|163<br>~~ee~~<br>~~ee~~<br>~~ee~~|0012h*<br>~~ns Gn~~<br>~~ns Gn~~<br>~~ee~~|2<br>~~Gn~~<br>~~Gn~~<br>~~es~~|CF Advanced True lDE TimingMode Capabilityand Setting (PIO6/MDMA4)*|
|164<br>~~ee~~<br>~~ee~~<br>~~ee~~|001Bh*<br>8D9Bh*<br>~~ns Gn~~<br>~~ee~~<br>~~ns Gn~~|2<br>~~Gn~~<br>~~es~~<br>~~Gn~~|CF Advanced PC card I/O and Memory Timing Mode Capability|
|165-168<br>~~ee~~<br>~~ee~~<br>~~ee~~|0000h<br>~~ee ~~<br>~~ns Gn~~|8<br> ~~es~~<br>~~Gn~~|Reserved|
|169<br>~~ee~~<br>~~ee~~|0001h<br>~~ns Gn~~|2<br>~~Gn~~|Trim bit in Data Set Management supported|
|170-216<br>~~ee~~<br>~~a~~<br>~~ee~~|0000h<br>~~es~~|94|Reserved|
|217<br>~~a~~<br>~~ee~~<br>~~ee~~|0001h<br>~~es~~<br>~~es~~|2|Solid State Device(non-rotatingmedia)|
|218-254<br>~~ee~~<br>~~ee~~<br>~~ee~~|0000h<br>~~es~~<br>~~es~~<br>~~es~~|74<br>~~Se~~|Reserved|
|255<br>~~ee~~<br>~~ee~~|XXA5<br>~~es~~<br>~~es~~|2<br>~~Se~~|IntegrityWord|
* Standard values for full functionality, depending on configuration XXXX Depending on Card capacity and drive geometry
## 10.8.1 Word 0: General Configuration
This field indicates the general characteristics of the device.
The default value for Word 0 is set to 848Ah . It is recommended that PC card modes of operation report only the 848Ah value as they are always intended as removable devices.
Alternate Configuration Values for Word 0 is 045Ah .
Some operating systems require Bit 6 of Word 0 to be set to ‘1’ (Non-removable device) to use the Card as the root storage device. The Card must be the root storage device when a host completely replaces conventional disk storage with a CompactFlash[TM] Card in True IDE mode. To support this requirement and provide capability for any future removable media cards, alternate value of Word 0 is set in True IDE Mode of operation.
## 10.8.2 Word 1: Default Number of Cylinders
This field contains the number of translated cylinders in the default translation mode. This value will be the same as the number of cylinders.
## 10.8.3 Word 3: Default Number of Heads
This field contains the number of translated heads in the default translation mode.
## 10.8.4 Word 6: Default Number of Sectors per Track
This field contains the number of sectors per track in the default translation mode.
## 10.8.5 Word 7-8: Number of Sectors per Card
This field contains the number of sectors per Card. This double Word value is also the first invalid address in LBA translation mode.
## 10.8.6 Word 10-19: Memory Card Serial Number
The contents of this field are right justified and padded without spaces (20h).
## 10.8.7 Word 23-26: Firmware Revision
This field contains the revision of the firmware for this product.
## 10.8.8 Word 27-46: Model Number
This field contains the model number for this product and is left justified and padded with spaces (20h).
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## 10.8.9 Word 47: Read/Write Multiple Sector Count
This field contains the maximum number of sectors that can be read or written per interrupt using the Read Multiple or Write Multiple commands.
## 10.8.10 Word 49: Capabilities
- Bit 13 Standby Timer: is set to ’0’ to indicate that the Standby timer operation is defined by the manufacturer.
- Bit 11: IORDY Supported If bit 11 is set to 1 then this CompactFlash[TM] Storage Card supports IORDY operation. If bit 11 is set to 0 then this CompactFlash[TM] Storage Card may support IORDY operation.
- Bit 10: IORDY may be disabled
- Bit 10 shall be set to 0, indicating that IORDY may not be disabled.
- Bit 9 LBA support: CompactFlash[TM] Memory Cards support LBA mode addressing.
- Bit 8 DMA Support: Read/Write DMA commands are supported.
## 10.8.11 Word 51: PIO Data Transfer Cycle Timing Mode
This field defines the mode for PIO data transfer. For backward compatibility with BIOSs written before Word 64 was defined for advanced modes, a device reports in Word 51, the highest original PIO mode it can support (PIO mode 0, 1 or 2). Bits 15:8: are set to 02H.
## 10.8.12 Word 53: Translation Parameter Valid
- Bit 0: is set to ‘1’ to indicate that Words 54 to 58 are valid
- Bit 1: is set to ‘1’ to indicate that Words 64 to 70 are valid
- Bit 2 shall be set to 1 indicating that word 88 is valid and reflects the supported True IDE UDMA
## 10.8.13 Word 54-56: Current Number of Cylinders, Heads, Sectors/Track
These fields contain the current number of user addressable Cylinders, Heads, and Sectors/Track in the current translation mode.
## 10.8.14 Word 57-58: Current Capacity
This field contains the product of the current cylinders, heads and sectors.
## 10.8.15 Word 59: Multiple Sector Setting
- Bits 15-9 are reserved and must be set to ‘0’.
- Bit 8 is set to ‘1’, to indicate that the Multiple Sector Setting is valid.
- Bits 7-0 are the current setting for the number of sectors to be transferred for every interrupt, on
- Read/Write Multiple commands; the only values returned are ‘00h’ or ‘01h’.
## 10.8.16 Word 60-61: Total Sectors Addressable in LBA Mode
This field contains the number of sectors addressable for the Card in LBA mode only.
## 10.8.17 Word 63: Multi-Word DMA transfer
Bits 15 through 8 of word 63 of the Identify Device parameter information is defined as the Multiword DMA mode selected field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit significant. Only one of bits may be set to one in this field by the CompactFlash[TM] Storage Card to indicate the multiword DMA mode which is currently selected.
Of these bits, bits 15 through 11 are reserved. Bit 8, if set to one, indicates that Multiword DMA mode 0 has been selected. Bit 9, if set to one, indicates that Multiword DMA mode 1 has been selected. Bit 10, if set to one, indicates that Multiword DMA mode 2 has been selected.
Selection of Multiword DMA modes 3 and above are specific to CompactFlash[TM] are reported in word 163 as described in Word 163.
Bits 7 through 0 of word 63 of the Identify Device parameter information is defined as the Multiword DMA data transfer supported field. If this field is supported, bit 1 of word 53 shall be set to one. This field is bit significant. Any number of bits may be set to one in this field by the CompactFlash[TM] Storage Card to indicate the Multiword DMA modes it is capable of supporting.
Of these bits, bits 7 through 2 are reserved. Bit 0, if set to one, indicates that the CompactFlash[TM] Storage Card supports Multiword DMA mode 0. Bit 1, if set to one, indicates that the CompactFlash[TM] Storage Card supports
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Multiword DMA modes 1 and 0. Bit 2, if set to one, indicates that the CompactFlash[TM] Storage Card supports Multiword DMA modes 2, 1 and 0.
Support for Multiword DMA modes 3 and above are specific to CompactFlash[TM] are reported in word 163 as described in Word 163.
## 10.8.18 Word 64: Advanced PIO transfer modes supported
This field is bit significant. Any number of bits may be set to ‘1’ in this field by the CompactFlash[TM] Memory Card to indicate the advanced PIO modes it is capable of supporting.
3 Bits 7-2 are reserved for future advanced PIO modes.
4 Bit 1 is set to ‘1’, indicates that the CompactFlash[TM] Memory Card supports PIO mode 4. 5 Bit 0 is set to ‘1’ to indicate that the CompactFlash[TM] Memory Card supports PIO mode 3. Support for PIO modes 5 and above are specific to CompactFlash[TM] are reported in word 163 as described in Word 163.
## 10.8.19 Word 65: Minimum Multi-Word DMA transfer cycle time
Word 65 of the parameter information of the Identify Device command is defined as the minimum Multiword DMA transfer cycle time. This field defines, in nanoseconds, the minimum cycle time that, if used by the host, the CompactFlash[TM] Storage Card guarantees data integrity during the transfer.
If this field is supported, bit 1 of word 53 shall be set to one. The value in word 65 shall not be less than the minimum cycle time for the fastest DMA mode supported by the device. This field shall be supported by all CompactFlash[TM] Storage Cards supporting DMA modes 1 and above. If bit 1 of word 53 is set to one, but this field is not supported, the Card shall return a value of zero in this field.
## 10.8.20 Word 66: Recommended Multi-Word DMA transfer cycle time
Word 66 of the parameter information of the Identify Device command is defined as the recommended Multiword DMA transfer cycle time. This field defines, in nanoseconds, the cycle time that, if used by the host, may optimize the data transfer from by reducing the probability that the CompactFlash[TM] Storage Card will need to negate the DMARQ signal during the transfer of a sector.
If this field is supported, bit 1 of word 53 shall be set to one. The value in word 66 shall not be less than the value in word 65. This field shall be supported by all CompactFlash[TM] Storage Cards supporting DMA modes 1 and above. If bit 1 of word 53 is set to one, but this field is not supported, the Card shall return a value of zero in this field.
## 10.8.21 Word 67: Minimum PIO transfer cycle time without flow control
Word 67 of the parameter information of the Identify Device command is defined as the minimum PIO transfer without flow control cycle time. This field defines, in nanoseconds, the minimum cycle time that, if used by the host, the CompactFlash[TM] Storage Card guarantees data integrity during the transfer without utilization of flow control.
If this field is supported, Bit 1 of word 53 shall be set to one.
Any CompactFlash[TM] Storage Card that supports PIO mode 3 or above shall support this field, and the value in word 67 shall not be less than the value reported in word 68.
If bit 1 of word 53 is set to one because a CompactFlash[TM] Storage Card supports a field in words 64-70 other than this field and the CompactFlash[TM] Storage Card does not support this field, the CompactFlash[TM] Storage Card shall return a value of zero in this field.
## 10.8.22 Word 68: Minimum PIO transfer cycle time with IORDY
Word 68 of the parameter information of the Identify Device command is defined as the minimum PIO transfer with IORDY flow control cycle time. This field defines, in nanoseconds, the minimum cycle time that the CompactFlash[TM] Storage Card supports while performing data transfers while utilizing IORDY flow control. If this field is supported, Bit 1 of word 53 shall be set to one.
Any CompactFlash[TM] Storage Card that supports PIO mode 3 or above shall support this field, and the value in word 68 shall be the fastest defined PIO mode supported by the CompactFlash[TM] Storage Card.
If bit 1 of word 53 is set to one because a CompactFlash[TM] Storage Card supports a field in words 64-70 other than this field and the CompactFlash[TM] Storage Card does not support this field, the CompactFlash[TM] Storage Card shall return a value of zero in this field.
## 10.8.23 Words 82-84: Features/command sets supported
Words 82, 83, and 84 shall indicate features/command sets supported. The value 0000h or FFFFh was placed in each of these words by CompactFlash[TM] Storage Cards prior to ATA-3 and shall be interpreted by the host as meaning that features/command sets supported are not indicated. Bits 1 through 13 of word 83 and bits 0 through 13 of word 84 are reserved. Bit 14 of word 83 and word 84 shall be set to one and bit 15 of word 83 and word 84
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shall be cleared to zero to provide indication that the features/command sets supported words are valid. The values in these words should not be depended on by host implementers.
- If bit 0 of word 82 is set to one, the SMART feature set is supported.
- If bit 1 of word 82 is set to one, the Security Mode feature set is supported.
- Bit 2 of word 82 shall be set to zero; the Removable Media feature set is not supported.
- Bit 3 of word 82 shall be set to one; the Power Management feature set is supported.
- Bit 4 of word 82 shall be set to zero; the Packet Command feature set is not supported.
- If bit 5 of word 82 is set to one, write cache is supported.
- If bit 6 of word 82 is set to one, look-ahead is supported.
- Bit 7 of word 82 shall be set to zero; release interrupt is not supported.
- Bit 8 of word 82 shall be set to zero; Service interrupt is not supported.
- Bit 9 of word 82 shall be set to zero; the Device Reset command is not supported.
- Bit 10 of word 82 shall be set to zero; the Host Protected Area feature set is not supported.
- Bit 11 of word 82 is obsolete.
- Bit 12 of word 82 shall be set to one; the CompactFlash[TM] Storage Card supports the Write Buffer command.
- Bit 13 of word 82 shall be set to one; the CompactFlash[TM] Storage Card supports the Read Buffer command.
- Bit 14 of word 82 shall be set to one; the CompactFlash[TM] Storage Card supports the NOP command.
- Bit 15 of word 82 is obsolete.
- Bit 0 of word 83 shall be set to zero; the CompactFlash[TM] Storage Card does not support the Download Microcode command.
- Bit 1 of word 83 shall be set to zero; the CompactFlash[TM] Storage Card does not support the Read DMA Queued and Write DMA Queued commands.
- Bit 2 of word 83 shall be set to one; the CompactFlash[TM] Storage Card supports the CFA feature set.
- If bit 3 of word 83 is set to one, the CompactFlash[TM] Storage Card supports the Advanced Power Management feature set.
- Bit 4 of word 83 shall be set to zero; the CompactFlash[TM] Storage Card does not support the Removable Media Status feature set.
- Bit 5 of Word 83 shall be cleared to zero; the Power Up in Standby feature set is not supported.
- Bit 6 of Word 83 shall be cleared to zero; Set Features subcommand requirement to spin-up after powerup is not supported.
- Bit 7 of Word 83 shall be cleared to zero
- Bit 8 of Word 83 shall be cleared to zero; the SET MAX security extension is not supported.
- Bit 9 of Word 83 shall be cleared to zero; automatic acoustic management is not supported.
- Bit 10 of word 83 shall be set to one, the 48-bit Address feature is supported,
- Bit 11 of Word 83 shall be cleared to zero; the DCO feature set is not supported.
- Bit 12 of Word 83 shall be set to one; the Flush Cache command is supported.
- Bit 13 of Word 83 shall be set to one, the 48-bit Address feature including the Flush Cache Ext command is supported.
- Bit 14 of Word 83 shall be set to one.
- Bit 15 of Word 83 shall be cleared to zero.
- Bit 0 of Word 84 shall be cleared to zero; SMART error logging is not supported.
- Bit 1 of Word 84 shall be cleared to zero; SMART self-test is not supported.
- Bit 2 of Word 84 shall be cleared to zero; Media serial number is not supported.
- Bit 3 of Word 84 shall be cleared to zero; Media Card Pass Through feature set not supported.
- Bit 4 of Word 84 shall be cleared to zero.
- Bit 5 of Word 84 shall be set to one if General Purpose Logging feature set is supported, or cleared to zero if the General Purpose Logging feature is not supported.
- Bit 6 of word 84 shall be set to one if the WRITE DMA FUA EXT and WRITE MULTIPLE FUA EXT commands are supported, or cleared to zero if they are not supported.
- Bit 7 of word 84 shall be cleared to zero. The CompactFlash[TM] Storage Card does not support the WRITE DMA QUEUED FUA EXT command.
- Bit 8 of word 84 shall be cleared to zero. The CompactFlash[TM] Storage Card does not support a world-wide name.
- Bit 9 of word 84 shall be cleared to zero. The CompactFlash[TM] Storage Card does not support the Streaming feature set.
- Bit 10 of word 84 shall be cleared to zero. The CompactFlash[TM] Storage Card does not support the Streaming feature set.
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- Bit 11 of word 84 is reserved.
- Bit 12 of word 84 is reserved.
- Bit 13 of word 84 shall be cleared to zero. The CompactFlash[TM] Storage Card does not support IDLE IMMEDIATE with UNLOAD FEATURE.
- Bit 14 of Word 84 shall be set to one.
- Bit 15 of Word 84 shall be cleared to zero.
## 10.8.24 Words 85-87: Features/command sets enabled
Words 85, 86, and 87 shall indicate features/command sets enabled. The value 0000h or FFFFh was placed in each of these words by CompactFlash[TM] Storage Cards prior to ATA-4 and shall be interpreted by the host as meaning that features/command sets enabled are not indicated. Bits 1 through 15 of word 86 are reserved. Bits 0- 13 of word 87 are reserved. Bit 14 of word 87 shall be set to one and bit 15 of word 87 shall be cleared to zero to provide indication that the features/command sets enabled words are valid. The values in these words should not be depended on by host implementers.
- If bit 0 of word 85 is set to one; the SMART feature set is enabled. Bit 0 can be changed by the host and is not reset after power cycle
- If bit 1 of word 85 is set to one, the Security Mode feature set has been enabled via the Security
- Set Password command.
- Bit 2 of word 85 shall be set to zero; the Removable Media feature set is not supported.
- Bit 3 of word 85 shall be set to one; the Power Management feature set is supported.
- Bit 4 of word 85 shall be set to zero; the Packet Command feature set is not enabled.
- If bit 5 of word 85 is set to one, write cache is enabled.
- If bit 6 of word 85 is set to one, look-ahead is enabled.
- Bit 7 of word 85 shall be set to zero; release interrupt is not enabled.
- Bit 8 of word 85 shall be set to zero; Service interrupt is not enabled.
- Bit 9 of word 85 shall be set to zero; the Device Reset command is not supported.
- Bit 10 of word 85 shall be set to zero; the Host Protected Area feature set is not supported.
- Bit 11 of word 85 is obsolete.
- Bit 12 of word 85 shall be set to one; the CompactFlash[TM] Storage Card supports the Write Buffer command.
- Bit 13 of word 85 shall be set to one; the CompactFlash[TM] Storage Card supports the Read Buffer command.
- Bit 14 of word 85 shall be set to one; the CompactFlash[TM] Storage Card supports the NOP command.
- Bit 15 of word 85 is obsolete.
- Bit 0 of word 86 shall be set to zero; the CompactFlash[TM] Storage Card does not support the Download Microcode command.
- Bit 1 of word 86 shall be set to zero; the CompactFlash[TM] Storage Card does not support the Read DMA Queued and Write DMA Queued commands.
- If bit 2 of word 86 shall be set to one, the CompactFlash[TM] Storage Card supports the CFA feature set.
- If bit 3 of word 86 is set to one, the Advanced Power Management feature set has been enabled via the Set Features command.
- Bit 4 of word 86 shall be set to zero; the CompactFlash[TM] Storage Card does not support the Removable Media Status feature set.
- Bit 5 of word 86 shall be cleared to zero. The PUIS feature set is not supported.
- Bit 6 of word 86 shall be cleared to zero. The PUIS feature set is not supported.
- Bit 7 of word 86 is reserved for ATA.
- Bit 8 of word 86 shall be cleared to zero. The ATA Security Extension is not supported.
- Bit 9 of word 86 shall be cleared to zero. The AAM feature set is not supported.
- Bit 10 of word 86 is set to one, the 48-bit Address feature set is supported.
- Bit 11 of word 86 shall be cleared to zero. The DCO feature set is not supported.
- If bit 12 is set to one, the Flush Cache command is supported.
- If bit 13 is set to one, the Flush Cache Ext command is supported.
- Bit 14 of word 86 is reserved for ATA.
- Bit 15 of word 86 shall be set to one indicating that words 119 and 120 are valid.
-
- Bit 0 of word 87 shall be cleared to zero. The CompactFlash[TM] Card does not support SMART error logging.
- Bit 1 of word 87 shall be cleared to zero. The CompactFlash[TM] Card does not support SMART self-test.
- Bit 2 of word 87 shall be cleared to zero. The CompactFlash[TM] Card does not support the media serial number field in words (205:176).
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- Bit 3 of word 87 shall be cleared to zero. The CompactFlash[TM] Card does not support the Media Card Pass Through feature.
- Bit 4 of word 87 shall be cleared to zero. The CompactFlash[TM] Card does not support the Streaming feature set.
- Bit 5 of word 87 shall be set to one if the CompactFlash[TM] Storage Card supports the General Purpose Logging feature set, or cleared to zero if the General Purpose Logging feature is not supported.
- Bit 6 of word 87 shall be set to one if the WRITE DMA FUA EXT and WRITE MULTIPLE FUA EXT commands are supported, or cleared to zero if they are not supported.
- Bit 7 of word 87 shall be cleared to zero. The CompactFlash[TM] Card does not support the WRITE DMA QUEUED FUA EXT command.
- Bit 8 of word 87 shall be cleared to zero. The CompactFlash[TM] Card does not support a world wide name.
- Bit 9 of word 87 shall be cleared to zero. The CompactFlash[TM] Card does not support the Streaming feature set.
- Bit 10 of word 87 shall be cleared to zero. The CompactFlash[TM] Card does not support the Streaming feature set.
- Bit 11 of word 87 is reserved.
- Bit 12 of word 87 is reserved.
- Bit 13 of word 87 shall be cleared to zero. The CompactFlash[TM] Card does not support IDLE IMMEDIATE with UNLOAD FEATURE.
- Bit 14 of word 87 shall be set to one and bit 15 of word 87 shall be cleared to zero to provide indication that the features/command sets enabled words are valid.
## 10.8.25 Word 88: True IDE Ultra DMA Modes Supported and Selected
Word 88 identifies the Ultra DMA transfer modes supported by the device and indicates the mode that is currently selected. Only one DMA mode shall be selected at any given time. If an Ultra DMA mode is selected, then no Multiword DMA mode shall be selected. If a Multiword DMA mode is selected, then no Ultra DMA mode shall be selected. Support of this word is mandatory if Ultra DMA is supported. Word 88 shall return a value of 0 if the device is not in True IDE mode or if it does not support UDMA in True IDE Mode.
- Bit 15: Reserved
- Bit 14: 1 = Ultra DMA mode 6 is selected 0 = Ultra DMA mode 6 is not selected
- Bit 13: 1 = Ultra DMA mode 5 is selected 0 = Ultra DMA mode 5 is not selected
- Bit 12: 1 = Ultra DMA mode 4 is selected 0 = Ultra DMA mode 4 is not selected
- Bit 11: 1 = Ultra DMA mode 3 is selected 0 = Ultra DMA mode 3 is not selected
- Bit 10: 1 = Ultra DMA mode 2 is selected 0 = Ultra DMA mode 2 is not selected
- Bit 9: 1 = Ultra DMA mode 1 is selected 0 = Ultra DMA mode 1 is not selected
- Bit 8: 1 = Ultra DMA mode 0 is selected 0 = Ultra DMA mode 0 is not selected
- Bit 7: Reserved
- Bit 6: 1 = Ultra DMA mode 6 and below are supported. Bits 0-5 shall be set to 1.
- Bit 5: 1 = Ultra DMA mode 5 and below are supported. Bits 0-4 shall be set to 1.
- Bit 4: 1 = Ultra DMA mode 4 and below are supported. Bits 0-3 shall be set to 1.
- Bit 3: 1 = Ultra DMA mode 3 and below are supported, Bits 0-2 shall be set to 1.
- Bit 2: 1 = Ultra DMA mode 2 and below are supported. Bits 0-1 shall be set to 1.
- Bit 1: 1 = Ultra DMA mode 1 and below are supported. Bit 0 shall be set to 1.
- Bit 0: 1 = Ultra DMA mode 0 is supported
## 10.8.26 Word 92: Master Password Revision Code
Word 92 contains the value of the Master Password Revision Code set when the Master Password was last changed. Valid values are 0001h through FFFEh. A value of 0000h or FFFFh indicates that the Master Password Revision is not supported. Support of this word is mandatory if the Security feature set is supported.
## 10.8.27 Words 100-103: Maximum user LBA for 48-bit address feature set
Words (103-100) contain a value that is one greater than the maximum LBA in user addressable space using 48-bit Addressing. The maximum value that shall be placed in this field is 0000FFFFFFFFFFFFh. Support of these words is mandatory.
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## 10.8.28 Word 105: Maximum number of 512-byte blocks of LBA Range Entries used by the Trim feature of the Data Set Management command
Word 105 contains the maximum number of 512-byte blocks of LBA Range Entries included with the Trim feature of the Data Set Management command that the CompactFlash[TM] device shall accept. A value of 0000h indicates that the maximum number of 512-byte blocks is not specified.
## 10.8.29 Word 128: Security Status
- Bit 8: Security Level If set to one indicates that security mode is enabled and the security level is maximum. If cleared to zero and security mode is enabled, indicates that the security level is high.
- Bit 5: Enhanced security erase unit feature supported
If set to one, indicates that the Enhanced security erase unit feature set is supported.
- Bit 4: Expire
- If set to one, indicates that the security count has expired and Security Unlock and Security Erase Unit are command aborted until a power-on reset or hard reset.
- Bit 3: Freeze
- If set to one, indicates that the security is Frozen.
- Bit 2: Lock If set to one, indicates that the security is locked.
- Bit 1: Enable/Disable If set to one, indicates that the security is enabled. If cleared to zero, indicates that the security is disabled.
- Bit 0: Capability If set to one, indicates that CompactFlash[TM] Storage Card supports security mode feature set. If cleared to zero, indicates that CompactFlash[TM ] Card does not support security mode feature set.
## 10.8.30 Word 160: Power Requirement Description
This word is required for CompactFlash[TM] Storage Cards that support power mode 1.
- Bit 15: VLD If set to 1, indicates that this word contains a valid power requirement description.
- If set to 0, indicates that this word does not contain a power requirement description.
- Bit 14: RSV
This bit is reserved and shall be 0.
- Bit 13: -XP If set to 1, indicates that the CompactFlash[TM] Storage Card does not have Power Level 1 commands. If set to 0, indicates that the CompactFlash[TM] Storage Card has Power Level 1 commands
- Bit 12: -XE If set to 1, indicates that Power Level 1 commands are disabled. If set to 0, indicates that Power Level 1 commands are enabled.
- Bit 0-11: Maximum current This field contains the CompactFlash[TM] Storage Card’s maximum current in mA.
## 10.8.31 Word 163: Advanced True IDE Timing mode capabilities and settings
This word describes the capabilities and current settings for CFA defined advanced timing modes using the True IDE interface.
Notice! The use of True IDE PIO Modes 5 and above or of Multiword DMA Modes 3 and above impose significant restrictions on the implementation of the host as indicated in section 5.3 : Additional Requirements for CF Advanced Timing Modes.
There are four separate fields defined that describe support and selection of Advanced PIO timing modes and Advanced Multiword DMA timing modes. The older modes are reported in words 63 and 64.
- Bits 2-0: Advanced True IDE PIO Mode Support Indicates the maximum True IDE PIO mode supported by the card.
- 0 Specified in word 64
- 1 PIO Mode 5
- 2 PIO Mode 6
- 3-7 Reserved
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- Bits 5-3: Advanced True IDE Multiword DMA Mode Support indicates the maximum True IDE Multiword DMA mode supported by the card.
- 0 Specified in word 63
- 1 Multiword DMA Mode 3
- 2 Multiword DMA Mode 4
- 3-7 Reserved
- Bits 8-6: Advanced True IDE PIO Mode Selected indicates the current True IDE PIO mode selected on the card.
- 0 Specified in word 64
- 1 PIO Mode 5
- 2 PIO Mode 6
- 3-7 Reserved
- Bits 11-9: Advanced True IDE Multiword DMA Mode Selected indicates the current True IDE Multiword DMA Mode Selected on the card.
- 0 Specified in word 63 1 Multiword DMA Mode 3 2 Multiword DMA Mode 4
- 3-7 Reserved
- Bits 15-12 are reserved.
## 10.8.32 Word 164: Advanced PC card I/O and Memory Timing modes capabilities and settings
This word describes the capabilities and current settings for CFA defined advanced timing modes using the Memory and PC Card I/O interface.
Notice! The use of PC Card I/O or Memory modes that are 100ns or faster impose significant restrictions on the implementation of the host as indicated in section 5.3 : Additional Requirements for CF Advanced Timing Modes.
- Bits 2-0: Maximum Advanced PC Card I/O Mode Support Indicates the maximum I/O timing mode supported by the card.
- 0 255 ns Cycle PC Card I/O Mode
- 1 120 ns Cycle PC Card I/O Mode
- 2 100 ns Cycle PC Card I/O Mode
- 3 80 ns Cycle PC Card I/O Mode
- 4-7 Reserved
- Bits 5-3: Maximum Memory timing mode supported Indicates the Maximum Memory timing mode supported by the card.
- 0 250 ns Cycle Memory Mode
- 1 120 ns Cycle Memory Mode
- 2 100 ns Cycle Memory Mode
- 3 80 ns Cycle Memory Mode
- 4-7 Reserved
- Bits 8-6: Maximum PC Card I/O UDMA timing mode supported Indicates the Maximum PC Card I/O UDMA timing mode supported by the card when bit 15 is set.
- 0 PC Card I/O UDMA mode 0 supported
- 1 PC Card I/O UDMA mode 1 supported
- 2 PC Card I/O UDMA mode 2 supported
- 3 PC Card I/O UDMA mode 3 supported
- 4 PC Card I/O UDMA mode 4 supported
- 5 PC Card I/O UDMA mode 5 supported
- 6 PC Card I/O UDMA mode 6 supported 7 Reserved
- Bits 11-9: Maximum PC Card Memory UDMA timing mode supported
- Indicates the Maximum PC Card Memory UDMA timing mode supported by the card when bit 15 is set. 0 PC Card Memory UDMA mode 0 supported 1 PC Card Memory UDMA mode 1 supported
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- 2 PC Card Memory UDMA mode 2 supported
- 3 PC Card Memory UDMA mode 3 supported
- 4 PC Card Memory UDMA mode 4 supported 5 PC Card Memory UDMA mode 5 supported 6 PC Card Memory UDMA mode 6 supported 7 Reserved
- Bits 14-12: PC Card Memory or I/O UDMA timing mode selected Indicates the PC Card Memory or I/O UDMA timing mode selected by the card. 0 PC Card I/O UDMA mode 0 selected
- 1 PC Card I/O UDMA mode 1 selected
- 2 PC Card I/O UDMA mode 2 selected
- 3 PC Card I/O UDMA mode 3 selected
- 4 PC Card I/O UDMA mode 4 selected
- 5 PC Card I/O UDMA mode 5 selected
- 6 PC Card I/O UDMA mode 6 selected
- 7 Reserved
- Bit 15: PC Card Memory and IO Modes Supported
## 10.8.33 Word 169: Data Set Management Support
Bits 15-1: reserved
Bit 0: shall be set to one to indicate support of the Trim bit of the Data Set Management command.
## **10.9 Idle (97h or E3h)**
This command causes the Card to set BSY, enter the Idle mode, clear BSY and generate an interrupt. If the sector count is non-zero, it is interpreted as a timer count (each count is 5ms) and the automatic power down mode is enabled. If the sector count is zero, the automatic power down mode is disabled. Note that this time base (5ms) is different from the ATA specification. If no Idle command is performed, the card goes to sleep mode after 20ms. Table 67 defines the Byte sequence of the Idle command.
Table 67: Idle
|Table 67: Idle|||||||||
|---|---|---|---|---|---|---|---|---|
|Task File Register|7|6|5|4|3|2|1|0|
|COMMAND|97h or E3h||||||||
|DRIVE/HEAD|nu|nu|nu|D|nu||||
|CYLINDER HI|nu||||||||
|CYLINDER LOW|nu||||||||
|SECTOR NUM|nu||||||||
|SECTOR COUNT|Timer Count (5ms increments)||||||||
|FEATURES|nu||||||||
## **10.10 Idle Immediate (95h or E1h)**
This command causes the Card to set BSY, enter the Idle mode, clear BSY and generate an interrupt. Table 68 defines the Idle Immediate command Byte sequence.
Table 68: Idle Immediate
|Table 68: Idle Immediate|||||||||
|---|---|---|---|---|---|---|---|---|
|Task File Register|7|6|5|4|3|2|1|0|
|COMMAND|95h or E1h||||||||
|DRIVE/HEAD|nu|nu|nu|D|nu||||
|CYLINDER HI|nu||||||||
|CYLINDER LOW|nu||||||||
|SECTOR NUM|nu||||||||
|SECTOR COUNT|nu||||||||
|FEATURES|nu||||||||
## **10.11 Initialize Drive Parameters (91h)**
This command enables the host to set the number of sectors per track and the number of heads per cylinder. Only the Sector Count and the Card/Drive/Head registers are used by this command. Table 69 defines the Initialize Drive Parameters command Byte sequence.
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Table 69: Initialize Drive Parameters
|Task File Register|7|6|5|4|3|2|1|0|
|---|---|---|---|---|---|---|---|---|
|COMMAND|91h||||||||
|DRIVE/HEAD|nu|nu|nu|D|Number of Heads minus 1||||
|CYLINDER HI|nu||||||||
|CYLINDER LOW|nu||||||||
|SECTOR NUM|nu||||||||
|SECTOR COUNT|Number of Sectors per Track||||||||
|FEATURES|nu||||||||
## **10.12 NOP (00h)**
This command always fails with the CompactFlash[TM] Memory Card returning command aborted. Table 70 defines the Byte sequence of the NOP command.
Table 70: NOP Task File Register 7 6 5 4 3 2 1 0 COMMAND 00h DRIVE/HEAD nu nu nu D nu CYLINDER HI nu CYLINDER LOW nu SECTOR NUM nu SECTOR COUNT nu ~~===~~ FEATURES nu **10.13 Read Buffer (E4h)** The Read Buffer command enables the host to read the current contents of the Card’s sector buffer. This command has the same protocol as the Read Sector(s) command. Table 71 defines the Read Buffer command Byte sequence.
Table 71: Read buffer Task File Register 7 6 5 4 3 2 1 0 COMMAND E4h DRIVE/HEAD nu nu nu D nu CYLINDER HI nu CYLINDER LOW nu SECTOR NUM nu SECTOR COUNT nu ~~===~~ FEATURES nu **10.14 Read DMA (C8h)** This command uses DMA mode to read from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register. When this command is issued the CompactFlash[TM] Storage Card sets BSY, puts all or part of the sector of data in the buffer. The Card is then permitted, although not required, to set DRQ, clear BSY. The Card asserts DMAREQ while data is available to be transferred. The Card asserts DMAREQ while data is available to be transferred. The host then reads the (512 * sector-count) bytes of data from the Card using DMA. While DMAREQ is asserted by the Card, the Host asserts –DMACK while it is ready to transfer data by DMA and asserts –IORD once for each 16 bit word to be transferred to the Host.
Interrupts are not generated on every sector, but upon completion of the transfer of the entire number of sectors to be transferred or upon the occurrence of an unrecoverable error.
At command completion, the Command Block Registers contain the cylinder, head and sector number of the last sector read. If an error occurs, the read terminates at the sector where the error occurred. The Command Block Registers contain the cylinder, head, and sector number of the sector where the error occurred. The amount of data transferred is indeterminate.
When a Read DMA command is received by the Card and 8 bit transfer mode has been enabled by the Set Features command, the Card shall return the Aborted error.
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Table 72: Read DMA
|Table 72: Read DMA|||||||||
|---|---|---|---|---|---|---|---|---|
|Task File Register|7|6|5|4|3|2|1|0|
|COMMAND|C8h||||||||
|DRIVE/HEAD|LBA|||D|Head (LBA 27:24)||||
|CYLINDER HI|Cylinder High (LBA23:16)||||||||
|CYLINDER LOW|Cylinder Low (LBA15:8)||||||||
|SECTOR NUM|Sector Number (LBA7:0)||||||||
|SECTOR COUNT|Sector Count||||||||
|FEATURES|nu||||||||
## **10.15 Read DMA Ext (25h) 48bit LBA**
This command uses DMA mode to read from 1 to 65536 sectors as specified in the Sector Count Register. A sector count of 0 requests 65536 sectors. The transfer begins at the sector specified in the Sector Number Register. When this command is issued the CompactFlash[TM] Storage Card sets BSY, puts all or part of the sector of data in the buffer. The Card is then permitted, although not required, to set DRQ, clear BSY. The Card asserts DMARQ while data is available to be transferred. The Card asserts DMARQ while data is available to be transferred. The host then reads the (512 * sector-count) bytes of data from the Card using DMA. While DMARQ is asserted by the Card, the Host asserts -DMACK while it is ready to transfer data by DMA and asserts -IORD once for each 16 bit word to be transferred to the Host.
Interrupts are not generated on every sector, but upon completion of the transfer of the entire number of sectors to be transferred or upon the occurrence of an unrecoverable error.
At command completion, the Command Block Registers contain the LBA of the last sector read. If an error occurs, the read terminates at the sector where the error occurred. The Command Block Registers contain the LBA of the sector where the error occurred. The amount of data transferred is indeterminate.
When a Read DMA Ext command is received by the Card and 8 bit transfer mode has been enabled by the Set Features command, the Card shall return the Aborted error.
Table 73: Read DMA Ext
|register write|previous|current|current|current|current|current|current|current|current|
|---|---|---|---|---|---|---|---|---|---|
|Task File Register|15:8|7|6|5|4|3|2|1|0|
|COMMAND|-|25h||||||||
|DRIVE/HEAD|-|1|1|1|Drive|Reserved||||
|LBA High|LBA (47:40)|LBA (23:16)||||||||
|LBA Mid|LBA (39:32)|LBA (15:8)||||||||
|LBA Low|LBA (31:24)|LBA (7:0)||||||||
|SECTOR COUNT|15:8|7:0||||||||
|FEATURES|nu|nu||||||||
## **10.16 Read Multiple (C4h)**
The Read Multiple command performs similarly to the Read Sectors command. Interrupts are not generated on every sector, but on the transfer of a block which contains the number of sectors defined by a Set Multiple command.
Command execution is identical to the Read Sectors operation except that the number of sectors defined by a Set Multiple command is transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector.
The block count of sectors to be transferred without intervening interrupts is programmed by the Set Multiple Mode command, which must be executed prior to the Read Multiple command. When the Read Multiple command is issued, the Sector Count Register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where:
n = (sector count) module (block count).
If the Read Multiple command is attempted before the Set Multiple Mode command has been executed or when Read Multiple commands are disabled, the Read Multiple operation is rejected with an Aborted Command error. Disk errors encountered during Read Multiple commands are posted at the beginning of the block or partial block transfer, but DRQ is still set and the data transfer will take place as it normally would, including transfer of corrupted data, if any.
Interrupts are generated when DRQ is set at the beginning of each block or partial block. The error reporting is the same as that on a Read Sector(s) Command. This command reads from 1 to 256 sectors as specified in the Sector
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Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register.
If an error occurs, the read terminates at the sector where the error occurred. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred. The flawed data are pending in the sector buffer.
Subsequent blocks or partial blocks are transferred only if the error was a correctable data error. All other errors cause the command to stop after transfer of the block which contained the error.
Table 74 defines the Read Multiple command Byte sequence.
Table 74: Read Multiple
|Table 74: Read Multiple|||||||||
|---|---|---|---|---|---|---|---|---|
|Task File Register|7|6|5|4|3|2|1|0|
|COMMAND|C4h||||||||
|DRIVE/HEAD|1|LBA|1|D|Head (LBA 27:24)||||
|CYLINDER HI|Cylinder High (LBA23:16)||||||||
|CYLINDER LOW|Cylinder Low (LBA15:8)||||||||
|SECTOR NUM|Sector Number (LBA7:0)||||||||
|SECTOR COUNT|Sector Count||||||||
|FEATURES|nu||||||||
## **10.17 Read Multiple Ext (29h) 48bit LBA**
The Read Multiple Ext command performs similarly to the Read Sectors Ext command. Interrupts are not generated on every sector, but on the transfer of a block, which contains the number of sectors defined by a Set Multiple command.
Command execution is identical to the Read Sectors Ext operation except that the number of sectors defined by a Set Multiple command is transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector.
The block count of sectors to be transferred without intervening interrupts is programmed by the Set Multiple Mode command, which shall be executed prior to the Read Multiple command. When the Read Multiple command is issued, the Sector Count Register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the block count, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where n = (sector count) modulo (block count).
If the Read Multiple Ext command is attempted before the Set Multiple Mode command has been executed, or when Read Multiple Ext command is disabled, the Read Multiple Ext operation is rejected with an Aborted Command error. Disk errors encountered during a Read Multiple Ext command are posted at the beginning of the block or partial block transfer, but DRQ is still set and the data transfer shall take place as it normally would, including transfer of corrupted data, if any.
Interrupts are generated when DRQ is set at the beginning of each block or partial block. The error reporting is the same as that on a Read Sector(s) Command. This command reads from 1 to 65536 sectors as specified in the Sector Count Register. A sector count of 0 requests 65536 sectors. The transfer begins at the sector specified in the Sector Number Register.
At command completion, the Command Block Registers contain the LBA of the last sector read. If an error occurs, the read terminates at the sector where the error occurred. The Command Block Registers contain the LBA of the sector where the error occurred. The flawed data is pending in the sector buffer. Subsequent blocks or partial blocks are transferred only if the error was a correctable data error. All other errors cause the command to stop after transfer of the block that contained the error.
Table 75: Read Multiple Ext
|register write|previous|current|current|current|current|current|current|current|current|
|---|---|---|---|---|---|---|---|---|---|
|Task File Register|15:8|7|6|5|4|3|2|1|0|
|COMMAND|-|29h||||||||
|DRIVE/HEAD|-|1|1|1|Drive|Reserved||||
|LBA High|LBA (47:40)|LBA (23:16)||||||||
|LBA Mid|LBA (39:32)|LBA (15:8)||||||||
|LBA Low|LBA (31:24)|LBA (7:0)||||||||
|SECTOR COUNT|15:8|7:0||||||||
|FEATURES|nu|nu||||||||
Note: This specification requires that CompactFlash[TM] Cards support a multiple block count of 1 and permits larger values to be supported.
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## **10.18 Read Sector(s) (20h or 21h)**
This command reads from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register. When this command is issued and after each sector of data (except the last one) has been read by the host, the Card sets BSY, puts the sector of data in the buffer, sets DRQ, clears BSY, and generates an interrupt. The host then reads the 512 Bytes of data from the buffer.
If an error occurs, the read terminates at the sector where the error occurred. The Command Block Registers contain the cylinder, head, and sector number of the sector where the error occurred. The flawed data are pending in the sector buffer. Table 76 defines the Read Sector command Byte sequence.
Table 76: Read sector(s)
Task File Register 7 6 5 4 3 2 1 0 COMMAND 20h (or 21h Legacy) DRIVE/HEAD 1 LBA 1 D Head (LBA 27:24) CYLINDER HI Cylinder High (LBA23:16) CYLINDER LOW Cylinder Low (LBA15:8) SECTOR NUM Sector Number (LBA7:0) SECTOR COUNT Sector Count ~~=~~ FEATURES nu **10.19 Read Sectors Ext (24h) 48bit LBA** This command reads from 1 to 65536 sectors as specified in the Sector Count Register. A sector count of 0 requests 65536 sectors. The transfer begins at the specified LBA. When this command is issued and after each sector of data (except the last one) has been read by the host, the CompactFlash[TM] Storage Card sets BSY, puts the sector of data in the buffer, sets DRQ, clears BSY, and generates an interrupt. The host then reads the 512 bytes of data from the buffer.
At command completion, the Command Block Registers contain the LBA of the last sector read. If an error occurs, the read terminates at the sector where the error occurred. The Command Block Registers contain the LBA of the sector where the error occurred. The flawed data is pending in the sector buffer.
Table 77: Read Multiple Ext
register write previous current Task File Register 15:8 7 6 5 4 3 2 1 0 - COMMAND 24h DRIVE/HEAD - 1 1 1 Drive Reserved LBA High LBA (47:40) LBA (23:16) LBA Mid LBA (39:32) LBA (15:8) LBA Low LBA (31:24) LBA (7:0) SECTOR COUNT 15:8 7:0 ~~oO~~ FEATURES nu nu **10.20 Read Verify Sector(s) (40h)** This command is identical to the Read Sectors command, except that DRQ is never set and no data is transferred to the host. When the command is accepted, the Card sets BSY. When the requested sectors have been verified, the Card clears BSY and generates an interrupt. If an error occurs, the verify terminates at the sector where the error occurs. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred. The Sector Count Register contains the number of sectors not yet verified. Table 78 defines the Read Verify Sector command Byte sequence. Table 78: Read Verify Sector(s) Task File Register 7 6 5 4 3 2 1 0 COMMAND 40h DRIVE/HEAD 1 LBA 1 D Head (LBA 27:24) CYLINDER HI Cylinder High (LBA23:16) CYLINDER LOW Cylinder Low (LBA15:8) SECTOR NUM Sector Number (LBA7:0) SECTOR COUNT Sector Count ~~=~~ FEATURES nu Swissbit AG Swissbit reserves the right to change products or specifications without notice. Revision: 1.23 Industriestrasse 4 CH-9552 Bronschhofen www.swissbit.com C-440_data_sheet_CF-HxBU_Rev123.doc Switzerland industrial@swissbit.com Page 75 of 106
If an error occurs, the verify terminates at the sector where the error occurs. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred. The Sector Count Register contains the number of sectors not yet verified.
## **10.21 Read Verify Ext (42h) 48bit LBA**
This command is identical to the Read Sector(s) Ext command, except that DRQ is never set and no data is transferred to the host. When the command is accepted, the CompactFlash[TM] Storage Card sets BSY. When the requested sectors have been verified, the CompactFlash[TM] Storage Card clears BSY and generates an interrupt. Upon command completion, the Command Block Registers contain the LBA of the last sector verified. If an error occurs, the Read Verify Command terminates at the sector where the error occurs. The Command Block Registers contain the LBA of the sector where the error occurred. The Sector Count Register contains the number of sectors not yet verified.
Table 79: Read Multiple Ext
register write previous current Task File Register 15:8 7 6 5 4 3 2 1 0 - COMMAND 42h DRIVE/HEAD - 1 1 1 Drive Reserved LBA High LBA (47:40) LBA (23:16) LBA Mid LBA (39:32) LBA (15:8) LBA Low LBA (31:24) LBA (7:0) SECTOR COUNT 15:8 7:0 ~~oo~~ FEATURES nu nu **10.22 Recalibrate (1Xh)** This command is effectively a NOP command to the Card and is provided for compatibility purposes. Table 80 defines the Recalibrate command Byte sequence. Table 80: Recalibrate Task File Register 7 6 5 4 3 2 1 0 COMMAND 1Xh DRIVE/HEAD 1 LBA 1 D nu CYLINDER HI nu CYLINDER LOW nu SECTOR NUM nu SECTOR COUNT nu ~~=~~ FEATURES nu **10.23 Request Sense (03h)** This command requests extended error information for the previous command. Table 81 defines the Request Sense command Byte sequence. Table 82 defines the valid extended error codes. The extended error code is returned to the host in the Error Register. Table 81: Request sense Task File Register 7 6 5 4 3 2 1 0 COMMAND 03h DRIVE/HEAD 1 LBA 1 D nu CYLINDER HI nu CYLINDER LOW nu SECTOR NUM nu SECTOR COUNT nu ~~=~~ FEATURES nu Swissbit AG Swissbit reserves the right to change products or specifications without notice. Revision: 1.23 Industriestrasse 4 CH-9552 Bronschhofen www.swissbit.com C-440_data_sheet_CF-HxBU_Rev123.doc Switzerland 76 of 106
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Table 82: Extended Error Codes
|Table 82: Extended Error Codes||
|---|---|
|Extended Error Code<br>Descri|Description|
|00h<br>No Error Detected|No Error Detected|
|01h<br>Self Test OK (No Error)|Self Test OK (No Error)|
|09h<br>Miscellaneous Error|Miscellaneous Error|
|21h<br>Invalid Address (Requested Head or Sector Invalid)|Invalid Address (Requested Head or Sector Invalid)|
|2Fh<br>Address Overflow (Address Too Large)|Address Overflow (Address Too Large)|
|35h, 36h<br>Supply or generated Voltage Out of Tolerance|Supply or generated Voltage Out of Tolerance|
|11h<br>Uncorrectable ECC Error|Uncorrectable ECC Error|
|18h<br>Corrected ECC Error|Corrected ECC Error|
|05h, 30-34h, 37h, 3Eh<br>Self Test or Diagnostic Failed|Self Test or Diagnostic Failed|
|10h, 14h<br>ID Not Found|ID Not Found|
|3Ah<br>Spare Sectors Exhausted|Spare Sectors Exhausted|
|1Fh<br>Data Transfer Error / Aborted Command|Data Transfer Error / Aborted Command|
|0Ch, 38h, 3Bh, 3Ch, 3Fh<br>Corrupted Media Format|Corrupted Media Format|
|03h<br>Write / Erase Failed|Write / Erase Failed|
## **10.24 Seek (7Xh)**
This command is effectively a NOP command to the Card although it does perform a range check of cylinder and head or LBA address and returns an error if the address is out of range. Table 83 shows the Seek command Byte sequence.
Table 83: Seek
|Table 83: Seek|||||||||
|---|---|---|---|---|---|---|---|---|
|Task File Register|7|6|5|4|3|2|1|0|
|COMMAND|7Xh||||||||
|DRIVE/HEAD|1|LBA|1|D|Head (LBA 27:24)||||
|CYLINDER HI|Cylinder High (LBA23:16)||||||||
|CYLINDER LOW|Cylinder Low (LBA15:8)||||||||
|SECTOR NUM|nu (LBA7:0)||||||||
|SECTOR COUNT|nu||||||||
|FEATURES|nu||||||||
## **10.25 Security Disable Password (F6h)**
This command requests a transfer of a single sector of data from the host. Table 84 defines the content of this sector of information. If the password selected by word 0 matches the password previously saved by the device, the device disables the lock mode. This command does not change the Master password that may be reactivated later by setting a User password.
Table 84: Security Disable Password
Task File Register 7 6 5 4 3 2 1 0 COMMAND F6h DRIVE/HEAD 1 LBA 1 D nu CYLINDER HI nu CYLINDER LOW nu SECTOR NUM nu SECTOR COUNT nu ~~==~~ FEATURES nu Table 85: Security Password Data Content **Word Content** 0 Control word Bit 0: identifier 0=compare User password 1=compare Master password Bit 1-15: Reserved 1-16 Password (32 bytes) ~~|~~ 17-255 Reserved Swissbit AG Swissbit reserves the right to change products or specifications without notice. Revision: 1.23 Industriestrasse 4 CH-9552 Bronschhofen www.swissbit.com C-440_data_sheet_CF-HxBU_Rev123.doc Switzerland
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## **10.26 Security Erase Prepare (F3h)**
This command shall be issued immediately before the Security Erase Unit command to enable device erasing and unlocking. This command prevents accidental erase of the CF card.
Table 86: Security Erase Prepare
|Task File Register|7|6|5|4|3|2|1|0|
|---|---|---|---|---|---|---|---|---|
|COMMAND|F3h||||||||
|DRIVE/HEAD|1|LBA|1|D|nu||||
|CYLINDER HI|nu||||||||
|CYLINDER LOW|nu||||||||
|SECTOR NUM|nu||||||||
|SECTOR COUNT|nu||||||||
|FEATURES|nu||||||||
## **10.27 Security Erase Unit (F4h)**
This command requests transfer of a single sector of data from the host. Table 85 defines the content of this sector of information. If the password does not match the password previously saved by the CF card, the CF card rejects the command with command aborted. The Security Erase Prepare command shall be completed immediately prior to the Security Erase Unit command. If the CF Card receives a Security Erase Unit command without an immediately prior Security Erase Prepare command, the CF card aborts the Security Erase Unit command.
Table 87: Security Erase Unit
|Table 87: Security Erase Unit|||||||||
|---|---|---|---|---|---|---|---|---|
|Task File Register|7|6|5|4|3|2|1|0|
|COMMAND|F4h||||||||
|DRIVE/HEAD|1|LBA|1|D|nu||||
|CYLINDER HI|nu||||||||
|CYLINDER LOW|nu||||||||
|SECTOR NUM|nu||||||||
|SECTOR COUNT|nu||||||||
|FEATURES|nu||||||||
## **10.28 Security Freeze Lock (F5h)**
The Security Freeze Lock command sets the CF card to Frozen mode. After command completion, any other commands that update the CF card Lock mode are rejected. Frozen mode is disabled by power off or hardware reset. If Security Freeze Lock is issued when the CF card is in Frozen mode, the command executes and the CF card remains in Frozen mode. After command completion, the Sector Count Register shall be set to 0. Commands disabled by Security Freeze Lock are:
If security mode feature set is not supported, this command shall be handled as Wear Level command.
Table 88: Security Freeze Lock
|Table 88: Security Freeze Lock|Table 88: Security Freeze Lock||||||||
|---|---|---|---|---|---|---|---|---|
|Task File Register|7|6|5|4|3|2|1|0|
|COMMAND|F5h||||||||
|DRIVE/HEAD|1|LBA|1|D|nu||||
|CYLINDER HI|nu||||||||
|CYLINDER LOW|nu||||||||
|SECTOR NUM|nu||||||||
|SECTOR COUNT|nu||||||||
|FEATURES|nu||||||||
## **10.29 Security Set Password (F1h)**
This command requests a transfer of a single sector of data from the host. Table 90 defines the content of the sector of information. The data transferred controls the function of this command. Table 91 defines the interaction of the identifier and security level bits.
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Table 89: Security Set Password Task File Register 7 6 5 4 3 2 1 0 COMMAND F1h DRIVE/HEAD 1 LBA 1 D nu CYLINDER HI nu CYLINDER LOW nu SECTOR NUM nu SECTOR COUNT nu FEATURES nu Table 90: Security Set Password Data Content **Word Content** 0 Control word Bit 0: identifier 0=set User password 1=set Master password Bit 1-7: Reserved Bit 8: Security level 0=High 1=Maximum - Bits 9 15: Reserved 1-16 Password (32 bytes) ~~ef~~ 17-255 Reserved Table 91: Identifier and Security Level Bit Interaction **Identifier Level Command result** User High The password supplied with the command shall be saved as the new User password. The lock mode shall be enabled from the next power-on or hardware reset. The CF card shall then be unlocked by either the User password or the previously set Master password. User Maximum The password supplied with the command shall be saved as the new User password. The lock mode shall be enabled from the next power-on or hardware reset. The CF card shall then be unlocked by only the User password. The Master password previously set is still stored in the CF card shall not be used to unlock the CF card. Master High or This combination shall set a Master password but shall not enable or disable the Lock mode. The ~~—~~ Maximum security level is not changed. **10.30 Security Unlock (F2h)** This command requests transfer of a single sector of data from the host. Table 85 defines the content of this sector of information. If the identifier bit is set to Master and the device is in high security level, then the password supplied shall be compared with the stored Master password. If the device is in the maximum security level, then the unlock command shall be rejected. If the identifier bit is set to user, then the device compares the supplied password with the stored User password. If the password compare fails then the device returns command aborted to the host and decrements the unlock counter. This counter is initially set to five and is decremented for each password mismatch when Security Unlock is issued and the device is locked. Once this counter reaches zero, the Security Unlock and Security Erase Unit commands are command aborted until after a power-on reset or a hardware reset is received. Security Unlock commands issued when the device is unlocked have no effect on the unlock counter.
Table 92: Security Unlock Task File Register 7 6 5 4 3 2 1 0 COMMAND F2h DRIVE/HEAD 1 LBA 1 D nu CYLINDER HI nu CYLINDER LOW nu SECTOR NUM nu SECTOR COUNT nu ~~a~~ FEATURES nu Swissbit AG Swissbit reserves the right to change products or specifications without notice. Revision: 1.23 Industriestrasse 4 CH-9552 Bronschhofen www.swissbit.com C-440_data_sheet_CF-HxBU_Rev123.doc Switzerland
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## **10.31 Set Features (EFh)**
## Table 93: Set Features
|Table 93: Set Features|||||||||
|---|---|---|---|---|---|---|---|---|
|Task File Register|7|6|5|4|3|2|1|0|
|COMMAND|EFh||||||||
|DRIVE/HEAD|nu|||D|nu||||
|CYLINDER HI|nu||||||||
|CYLINDER LOW|nu||||||||
|SECTOR NUM|nu||||||||
|SECTOR COUNT|Config||||||||
|FEATURES|Feature||||||||
## Table 94: Features Supported
|Feature|Operation|
|---|---|
|01h/81h|Enable/Disable 8-bit data transfers.|
|02h/82h|Enable/Disable write cache.|
|03h|Set transfer mode based on value in Sector Count register.|
|05h/85h|Enable/Disable advance power management.|
|09h/89h|Enable/Disable extended power operations.|
|0Ah/8Ah|Enable/Disable power level 1 commands.|
|55h/AAh|Disable/Enable Read Look Ahead.|
|66h/CCh|Disable/Enable Power On Reset (POR) established of defaults at Soft Reset.|
|69h|NOP Accepted for backward compatibility.|
|96h|NOP Accepted for backward compatibility.|
|97h|Accepted for backward compatibility. Use of this Feature is not recommended.|
|9Ah|Set the host current source capability.<br>Allows trade-off between current drawn and read/write speed.|
|BBh|4 bytes of data apply on Read/Write Long commands|
Features 01h and 81h are used to enable and clear 8 bit data transfer modes in True IDE Mode. If the 01h feature command is issued all data transfers shall occur on the low order D[7:0] data bus and the –IOIS16 signal shall not be asserted for data register accesses. The host shall not enable this feature for DMA transfers. Features 02h and 82h allow the host to enable or disable write cache in CompactFlash[TM] Storage Cards that implement write cache. When the subcommand disable write cache is issued, the CompactFlash[TM] Storage Card shall initiate the sequence to flush cache to non-volatile memory before command completion. Feature 03h allows the host to select the PIO or Multiword DMA transfer mode by specifying a value in the Sector Count register. The upper 5 bits define the type of transfer and the low order 3 bits encode the mode value. One PIO mode shall be selected at all times. For Cards which support DMA, one DMA mode shall be selected at all times. The host may change the selected modes by the Set Features command.
Table 95: Transfer Mode Values Mode Bits (7:3) Bits (2:0) PIO default mode 00000b 000b PIO default mode, disable IORDY 00000b 001b PIO flow control transfer mode 00001b Mode ~~[(1)]~~ Reserved 00010b N/A Multi-Word DMA mode 00100b Mode ~~[(1)]~~ Ultra DMA mode 01000b Mode ~~[(1)] ===~~ Reserved 1000b N/A (1)Mode = transfer mode number Notes: Multiword DMA is not permitted for devices configured in the PC Card Memory or the PC Card I/O interface mode.
If a CompactFlash[TM] Storage Card supports PIO modes greater than 0 and receives a Set Features command with a Set Transfer Mode parameter and a Sector Count register value of “00000000b”, it shall set its default PIO mode. If the value is “00000001b” and the CompactFlash[TM] Storage Card supports disabling of IORDY, then the CompactFlash[TM] Storage Card shall set its default PIO mode and disable IORDY. A CompactFlash[TM] Storage Card shall support all PIO modes below the highest mode supported, e.g., if PIO mode 1 is supported PIO mode 0 shall be supported.
Support of IORDY is mandatory when PIO mode 3 or above is the current mode of operation.
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A CompactFlash[TM] Storage Card reporting support for Multiword DMA modes shall support all Multiword DMA modes below the highest mode supported. For example, if Multiword DMA mode 2 support is reported, then modes 1 and 0 shall also be supported. Note that Multiword DMA shall not be supported while PC Card interface modes are selected.
A CompactFlash Storage Card reporting support for Ultra DMA modes shall support all Ultra DMA modes below the highest mode supported. For example, if Ultra DMA mode 2 support is reported then modes 1 and 0 shall also be supported.
If an Ultra DMA mode is enabled, any previously enabled Multiword DMA mode shall be disabled by the device. If a Multiword DMA mode is enabled any previously enabled Ultra DMA mode shall be disabled by the device. Feature 05h allows the host to enable Advanced Power Management. To enable Advanced Power Management, the host writes the Sector Count register with the desired advanced power management level and then executes a Set Features command with subcommand code 05h. The power management level is a scale from the lowest power consumption setting of 01h to the maximum performance level of FEh. Table 96: Advanced power management levels shows these values.
Table 96: Advanced power management levels
|Table 96: Advanced power management levels||
|---|---|
|Level|Sector Count Value|
|Maximum performance|FEh|
|Intermediate power management levels without Standby|81h-FDh|
|Minimum power consumption without Standby|80h|
|Intermediate power management levels with Standby|02h-7Fh|
|Minimum power consumption with Standby|01h|
|Reserved|FFh|
|Reserved|00h|
In the current version the advanced power management levels are accepted, but don’t influence performance and power consumption.
Device performance may increase with increasing power management levels. Device power consumption may increase with increasing power management levels. The power management levels may contain discrete bands. For example, a device may implement one power management method from 80h to A0h and a higher performance, higher power consumption method from level A1h to FEh. Advanced power management levels 80h and higher do not permit the device to spin down to save power.
Feature 85h disables Advanced Power Management. Subcommand 85h may not be implemented on all devices that implement Set Features subcommand 05h.
Features 0Ah and 8Ah are used to enable and disable Power Level 1 commands. Feature 0Ah is the default feature for the CF+ CompactFlash[TM] Storage Card with extended power as they require Power Level 1 to perform their full set of functions.
Power Enhanced CF Storage Cards are required to power up and execute all supported commands and protocols in Power Level 0, their default feature shall be 8Ah: Disable Power Level 1 Commands. No commands are actually excluded for such cards in Power Level 0 because no commands require Power Level 1. The 8Ah default allows the cards to restrict their operating power to Power Level 0 limits for compatibility with hosts that do not recognize or support the extended power capabilities of Power Enhanced CF Storage Cards. It also allows hosts that support extended power to take advantage of it by setting the feature to 0Ah: Enable Power Level 1 Commands. Features 55h and BBh are the default features for the CompactFlash[TM] Storage Card; thus, the host does not have to issue this command with these features unless it is necessary for compatibility reasons.
Feature code 9Ah enables the host to configure the card to best meet the host system’s power requirements. The host sets a value in the Sector Count register that is equal to one-fourth of the desired maximum average current (in mA) that the card should consume. For example, if the Sector Count register were set to 6, the card would be configured to provide the best possible performance without exceeding 24 mA. Upon completion of the command, the card responds to the host with the range of values supported by the card. The minimum value is set in the Cylinder Low register, and the maximum value is set in the Cylinder Hi register. The default value, after a power on reset, is to operate at the highest performance and therefore the highest current mode. The card shall accept values outside this programmable range, but shall operate at either the lowest power or highest performance as appropriate.
Features 66h and CCh can be used to enable and disable whether the Power On Reset (POR) Defaults shall be set when a soft reset occurs. The default setting is to revert to the POR defaults when a soft reset occurs.
## **10.32 Set Multiple Mode (C6h)**
This command enables the Card to perform Read and Write Multiple operations and establishes the block count for these commands. The Sector Count Register is loaded with the number of sectors per block. Upon receipt of the command, the Card sets BSY and checks the Sector Count Register.
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If the Sector Count Register contains a valid value and the block count is supported, the value is loaded for all subsequent Read Multiple and Write Multiple commands and execution is enabled. If a block count is not supported, an Aborted Command error is posted, and Read Multiple and Write Multiple commands are disabled. If the Sector Count Register contains ‘0’ when the command is issued, Read and Write Multiple commands are disabled. At power on the default mode is Read and Write Multiple disabled, unless it is disabled by a Set Feature command. Table 97 defines the Set Multiple Mode command Byte sequence.
Table 97: Set Multiple Mode
Task File Register 7 6 5 4 3 2 1 0 COMMAND C6h DRIVE/HEAD nu D nu CYLINDER HI nu CYLINDER LOW nu SECTOR NUM nu SECTOR COUNT Sector Count ~~==~~ FEATURES nu **10.33 Set Sleep Mode (99h or E6)** This command causes the CompactFlash[TM] Memory Card to set BSY, enter the Sleep mode, clear BSY and generate an interrupt. Recovery from sleep mode is accomplished by simply issuing another command. Sleep mode is also entered when internal timers expire so the host does not need to issue this command except when it wishes to enter Sleep mode immediately. The default value for the timer is 20 milliseconds. Note that this time base (5ms) is different from the ATA Specification. Table 98 defines the Set Sleep Mode command Byte sequence.
Table 98: Set Sleep Mode
Task File Register 7 6 5 4 3 2 1 0 COMMAND 99h or E6h DRIVE/HEAD nu D nu CYLINDER HI nu CYLINDER LOW nu SECTOR NUM nu SECTOR COUNT nu ~~==~~ FEATURES nu **10.34 S.M.A.R.T. (B0h)** The intent of self-monitoring, analysis, and reporting technology (the SMART feature set) is to protect user data and minimize the likelihood of unscheduled system downtime that may be caused by predictable degradation and/or fault of the device. By monitoring and storing critical performance and calibration parameters, SMART feature set devices attempt to predict the likelihood of near-term degradation or fault condition. Providing the host system the knowledge of a negative reliability condition allows the host system to warn the user of the impending risk of a data loss and advise the user of appropriate action. Support of this feature set is indicated in the IDENTIFY DEVICE data (Word 82 bit 0).
Table 99: S.M.A.R.T. Features Task File Register 7 6 5 4 3 2 1 0 COMMAND B0h DRIVE/HEAD 1 1 1 D nu CYLINDER HI C2h CYLINDER LOW 4Fh SECTOR NUM nu SECTOR COUNT XXh ~~——==~~ FEATURES Feature Details of S.M.A.R.T. features are described in Section 11. Swissbit AG Swissbit reserves the right to change products or specifications without notice. Revision: 1.23 Industriestrasse 4 CH-9552 Bronschhofen www.swissbit.com C-440_data_sheet_CF-HxBU_Rev123.doc Switzerland 82 of 106
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## **10.35 Standby (96h or E2)**
This command causes the Card to set BSY, enter the Sleep mode (which corresponds to the ATA ‘Standby’ Mode), clear BSY and return the interrupt immediately. Recovery from Sleep mode is accomplished by issuing another command. Table 100 defines the Standby command Byte sequence.
Table 100: Standby
Task File Register 7 6 5 4 3 2 1 0 COMMAND 96h or E2h DRIVE/HEAD nu D nu CYLINDER HI nu CYLINDER LOW nu SECTOR NUM nu SECTOR COUNT nu ~~==~~ FEATURES nu **10.36 Standby Immediate (94h or E0h)** This command causes the Card to set BSY, enter the Sleep mode (which corresponds to the ATA Standby Mode), clear BSY and return the interrupt immediately.
Recovery from Sleep mode is accomplished by issuing another command. Table 101 defines the Standby Immediate Byte sequence.
Table 101: Standby Immediate Task File Register 7 6 5 4 3 2 1 0 COMMAND 94h or E0h DRIVE/HEAD nu D nu CYLINDER HI nu CYLINDER LOW nu SECTOR NUM nu SECTOR COUNT nu ~~==~~ FEATURES nu **10.37 Translate Sector (87h)** This command is effectively a NOP command and only implemented for backward compatibility. The Sector Count Register will always be returned with a ‘00h’ indicating Translate Sector is not needed. Table 102 defines the Translate Sector command Byte sequence.
Table 102: Translate Sector Task File Register 7 6 5 4 3 2 1 0 COMMAND 87h DRIVE/HEAD 1 LBA 1 D Head (LBA 27:24) CYLINDER HI Cylinder High (LBA23:16) CYLINDER LOW Cylinder Low (LBA15:8) SECTOR NUM nu (LBA7:0) SECTOR COUNT nu ~~——==~~ FEATURES nu Swissbit AG Swissbit reserves the right to change products or specifications without notice. Revision: 1.23 Industriestrasse 4 CH-9552 Bronschhofen www.swissbit.com C-440_data_sheet_CF-HxBU_Rev123.doc Switzerland
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## **10.38 Write Buffer (E8h)**
The Write Buffer command enables the host to overwrite contents of the Card’s sector buffer with any data pattern desired. This command has the same protocol as the Write Sector(s) command and transfers 512 Bytes. Table 103 defines the Write Buffer command Byte sequence.
Table 103: Write Buffer
|Table 103: Write Buffer|||||||||
|---|---|---|---|---|---|---|---|---|
|Task File Register|7|6|5|4|3|2|1|0|
|COMMAND|E8h||||||||
|DRIVE/HEAD|nu|||D|nu||||
|CYLINDER HI|nu||||||||
|CYLINDER LOW|nu||||||||
|SECTOR NUM|nu||||||||
|SECTOR COUNT|nu||||||||
|FEATURES|nu||||||||
## **10.39 Write DMA (CAh)**
This command uses DMA mode to write from 1 to 256 sectors as specified in the Sector Count register. A sector count of 0 requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register. When this command is issued the CompactFlash[TM] Storage Card sets BSY, puts all or part of the sector of data in the buffer. The Card is then permitted, although not required, to set DRQ, clear BSY. The Card asserts DMAREQ while data is available to be transferred. The host then writes the (512 * sector-count) bytes of data to the Card using DMA. While DMAREQ is asserted by the Card, the Host asserts –DMACK while it is ready to transfer data by DMA and asserts –IOWR once for each 16 bit word to be transferred from the Host.
Interrupts are not generated on every sector, but upon completion of the transfer of the entire number of sectors to be transferred or upon the occurrence of an unrecoverable error. At command completion, the Command Block Registers contain the cylinder, head and sector number of the last sector written. If an error occurs, the write terminates at the sector where the error occurred. The Command Block Registers contain the cylinder, head, and sector number of the sector where the error occurred. The amount of data transferred is indeterminate. When a Write DMA command is received by the Card and 8 bit transfer mode has been enabled by the Set Features command, the Card shall return the Aborted error.
Table 104: Write DMA
|Table 104: Write DMA|||||||||
|---|---|---|---|---|---|---|---|---|
|Task File Register|7|6|5|4|3|2|1|0|
|COMMAND|CAh||||||||
|DRIVE/HEAD|LBA|||D|Head (LBA 27:24)||||
|CYLINDER HI|Cylinder High (LBA23:16)||||||||
|CYLINDER LOW|Cylinder Low (LBA15:8)||||||||
|SECTOR NUM|Sector number (LBA7:0)||||||||
|SECTOR COUNT|Sector Count||||||||
|FEATURES|nu||||||||
## **10.40 Write DMA Ext (35h) 48bit LBA**
This command uses DMA mode to write from 1 to 65536 sectors as specified in the Sector Count Register. A sector count of 0 requests 65536 sectors. The transfer begins at the sector specified in the Sector Number Register. When this command is issued the CompactFlash[TM] Storage Card sets BSY, puts all or part of the sector of data in the buffer. The Card is then permitted, although not required, to set DRQ, clear BSY. The Card asserts DMARQ while data is available to be transferred. The host then writes the (512 * sector-count) bytes of data to the Card using the DMA protocol. While DMARQ is asserted by the Card, the Host asserts -DMACK while it is ready to transfer data by DMA and asserts -IOWR once for each 16 bit word to be transferred from the Host.
Interrupts are not generated on every sector, but upon completion of the transfer of the entire number of sectors to be transferred or upon the occurrence of an unrecoverable error.
At command completion, the Command Block Registers contain the LBA of the last sector written. If an error occurs, the write terminates at the sector where the error occurred. The Command Block Registers contain the LBA of the sector where the error occurred. The amount of data transferred is indeterminate.
When a Write DMA command is received by the Card and 8 bit transfer mode has been enabled by the Set Features command, the Card shall return the Aborted error.
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Table 105: Write DMA Ext
|Table 105: Write DMA Ext|Table 105: Write DMA Ext|||||||||
|---|---|---|---|---|---|---|---|---|---|
|register write|previous|current||||||||
|Task File Register|15:8|7|6|5|4|3|2|1|0|
|COMMAND|-|35h||||||||
|DRIVE/HEAD|-|1|1|1|Drive|Reserved||||
|LBA High|LBA (47:40)|LBA (23:16)||||||||
|LBA Mid|LBA (39:32)|LBA (15:8)||||||||
|LBA Low|LBA (31:24)|LBA (7:0)||||||||
|SECTOR COUNT|15:8|7:0||||||||
|FEATURES|nu|nu||||||||
## **10.41 Write Multiple Command (C5h)**
This command is similar to the Write Sectors command. The Card sets BSY within 400ns of accepting the command. Interrupts are not presented on each sector but on the transfer of a block which contains the number of sectors defined by Set Multiple. Command execution is identical to the Write Sectors operation except that the number of sectors defined by the Set Multiple command is transferred without intervening interrupts. DRQ qualification of the transfer is required only at the start of the data block, not on each sector. The block count of sectors to be transferred without intervening interrupts is programmed by the Set Multiple Mode command, which must be executed prior to the Write Multiple command.
When the Write Multiple command is issued, the Sector Count Register contains the number of sectors (not the number of blocks or the block count) requested. If the number of requested sectors is not evenly divisible by the sector/block, as many full blocks as possible are transferred, followed by a final, partial block transfer. The partial block transfer is for n sectors, where:
n = (sector count) module (block count).
If the Write Multiple command is attempted before the Set Multiple Mode command has been executed or when Write Multiple commands are disabled, the Write Multiple operation will be rejected with an aborted command error.
Errors encountered during Write Multiple commands are posted after the attempted writes of the block or partial block transferred. The Write command ends with the sector in error, even if it is in the middle of a block. Subsequent blocks are not transferred in the event of an error. Interrupts are generated when DRQ is set at the beginning of each block or partial block.
The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred and the Sector Count Register contains the residual number of sectors that need to be transferred for successful completion of the command. For example, each block has 4 sectors, a request for 8 sectors is issued and an error occurs on the third sector. The Sector Count Register contains 6 and the address is that of the third sector.
Note: The current revision of the CompactFlash[TM] Memory Card only supports a block count of 1 as indicated in the Identify Drive Command information. The Write Multiple command is provided for compatibility with future products which may support a larger block count.
Table 106 defines the Write Multiple command Byte sequence.
Table 106: Write Multiple
|Table 106: Write Multiple|||||||||
|---|---|---|---|---|---|---|---|---|
|Task File Register|7|6|5|4|3|2|1|0|
|COMMAND|C5h||||||||
|DRIVE/HEAD|1|LBA|1|D|Head (LBA 27:24)||||
|CYLINDER HI|Cylinder High (LBA23:16)||||||||
|CYLINDER LOW|Cylinder Low (LBA15:8)||||||||
|SECTOR NUM|Sector number (LBA7:0)||||||||
|SECTOR COUNT|Sector Count||||||||
|FEATURES|nu||||||||
## **10.42 Write Multiple Ext (39h) 48bit LBA**
The Write Multiple Ext command is similar to the Write Multiple command, except that LBA addressing is mandatory, the LBA associated with this command is a 48 bit address, and the sector count field is a 16 bit field. The second (lower in the table) part of each 16 bit field can be written to or read from by setting the HOB bit of the Device Control Register to 1 before reading or writing the field. Reading or writing the task file shall reset the HOA bit to 0.
Error handling is similar to the Write Multiple command, except that the error sector address is always returned as a 48 bit address, and the sector count is a 16 bit number.
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Table 107: Write Multiple Ext
|register write|previous|current|current|current|current|current|current|current|current|
|---|---|---|---|---|---|---|---|---|---|
|Task File Register|15:8|7|6|5|4|3|2|1|0|
|COMMAND|-|39h||||||||
|DRIVE/HEAD|-|1|1|1|Drive|Reserved||||
|LBA High|LBA (47:40)|LBA (23:16)||||||||
|LBA Mid|LBA (39:32)|LBA (15:8)||||||||
|LBA Low|LBA (31:24)|LBA (7:0)||||||||
|SECTOR COUNT|15:8|7:0||||||||
|FEATURES|nu|nu||||||||
## **10.43 Write Multiple without Erase (CDh)**
This command is similar to the Write Multiple command with the exception that an implied erase before write operation is not performed. The sectors should be pre-erased with the Erase Sector(s) command before this command is issued. Table 108 defines the Write Multiple without Erase command Byte sequence.
Table 108: Write Multiple without Erase
Task File Register 7 6 5 4 3 2 1 0 COMMAND CDh DRIVE/HEAD 1 LBA 1 D Head (LBA 27:24) CYLINDER HI Cylinder High (LBA23:16) CYLINDER LOW Cylinder Low (LBA15:8) SECTOR NUM Sector number (LBA7:0) SECTOR COUNT Sector Count ~~===~~ FEATURES nu **10.44 Write Sector(s) (30h or 31h)** This command writes from 1 to 256 sectors as specified in the Sector Count Register. A sector count of zero requests 256 sectors. The transfer begins at the sector specified in the Sector Number Register. When this command is accepted, the Card sets BSY, sets DRQ and clears BSY, then waits for the host to fill the sector buffer with the data to be written. No interrupt is generated to start the first host transfer operation. No data should be transferred by the host until BSY has been cleared by the host.
For multiple sectors, after the first sector of data is in the buffer, BSY will be set and DRQ will be cleared. After the next buffer is ready for data, BSY is cleared, DRQ is set and an interrupt is generated. When the final sector of data is transferred, BSY is set and DRQ is cleared. It will remain in this state until the command is completed at which time BSY is cleared and an interrupt is generated. If an error occurs during a write of more than one sector, writing terminates at the sector where the error occurred. The Command Block Registers contain the cylinder, head and sector number of the sector where the error occurred. The host may then read the command block to determine what error has occurred, and on which sector. Table 109 defines the Write Sector(s) command Byte sequence.
Table 109: Write Sector(s)
Task File Register 7 6 5 4 3 2 1 0 COMMAND 30h or 31h DRIVE/HEAD 1 LBA 1 D Head (LBA 27:24) CYLINDER HI Cylinder High (LBA23:16) CYLINDER LOW Cylinder Low (LBA15:8) SECTOR NUM Sector number (LBA7:0) SECTOR COUNT Sector Count ~~==~~ FEATURES nu Swissbit AG Swissbit reserves the right to change products or specifications without notice. Industriestrasse 4 CH-9552 Bronschhofen www.swissbit.com C-440_data_sheet_CF-HxBU_Rev123.doc Switzerland
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## **10.45 Write Sector(s) Ext (34h) 48bit LBA**
This is the 48-bit address version of the Write Sector(s) command.
This command writes from 1 to 65,536 sectors as specified in the Sector Count Register. A sector count value of 0000h requests 65,536 sectors. The device shall interrupt for each DRQ block transferred.
If an error occurs during a write of more than one sector, writing terminates at the sector where the error occurs. The Command Block Registers contain the 48-bit LBA of the sector where the error occurred. The host may then read the command block to determine what error has occurred, and on which sector.
Table 110: Write Sector(s) Ext
register write previous current Task File Register 15:8 7 6 5 4 3 2 1 0 - COMMAND 34h DRIVE/HEAD - 1 1 1 Drive Reserved LBA High LBA (47:40) LBA (23:16) LBA Mid LBA (39:32) LBA (15:8) LBA Low LBA (31:24) LBA (7:0) SECTOR COUNT 15:8 7:0 ~~a~~ FEATURES nu nu **10.46 Write Sector(s) without Erase (38h)** This command is similar to the Write Sector(s) command with the exception that an implied erase before write operation is not performed. This command has the same protocol as the Write Sector(s) command. The sectors should be pre-erased with the Erase Sector(s) command before this command is issued. If the sector is not preerased a normal write sector operation will occur. Table 111 defines the Write Sector(s) without Erase command Byte sequence.
Table 111: Write Sector(s) without Erase
Task File Register 7 6 5 4 3 2 1 0 COMMAND 38h DRIVE/HEAD 1 LBA 1 D Head (LBA 27:24) CYLINDER HI Cylinder High (LBA23:16) CYLINDER LOW Cylinder Low (LBA15:8) SECTOR NUM Sector number (LBA7:0) SECTOR COUNT Sector Count ~~==~~ FEATURES nu **10.47 Write Verify (3Ch)** This command is similar to the Write Sector(s) command, except each sector is verified immediately after being written. This command has the same protocol as the Write Sector(s) command. Table 112 defines the Write Verify command Byte sequence. Table 112: Write Verify Task File Register 7 6 5 4 3 2 1 0 COMMAND 3Ch DRIVE/HEAD 1 LBA 1 D Head (LBA 27:24) CYLINDER HI Cylinder High (LBA23:16) CYLINDER LOW Cylinder Low (LBA15:8) SECTOR NUM Sector number (LBA7:0) SECTOR COUNT Sector Count ~~===~~ FEATURES nu Swissbit AG Swissbit reserves the right to change products or specifications without notice. Industriestrasse 4 CH-9552 Bronschhofen www.swissbit.com C-440_data_sheet_CF-HxBU_Rev123.doc Switzerland
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## **11 S.M.A.R.T Functionality**
The C-4x0 CF cards support the following SMART commands, determined by the Feature Register value.
Table 113: S.M.A.R.T. Features Supported
|Feature<br>~~—_—~~|Operation<br>~~—_—~~|
|---|---|
|D0h<br>~~—_—~~|SMART Read Data<br>~~—_—~~|
|D1h<br>~~—_—~~|SMART Read Attribute Thresholds<br>~~—_—~~|
|D2h<br>~~—_—~~|SMART Enable/Disable Attribute<br>~~—_—~~|
|D8h<br>~~—_—~~|SMART Enable Operations<br>~~—_—~~|
|D9h<br>~~—_—~~|Autosave SMART Disable Operations<br>~~—_—~~|
|DAh<br>~~—_—~~|SMART Return Status<br>~~—_—~~|
## **11.1 S.M.A.R.T. Enable / Disable operations**
This command enables / disables access to the SMART capabilities of the CF card. The state of SMART (enabled or disabled) is preserved across power cycles.
Table 114: S.M.A.R.T. Enable / Disable operations (Feature D8h / D9h)
Task File Register 7 6 5 4 3 2 1 0 COMMAND B0h DRIVE/HEAD 1 1 1 D nu CYLINDER HI C2h CYLINDER LOW 4Fh SECTOR NUM nu SECTOR COUNT nu ~~===~~ FEATURES D8h / D9h **11.2 S.M.A.R.T. Enable / Disable Attribute Autosave** This command is effectively a no-operation as the data for the SMART functionality is always available and kept current in the CF card.
Table 115: S.M.A.R.T. Enable / Disable Attribute Autosave (Feature D2h) Task File Register 7 6 5 4 3 2 1 0 COMMAND B0h DRIVE/HEAD 1 1 1 D nu CYLINDER HI C2h CYLINDER LOW 4Fh SECTOR NUM nu SECTOR COUNT 00h or F1h ~~==~~ FEATURES D2h **11.3 S.M.A.R.T. Read data** This command returns one sector of SMART data. Table 116: S.M.A.R.T. read data (Feature D0h) Task File Register 7 6 5 4 3 2 1 0 COMMAND B0h DRIVE/HEAD 1 1 1 D nu CYLINDER HI C2h CYLINDER LOW 4Fh SECTOR NUM nu SECTOR COUNT nu ~~==~~ FEATURES D0h Swissbit AG Swissbit reserves the right to change products or specifications without notice. Revision: 1.23 Industriestrasse 4 CH-9552 Bronschhofen www.swissbit.com C-440_data_sheet_CF-HxBU_Rev123.doc Switzerland industrial@swissbit.com Page 88 of 106
The data structure returned is:
## Table 117: S.M.A.R.T. Data Structure
|~~a~~||~~(~~|
|---|---|---|
|Offset<br>~~a~~|Value Descri|Value Description<br>~~(~~|
|0..1<br>~~a~~<br>~~es~~<br>~~sO~~|0010h SMART structure version for firmware<br>~~sO~~|0010h SMART structure version for firmware“1”<br>~~(~~|
|2..361<br>~~es~~<br>~~sO~~<br>~~Re Oe~~|~~sO~~<br>~~Oe~~|Attribute entries 1 to 30 (12 bytes each)|
|362<br>~~sO~~<br>~~Re Oe~~|00h<br>~~sO~~<br>~~Oe~~|Off-line data collection status (no off-line data collection)|
|363<br>~~Re Oe~~<br>~~nn~~<br>~~ne~~|00h<br>~~Oe~~<br>~~nn~~|Self-test execution status byte (self-test completed)<br>~~nn~~|
|364..365<br>~~ne~~<br>~~Re Oe~~|0000h Total time to complete off<br>~~Oe~~|0000h Total time to complete off-line data collection|
|366<br>~~ne~~<br>~~Re Oe~~|00h<br>~~Oe~~|-|
|367<br>~~Re Oe~~<br>~~nn~~<br>~~ne~~|00h<br>~~Oe~~<br>~~nn~~|Off-line data collection capability (no off-line data collection)<br>~~nn~~|
|368..369<br>~~ne~~<br>~~sO~~|0003h SMART capabilities<br>~~sO~~|0003h SMART capabilities|
|370<br>~~ne~~<br>~~sO~~<br>~~Re Oe~~|00h<br>~~sO~~<br>~~Oe~~|Error logging capability (no error logging)|
|371<br>~~sO~~<br>~~Re Oe~~|00h<br>~~sO~~<br>~~Oe~~|-|
|372<br>~~Re Oe~~<br>~~nn~~<br>~~ne~~|00h<br>~~Oe~~<br>~~nn~~|Short self-test routine recommended polling time<br>~~nn~~|
|373<br>~~ne~~|00h|Extended self-test routine recommended polling time|
|374..385<br>~~ne~~<br>~~sO~~<br>~~es~~|00h<br>~~sO~~|Reserved|
|386..387<br>~~es~~<br>~~ns~~|0004h SMART Swissbit Structure Version for SMART for firmware<br>~~Gn~~|0004h SMART Swissbit Structure Version for SMART for firmware“1”<br>~~Gn~~|
|388..391<br>~~es~~<br>~~ns~~<br>~~ne~~|~~Gn~~|“Commit”counter<br>~~Gn~~|
|392..395<br>~~ns~~<br>~~ne~~<br>~~es es~~|~~Gn~~<br>~~es~~|Wear Level Threshold<br>~~Gn~~|
|396<br>~~ne~~<br>~~es es~~<br>~~ns~~|~~es~~<br>~~Gn~~|Global Bad Block Management active<br>~~Gn~~|
|397<br>~~es es~~<br>~~ns~~<br>~~ne~~|~~es~~<br>~~Gn~~|Global Wear Leveling active<br>~~Gn~~|
|398..401<br>~~ns~~<br>~~ne~~<br>~~es es~~|~~Gn~~<br>~~es~~|Average Flash Block Erase Count<br>~~Gn~~|
|402..405<br>~~ne~~<br>~~es es~~<br>~~es~~|~~es~~|Number of Flash Blocks involved into the Wear Leveling|
|406..510<br>~~es es~~<br>~~es~~<br>~~ns~~|00h<br>~~es~~|-|
|511<br>~~es~~<br>~~ns~~||Data structure checksum|
The byte order for the multi-byte values is little Endian (least significant byte first), unless specified otherwise.
There are 12 attributes that are defined in the CF card. These return their data in the attribute section of the SMART data, using a 12 byte data field.
The field at offset 386 gives a version number for the contents of the SMART data structure.
The byte at offset 396 is 0 if the bad block management is still working chip local, and 1 if the global bad block management has started. This happens when one of the flash chips runs out of spare blocks, in this case spare blocks from different flash chips are used.
The byte at offset 397 is 0 if the wear leveling has not yet started its global operation and 1 if the global wear leveling has started. This happens when the most used chip has reached the erase count threshold defined in the Erase Count Attribute.
In the following sections the Attributes for different SMART structure versions (Byte 0…1) are specified that may depend on the firmware.
## 11.3.1 SMART Attributes for SMART structure version 0010h
## 11.3.1.1 Spare Block Count Attribute
This attribute gives information about the amount of available spare blocks.
Table 118: Spare Block Count Attribute for SMART structure version 0010h
|Offset|Value|Description|
|---|---|---|
|0|c4h|Attribute ID–Reallocation Count|
|1..2|0003h|Flags–Pre-fail type, value is updated during normal operation|
|3||Attribute value. The value returned here is the minimum percentage of remaining<br>spare blocks over all flash chips, i.e. min over all chips (100 × current spare blocks<br>/ initial spare blocks)|
|4||Attribute value (worst value)|
|5..7||sum of initial number of spare blocks for all flash chips|
|8..10||sum of the current number of spare blocks for all flash chips|
|11|00h|Reserved|
This attribute is used for the SMART Return Status command. If the attribute value field is less than the spare block threshold, the SMART Return Status command will indicate a threshold exceeded condition.
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## 11.3.1.2 Spare Block Count Worst Chip Attribute Threshold
This attribute gives information about the amount of available spare blocks on the flash chip that has the lowest current number of spare blocks.
Table 119: Spare Block Count Attribute for SMART structure version 0010h
|Offset<br>~~———~~|Value<br>~~———~~|Description<br>~~———~~|
|---|---|---|
|0<br>~~———~~|D5h<br>~~———~~|Attribute ID–Reallocation Count<br>~~———~~|
|1..2<br>~~———~~|0003h<br>~~———~~|Flags–Pre-fail type, value is updated during normal operation<br>~~———~~|
|3<br>~~———~~|64h<br>~~———~~|Attribute value. This value is fixed at 100.<br>~~———~~|
|4<br>~~———~~|64h<br>~~———~~|Attribute value (worst value)<br>~~———~~|
|5..7<br>~~———~~|~~———~~|Initial number of spare blocks of the flash chip with the lowest current number of<br>spare blocks<br>~~———~~|
|8..10<br>~~———~~|~~———~~|Current number of spare blocks of the flash chip with the lowest current number<br>of spare blocks<br>~~———~~|
|11<br>~~———~~|00h<br>~~———~~|Reserved<br>~~———~~|
|Offset<br>~~——~~|Value<br>~~——~~|Description<br>~~——~~|
|---|---|---|
|0<br>~~——~~|E5h<br>~~——~~|Attribute ID–Erase Count Usage (vendor specific)<br>~~——~~|
|1..2<br>~~——~~|0003h<br>~~——~~|Flags–Pre-fail type, value is updated during normal operation<br>~~——~~|
|3<br>~~——~~|~~——~~|Attribute value. The value returned here is an estimation of the remaining card<br>life, in percent, based on the number of flash block erases compared to the target<br>number of erase cycles per block.<br>~~——~~|
|4<br>~~——~~|~~——~~|Attribute value (worst value)<br>~~——~~|
|5..10<br>~~——~~|~~——~~|Estimated total number of block erases<br>~~——~~|
|11<br>~~——~~|00h<br>~~——~~|Reserved<br>~~——~~|
## 11.3.1.4 Total ECC Errors Attribute
This attribute gives information about the total number of ECC errors that have occurred on flash read commands. This attribute is not used for the SMART Return Status command.
Table 121: Total ECC Errors Attribute for SMART structure version 0010h
Offset Value Description 0 CBh Attribute ID – Number of ECC errors 1..2 0002h Flags – Advisory type, value is updated during normal operation 3 64h Attribute value. This value is fixed at 100. 4 64h Attribute value (worst value) 5..8 Total number of ECC errors (correctable and uncorrectable) 9..10 - ~~7~~ 11 00h Reserved 11.3.1.5 Correctable ECC Errors Attribute This attribute gives information about the total number of correctable ECC errors that have occurred on flash read commands. This attribute is not used for the SMART Return Status command.
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Table 122: Correctable ECC Errors Attribute for SMART structure version 0010h
|Offset|Value|Description|
|---|---|---|
|0|CCh|Attribute ID–Number of corrected ECC errors|
|1..2|0002h|Flags–Advisory type, value is updated during normal operation|
|3|64h|Attribute value. This value is fixed at 100.|
|4|64h|Attribute value (worst value)|
|5..8||Total number of correctable ECC errors|
|9..10||-|
|11|00h|Reserved|
## 11.3.1.6 UDMA CRC Errors Attribute
This attribute gives information about the total number of UDMA CRC errors that have occurred on flash read commands. This attribute is not used for the SMART Return Status command.
Table 123: UDMA CRC Errors Attribute for SMART structure version 0010h
|Table 123: UDMA CRC Errors Attribute for SMART structure version 0010h||
|---|---|
|Offset<br>Value<br>Description<br>0<br>C7h<br>Attribute ID–UDMA CRC error rate<br>1..2<br>0002h<br>Flags–Advisory type, value is updated during normal operation<br>3<br>64h<br>Attribute value. This value is fixed at 100.<br>4<br>64h<br>Attribute value (worst value)<br>5..8<br>Total number of UDMA CRC errors<br>9..10<br>-<br>11<br>00h<br>Reserved<br>~~==~~||
|11.3.1.7 Total Number of Reads Attribute||
|This attribute gives information about the total number of flash read commands. This can be useful for the||
|interpretation of the number of correctable or total ECC errors. This attribute is not used for the SMART Return||
|Status command.||
|Status command.||
|---|---|
|Table 124: Total Number of Reads Attribute for SMART structure version 0010h||
|Offset<br>Value<br>Description<br>0<br>E8h<br>Attribute ID–Number of Reads (vendor specific)<br>1..2<br>0002h<br>Flags–Advisory type, value is updated during normal operation<br>3<br>64h<br>Attribute value. This value is fixed at 100.<br>4<br>64h<br>Attribute value (worst value)<br>5..10<br>Total number of flash read commands<br>11<br>00h<br>Reserved<br>~~——~~||
|11.3.1.8 Power On Count Attribute||
|Table 125: Power On Count Attribute for SMART structure version 0010h||
|Offset<br>Value<br>Description<br>0<br>0Ch<br>Attribute ID–Power On Count<br>1..2<br>0002h<br>Flags–Advisory type, value is updated during normal operation<br>3<br>64h<br>Attribute value. This value is fixed at 100.<br>4<br>64h<br>Attribute value (worst value)<br>5..8<br>Number of Power On cycles<br>9..10<br>-<br>11<br>00h<br>Reserved<br>~~=~~||
|11.3.1.9 Total LBAs Written Attribute||
|This attribute gives the total amount of data written to the disk, in units of 32MB (65536 sectors). This number can||
|be converted to Terabytes written (TBW) by dividing the raw attribute value by 231.||
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Table 126: Total LBAs Written for SMART structure version 0010h
|Offset|Value|Description|
|---|---|---|
|0|F1h|Attribute ID–Total LBAs Written (vendor specific)|
|1..2|0002h|Flags–Advisory type, value is updated during normal operation|
|3|64h|Attribute value. This value is fixed at 100.|
|4|64h|Attribute value (worst value)|
|5..10||Total number of LBAs written to the disk, divided by 65536|
|11|00h|Reserved|
## 11.3.1.10 Total LBAs Read Attribute
This attribute gives the total amount of data read from the disk, in units of 32MB (65536 sectors). This number can be converted to Terabytes written (TBW) by dividing the raw attribute value by 2[31] .
|Offset<br>~~——————~~|Value<br>~~——————~~|Description<br>~~——————~~|
|---|---|---|
|0<br>~~——————~~|F2h<br>~~——————~~|Attribute ID–Total LBAs Read (vendor specific)<br>~~——————~~|
|1..2<br>~~——————~~|0002h<br>~~——————~~|Flags–Advisory type, value is updated during normal operation<br>~~——————~~|
|3<br>~~——————~~|64h<br>~~——————~~|Attribute value. This value is fixed at 100.<br>~~——————~~|
|4<br>~~——————~~|64h<br>~~——————~~|Attribute value (worst value)<br>~~——————~~|
|5..10<br>~~——————~~|~~——————~~|Total number of LBAs read from the disk, divided by 65536<br>~~——————~~|
|11<br>~~——————~~|00h<br>~~——————~~|Reserved<br>~~——————~~|
|Table 128: Anchor Block Status for SMART structure version 0010h|
|---|
|Offset<br>Value<br>Description<br>0<br>D6h<br>Attribute ID–Anchor Block Status (vendor specific)<br>1..2<br>0002h<br>Flags–Advisory type, value is updated during normal operation<br>3<br>64h<br>Attribute value. This value is fixed at 100.<br>4<br>64h<br>Attribute value (worst value)<br>5..10<br>-<br>11<br>00h<br>Reserved<br>~~——_—~~|
|11.3.1.12 Trim Status Attribute|
|This attribute gives percent ratio for the disk space that is currently in the trimmed state, reported as the|
|attribute value. The range for the attribute value is 1 to 99, it does not reach 100 even for a fully trimmed card|
|since the firmware-management blocks are also counted that do not have a trim status.|
||Table 129: Trim Status for SMART structure version 0010h|Table 129: Trim Status for SMART structure version 0010h||
|---|---|---|---|
|Offset<br>Value<br>Description<br>0<br>D7h<br>Attribute ID–Trim Status (vendor specific)<br>1..2<br>0002h<br>Flags–Advisory type, value is updated during normal operation<br>3<br>64h<br>Attribute value<br>4<br>64h<br>Attribute value (worst value)<br>5..10<br>-<br>11<br>00h<br>Reserved<br>~~———————~~||||
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## **11.4 S.M.A.R.T. Read Attribute Thresholds**
This command returns one sector of SMART attribute thresholds.
## Table 130: S.M.A.R.T. read data (Feature D1h)
|Task File Register|7|6|5|4|3|2|1|0|
|---|---|---|---|---|---|---|---|---|
|COMMAND|B0h||||||||
|DRIVE/HEAD|1|1|1|D|nu||||
|CYLINDER HI|C2h||||||||
|CYLINDER LOW|4Fh||||||||
|SECTOR NUM|nu||||||||
|SECTOR COUNT|nu||||||||
|FEATURES|D1h||||||||
The data structure returned is: Table 131: S.M.A.R.T. Data Structure
|Offset|Value Descri|Value Description|
|---|---|---|
|0..1|0010h SMART structure version for Firmware|0010h SMART structure version for Firmware“1”|
|2..361|Attribute threshold entries 1 to 30 (12 bytes each)|Attribute threshold entries 1 to 30 (12 bytes each)|
|362..379|00h<br>Reserved|Reserved|
|380..510|00h|-|
|511|Data structure checksum|Data structure checksum|
|Table 132: Spare Block Count Attribute Threshold<br>Offset<br>Value<br>Description<br>0<br>C4h<br>Attribute ID–Reallocation Count<br>1<br>19h*<br>Spare Block Count Threshold (*typical 25%, could vary)<br>2..11<br>00h<br>Reserved<br>Table 133: Spare Block Count Worst Chip Attribute Threshold<br>Offset<br>Value<br>Description<br>0<br>D5h<br>Attribute ID–Reallocation Count<br>1<br>00h<br>No threshold<br>2..11<br>00h<br>Reserved<br>Table 134: Erase Count Attribute Threshold<br>Offset<br>Value<br>Description<br>0<br>E5h<br>Attribute ID–Erase Count Usage (vendor specific)<br>1<br>01h*<br>Erase Count Threshold (*typical 1%, could vary)<br>2..11<br>00h<br>Reserved<br>~~——————<—~~|
|---|
|Table 135: Total ECC Errors Attribute Threshold<br>Offset<br>Value<br>Description<br>0<br>CBh<br>Attribute ID–Number of ECC errors<br>1<br>00h<br>No threshold for the Total ECC Errors Attribute<br>2..11<br>00h<br>Reserved<br>Table 136: Correctable ECC Errors Attribute Threshold<br>~~——=~~<br>~~SSS~~|
|Offset<br>Value<br>Description<br>0<br>CCh<br>Attribute ID–Number of corrected ECC errors<br>1<br>00h<br>No threshold for the Correctable ECC Errors Attribute<br>2..11<br>00h<br>Reserved<br>~~——————~~|
|Swissbit AG<br>Swissbit reserves the right to change products or specifications without notice.<br>Revision: 1.23<br>Table 137: UDMA CRC Errors Attribute<br>Offset<br>Value<br>Description<br>0<br>C7h<br>Attribute ID–UDMA CRC error rate<br>1<br>00h<br>No threshold for the UDMA CRC Errors Attribute<br>2..11<br>00h<br>Reserved<br>~~—=a~~|
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Table 138: Total Number of Reads Attribute
**==> picture [504 x 426] intentionally omitted <==**
**----- Start of picture text -----**<br>
|||||
|---|---|---|---|
|Offset|Value|Description|
|0|E8h|Attribute ID – Number of Reads (vendor specific)|
|1|00h|No threshold for the Total Number of Reads Attribute|
|———<—<—|2..11|00h|Reserved|
|Table 139: Power On Count Attribute|
|Offset|Value|Description|
|0|0Ch|Attribute ID – Power On Count|
|1|00h|No threshold for the Power On Count Attribute|
|————|2..11|00h|Reserved|
|Table 140: Total LBAs Written Attribute|
|Offset|Value|Description|
|0|F1h|Attribute ID – Total LBAs Written|(vendor specific)|
|1|00h|No threshold for the Total LBAs Written Attribute|
|———<—<—|2..11|00h|Reserved|
|Table 141: Total LBAs Read Attribute|
|Offset|Value|Description|
|0|F2h|Attribute ID – Total LBAs Read|(vendor specific)|
|1|00h|No threshold for the Total LBAs Read Attribute|
|———<|2..11|00h|Reserved|
|Table 142: Anchor Block Status Attribute|
|Offset|Value|Description|
|0|D6h|Attribute ID – Anchor Block Status (vendor specific)|
|1|00h|No threshold for the Anchor Block Status Attribute|
|————<———|2..11|00h|Reserved|
|Table 143: Trim Status Attribute|
|Offset|Value|Description|
|0|D7h|Attribute ID – Trim Status (vendor specific)|
|1|00h|No threshold for the Trim Status Attribute|
|2..11|00h|Reserved|
|——|
**----- End of picture text -----**<br>
## **11.5 S.M.A.R.T. Return Status**
This command checks the device reliability status. If a threshold exceeded condition exists for either the Spare Block Count attribute or the Erase Count attribute, the device will set the Cylinder Low register to F4h and the Cylinder High register to 2Ch. If no threshold exceeded condition exists, the device will set the Cylinder Low register to 4Fh and the Cylinder High register to C2h.
Table 144: S.M.A.R.T. read data (Feature D1h)
**==> picture [457 x 92] intentionally omitted <==**
**----- Start of picture text -----**<br>
||||||||||
|---|---|---|---|---|---|---|---|---|
|Task File Register|7|6|5|4|3|2|1|0|
|COMMAND|B0h|
|DRIVE/HEAD|1|1|1|D|nu|
|CYLINDER HI|C2h|
|CYLINDER LOW|4Fh|
|SECTOR NUM|nu|
|SECTOR COUNT|nu|
|FEATURES|DAh|
**----- End of picture text -----**<br>
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## **12 CIS information (typical)**
- `0000: Code 01, link 03 D9 01 FF` - Device Info Tuple - Link is 3 bytes - I/O Device, No WPS, speed=250ns if no wait - (One) 2 Kilobytes of address space - End of CISTPL_DEVICE
|000A: Code 1C, link 04|000A: Code 1C, link 04|
|---|---|
|02 D9 01 FF|02 D9 01 FF|
|-|Other Conditions Info Tuple|
|-|Link is 4 bytes|
|-|Conditions: 3V operation is allowed, and WAIT is used|
|-|I/O Device, No WPS, speed = 250 ns if no wait|
|-|(One) 2 Kilobytes of address space|
|-|End of CISTPL_DEVICE|
|0016: Code 18, link 02|0016: Code 18, link 02|
|---|---|
|DF 01|DF 01|
|-|JEDEC programming info Tuple|
|-|Link is 2 bytes|
|-|Device manufacturer ID|
|-|Manufacturer specific info|
`001E: Code 20, link 04 00 00 00 00`
- Manufacturer ID Tuple
- - Link length is 4 bytes - PC Card manufacturer code - Manufacturer specific info
`002A: Code 21, link 02 04 01`
- Function ID Tuple
- - Link length is 2 bytes - Fixed disk drive - R=0: no expansion ROM; P=1: configure at POST
`0032: Code 22, link 02 01 01`
- Function Extension Tuple
- - Link length is 2 bytes
- Disk interface information
- PC card ATA interface
`003A: Code 22, link 03 02 04 07`
- Function Extension Tuple
- - Link length is 3 bytes
- PC card ATA basic features
- D=0: single drive on card; U=0: no unique serial number; S=1: silicon device; V=0: no VPP required
- - I=0: twin IOIS16# unspecified; E=0: index bit not emulated; N=0: I/O includes 0x3F7;
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## P=7: sleep, standby, idle supported
`0044: Code 1A, link 05`
`01 07 00 02 07`
- Configuration Tuple
- - Link length is 5 bytes - RFS: reserved; RMS: 1 byte register mask; RAS: 2 bytes base address - Last configuration entry is 07H
- Configuration registers are located at 0200h
- - Configuration registers 0 to 2 are present
## `0052: Code 1B, link 0B C0 C0 A1 27 55 4D 5D 75 08 00 20`
- Configuration Tuple
- Link length is 11 bytes
- Memory mapped configuration, index=0; I=1: Interface byte follows; D=1: Default entry
- W=1: wait required; R=1: ready/busy active; P=0: WP not used; B=0: BVD1, BVD2 not used; Type=0: Memory interface
- M=1: misc info present; MS=1: 2 byte memory length; IR=0: no interrupt is used; IO=0: no I/O space is used; T=0: no timing info specified; Power=1: VCC info, no VPP
- DI: no power-down current; PI=1: peak current info; AI: no average current info;
SI: no static current info; HV=1: max voltage info; LV=1: min voltage info; NV=1: nominal voltage info - Nominal voltage 5.0V
- Minimum voltage 4.5V
- Maximum voltage 5.5V
- Peak current 80 mA
- Length of memory space is 2 Kbyte
- - X=0: no more misc fields; P=1: power-down supported; RO=0: read/write media; A=0: audio not supported; T=0: no twins supported
## `006C: Code 1B, link 06 00 01 21 B5 1E 4D`
- Configuration Tuple
- Link length is 6 bytes
- Memory mapped configuration, index=0
- Power=1: VCC info, no VPP
- PI=1: peak current info; NV=1: nominal voltage info
- X=1: extension byte present
- - Nominal voltage 3.30V - Peak current 45 mA
`007C: Code 1B, link 0D`
`C1 41 99 27 55 4D 5D 75 64 F0 FF FF 20`
- Configuration Tuple
- - Link length is 11 bytes
- Memory mapped configuration, index=0; I=1: Interface byte follows; D=1: Default entry
- W=1: wait required; R=1: ready/busy active; P=0: WP not used; B=0: BVD1, BVD2 not used; Type=0: Memory interface
- M=1: misc info present; MS=1: 2 byte memory length; IR=0: no interrupt is used;
- IO=0: no I/O space is used; T=0: no timing info specified; Power=1: VCC info, no VPP
- DI: no power-down current; PI=1: peak current info; AI: no average current info;
- SI: no static current info; HV=1: max voltage info; LV=1: min voltage info; NV=1: nominal voltage info
- - Nominal voltage 5.0V
- Minimum voltage 4.5V
- Maximum voltage 5.5V
- Peak current 80 mA
- Length of memory space is 2 Kbyte
- X=0: no more misc fields; P=1: power-down supported; RO=0: read/write media; A=0: audio not supported; T=0: no twins supported
Swissbit reserves the right to change products or specifications without notice.
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## `009A: Code 1B, link 06 01 01 21 B5 1E 4D`
- Configuration Tuple
- Link length is 6 bytes
- - I/O mapped, index=1
- Power=1: VCC info, no VPP
- PI=1: peak current info; NV=1: nominal voltage info
- - X=1: extension byte present - Nominal voltage 3.30V - Peak current 45 mA
## `00AA: Code 1B, link 12`
`C2 41 99 27 55 4D 5D 75 EA 61 F0 01 07 F6 03 01 EE 20`
- Configuration Tuple
- Link length is 18 bytes
- I/O mapped, index=2; I=1: Interface byte follows; D=1: Default entry
- W=0: wait not required; R=1: ready/busy active; P=0: WP not used; B=0: BVD1, BVD2 not used; Type=1: I/O interface
- M=1: misc info present; MS=0: no memory space info; IR=1: interrupt is used; IO=1: I/O space is used; T=0: no timing info specified; Power=1: VCC info, no VPP
- DI: no power-down current; PI=1: peak current info; AI: no average current info; SI: no static; current info; HV=1: max voltage info; LV=1: min voltage info; NV=1: nominal voltage info
- - Nominal voltage 5.0V
- Minimum voltage 4.5V
- Maximum voltage 5.5V
- - Peak current 80 mA
- R=1: range follows; S=1: support 16 bit hosts; E=1: support 8 bit hosts; IO=10: 10 lines decoded
- LS=1: 1 byte length; AS=2: 2 byte address; NR=1: 2 address ranges
- - Address range 1 0x1F0 to 0x1F7
- Address range 2 0x3F6 to 0x3F7
- S=1: interrupt sharing logic; P=1: pulse mode supported; L=1: level mode supported; M=0: masks V..N not present; IRQN=14: use interrupt 14
- X=0: no more misc fields; P=1: power-down supported; RO=0: read/write media; A=0: audio not supported; T=0: no twins supported
`00D2: Code 1B, link 06 02 01 21 B5 1E 4D`
- Configuration Tuple
- Link length is 6 bytes
- I/O mapped, index=2
- Power=1: VCC info, no VPP
- PI=1: peak current info; NV=1: nominal voltage info
- X=1: extension byte present
- Nominal voltage 3.30V
- - Peak current 45 mA
`00E2: Code 1B, link 12`
`C3 41 99 27 55 4D 5D 75 EA 61 70 01 07 76 03 01 EE 20`
- Configuration Tuple
- Link length is 18 bytes
- I/O mapped, index=2; I=1: Interface byte follows; D=1: Default entry
- W=0: wait not required; R=1: ready/busy active; P=0: WP not used; B=0: BVD1, BVD2 not used; Type=1: I/O interface
- M=1: misc info present; MS=0: no memory space info; IR=1: interrupt is used; IO=1: I/O space is used; T=0: no timing info specified; Power=1: VCC info, no VPP
- DI: no power-down current; PI=1: peak current info; AI: no average current info; SI: no static; current info; HV=1: max voltage info; LV=1: min voltage info; NV=1: nominal voltage info
Swissbit reserves the right to change products or specifications without notice.
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- Nominal voltage 5.0V
- Minimum voltage 4.5V
- Maximum voltage 5.5V
- - Peak current 80 mA
- R=1: range follows; S=1: support 16 bit hosts; E=1: support 8 bit hosts; IO=10: 10 lines decoded
- - LS=1: 1 byte length; AS=2: 2 byte address; NR=1: 2 address ranges - Address range 1 0x170 to 0x177 - Address range 2 0x376 to 0x377
- S=1: interrupt sharing logic; P=1: pulse mode supported; L=1: level mode supported; M=0: masks V..N not present; IRQN=14: use interrupt 14
- X=0: no more misc fields; P=1: power-down supported; RO=0: read/write media; A=0: audio not supported; T=0: no twins supported
## `010A: Code 1B, link 06`
`03 01 21 B5 1E 4D`
- Configuration Tuple
- Link length is 6 bytes
- I/O mapped, index=3
- Power=1: VCC info, no VPP
- PI=1: peak current info; NV=1: nominal voltage info
- - X=1: extension byte present - Nominal voltage 3.30V - Peak current 45 mA
## `011A: Code 1B, link 04`
`07 00 28 D3`
- Configuration Tuple
- Link length is 4 bytes
- I/O mapped, index=7
- No feature descriptions follow
- - Swissbit specific data - Swissbit specific data
## `0126: Code 14, link 00`
- No link control Tuple
- - Link length is 0 bytes
## `012A: Code 15, link` _**`14*)`**_
## `04 01` _**`53 77 69 73 73 62 69 74 00 43 46 20 43 61 72 64`**_ `00 FF *)`
- Level 1 version/product info
- Link length is 21 bytes
- PCMCIA2.0/JEIDA4.1
- - PCMCIA2.0/JEIDA4.1
- Product name: “ Swissbit ” “ CF Card ” *) can vary in different configurations
- - The length of the strings will affect the following start addresses
## _**`0156`**_ `: Code FF, link FF`
- End of CISTPL_VERS_1
- End of CIS
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## **13 Package mechanical**
## Figure 21: Type I CompactFlash[TM] Memory Card Dimensions
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## **14 Declaration of Conformity** CE
We
Manufacturer:
Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Switzerland
declare under our sole responsibility that the product
Product Type: CompactFlash™ Card Brand Name: SWISSMEMORY™ CompactFlash™ Product Series: C-440 Part Number: SFCFxxxxHxxxxxx-x-xx-xxx-xxx
to which this declaration relates is in conformity with the following directives:
EN55022:2006 +A1:r B FCC47 Part 15 Subpart B §15.111 EN 61000-4-2:2009 EN 61000-4-3:2006+A1:2008+A2:2010 EN 61000-6-2:2005 2012/19/EC Category 3 (WEEE)
following the provisions of Directive
Electromagnetic compatibility 2004/108/EC Restriction of the use of certain hazardous substances 2011/65/EU
Swissbit AG, February 2014
**==> picture [95 x 40] intentionally omitted <==**
**----- Start of picture text -----**<br>
qe F<br>**----- End of picture text -----**<br>
Manuela Kögel Head of Quality Management
Swissbit AG Industriestrasse 4 CH-9552 Bronschhofen Switzerland
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## **15 RoHS and WEEE update from Swissbit**
Dear Valued Customer,
We at Swissbit place great value on the environment and thus pay close attention to the diverse aspects of manufacturing environmentally and health friendly products. The European Parliament and the Council of the European Union have published two Directives defining a European standard for environmental protection. This states that CompactFlash Cards must comply with both Directives in order for them to be sold on the European market:
- RoHS – Restriction of Hazardous Substances
- WEEE – Waste Electrical and Electronic Equipment
Swissbit would like to take this opportunity to inform our customers about the measures we have implemented to adapt all our products to the European norms.
## What is the WEEE Directive (2012/19/EC)?
The Directive covers the following points:
- Prevention of WEEE
- Recovery, recycling and other measures leading to a minimization of wastage of electronic and electrical equipment
- Improvement in the quality of environmental performance of all operators involved in the EEE life cycle, as well as measures to incorporate those involved at the EEE waste disposal points
## What are the key elements?
The WEEE Directive covers the following responsibilities on the part of producers:
Producers must draft a disposal or recovery scheme to dispose of EEE correctly. Producers must be registered as producers in the country in which they distribute the goods. They must also supply and publish information about the EEE categories.
Producers are obliged to finance the collection, treatment and disposal of WEEE.
## Inclusion of WEEE logos on devices
In reference to the Directive, the WEEE logo must be printed directly on all devices that have sufficient space. «In exceptional cases where this is necessary because of the size of the product, the symbol of the WEEE Directive shall be printed on the packaging, on the instructions of use and on the warranty» (WEEE Directive 2012/19/EC)
## When does the WEEE Directive take effect?
The Directive came into effect internationally on July 04, 2012.
## What is RoHS (2011/65/EU)?
The goals of the Directive are to:
- Place less of a burden on human health and to protect the environment by restricting the use of hazardous substances in new electrical and electronic devices
- To support the WEEE Directive (see above)
RoHS enforces the restriction of the following 6 hazardous substances in electronic and electrical devices:
- Lead (Pb) – no more than 0.1% by weight in homogeneous materials
- Mercury (Hg) – no more than 0.1% by weight in homogeneous materials
- Cadmium (Cd) – no more than 0.01% by weight in homogeneous materials
- Chromium (Cr6+) – no more than 0.1% by weight in homogeneous materials
- PBB, PBDE – no more than 0.1% by weight in homogeneous materials
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## Swissbit is obliged to minimize the hazardous substances in the products.
According to part of the Directive, manufacturers are obliged to make a self-declaration for all devices with RoHS. Swissbit carried out intensive tests to comply with the self-declaration. We have also already taken steps to have the analyses of the individual components guaranteed by third-party companies.
Swissbit carried out the following steps during the year with the goal of offering our customers products that are fully compliant with the RoHS Directive.
- Preparing all far-reaching directives, logistical enhancements and alternatives regarding the full understanding and introduction of the RoHS Directive’s standards
- Checking the components and raw materials:
- Replacing non-RoHS-compliant components and raw materials in the supply chain
- `o` Cooperating closely with suppliers regarding the certification of all components and raw materials used by Swissbit
- Modifying the manufacturing processes and procedures
- Successfully adapting and optimizing the new management-free integration process in the supply chain
- Updating existing production procedures and introducing the new procedures to support the integration process and the sorting of materials
- Carrying out the quality process
- Performing detailed function and safety tests to ensure the continuous high quality of the Swissbit product line
## When does the RoHS Directive take effect?
As of June 08, 2011 only new electrical and electronic devices with approved quantities of RoHS will be put on the market.
When will Swissbit be offering RoHS-approved products?
Swissbit’s RoHS-approved products are available now. Please contact your Swissbit contact person to find out more about exchanging your existing products for RoHS-compliant devices.
For your attention
We understand that packaging and accessories are not EEE material and are therefore not subject to the WEEE or RoHS Directives.
Contact details: Swissbit AG Industriestrasse 4-8 CH 9552 Bronschhofen Tel: +41 71 913 03 03 – Fax: +41 71 913 03 15 E-mail: info@swissbit.com – Website: www.swissbit.com
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## **16 Part Number Decoder**
**S F CF 32GB H 2 B U 4 TO** - **I - Q T - 517 - STD** 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Manuf. Option Memory Type Configuration Product Type Manuf. Code: Flash Mode Density Manuf. Code: Flash Package Form Factor Temp. Option Product Generation Flash vendor Code Memory Organization Number of flash chips Technology
## **16.1 Manufacturer**
## **16.2 Memory Type**
|Swissbit code|S|
|---|---|
|||
|Flash|F|
## **16.3 Product Type**
## **16.4 Density**
## **16.5 Platform**
## **16.6 Product Generation**
## **16.7 Memory Organization**
## **16.8 Controller type**
## **16.9 Number of Flash Chip**
## **16.10 Flash Code**
||Compact Flash||CF|
|---|---|---|---|
|2 GByte<br>2048<br>4 GByte<br>4096<br>8 GByte<br>8192<br>16 GByte<br>16GB<br>32 GByte<br>32GB<br>64GByte<br>64GB<br>128 GByte<br>128G<br>Compact Flash<br>H<br>~~—~~||||
||First generation||1|
||Second generation||2|
|||||
||x8||B|
|||||
||C-400 Series|CF Card|U|
|||||
||1 Flash||1|
||2 Flash||2|
||4 Flash||4|
|||||
||Toshiba||TO|
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Micron MT Samsung SA
## **16.11 Temp. Option**
Industrial Temp. Range -40°C …+85°C I Standard Temp Range 0°C …+70°C C
## **16.12 DIE Classification**
## **16.13 PIN Mode**
## **16.14 Compact Flash XYZ**
## **16.15 Option**
SLC MONO (single die package) M SLC DDP (dual die package) D SLC QDP (quad die package) Q ~~——=~~ SLC ODP (Octal die package) N - Normal nCE & R/nB TSOP S Dual nCE & Dual R/nB - TSOP T - Quad nCE & Quad R/nB TSOP U Normal nCE & R/nB – LGA A Dual nCE & Dual R/nB – LGA B – ~~==~~ Quad nCE & Quad R/nB LGA C X CFC Mode
Removable/fix DMA True IDE PC Card PIO X support Mode Mode Removable yes yes 1 Fix yes yes 2 Fix yes - 3 - Removable yes 4 Fix Removable yes yes 5* ~~==~~ Fix Removable yes - 6 *default Y Firmware revision per product generation FW Revision Y First FW Revision 1 ~~—~~ Second FW Revision 2 Z max performance index Max PIO Mode / CIS Z PIO4 (MDMA2 if enabled) 1 PIO6 (MDMA4 if enabled) 2 UDMA4 (PIO6, MDMA4) 3 UDMA6 (MDMA2, PIO4) 6 ~~—=~~ UDMA6 (MDMA4, PIO6) 7 Standard STD Only LBA28 command support L28
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## **17 Swissbit CF Label specification**
## **17.1 Front side label**
## **17.2 Back side label**
## 17.2.1 Label content
- Swissbit logo
- CF logo
- Part number (defined by the data sheet)
- Barcode as assembly lot number (Code128)
- `o` Lot number
- CE logo
- `o` RoHS logo
- WEEE logo
- Manufacturing date
- “Made in Germany”
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## **18 Revision History**
Table 145: Document Revision History
|Date|Revision Details|Revision Details|
|---|---|---|
|March 28, 2012|1.00|Initial release|
|December 18, 2012|1.10|New CE Declaration, new picture of the back side label|
|May 30, 2013|1.20|Added FW 2, PC-Card specification limitation|
|July 26, 2013|1.21|Added Trim Status attribute|
|September 25, 2013|1.22|3.3V operating voltage expanded to ±10%|
|February 06, 2014|1.23|Added LBA28 differences to STD|
## Disclaimer:
No part of this document may be copied or reproduced in any form or by any means, or transferred to any third party, without the prior written consent of an authorized representative of Swissbit AG (“SWISSBIT”). The information in this document is subject to change without notice. SWISSBIT assumes no responsibility for any errors or omissions that may appear in this document, and disclaims responsibility for any consequences resulting from the use of the information set forth herein. SWISSBIT makes no commitments to update or to keep current information contained in this document. The products listed in this document are not suitable for use in applications such as, but not limited to, aircraft control systems, aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. Moreover, SWISSBIT does not recommend or approve the use of any of its products in life support devices or systems or in any application where failure could result in injury or death. If a customer wishes to use SWISSBIT products in applications not intended by SWISSBIT, said customer must contact an authorized SWISSBIT representative to determine SWISSBIT willingness to support a given application. The information set forth in this document does not convey any license under the copyrights, patent rights, trademarks or other intellectual property rights claimed and owned by SWISSBIT. The information set forth in this document is considered to be “Proprietary” and “Confidential” property owned by SWISSBIT.
ALL PRODUCTS SOLD BY SWISSBIT ARE COVERED BY THE PROVISIONS APPEARING IN SWISSBIT’S TERMS AND CONDITIONS OF SALE ONLY, INCLUDING THE LIMITATIONS OF LIABILITY, WARRANTY AND INFRINGEMENT PROVISIONS. SWISSBIT MAKES NO WARRANTIES OF ANY KIND, EXPRESS, STATUTORY, IMPLIED OR OTHERWISE, REGARDING INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED PRODUCTS FROM INTELLECTUAL PROPERTY INFRINGEMENT, AND EXPRESSLY DISCLAIMS ANY SUCH WARRANTIES INCLUDING WITHOUT LIMITATION ANY EXPRESS, STATUTORY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
©2014 SWISSBIT AG All rights reserved.
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Updated at February 9, 2023
Swissbit is a premier independent European manufacturer specializing in industrial-grade storage and embedded IoT solutions. Founded in 2001, the company is globally recognized for engineering highly reliable products designed to meet the rigorous demands of the industrial, automotive, telecommunications, and medical sectors. With manufacturing operations rooted in Germany, Swissbit delivers exceptional quality, long-term component availability, and custom optimization for mission-critical applications. The core of the company's offering centers on advanced semiconductor memory solutions, with a strong emphasis on high-performance flash memory cards. These robust storage options, which include industrial SD cards, microSD memory cards, and CompactFlash, are specifically engineered to provide secure, reliable data retention in extreme operating environments. Swissbit's flash memory products integrate sophisticated wear-leveling and error-correction technologies to guarantee maximum endurance and data integrity over extended product lifecycles. Beyond portable flash memory cards, Swissbit's comprehensive storage ecosystem encompasses managed NAND BGAs, USB flash drives, and a wide array of solid-state drives across multiple interfaces. By combining cutting-edge packaging expertise with hardware-based security features, Swissbit empowers design engineers to reliably store and protect sensitive data across the entire spectrum of modern connected devices.
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