RJK0355DSP-00#J0

## **RJK0355DSP** 

## Silicon N Channel Power MOS FET Power Switching 

REJ03G1650-0301 Rev.3.01 Apr 24, 2008 

## **Features** 

- Capable of 4.5 V gate drive 

- Low drive current 

- High density mounting 

- Low on-resistance RDS(on) = 8.5 m Ω typ. (at VGS = 10 V) 

- Pb-free 

## **Outline** 

RENESAS Package code: PRSP0008DD-D (Package name: SOP-8<FP-8DAV>) 

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6 5<br>7<br>8<br>1  [2 3 4]<br>**----- End of picture text -----**<br>


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5 6 7 8<br>D D D D<br>4 1, 2, 3      Source<br>G 4              Gate<br>5, 6, 7, 8  Drain<br>S S S<br>1 2 3<br>**----- End of picture text -----**<br>


## **Absolute Maximum Ratings** 

(Ta = 25°C) 

||||(Ta = 25°C)|
|---|---|---|---|
|**Item**|**Symbol**|**Ratings **|**Unit**|
|Drain to source voltage|VDSS|30|V|
|Gate to source voltage|VGSS|±20|V|
|Drain current|ID|12|A|
|Drainpeak current|ID(pulse)<br>Note1|96|A|
|Body-drain diode reverse drain current|IDR|12|A|
|Avalanche current|IAP Note 2|9|A|
|Avalanche energy|EAR Note 2|8.1|mJ|
|Channel dissipation|PchNote3|1.8|W|
|Channel to ambient thermal impedance|θch-aNote3|69.4|°C/W|
|Channel temperature|Tch|150|°C|
|Storage temperature|Tstg|–55 to +150|°C|



Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1% 

2. Value at Tch = 25°C, Rg ≥ 50 Ω 

3. When using the glass epoxy board (FR4 40 x 40 x 1.6 mm), PW ≤ 10s 

REJ03G1650-0301  Rev.3.01  Apr 24, 2008 Page 1 of 6 

**RJK0355DSP** 

## **Electrical Characteristics** 

(Ta = 25°C) 

|||||||(Ta = 25°C)|
|---|---|---|---|---|---|---|
|**Item**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Test Conditions**|
|Drain to source breakdown voltage|V(BR)DSS|30|—|—|V|ID= 10 mA, VGS= 0|
|Gate to source leak current|IGSS|—|—|± 0.1|µA|VGS= ±20 V, VDS= 0|
|Zerogate voltage drain current|IDSS|—|—|1|µA|VDS= 30 V, VGS= 0|
|Gate to source cutoff voltage|VGS(off)|1.2|—|2.5|V|VDS= 10 V, ID= 1 mA|
|Static drain to source on state<br>resistance|RDS(on)|—|8.5|11.1|mΩ|ID= 6 A, VGS= 10 VNote4|
||RDS(on)|—|12.0|16.8|mΩ|ID= 6 A, VGS= 4.5 VNote4|
|Forward transfer admittance||yfs||—|35|—|S|ID= 6 A, VDS= 10 VNote4|
|Input capacitance|Ciss|—|860|—|pF|VDS= 10 V<br>VGS= 0<br>f = 1 MHz|
|Output capacitance|Coss|—|165|—|pF||
|Reverse transfer capacitance|Crss|—|53|—|pF||
|Gate Resistance|Rg|—|4.2|—|Ω||
|Totalgate charge|Qg|—|6.0|—|nC|VDD= 10 V<br>VGS= 4.5 V<br>ID= 6 A|
|Gate to source charge|Qgs|—|2.3|—|nC||
|Gate to drain charge|Qgd|—|1.4|—|nC||
|Turn-on delaytime|td(on)|—|6.9|—|ns|VGS= 10 V, ID= 6 A<br>VDD ≅10 V<br>RL= 1.67Ω<br>Rg = 4.7Ω|
|Rise time|tr|—|3.5|—|ns||
|Turn-off delaytime|td(off)|—|40.2|—|ns||
|Fall time|tf|—|4.8|—|ns||
|Body–drain diode forward voltage|VDF|—|0.82|1.07|V|IF= 12 A, VGS= 0Note3|
|Body–drain diode reverse recovery<br>time|trr|—|20|—|ns|IF= 12 A, VGS= 0<br>diF/ dt = 100 A/µs|



Notes: 4. Pulse test 

REJ03G1650-0301  Rev.3.01  Apr 24, 2008 Page 2 of 6 

**RJK0355DSP** 

## **Main Characteristics** 

Power vs. Temperature Derating 

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4.0<br>Test Condition :<br>   When using the glass epoxy board<br>   (FR4  40x40x1.6 mm), PW ≤ 10 s<br>3.0<br>2.0<br>1.0<br>0 50 100 150 200<br>Ambient Temperature   Ta  (°C)<br>Typical Output Characteristics<br>20<br>4.5 V<br>10 V 3.2 V Pulse Test<br>16<br>12 3.0 V<br>8<br>2.8 V<br>4<br>0 2 4 6 8 10<br>Drain to Source Voltage    VDS   (V)<br>Drain to Source Saturation Voltage vs.<br>Gate to Source Voltage<br>200<br>Pulse Test<br>150<br>100<br>ID = 10 A<br>50 5 A<br>2 A<br>0<br>4 8 12 16 20<br>Gate to Source Voltage    VGS   (V)<br>VGS = 2.6 V<br>Channel Dissipation   Pch  (W)<br>   (A)<br>D<br>Drain Current    I<br>  (mV)<br>DS (on)<br>Drain to Source Saturation Voltage                                     V<br>**----- End of picture text -----**<br>


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Maximum Safe Operation Area<br>**----- End of picture text -----**<br>


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500<br>100<br>10<br>1 Operation in<br>this area is<br>limited by RDS(on)<br>0.1<br>Ta = 25 °C<br>1 shot Pulse<br>0.01<br>0.1 0.3 1 3 10 30 100<br>Drain to Source Voltage   VDS  (V)<br>Note 5 : When using the glass epoxy board<br>  (FR4  40x40x1.6 mm)<br>Typical Transfer Characteristics<br>20<br>VDS = 10 V<br>Pulse Test<br>16<br>12<br>8<br>25°C<br>4 Tc = 75°C<br>–25°C<br>0 1 2 3 4 5<br>Gate to Source Voltage    VGS  (V)<br>PW = 10 ms1 ms<br>100<br>µs<br>10<br>µs<br>Note 5<br>DC Operation (PW ≤ 10 s)<br>  (A)<br>D<br>Drain Current   I<br>   (A)<br>D<br>Drain Current    I<br>**----- End of picture text -----**<br>


Static Drain to Source on State Resistance vs. Drain Current 

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100<br>Pulse Test<br>30<br>VGS = 4.5 V<br>10<br>10 V<br>3<br>1<br>1 3 10 30 100 300 1000<br>Drain Current    ID    (A)<br>)Ω<br>  (m<br>DS (on)<br>Drain to Source on State Resistance                                      R<br>**----- End of picture text -----**<br>


REJ03G1650-0301  Rev.3.01  Apr 24, 2008 Page 3 of 6 

**RJK0355DSP** 

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Static Drain to Source on State Resistance<br>vs. Temperature<br>50<br>Pulse Test<br>40<br>30<br>ID = 2 A, 5 A, 10 A<br>20<br>VGS = 4.5 V<br>10<br>10 V 2 A, 5 A, 10 A<br>0<br>–25 0 25 50 75 100 125 150<br>Case Temperature    Tc    (°C)<br>Dynamic Input Characteristics<br>50 20<br>ID = 12 A VGS<br>40 16<br>VDD = 25 V<br>10 V<br>30 12<br>VDS<br>20 8<br>10 4<br>VDD = 25 V<br>          10 V<br>0 0<br>0 8 16 24 32 40<br>Gate Charge     Qg   (nc)<br>Maximum Avalanche Energy vs.<br>Channel Temperature Derating<br>20<br>IAP = 9 A<br>16 VDD = 15 V<br>duty < 0.1 %<br>Rg ≥ 50 Ω<br>12<br>8<br>4<br>0<br>25 50 75 100 125 150<br>Channel Temperature   Tch  (°C)<br>)Ω<br>  (m<br>DS (on)<br>Static Drain to Source on State Resistance                                                R<br>   (V)<br>DS<br>Drain to Source Voltage    V<br>  (mJ)<br>AR<br>Repetitive Avalanche Energy   E<br>**----- End of picture text -----**<br>


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Typical Capacitance vs.<br>Drain to Source Voltage<br>10000<br>3000<br>1000<br>Ciss<br>300<br>100 Coss<br>30 Crss<br>VGS = 0<br>f = 1 MHz<br>10<br>0 10 20 30<br>Drain to Source Voltage   VDS   (V)<br>Reverse Drain Current vs.<br>Source to Drain Voltage<br>50<br>10 V Pulse Test<br>40 5 V<br>30<br>20<br>10 VGS = 0, –5 V<br>0 0.4 0.8 1.2 1.6 2.0<br>Source to Drain Voltage   VSD  (V)<br>Capacitance   C  (pF)<br>  (A)<br>DR<br>Reverse Drain Current   I<br>**----- End of picture text -----**<br>


REJ03G1650-0301  Rev.3.01  Apr 24, 2008 Page 4 of 6 

**RJK0355DSP** 

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Normalized Transient Thermal Impedance vs. Pulse Width<br>10<br>D = 1<br>1<br>0.5<br>0.1<br>θch - f(t)  = γs (t) x θch - f<br>0.01 θch - f = 100 ° C/W, Ta = 25 ° C<br>When using the glass epoxy board<br>(FR4  40 x 40 x 1.6 mm)<br>0.001 PDM D = [PW] T<br>PW<br>T<br>0.0001<br>10 µ 100 µ 1 m 10 m 100 m 1 10 100 1000 10000<br>Pulse Width   PW  (s)<br>Avalanche Test Circuit Avalanche Waveform<br>1 VDSS<br>VDS L EAR =         L 2 • IAP [2 ] • VDSS – VDD<br>Monitor<br>IAP V<br>Monitor (BR)DSS<br>IAP<br>Rg D. U. T VDD VDS<br>ID<br>Vin<br>50 Ω<br>15 V<br>VDD<br>0<br>Switching Time Test Circuit Switching Time Waveform<br>Vin Monitor Vout 90%<br>Monitor<br>D.U.T.<br>Rg RL Vin 10%<br>Vout 10% 10%<br>Vin VDS<br>10 V = 10 V<br>90% 90%<br>td(on) tr td(off) tf<br>0.1<br>0.05<br>0.2<br>0.02<br>0.01<br>1shot pulse<br>s  (t)<br>γ<br>Normalized Transient Thermal Impedance<br>**----- End of picture text -----**<br>


REJ03G1650-0301  Rev.3.01  Apr 24, 2008 Page 5 of 6 

**RJK0355DSP** 

## **Package Dimensions** 

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Package Name JEITA Package Code RENESAS Code Previous Code MASS[Typ.]<br>SOP-8 P-SOP8-3.95 × 4.9-1.27 PRSP0008DD-D FP-8DAV 0.085g<br>* [1] D<br>8 5 bp<br>Index mark<br>1 4 Terminal cross section NOTE)1. DIMENSIONS "*1(Nom)" AND "*2"<br>Z DO NOT INCLUDE MOLD FLASH.<br>* [3] bp x M (Ni/Pd/Au plating) 2. DIMENSION "*3" DOES NOTINCLUDE TRIM OFFSET.<br>e<br>Reference Dimension in Millimeters<br>Symbol Min Nom Max<br>L1 DE 4.903.95 5.3<br>A2<br>A1 0.10 0.14 0.25<br>A 1.75<br>bp 0.34 0.40 0.46<br>b1<br>c 0.15 0.20 0.25<br>L c1<br>0° 8°<br>y HE 5.80 6.10 6.20<br>Detail F e 1.27<br>x 0.25<br>y 0.1<br>Z 0.75<br>L 0.40 0.60 1.27<br>L1 1.08<br>F<br>E E<br>2* H c<br>A<br>A1<br>**----- End of picture text -----**<br>


## **Ordering Information** 

|**Part No.**|**Quantity**|**Shipping Container**|
|---|---|---|
|RJK0355DSP-00-J0|2500pcs|Taping|



REJ03G1650-0301  Rev.3.01  Apr 24, 2008 Page 6 of 6 

Sales Strategic Planning Div.    Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 

## Notes: 

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© 2008. Renesas Technology Corp., All rights reserved.  Printed in Japan. Colophon .7.2 

To our customers, 

## Old Com an Name in Catalo s and Other Documents p y g 

On April 1[st] , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. 

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Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. 

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Notice<br>1.  All information included in this document is current as of the date this document is issued. Such information, however, is<br>subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please<br>confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to<br>additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.<br>2.  Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights<br>of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.<br>No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights<br>of Renesas Electronics or others.<br>3.  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Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with<br>applicable laws and regulations.<br>11.  This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas<br>Electronics.<br>12.  Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this<br>document or Renesas Electronics products, or if you have any other inquiries.<br>(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-<br>owned subsidiaries.<br>(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.<br>**----- End of picture text -----**<br>