RJE0617JSP-00#J0
Dual MOSFET, Dual P Channel, 60 V, 1.5 A
- Manufacturer: RENESAS
- Product type: Dual MOSFETs
- SVHC: No SVHC (25-Jun-2025)
- No. of Pins: 8Pins
- Channel Type: Dual P Channel
- Product Range: -
- Qualification: AEC-Q101
- Transistor Case Style: SOP
- Operating Temperature Max: 150°C
- Power Dissipation N Channel: -
- Power Dissipation P Channel: 1.5W
- Drain Source Voltage Vds N Channel: -
- Drain Source Voltage Vds P Channel: 60V
- Continuous Drain Current Id N Channel: -
- Continuous Drain Current Id P Channel: 1.5A
- Drain Source On State Resistance N Channel: -
- Drain Source On State Resistance P Channel: 0.35ohm
| Delivery and price | |
|---|---|
| Units per pack | 2500 |
| Price | 1.12 € |
| Current stock | 10+ |
| Lead time | 30 days |
Preliminary Datasheet ## **RJE0617JSP** –60V, –1.5A, P Channel Thermal FET Power Switchin g R07DS1070EJ0500 Rev.5.00 Jan 31, 2020 ## **Description** This FET has the over temperature shut-down capability sensing to the junction temperature. This FET has the built-in over temperature shut-down circuit in the gate area. And this circuit operation to shut-down the gate voltage in case of high junction temperature like applying over power consumption, over current etc.. ## **Features** - Logic level operation (3 V Gate drive). - Built-in the over temperature shut-down circuit. - High endurance capability against to the short circuit. - Hysteresis type shut down operation. - High density mounting. - Built-in the current limitation circuit. - Power supply voltage applies 12 V. - AEC-Q101compliant. ## **Outline** **==> picture [469 x 136] intentionally omitted <==** **----- Start of picture text -----**<br> RENESAS Package code: PRSP0008DD-D<br>(Package name: SOP-8 (FP-8DAV))<br>6 5<br>7<br>8 7 8 5 6<br>1 [2 3 4]<br>2 Current 4 Current<br>Gate Resistor Limitation Gate Resistor Limitation<br>Circuit Circuit 1, 3 Source<br>Temperature Latch Gate Temperature Latch Gate 2, 4 Gate<br>Sensi ng Circuit Shut-d own Sensi ng Circuit Shut-d own 5, 6, 7, 8 Drain<br>Circuit Circuit Circuit Circuit<br>1 3<br>MOS1 MOS2<br>**----- End of picture text -----**<br> ## **Absolute Maximum Ratings** (Ta = 25°C) ||||(Ta = 25°C)| |---|---|---|---| |**Item**|**Symbol**|**Ratings **|**Unit**| |Drainto sourcevoltage|VDSS|–60|V| |Gate to sourcevoltage|VGSS|–16|V| |Gate to source voltage|VGSS|2.5|V| |Draincurrent|IDNote4|–1.5|A| |Body-draindiodereverse draincurrent|IDR|–1.5|A| |Avalanche current|IAPNote 3|–1.5|A| |Avalanche energy|EARNote 3|9.6|mJ| |Channeldissipation|Pch Note 1|1|W| |Channel dissipation|Pch Note 2|1.5|W| |Channeltemperature|Tch|150|C| |Storage temperature|Tstg|–55 to+150|C| Notes: 1. 1 Drive operation : When using the glass epoxy board (FR4 40 40 1.6 mm), PW 10 s 2. 2 Drive operation : When using the glass epoxy board (FR4 40 40 1.6 mm), PW 10 s 3. Tch = 25C, Rg 50 4. It provides by the current limitation lower bound value. R07DS1070EJ0500 Rev.5.00 Jan 31, 2020 Page 1 of 7 **RJE0617JSP** **Preliminary** ## **Typical Operation Characteristics** (Ta = 25°C) |||||||(Ta = 25°C)| |---|---|---|---|---|---|---| |**Item**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Test Conditions**| |Input voltage|VIH|–3|—|—|V|| ||VIL|—|—|–1.2|V|| |Input current<br>(Gate non shut down)|IIH1|—|—|–100|µA|Vi = –8 V,VDS= 0| ||IIH2|—|—|–50|µA|Vi = –3.5 V,VDS= 0| ||IIL|—|—|–10|µA|Vi = –1.2 V,VDS= 0| |Input current<br>(Gate shut down)|IIH(sd)1|—|–0.8|—|mA|Vi = –8 V,VDS= 0| ||IIH(sd)2|—|–0.35|—|mA|Vi = –3.5 V,VDS= 0| |Shut down temperature|Tsd|—|175|—|C|Channel temperature| |Return temperature|Thr|—|105|—|C|Channel temperature| |Gate operation voltage|Vop|–3|—|–12|V|| |Drain current<br>(Current limitation value)|ID limt|–1.5|—|—|A|VGS= –12 V, VDS= –10 VNote 5| Notes; 5. Pulse test ## **Electrical Characteristics** (Ta = 25°C) |||||||(Ta = 25°C)| |---|---|---|---|---|---|---| |**Item**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|**Test Conditions**| |Drain current|ID|–1.5|—|–12|A|VGS= –3.5 V,VDS= –10 VNote 6| ||ID|—|—|–40|mA|VGS= –1.2 V,VDS= –10 V| ||ID|–1.5|—|—|A|VGS= –12 V,VDS= –10 VNote 6| ||ID|–0.8|—|—|A|VGS= –3 V,VDS= –10 VNote 6| |Drain to source breakdown<br>voltage|V(BR)DSS|–60|—|—|V|ID= –10 mA, VGS= 0| |Gate to source breakdown<br>voltage|V(BR)GSS|–16|—|—|V|IG= –800A,VDS= 0| ||V(BR)GSS|2.5|—|—|V|IG= 100A,VDS= 0| |Gate to source leak current|IGSS|—|—|–100|A|VGS= –8 V,VDS= 0| ||IGSS|—|—|–50|A|VGS= –3.5 V,VDS= 0| ||IGSS|—|—|–10|A|VGS= –1.2 V,VDS= 0| ||IGSS|—|—|100|A|VGS= 2.4 V,VDS= 0| |Input current (shut down)|IGS(OP)|—|–0.8|—|mA|VGS= –8 V,VDS= 0| ||IGS(OP)|—|–0.35|—|mA|VGS= –3.5 V,VDS= 0| |Zero gate voltage drain current|IDSS|—|—|–10|A|VDS= –60 V,VGS= 0| ||IDSS|—|—|–10|A|VDS= –48 V, VGS= 0<br>Ta = 125C| |Gate to source cutoff voltage|VGS(off)|–0.9|—|–2.1|V|VDS= –10 V,ID= –1 mA| |Forward transfer admittance||yfs||1.5|2.7|—|S|ID= –0.75 A,VGS= –10 VNote 6| |Static drain to source on state<br>resistance|RDS(on)|—|445|800|m|ID= –0.4 A,VGS= –3VNote 6| ||RDS(on)|—|363|425|m|ID= –0.75 A,VGS= –4 VNote 6| ||RDS(on)|—|272|350|m|ID= –0.75 A,VGS= –10 VNote 6| |Output capacitance|Coss|—|213|—|pF|VDS= –10 V, VGS= 0,<br>f = 1MHz| |Turn-on delaytime|td(on)|—|0.9|—|s|VGS= –10 V, ID= –0.75 A,<br>RL= 40| |Rise time|tr|—|3.4|—|s|| |Turn-off delaytime|td(off)|—|3.2|—|s|| |Fall time|tf|—|6.3|—|s|| |Body-drain diode forward voltage|VDF|—|–0.8|—|V|IF= –1.5 A,VGS= 0| |Body-drain diode reverse<br>recoverytime|trr|—|70|—|ns|IF= –1.5 A, VGS= 0<br>diF/dt = 50 A/s| |Over load shut down<br>operation timeNote 7|tos|—|5.4|—|ms|VGS= –5 V, VDD= –16 V| Notes: 6. Pulse test 7. Including the junction temperature rise of the over loaded condition. R07DS1070EJ0500 Rev.5.00 Jan 31, 2020 Page 2 of 7 **RJE0617JSP** **Preliminary** ## **Main Characteristics** **==> picture [213 x 678] intentionally omitted <==** **----- Start of picture text -----**<br> Power vs. Temperature Derating<br>4.0<br>3.0<br>2.0<br>1.0<br>0<br>0 50 100 150 200<br>Ambient Temperature Ta (°C)<br>Typical Output Characteristics<br>Pulse Test<br>0<br>Drain to Source Voltage VDS (V)<br>Drain Source Saturation Voltage vs.<br>Gate to Source Voltage<br>Pulse Test<br>0<br>0<br>Gate to Source Voltage VGS (V)<br>2 Driver Operation<br>1 Driver Operation<br>Channel Dissipation Pch (W)<br> (A)<br>D<br>Drain Current I<br> (mV)<br>DS(on)<br>Drain to Source Saturation Voltage<br> V<br>**----- End of picture text -----**<br> Maximum Safe Operation Area **==> picture [197 x 401] intentionally omitted <==** **----- Start of picture text -----**<br> Ta = 25 C Thermal shut down<br>1 shot Pulse operation area<br>1 Driver Operation<br>Operation<br>in this area<br>is limited R<br>DS(on)<br>Drain to Source Voltage VDS (V)<br>Note 8:<br>When using the glass epoxy board.<br>(FR4 40 x 40 x 1.6 mm)<br>Typical Transfer Characteristics<br>Pulse Test<br>Tc = 150°C<br>25°C<br>0<br>0<br>PW = 10ms<br>DC Operation (PW<br>≦<br>10s)<br>Note 8<br> (A)<br>D<br>Drain Current I<br> (A)<br>D<br>Drain Current I<br>**----- End of picture text -----**<br> Gate to Source Voltage VGS (V) Static Drain to Source On State Resistance vs. Drain Current **==> picture [180 x 183] intentionally omitted <==** **----- Start of picture text -----**<br> 10000<br>Pulse Test<br>1000<br>100<br>10<br>Drain Current ID (A)<br>**----- End of picture text -----**<br> R07DS1070EJ0500 Rev.5.00 Jan 31, 2020 Page 3 of 7 **RJE0617JSP** **Preliminary** **==> picture [205 x 659] intentionally omitted <==** **----- Start of picture text -----**<br> Static Drain to Source On State Resistance<br>vs. Temperature<br>800<br>Pulse Test<br>−0.75 A<br>ID = −1.5 A<br>600<br>VGS = −3 V −0.4 A<br>−0.4 A<br>400<br>−0.4 A<br>−0.75 A<br>200<br>−4 V ID = −1.5 A<br>−10 V<br>0<br>−50 −25 0 25 50 75 100 125 150<br>Case Temperature Tc (°C)<br>Switching Characteristics<br>100<br>10<br>tf<br>tr<br>td(off)<br>1<br>td(on)<br>V GS = −10 V, V DD = −30 V<br>PW = 300 μs, duty ≤ 1 %<br>0.1<br>−0.1 −1 −10<br>Drain Current ID (A)<br>Reverse Drain Current vs.<br>Source to Drain Voltage<br>–1.5<br>Pulse Test<br>–1.0 –5 V V GS = 0 V<br>–0.5<br>0 –0.5 –1.0 –1.5<br>Source to Drain Voltage VSD (V)<br>)Ω<br> (m<br>DS(on)<br>Static Drain to Source On State Resistance R<br>s)<br>μ<br>Switching Time t (<br> (A)<br>DR<br>Reverse Drain Current I<br>**----- End of picture text -----**<br> Body-Drain Diode Reverse Recovery Time **==> picture [182 x 176] intentionally omitted <==** **----- Start of picture text -----**<br> 1000<br>100<br>di / dt = 50 A / μ s<br>VGS = 0<br>10<br>−0.1 −1 −10<br>Reverse Drain Current IDR (A)<br>Reverse Recovery Time trr (ns)<br>**----- End of picture text -----**<br> Typical Capacitance vs. Drain to Source Voltage **==> picture [197 x 402] intentionally omitted <==** **----- Start of picture text -----**<br> 1000<br>VGS = 0<br>f = 1 MHz<br>Coss<br>100<br>10<br>−0 −10 −20 −30 −40 −50 −60<br>Drain to Source Voltage VDS (V)<br>Gate to Source Voltage vs.<br>Shutdown Time of Load-Short Test<br>−16<br>−14<br>−12<br>−10 VDD = −16 V<br>−8<br>−6<br>−4<br>−2<br>0<br>0.1 1 10 100<br>Shutdown Time of Load-Short Test Pw (ms)<br>Capacitance C (pF)<br> (V)<br>GS<br>Gate to Source Voltage V<br>**----- End of picture text -----**<br> R07DS1070EJ0500 Rev.5.00 Jan 31, 2020 Page 4 of 7 **RJE0617JSP** **Preliminary** **==> picture [419 x 665] intentionally omitted <==** **----- Start of picture text -----**<br> Forward transfer admittance vs. Shutdown Case Temperature vs.<br>Drain Current Gate to Source Voltage<br>10 200<br>Ta = –40°C 180<br>25°C<br>160<br>1 150 ° C<br>140<br>120<br>VDS = –10 V<br>Pulse Test ID = –0.2 A<br>0.1 100<br>–0.1 –1 –10 0<br>Drain Current ID (A) Gate to Source Voltage VGS (V)<br>Normalized Transient Thermal Impedance vs. Pulse Width (1 Drive Operation)<br>10<br>D = 1<br>1<br>0.5<br>0.1<br>0.01<br>When using the glass epoxy board<br>(FR4 40 x 40 x 1.6 mm)<br>0.001 PDM D = [PW] T<br>PW<br>T<br>0.0001<br>1 m 10 m 100 m 1 10 100 1000 10000<br>Pulse Width PW (S)<br>Normalized Transient Thermal Impedance vs. Pulse Width<br>(Operatioon of 2 devices; allowable value per device)<br>10<br>D = 1<br>1<br>0.5<br>0.1<br>0.01<br>When using the glass epoxy board<br>(FR4 40 x 40 x 1.6 mm)<br>0.001 PDM D = [PW] T<br>PW<br>T<br>0.0001<br>1 m 10 m 100 m 1 10 100 1000 10000<br>Pulse Width PW (S)<br>0.1<br>0.1<br>0.2<br>0.2<br>0.02<br>0.02<br>0.05<br>0.05<br>0.01<br>0.01<br>1shot pulse<br>1shot pulse<br>C)<br> °<br>Forward transfer admittance |yfs| (S)<br>Shutdown Case Temperature Tc (<br>**----- End of picture text -----**<br> R07DS1070EJ0500 Rev.5.00 Jan 31, 2020 Page 5 of 7 **RJE0617JSP** **Preliminary** **==> picture [401 x 154] intentionally omitted <==** **----- Start of picture text -----**<br> Switching Time Test Circuit Waveform<br>Vin Monitor Vout Vin<br>Monitor<br>10%<br>D.U.T.<br>Rg RL<br>90%<br>Vin VDD 90% 90%<br>–10 V = –30 V<br>Vout 10% 10%<br>td(on) t r td(off) tf<br>**----- End of picture text -----**<br> **==> picture [439 x 166] intentionally omitted <==** **----- Start of picture text -----**<br> Avalanche Test Circuit Avalanche Waveform<br>VMonitorDS L EAR = 12 L · I AP [2] · VDSS VDSS– VDD<br>IAP<br>Monitor<br>0<br>Rg D. U. T VDD VDD<br>Vin<br>ID<br> –10 V<br>IAP VDS<br>V<br>(BR)DSS<br>**----- End of picture text -----**<br> R07DS1070EJ0500 Rev.5.00 Jan 31, 2020 Page 6 of 7 **RJE0617JSP** **Preliminary** ## **Package Dimensions** **==> picture [482 x 322] intentionally omitted <==** **----- Start of picture text -----**<br> Package Name JEITA Package Code RENESAS Code Previous Code MASS[Typ.]<br>SOP-8 P-SOP8-3.95 × 4.9-1.27 PRSP0008DD-D FP-8DAV 0.085g<br>* [1] D<br>8 5 bp<br>Index mark<br>1 4 Terminal cross section NOTE)1. DIMENSIONS "*1(Nom)" AND "*2"<br>Z DO NOT INCLUDE MOLD FLASH.<br>* [3] bp x M (Ni/Pd/Au plating) 2. DIMENSION "INCLUDE TRIM OFFSET.*3" DOES NOT<br>e<br>Reference Dimension in Millimeters<br>Symbol Min Nom Max<br>L1 DE 4.903.95 5.3<br>A2<br>A1 0.10 0.14 0.25<br>A 1.75<br>bp 0.34 0.40 0.46<br>b1<br>c 0.15 0.20 0.25<br>L c1<br>0° 8°<br>y HE 5.80 6.10 6.20<br>Detail F e 1.27<br>x 0.25<br>y 0.1<br>Z 0.75<br>L 0.40 0.60 1.27<br>L1 1.08<br>F<br>E E<br>2* H c<br>A<br>A1<br>**----- End of picture text -----**<br> ## **Ordering Information** |**Orderable Part Number**|<br>**Quantity**|**Shipping Container**| |---|---|---| |RJE0617JSP-00-J0|2500pcs/reel|Taping| Note: The symbol of 2nd "-" is occasionally presented as "#". R07DS1070EJ0500 Rev.5.00 Jan 31, 2020 Page 7 of 7 **==> picture [481 x 409] intentionally omitted <==** **----- Start of picture text -----**<br> Notice<br>1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. 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Updated at June 9, 2026
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