RFP70N06

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_**RFP70N06**_ 

## _**Data Sheet**_ 

## _**September 2013**_ 

## _**N-Channel Power MOSFET 60V, 70A, 14 mΩ**_ 

These are N-Channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. These transistors can be operated directly from integrated circuits. 

Formerly developmental type TA78440. 

## _**Ordering Information**_ 

|**PART NUMBER**|**PACKAGE**|**BRAND**|
|---|---|---|
|RFP70N06|TO-220AB|RFP70N06|



## _**Features**_ 

- 70A, 60V 

- rDS(on) = 0.014Ω 

- Temperature Compensated PSPICE[®] Model 

- Peak Current vs Pulse Width Curve 

- UIS Rating Curve (Single Pulse) 

- 175[o] C Operating Temperature 

- Related Literature 

- TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” 

## _**Symbol**_ 

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NOTE: When ordering use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in tape and reel, e.g. RF1S70N06SM9A. 

## _**Packaging**_ 

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JEDEC TO-220AB<br>**----- End of picture text -----**<br>


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SOURCE<br>DRAIN<br>GATE<br>DRAIN<br>(FLANGE)<br>**----- End of picture text -----**<br>


©2005 Fairchild Semiconductor Corporation 

RFP70N06 Rev. D1 

_**RFP70N06**_ 

## **Absolute Maximum Ratings** TC = 25[o] C, Unless Otherwise Specified 

||**RFP70N06**|**UNITS**|
|---|---|---|
|Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS|60|V|
|Drain to Gate Voltage (RGS= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . .VDGR|60|V|
|Continuous Drain Current  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID|70|A|
|Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM|Refer to Peak Current Curve||
|Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS|±20|V|
|Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS|Refer to UIS Curve|A|
|Power Dissipation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD|150|W|
|Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .|1.0|W/oC|
|Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG|-55 to 175|oC|
|Maximum Temperature for Soldering|||
|Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . .TL|300|oC|
|Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg|260|oC|



_CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied._ 

## NOTE: 

1. TJ = 25[o] C to 150[o] C. 

## **Electrical Specifications** TC = 25[o] C, Unless Otherwise Specified 

|**PARAMETER**|**SYMBOL**|**TEST CONDITIONS**|**TEST CONDITIONS**|**MIN**|**TYP**|**MAX**|**UNITS**|
|---|---|---|---|---|---|---|---|
|Drain to Source Breakdown Voltage|BVDSS|ID= 250µA, VGS= 0V (Figure 11)||60|-|-|V|
|Gate Threshold Voltage|VGS(TH)|VGS= VDS, ID= 250µA (Figure 10)||2|-|4|V|
|Zero Gate Voltage Drain Current|IDSS|VDS= 60V, VGS= 0V||-|-|1|µA|
|||VDS= 0.8 x Rated BVDSS, TC= 150oC||-|-|25|µA|
|Gate to Source Leakage Current|IGSS|VGS=±20V||-|-|±100|nA|
|Drain to Source On Resistance (Note 2)|rDS(ON)|ID= 70A, VGS= 10V (Figure 9)||-|-|0.014|Ω|
|Turn-On Time|t(ON)|VDD= 30V, ID ≈70A, RL= 0.43Ω,<br>VGS= 10V, RGS= 2.5Ω<br>(Figure 13)<br>~~a~~||-|-|190|ns|
|Turn-On Delay Time|td(ON)|||-|10|-|ns|
|Rise Time|tr|||-|137|-|ns|
|Turn-Off Delay Time|td(OFF)|||-|32|-|ns|
|Fall Time|tf|||-|24|-|ns|
|Turn-Off Time|t(OFF)<br>~~a~~|||-|-|73|ns|
|Total Gate Charge<br>~~———~~|Qg(TOT)<br>~~———~~<br>~~a~~|VGS= 0V to 20V<br>~~———~~<br>~~a~~|VDD= 48V, ID= 70A,<br>RL= 0.68Ω<br>Ig(REF)= 2.2mA<br>(Figure 13)<br>~~———~~|-<br>~~———~~|120<br>~~———~~|156<br>~~———~~|nC<br>~~———~~|
|Gate Charge at 10V<br>~~———~~|Qg(10)<br>~~———~~<br>~~a~~|VGS= 0V to 10V<br>~~———~~<br>~~a~~||-<br>~~———~~|65<br>~~———~~|85<br>~~———~~|nC<br>~~———~~|
|Threshold Gate Charge<br>~~———~~|Qg(TH)<br>~~———~~<br>~~a~~|VGS= 0V to 2V<br>~~———~~<br>~~a~~||-<br>~~———~~|5.0<br>~~———~~|6.5<br>~~———~~|nC<br>~~———~~|
|Input Capacitance<br>~~———~~<br>~~SS~~|CISS<br>~~———~~<br>~~a~~<br>~~SS~~|VDS= 25V, VGS= 0V, f = 1MHz<br>(Figure 12)<br>~~———~~<br>~~a~~<br>~~SS~~||-<br>~~———~~<br>~~SS~~|2250<br>~~———~~<br>~~SS~~|-<br>~~———~~<br>~~SS~~|pF<br>~~———~~<br>~~SS~~|
|Output Capacitance<br>~~SS~~|COSS<br>~~SS~~|||-<br>~~SS~~|792<br>~~SS~~|-<br>~~SS~~|pF<br>~~SS~~|
|Reverse Transfer Capacitance<br>~~SS~~|CRSS<br>~~SS~~|||-<br>~~SS~~|206<br>~~SS~~|-<br>~~SS~~|pF<br>~~SS~~|
|Thermal Resistance, Junction to Case<br>~~SS~~|RθJC<br>~~SS~~|~~SS~~||-<br>~~SS~~|-<br>~~SS~~|1.0<br>~~SS~~|oC/W<br>~~SS~~|
|Thermal Resistance, Junction to Ambient<br>~~SS~~<br>~~SS~~|RθJA<br>~~SS~~<br>~~SS~~|TO-220<br>~~SS~~<br>~~SS~~||-<br>~~SS~~<br>~~SS~~|-<br>~~SS~~<br>~~SS~~|62<br>~~SS~~<br>~~SS~~|oC/W<br>~~SS~~<br>~~SS~~|
|||-<br>~~SS~~||-<br>~~SS~~|-<br>~~SS~~|-<br>~~SS~~|-<br>~~SS~~|



2. Pulse test: pulse width ≤ 300ms, duty cycle ≤ 2%. 

3. Repetitive rating: pulse width is limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) and Peak Current Capability Curve (Figure 5). 

©2005 Fairchild Semiconductor Corporation 

RFP70N06 Rev. D1 

_**RFP70N06**_ 

## _**Typical Performance Curves**_ 

TC = 25[o] C, Unless Otherwise Specified 

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1.2 80<br>70<br>1.0 ry [| | f [yd p | | | fT |<br>60<br>0.8 HN SP<br>50<br>0.6 40<br>pt} IN~ ft —a | TYer| |<br>30<br>0.4 PF TN Ne<br>20<br>0.2 | | | | NE ee<br>0 aaaaN 100 a<br>0 25 50 75 100 125 150 175 25 50 75 100 125 150 175<br>TC, CASE TEMPERATURE ( [o] C) TC, CASE TEMPERATURE ( [o] C)<br>FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE  FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs<br>TEMPERATURE CASE TEMPERATURE<br>, DRAIN CURRENT (A)<br>ID<br>POWER DISSIPATION MULTIPLIER<br>**----- End of picture text -----**<br>


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1<br>0.5<br>So ee<br>ee 0.2 SS _<br>SS PDM<br>0.1 0.1<br>0.05<br>0.02 ee ae ee ee eee eee t1 t 2<br>NOTES:<br>pe 0.01 Oh DUTY FACTOR: D = t1/t2<br>rer Cn rn eet<br>SINGLE PULSE PEAK TJ = PDM x Z θ JC x R θ JC + TC<br>0.01 ee EP<br>10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1]<br>t, RECTANGULAR PULSE DURATION (s)<br>FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE<br>500 1000<br>TC = 25 [o] C<br>peeepes= tthe ere eno<br>FOR TEMPERATURES<br>Se eee eee 100 µ s PSCC ABOVE 25 [o] C DERATE PEAK |<br>100 Ad Se ell FPS CURRENT AS FOLLOWS:<br>EEE te tet TEN I = I25    | 175 ----------------------- 150 – TC   <br>1ms<br>OPERATION IN THIS<br>10 AREA MAY BE LIMITED BY rDS(ON) HE 10ms A VGS = 10V UT |<br>jiimmel 100 ea<br>T C  = 25 [o] C TRANSCONDUCTANCE<br>TJ = MAX RATED MAY LIMIT CURRENT<br>SINGLE PULSE IN THIS REGION<br>1 REIE | EPPB= 50 FSoA SSa<br>1 10 100 ot<br>10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1]<br>VDS, DRAIN TO SOURCE VOLTAGE (V) t, PULSE WIDTH (s)<br>, NORMALIZED<br>JC<br>θ<br> Z<br>THERMAL IMPEDANCE<br>, DRAIN CURRENT (A) , PEAK CURRENT (A)<br>ID IDM<br>**----- End of picture text -----**<br>


**FIGURE 4. FORWARD BIAS SAFE OPERATING AREA** 

**FIGURE 5. PEAK CURRENT CAPABILITY** 

©2005 Fairchild Semiconductor Corporation 

RFP70N06 Rev. D1 

_**RFP70N06**_ 

## _**Typical Performance Curves**_ 

## TC = 25[o] C, Unless Otherwise Specified **(Continued)** 

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300 200<br>If R = 0<br>tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) VGS = 20V VGS = 10V VGS = 8V VGS = 7V<br>If R  ≠  0<br>a tAV = (L/R) ln [(IAS*R)/(1.3*RATED BVDSS-VDD) +1] 160 =<br>100<br>STARTING TJ = 25 [o] C PULSE DURATION = 80 µ s<br>120 DUTY CYCLE = 0.5% MAX<br>TC = 25 [o] C<br>80 V GS  = 6V<br>STARTING TJ = 150 [o] C 40 VGS = 5V<br>BS Zia<br>VGS = 4.5V<br>10 HeaSS e n 0<br>0.01 0.1 1 10 0 1 2 3 4 5<br>tAV, TIME IN AVALANCHE (ms) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>, DRAIN CURRENT (A)<br>, AVALANCHE CURRENT (A) ID<br>IAS<br>**----- End of picture text -----**<br>


NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. 

**FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY** 

**FIGURE 7. SATURATION CHARACTERISTICS** 

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200<br>PULSE DURATION = 80 µ s<br>DUTY CYCLE = 0.5% MAX<br>160 V DD  = 15V -55 [o] C 25 [o] C<br>175 [o] C<br>120<br>[7<br>80<br>of<br>40 I<br>0 7Ae<br>0 2 4 6 8 10<br>VGS, GATE TO SOURCE VOLTAGE (V)<br>FIGURE 8. TRANSFER CHARACTERISTICS<br>2.0<br> VGS = VDS, ID = 250 µ A<br>1.5<br>1.0<br>0.5<br>0<br>-80 -40 0 40 80 120 160 200<br>TJ, JUNCTION TEMPERATURE ( [o] C)<br>, DRAIN TO SOURCE CURRENT (A)<br>IDS(ON)<br>NORMALIZED GATE<br>THRESHOLD VOLTAGE<br>**----- End of picture text -----**<br>


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2.5<br>PULSE DURATION = 250 µ s<br>DUTY CYCLE = 0.5% MAX<br>VGS = 10V, ID = 70A<br>2<br>1.5<br>1<br>0.5<br>0<br>-80 -40 0 40 80 120 160 200<br>TJ, JUNCTION TEMPERATURE ( [o] C)<br>FIGURE 9. NORMALIZED DRAIN TO SOURCE ON<br>RESISTANCE vs JUNCTION TEMPERATURE<br>2.0<br>ID = 250 µ A<br>1.5<br>1.0<br>0.5<br>0<br>-80 -40 0 40 80 120 160 200<br>TJ, JUNCTION TEMPERATURE ( [o] C)<br>ON RESISTANCE<br>NORMALIZED DRAIN TO SOURCE<br>BREAKDOWN VOLTAGE<br>NORMALIZED DRAIN TO SOURCE<br>**----- End of picture text -----**<br>


**FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE** 

**FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE** 

©2005 Fairchild Semiconductor Corporation 

RFP70N06 Rev. D1 

_**RFP70N06**_ 

## _**Typical Performance Curves**_ TC = 25[o] C, Unless Otherwise Specified **(Continued)** 

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5000<br>VGS = 0V, f = 1MHz<br>CISS = CGS + CGD<br>4000 CRSS = CGD<br>CISS COSS ≈  CDS + CGS<br>3000<br>2000<br>COSS<br>1000<br>CRSS<br>0<br>0 5 10 15 20 25<br>VDS, DRAIN TO SOURCE VOLTAGE (V)<br>C, CAPACITANCE (pF)<br>**----- End of picture text -----**<br>


**FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE** 

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60 10<br>VDD = BVDSS VDD = BVDSS<br>45 7.5<br>RL = 0.86 Ω<br>IG(REF) = 2.2mA<br>30 5<br>VGS = 10V<br>0.75 BVDSS<br>0.50 BVDSS<br>150 OL 0.25 BVDSS aN 2.50<br>20 IG(REF) t, TIME ( µ s) 80 IG(REF)<br>IG(ACT) IG(ACT)<br>NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.<br>FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR<br>CONSTANT GATE CURRENT<br>, DRAIN TO SOURCE VOLTAGE (V) , GATE TO SOURCE VOLTAGE (V)<br>DS GS<br>V V<br>**----- End of picture text -----**<br>


## _**Test Circuits and Waveforms**_ 

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VDS<br>BVDSS<br>L tP<br>VDS<br>REQUIRED PEAK IVARY tP TO OBTAINAS RG +VDD IAS VDD<br>VGS -<br>DUT<br>tP<br>0V IAS 0<br>0.01 Ω<br>tAV<br>**----- End of picture text -----**<br>


**FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT** 

**FIGURE 15. UNCLAMPED ENERGY WAVEFORMS** 

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VDS<br>VGS RL<br>+<br>VDD<br>-<br>DUT<br>RGS<br>VGS<br>**----- End of picture text -----**<br>


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tON tOFF<br>td(ON) td(OFF)<br>tr tf<br>VDS<br>90% 90%<br>10% 10%<br>0<br>90%<br>VGS 50% 50%<br>PULSE WIDTH<br>10%<br>0<br>**----- End of picture text -----**<br>


**FIGURE 16. SWITCHING TIME TEST CIRCUIT** 

**FIGURE 17. SWITCHING WAVEFORMS** 

©2005 Fairchild Semiconductor Corporation 

RFP70N06 Rev. D1 

_**RFP70N06**_ 

## _**Test Circuits and Waveforms**_ **(Continued)** 

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VDS<br>RL<br>VGS +<br>— VDD<br>-<br>DUT<br>Ig(REF)<br>**----- End of picture text -----**<br>


**FIGURE 18. GATE CHARGE TEST CIRCUIT** 

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VDD Qg(TOT)<br>=———_—<br>N \ N eo VDS VGS = 20V<br>| -—_— Qg(10) N N<br>_ +,—_+|<br>N<br>VGS VGS = 10V<br>a<br>,<br>VGS = 2V N N<br>0 mmm<br>_ _ Qg(TH)<br>Ig(REF)<br>0<br>**----- End of picture text -----**<br>


**FIGURE 19. GATE CHARGE WAVEFORM** 

©2005 Fairchild Semiconductor Corporation 

RFP70N06 Rev. D1 

_**RFP70N06**_ 

## _**PSPICE Electrical Model**_ 

.SUBCKT  RFG70N06  2 1 3 ; 

rev 3/20/92 

CA  12  8  5.56e-9 CB  15  14  5.30e-9 CIN  6  8 2.63e-9 

**RLDRAIN** CB  15  14  5.30e-9 **DPLCAP 5** CIN  6  8 2.63e-9 **10 2 LDRAIN[DRAIN]** DBODY  7  5  DBDMOD DBREAK  5 11  DBKMOD **RSCL2 RSCL1 DBREAK** DPLCAP 10  5  DPLCAPMOD **+ 51 5 51 ESCL** EBREAK  11  7  17  18  65.18 EDS  14  8  5  8  1 **50 11 DBODY** EGS  13  8  6  8  1ESG  6  10  6  8  1 **ESG + 68 VTO 16 RDRAIN EBREAK 1817+** EVTO  20  6  18  8  1 **+ -** IT  8  17  1 **GATE1 RLGATE9 20 + EVTO18 - 6 MOS121 MOS2 8 RGATE** LDRAIN  2  5  1e-9 **LGATE RIN CIN RLSOURCE** LGATE 1  9  3.10e-9 **RSOURCE** LSOURCE  3  7  1.82e-9 ~~' Lm~~ **8 7 3 SOURCE** MOS1  16  6  8  8  MOSMOD  M = 0.99 **LSOURCE S1A S2A** MOS2  16  21  8  8  MOSMOD  M = 0.01 **12** ~~LE~~ **15 RBREAK** ~~re~~ **13 14 17 18** RBREAK  17  18  RBKMOD  1 **8 13** RDRAIN  50  16  RDSMOD  4.66e-3 **S1B S2B RVTO** RLDRAIN  2  5  10 **13 CA CB 19** RGATE  9  20  1.21RLGATE 1  9  31RLGATE 1  9  31 **+ + 14 IT VBAT** RIN  6  8  1e9 **EGS 68 EDS 58 + - -** 

RBREAK  17  18  RBKMOD  1 RDRAIN  50  16  RDSMOD  4.66e-3 RLDRAIN  2  5  10 RGATE  9  20  1.21RLGATE 1  9  31RLGATE 1  9  31 RIN  6  8  1e9 RSOURCE  8  7  RDSMOD  3.92e-3 RLSOURCE  3  7  18.2 RVTO  18  19  RVTOMOD  1 

S1A  6  12  13  8  S1AMOD S1B  13  12  13  8  S1BMOD S2A  6  15  14  13  S2AMOD S2B  13  15  14  13  S2BMOD 

VBAT  8  19  DC  1 VTO  21  6   0.605 

.MODEL DBDMOD D (IS = 7.91e-12 RS = 3.87e-3 TRS1 = 2.71e-3 TRS2 = 2.50e-7 CJO = 4.84e-9 TT = 4.51e-8) .MODEL DBKMOD D (RS = 3.9e-2 TRS1 =1.05e-4 TRS2 = 3.11e-5) .MODEL DPLCAPMOD D (CJO = 4.8e-9 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 3.46 KP = 47 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 8.46e-4 TC2 = -8.48e-7) .MODEL RDSMOD RES (TC1 = 2.23e-3 TC2 = 6.56e-6) .MODEL RVTOMOD RES (TC1 = -3.29e-3 TC2 = 3.49e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -8.35 VOFF= -6.35) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.35 VOFF= -8.35) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF= 3.0) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.0 VOFF= -2.0) 

.ENDS 

NOTE: For further discussion of  the PSPICE model, consult **A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options** ; written by William J. Hepp and C. Frank Wheatley. 

©2005 Fairchild Semiconductor Corporation 

RFP70N06 Rev. D1 

_**RFP70N06**_ 

## **TRADEMARKS** 

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|||||||||
|---|---|---|---|---|---|---|---|
|The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not|
|intended to be an exhaustive list of all such trademarks.|
|AccuPower™|F-PFS™|Sync-Lock™|
|AX-CAP|[®]|*|FRFET|[®]|tm|[®]|®*|
|BitSiC™|Global Power Resource|[SM]|PowerTrench|[®]|
|E|GENERALSYSTEM|
|Build it Now™|GreenBridge™|PowerXS™|
|CorePLUS™|Green FPS™|Programmable Active Droop™|TinyBoost|[®]|
|CorePOWER™|Green FPS™ e-Series™|QFET|[®]|TinyBuck|[®]|
|CROSSVOLT|™|G|max|™|QS™|TinyCalc™|
|CTL™|GTO™|Quiet Series™|TinyLogic|[®]|
|TINYOPTO™|
|Current Transfer Logic™|IntelliMAX™|RapidConfigure™|
|DEUXPEED|[®]|ISOPLANAR™|™|TinyPower™|
|Dual Cool™|Marking Small Speakers Sound Louder|TinyPWM™|
|EcoSPARK|[®]|and Better™|Saving our world, 1mW/W/kW at a time™|TinyWire™TranSiC™|
|EfficentMax™|MegaBuck™|SignalWise™|TriFault Detect™|
|ESBC™|MICROCOUPLER™|SmartMax™|TRUECURRENT|[®]|*|
|®|MicroFET™MicroPak™|SMART START™Solutions for Your Success™|SerDes™|
|Fairchild|[®]|MicroPak2™|SPM|[®]|
|Fairchild Semiconductor|[®]|MillerDrive™|STEALTH™|WZ...|
|FACT Quiet Series™|MotionMax™|SuperFET|[®]|UHC|[®]|
|FACT|[®]|mWSaver|[®]|SuperSOT™-3|Ultra FRFET™|
|FAST|[®]|OptoHiT™|SuperSOT™-6|UniFET™|
|FastvCore™|OPTOLOGIC|[®]|SuperSOT™-8|VCX™|
|FETBench™|OPTOPLANAR|[®]|SupreMOS|[®]|VisualMax™|
|FPS™|SyncFET™|VoltagePlus™|
|XS™|

**----- End of picture text -----**<br>


*Trademarks of System General Corporation, used under license by Fairchild Semiconductor. 

## **DISCLAIMER** 

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. 

## **LIFE SUPPORT POLICY** 

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. 

As used here in: 

1. Life support devices or systems are devices or systems which, (a) are 2. A critical component in any component of a life support, device, or intended for surgical implant into the body or (b) support or sustain life, system whose failure to perform can be reasonably expected to cause and (c) whose failure to perform when properly used in accordance with the failure of the life support device or system, or to affect its safety or instructions for use provided in the labeling, can be reasonably effectiveness. expected to result in a significant injury of the user. 

## **ANTI-COUNTERFEITING POLICY** 

Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website, www.Fairchildsemi.com, under Sales Support. 

Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are experiencing counterfeiting of their parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed application, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild’s full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. 

## **PRODUCT STATUS DEFINITIONS** 

## **Definition of Terms** 

**==> picture [459 x 97] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||
|---|---|---|
|Datasheet Identification|Product Status|Definition|
|Advance Information|Formative / In Design|Datasheet contains the design specifications for product development. Specifications|
|may change in any manner without notice.|
|Datasheet contains preliminary data; supplementary data will be published at a later|
|Preliminary|First Production|date. Fairchild Semiconductor reserves the right to make changes at any time without|
|notice to improve design.|
|No Identification Needed|Full Production|Datasheet contains final specifications. Fairchild Semiconductor reserves the right to|
|make changes at any time without notice to improve the design.|
|Obsolete|Not In Production|Datasheet contains specifications on a product that is discontinued by Fairchild|
|Semiconductor. The datasheet is for reference information only.|

**----- End of picture text -----**<br>


Rev. I66 

©2005 Fairchild Semiconductor Corporation 

RFP70N06 Rev. D1 

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