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RFM95W-915S2
Automated Meter Reading Module, GFSK, GMSK, MSK, OOK, 300Kbps, 915MHz, -148dBm, 1.8V to 3.7V, SPI
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: HOPERF
- Product type: RF Transceivers - Sub 2.4GHz ISM Band
- Data Rate Max: 300Kbps
- Frequency Max: 915MHz
- Product Range: LoRa RFM95 Series
- RF Modulation: FSK, GFSK, GMSK, MSK, OOK
- Supply Current: 120mA
- Transmit Power: 13dBm
- Sensitivity dBm: -148dBm
- Module Interface: SPI
- Supply Voltage Max: 3.7V
- Supply Voltage Min: 1.8V
- RF Transceiver Applications: Automated Meter Reading, Industrial Monitoring & Control, Home & Building Automation
| Delivery and price | |
|---|---|
| Units per pack | 250 |
| Price | 12.55 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
**RFM95/96/97/98** （ **W** ）
~~ee~~
## **RFM95/96/97/98(W) - Low Power Long Range Transceiver Module V1.0**
## **GENERAL DESCRIPTION**
The RFM95/96/97/98(W) transceivers feature the LoRa[TM ] long range modem that provides ultra-long range spread spectrum communication and high interference immunity whilst minimising current consumption.
Using Hope RF’s patented LoRa[TM ] modulation technique RFM95/96/97/98(W) can achieve a sensitivity of over - 148dBm using a low cost crystal and bill of materials. The high sensitivity combined with the integrated +20 dBm power amplifier yields industry leading link budget making it optimal for any application requiring range or robustness. LoRa[TM ] also provides significant advantages in both blocking and selectivity over conventional modulation techniques, solving the traditional design compromise between range, interference immunity and energy consumption.
These devices also support high performance (G)FSK modes for systems including WMBus, IEEE802.15.4g. The RFM95/96/97/98(W) deliver exceptional phase noise, selectivity, receiver linearity and IIP3 for significantly lower current consumption than competing devices.
## **KEY PRODUCT FEATURES**
## **RFM95/96/97/98(W)**
## **APPLICATIONS**
Automated Meter Reading.
:¢ LoRa[TM ] Modem. Home and Building Automation. : 168 dB maximum link budget.[¢] Wireless Alarm and Security Systems.
:¢ Industrial Monitoring and Control
Industrial Monitoring and Control
- +20 dBm - 100 mW constant RF output vs. V supply.
: +14 dBm high efficiency PA.[¢]
Long range Irrigation Systems
Programmable bit rate up to 300 kbps.
High sensitivity: down to -148 dBm.
Bullet-proof front end: IIP3 = -12.5 dBm.
Excellent blocking immunity.
Low RX current of 10.3 mA, 200 nA register retention.
Fully integrated synthesizer with a resolution of 61 Hz.
FSK, GFSK, MSK, GMSK, LoRa[TM ] and OOK modulation.
Built-in bit synchronizer for clock recovery.
Preamble detection.
127 dB Dynamic Range RSSI.
Automatic RF Sense and CAD with ultra-fast AFC.
Packet engine up to 256 bytes with CRC.
Built-in temperature sensor and low battery indicator.
Modue Size ： 16*16mm
Page 1
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**RFM95/96/97/98** （ **W** ）
## **Section Page**
|1.|GeneralDescription .................................................................................................................................................9|
|---|---|
||1.1.<br>Simplified BlockDiagram .................................................................................................................................9|
||1.2.<br>Product Versions .........................................................................................................................................10|
||1.3.<br>PinDiagram ...................................................................................................................................................10|
||1.4.<br>PinDescription ...............................................................................................................................................11|
|2.|Electrical Characteristics.......................................................................................................................................12|
||2.1.<br>ESD Notice....................................................................................................................................................12|
||2.2.<br>Absolute Maximum Ratings...........................................................................................................................12|
||2.3.<br>OperatingRange............................................................................................................................................12|
||2.4.<br>Chip Specification .......................................................................................................................................13|
||2.4.1. PowerConsumption ..................................................................................................................................13|
||2.4.2. FrequencySynthesis .................................................................................................................................13|
||2.4.3. FSK/OOK ModeReceiver .........................................................................................................................14|
||2.4.4. FSK/OOK ModeTransmitter .....................................................................................................................15|
||2.4.5. Electrical specification for LoraTMmodulation ..........................................................................................16|
||2.4.6. DigitalSpecification ...................................................................................................................................19|
|3.|RFM95/96/97/98(W)Features ................................................................................................................................20|
||3.1.<br>LoRaTMModem .............................................................................................................................................21|
||3.2.<br>FSK/OOKModem ...........................................................................................................................................21|
|4.|RFM95/96/97/98(W) Digital Electronics.................................................................................................................22|
||4.1.<br>The LoRaTMModem .....................................................................................................................................22|
||4.1.1. Link Design Using the LoRaTM Modem .................................................................................................23|
||4.1.2. LoRaTM Digital Interface ........................................................................................................................29|
||4.1.3. Operation of the LoRaTMModem .............................................................................................................31|
||4.1.4. Frequency Settings ................................................................................................................................32|
||4.1.5. LoRaTM Modem State Machine Sequences ...........................................................................................33|
||4.2.<br>FSK/OOKModem ..........................................................................................................................................41|
||4.2.1. Bit Rate Setting.........................................................................................................................................41|
||4.2.2. FSK/OOKTransmission ............................................................................................................................42|
||4.2.3. FSK/OOKReception .................................................................................................................................43|
||4.2.4. Operating Modes in FSK/OOKMode ........................................................................................................50|
||4.2.5. StartupTimes ............................................................................................................................................50|
||4.2.6. Receiver StartupOptions ..........................................................................................................................53|
||4.2.7. Receiver RestartMethods .........................................................................................................................54|
||4.2.8. Top LevelSequencer ................................................................................................................................55|
||4.2.9. Data Processing in FSK/OOKMode .........................................................................................................60|
||4.2.10. FIFO .....................................................................................................................................................61|
||4.2.11. Digital IO PinsMapping ...........................................................................................................................64|
||4.2.12. ContinuousMode ....................................................................................................................................65|
Page 2
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**RFM95/96/97/98** （ **W** ）
## **Section Page**
||4.2.13. Packet Mode...........................................................................................................................................66|
|---|---|
||4.2.14. io-homecontrol® Compatibility Mode......................................................................................................74|
||4.3.<br>SPIInterface ..................................................................................................................................................75|
|5.|RFM95/96/97/98(W) Analog & RF FrontendElectronics........................................................................................76|
||5.1.<br>Power Supply Strategy..................................................................................................................................76|
||5.2.<br>Low Battery Detector.....................................................................................................................................76|
||5.3.<br>Frequency Synthesis.....................................................................................................................................76|
||5.3.1. CrystalOscillator .......................................................................................................................................76|
||5.3.2. CLKOUTOutput ........................................................................................................................................77|
||5.3.3.PLL ............................................................................................................................................................77|
||5.3.4. RCOscillator .............................................................................................................................................77|
||5.4.<br>Transmitter Description ...............................................................................................................................78|
||5.4.1. ArchitectureDescription ............................................................................................................................78|
||5.4.2. RF PowerAmplifiers..................................................................................................................................78|
||5.4.3. High Power +20 dBm Operation...............................................................................................................79|
||5.4.4. Over Current Protection .........................................................................................................................80|
||5.5.<br>ReceiverDescription ......................................................................................................................................80|
||5.5.1. Overview...................................................................................................................................................80|
||5.5.2. Receiver Enabled and Receiver ActiveStates ..........................................................................................80|
||5.5.3. Automatic Gain Control In FSK/OOK Mode..............................................................................................80|
||5.5.4. RSSI in FSK/OOKMode ...........................................................................................................................81|
||5.5.5. RSSI in LoRaTM Mode.............................................................................................................................82|
||5.5.6. ChannelFilter ............................................................................................................................................82|
||5.5.7. TemperatureMeasurement .......................................................................................................................83|
|6.|Description of theRegisters....................................................................................................................................84|
||6.1.<br>Register TableSummary ...............................................................................................................................84|
||6.2.<br>FSK/OOK Mode RegisterMap.......................................................................................................................87|
||6.3.<br>Band Specific AdditionalRegisters ..............................................................................................................100|
||6.4.<br>LoRaTM Mode RegisterMap .......................................................................................................................102|
|7.|ApplicationInformation ........................................................................................................................................108|
||7.1.<br>Crystal ResonatorSpecification ...................................................................................................................108|
||7.2.<br>Reset of the Chip.........................................................................................................................................108|
||7.2.1.POR.........................................................................................................................................................108|
||7.2.2. Manual Reset .......................................................................................................................................109|
||7.3.<br>Top Sequencer: Listen ModeExamples ......................................................................................................109|
||7.3.1. Wake on Preamble Interrupt...................................................................................................................109|
||7.3.2. Wake on SyncAddress Interrupt ...........................................................................................................112|
||7.4.<br>Top Sequencer: Beacon Mode .................................................................................................................115|
||7.4.1. Timingdiagram........................................................................................................................................115|
Page 3
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**RFM95/96/97/98(W)**
## **Section Page**
||7.4.2. SequencerConfiguration.........................................................................................................................115|7.4.2. SequencerConfiguration.........................................................................................................................115|
|---|---|---|
||7.5.|Example CRC Calculation ........................................................................................................................117|
||7.6.|Example Temperature Reading ................................................................................................................118|
|8.|PackagingInformation .........................................................................................................................................119||
||8.1.|Package Outline Drawing............................................................................................................................119|
||8.2.|Recommended LandPattern .......................................................................................................................120|
Page 4
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**RFM95/96/97/98(W)**
## **Section Page**
|Table 1. RFM95/96/97/98(W) Device Variants and Key Parameters .............................................................................10|Table 1. RFM95/96/97/98(W) Device Variants and Key Parameters .............................................................................10|
|---|---|
|Table 2. Absolute Maximum Ratings .............................................................................................................................12|Table 2. Absolute Maximum Ratings .............................................................................................................................12|
|Table 3. Operating Range .............................................................................................................................................12|Table 3. Operating Range .............................................................................................................................................12|
|Table 4. Power Consumption Specification ...................................................................................................................13|Table 4. Power Consumption Specification ...................................................................................................................13|
|Table 5. Frequency Synthesizer Specification ..............................................................................................................13|Table 5. Frequency Synthesizer Specification ..............................................................................................................13|
|Table 6. FSK/OOK Receiver Specification ....................................................................................................................14|Table 6. FSK/OOK Receiver Specification ....................................................................................................................14|
|Table 7. Transmitter Specification .................................................................................................................................15|Table 7. Transmitter Specification .................................................................................................................................15|
|Table 8. LoRa Receiver Specification. ..........................................................................................................................17|Table 8. LoRa Receiver Specification. ..........................................................................................................................17|
|Table 9. Digital Specification .........................................................................................................................................19|Table 9. Digital Specification .........................................................................................................................................19|
|Table 10. Example LoRaTM Modem Performances .....................................................................................................22|Table 10. Example LoRaTM Modem Performances .....................................................................................................22|
|Table 11. Range of Spreading Factors ..........................................................................................................................24|Table 11. Range of Spreading Factors ..........................................................................................................................24|
|Table 12. Cyclic Coding Overhead ................................................................................................................................24|Table 12. Cyclic Coding Overhead ................................................................................................................................24|
|Table 13. LoRaTM Operating Mode Functionality .........................................................................................................31|Table 13. LoRaTM Operating Mode Functionality .........................................................................................................31|
|Table 14. LoRa CAD Consumption Figures ..................................................................................................................40|Table 14. LoRa CAD Consumption Figures ..................................................................................................................40|
|Table 15. DIO Mapping LoRaTM Mode .........................................................................................................................41|Table 15. DIO Mapping LoRaTM Mode .........................................................................................................................41|
|Table 16. Bit Rate Examples .........................................................................................................................................42|Table 16. Bit Rate Examples .........................................................................................................................................42|
|Table 17. Preamble Detector Settings ...........................................................................................................................48|Table 17. Preamble Detector Settings ...........................................................................................................................48|
|Table 18. RxTrigger Settings to Enable Timeout Interrupts ..........................................................................................49|Table 18. RxTrigger Settings to Enable Timeout Interrupts ..........................................................................................49|
|Table 19. Basic Transceiver Modes ..............................................................................................................................50|Table 19. Basic Transceiver Modes ..............................................................................................................................50|
|Table 20. Receiver Startup Time Summary ..................................................................................................................51|Table 20. Receiver Startup Time Summary ..................................................................................................................51|
|Table 21. Receiver Startup Options ..............................................................................................................................54|Table 21. Receiver Startup Options ..............................................................................................................................54|
|Table 22. Sequencer States ..........................................................................................................................................55|Table 22. Sequencer States ..........................................................................................................................................55|
|Table 23. Sequencer Transition Options .......................................................................................................................56|Table 23. Sequencer Transition Options .......................................................................................................................56|
|Table 24. Sequencer Timer Settings .............................................................................................................................58|Table 24. Sequencer Timer Settings .............................................................................................................................58|
|Table 25. Status of FIFO when Switching Between Different Modes of the Chip .........................................................62|Table 25. Status of FIFO when Switching Between Different Modes of the Chip .........................................................62|
|Table 26. DIO Mapping, Continuous Mode ...................................................................................................................64|Table 26. DIO Mapping, Continuous Mode ...................................................................................................................64|
|Table 27. DIO Mapping, Packet Mode ..........................................................................................................................64|Table 27. DIO Mapping, Packet Mode ..........................................................................................................................64|
|Table 28. CRC Description ...........................................................................................................................................72|Table 28. CRC Description ...........................................................................................................................................72|
|Table 29. Power Amplifier Mode Selection Truth Table ................................................................................................78|Table 29. Power Amplifier Mode Selection Truth Table ................................................................................................78|
|Table 30. High Power Settings ......................................................................................................................................79|Table 30. High Power Settings ......................................................................................................................................79|
|Table 31. Operating Range, +20dBm Operation ...........................................................................................................79|Table 31. Operating Range, +20dBm Operation ...........................................................................................................79|
|Table 32. Operating Range, +20dBm Operation ...........................................................................................................79|Table 32. Operating Range, +20dBm Operation ...........................................................................................................79|
|Table 33. Trimming of the OCP Current ........................................................................................................................80|Table 33. Trimming of the OCP Current ........................................................................................................................80|
|Table 34. LNA Gain Control and Performances ............................................................................................................81|Table 34. LNA Gain Control and Performances ............................................................................................................81|
|Table 35. RssiSmoothing Options .................................................................................................................................82|Table 35. RssiSmoothing Options .................................................................................................................................82|
|Table 36. Available RxBw Settings ................................................................................................................................82|Table 36. Available RxBw Settings ................................................................................................................................82|
|Table 37. Registers Summary .......................................................................................................................................84|Table 37. Registers Summary .......................................................................................................................................84|
|Table 38. Register Map .................................................................................................................................................87|Table 38. Register Map .................................................................................................................................................87|
|Table 39. Low Frequency Additional Registers ...........................................................................................................100|Table 39. Low Frequency Additional Registers ...........................................................................................................100|
Page 5
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**RFM95/96/97/98(W)**
**Section Page**
|Table 40. High Frequency Additional Registers ..........................................................................................................101|Table 40. High Frequency Additional Registers ..........................................................................................................101|Table 40. High Frequency Additional Registers ..........................................................................................................101|
|---|---|---|
|Table 41. Crystal Specification ....................................................................................................................................108|Table 41. Crystal Specification ....................................................................................................................................108|Table 41. Crystal Specification ....................................................................................................................................108|
|Table 42. Listen Mode with PreambleDetect Condition Settings .................................................................................111|Table 42. Listen Mode with PreambleDetect Condition Settings .................................................................................111|Table 42. Listen Mode with PreambleDetect Condition Settings .................................................................................111|
|Table 43. Listen Mode with PreambleDetect Condition Recommended DIO Mapping ...............................................111|Table 43. Listen Mode with PreambleDetect Condition Recommended DIO Mapping ...............................................111|Table 43. Listen Mode with PreambleDetect Condition Recommended DIO Mapping ...............................................111|
|Table 44. Listen Mode with SyncAddress Condition Settings .....................................................................................114|Table 44. Listen Mode with SyncAddress Condition Settings .....................................................................................114|Table 44. Listen Mode with SyncAddress Condition Settings .....................................................................................114|
|Table 45. Listen Mode with PreambleDetect Condition Recommended DIO Mapping ...............................................114|Table 45. Listen Mode with PreambleDetect Condition Recommended DIO Mapping ...............................................114|Table 45. Listen Mode with PreambleDetect Condition Recommended DIO Mapping ...............................................114|
|Table 46. Beacon Mode Settings ................................................................................................................................116|Table 46. Beacon Mode Settings ................................................................................................................................116|Table 46. Beacon Mode Settings ................................................................................................................................116|
|Table 47. Revision History ...........................................................................................................................................121|Table 47. Revision History ...........................................................................................................................................121|Table 47. Revision History ...........................................................................................................................................121|
Page 6
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**RFM95/96/97/98(W)**
## **Section Page**
|Figure 1. Block Diagram ...............................................................................................................................................9|Figure 1. Block Diagram ...............................................................................................................................................9|Figure 1. Block Diagram ...............................................................................................................................................9|
|---|---|---|
|Figure 2. Pin Diagrams ...............................................................................................................................................10|Figure 2. Pin Diagrams ...............................................................................................................................................10|Figure 2. Pin Diagrams ...............................................................................................................................................10|
|Figure 3. RFM95/96/97/98(W) Block Schematic Diagram ..........................................................................................20|Figure 3. RFM95/96/97/98(W) Block Schematic Diagram ..........................................................................................20|Figure 3. RFM95/96/97/98(W) Block Schematic Diagram ..........................................................................................20|
|Figure 4. LoRaTM Modem Connectivity ......................................................................................................................23|Figure 4. LoRaTM Modem Connectivity ......................................................................................................................23|Figure 4. LoRaTM Modem Connectivity ......................................................................................................................23|
|Figure 5. Interrupts generated in the case of successful frequency hopping communication. .....................................28|Figure 5. Interrupts generated in the case of successful frequency hopping communication. .....................................28|Figure 5. Interrupts generated in the case of successful frequency hopping communication. .....................................28|
|Figure 6. Channel activity detection (CAD) time as a function of spreading factor ......................................................39|Figure 6. Channel activity detection (CAD) time as a function of spreading factor ......................................................39|Figure 6. Channel activity detection (CAD) time as a function of spreading factor ......................................................39|
|Figure 7. Consumption Profile of the LoRa CAD Process ............................................................................................40|Figure 7. Consumption Profile of the LoRa CAD Process ............................................................................................40|Figure 7. Consumption Profile of the LoRa CAD Process ............................................................................................40|
|Figure 8. OOK Peak Demodulator Description .............................................................................................................44|Figure 8. OOK Peak Demodulator Description .............................................................................................................44|Figure 8. OOK Peak Demodulator Description .............................................................................................................44|
|Figure 9. Floor Threshold Optimization ........................................................................................................................45|Figure 9. Floor Threshold Optimization ........................................................................................................................45|Figure 9. Floor Threshold Optimization ........................................................................................................................45|
|Figure 10. Bit Synchronizer Description .......................................................................................................................46|Figure 10. Bit Synchronizer Description .......................................................................................................................46|Figure 10. Bit Synchronizer Description .......................................................................................................................46|
|Figure 11. FEI Process .................................................................................................................................................47|Figure 11. FEI Process .................................................................................................................................................47|Figure 11. FEI Process .................................................................................................................................................47|
|Figure 12. Startup Process ...........................................................................................................................................50|Figure 12. Startup Process ...........................................................................................................................................50|Figure 12. Startup Process ...........................................................................................................................................50|
|Figure 13. Time to Rssi Sample ...................................................................................................................................52|Figure 13. Time to Rssi Sample ...................................................................................................................................52|Figure 13. Time to Rssi Sample ...................................................................................................................................52|
|Figure 14. Tx to Rx Turnaround ...................................................................................................................................52|Figure 14. Tx to Rx Turnaround ...................................................................................................................................52|Figure 14. Tx to Rx Turnaround ...................................................................................................................................52|
|Figure 15. Rx to Tx Turnaround ...................................................................................................................................52|Figure 15. Rx to Tx Turnaround ...................................................................................................................................52|Figure 15. Rx to Tx Turnaround ...................................................................................................................................52|
|Figure 16. Receiver Hopping ........................................................................................................................................53|Figure 16. Receiver Hopping ........................................................................................................................................53|Figure 16. Receiver Hopping ........................................................................................................................................53|
|Figure 17. Transmitter Hopping ....................................................................................................................................53|Figure 17. Transmitter Hopping ....................................................................................................................................53|Figure 17. Transmitter Hopping ....................................................................................................................................53|
|Figure 18. Timer1 and Timer2 Mechanism ...................................................................................................................57|Figure 18. Timer1 and Timer2 Mechanism ...................................................................................................................57|Figure 18. Timer1 and Timer2 Mechanism ...................................................................................................................57|
|Figure 19. Sequencer State Machine ...........................................................................................................................59|Figure 19. Sequencer State Machine ...........................................................................................................................59|Figure 19. Sequencer State Machine ...........................................................................................................................59|
|Figure 20. RFM95/96/97/98(W) Data Processing Conceptual View .............................................................................60|Figure 20. RFM95/96/97/98(W) Data Processing Conceptual View .............................................................................60|Figure 20. RFM95/96/97/98(W) Data Processing Conceptual View .............................................................................60|
|Figure 21. FIFO and Shift Register (SR) ......................................................................................................................61|Figure 21. FIFO and Shift Register (SR) ......................................................................................................................61|Figure 21. FIFO and Shift Register (SR) ......................................................................................................................61|
|Figure 22. FifoLevel IRQ Source Behavior ...................................................................................................................62|Figure 22. FifoLevel IRQ Source Behavior ...................................................................................................................62|Figure 22. FifoLevel IRQ Source Behavior ...................................................................................................................62|
|Figure 23. Sync Word Recognition ...............................................................................................................................63|Figure 23. Sync Word Recognition ...............................................................................................................................63|Figure 23. Sync Word Recognition ...............................................................................................................................63|
|Figure 24. Continuous Mode Conceptual View ............................................................................................................65|Figure 24. Continuous Mode Conceptual View ............................................................................................................65|Figure 24. Continuous Mode Conceptual View ............................................................................................................65|
|Figure 25. Tx Processing in Continuous Mode .............................................................................................................65|Figure 25. Tx Processing in Continuous Mode .............................................................................................................65|Figure 25. Tx Processing in Continuous Mode .............................................................................................................65|
|Figure 26. Rx Processing in Continuous Mode ............................................................................................................66|Figure 26. Rx Processing in Continuous Mode ............................................................................................................66|Figure 26. Rx Processing in Continuous Mode ............................................................................................................66|
|Figure 27. Packet Mode Conceptual View ...................................................................................................................67|Figure 27. Packet Mode Conceptual View ...................................................................................................................67|Figure 27. Packet Mode Conceptual View ...................................................................................................................67|
|Figure 28. Fixed Length Packet Format .......................................................................................................................68|Figure 28. Fixed Length Packet Format .......................................................................................................................68|Figure 28. Fixed Length Packet Format .......................................................................................................................68|
|Figure 29. Variable Length Packet Format ...................................................................................................................69|Figure 29. Variable Length Packet Format ...................................................................................................................69|Figure 29. Variable Length Packet Format ...................................................................................................................69|
|Figure 30. Unlimited Length Packet Format .................................................................................................................69|Figure 30. Unlimited Length Packet Format .................................................................................................................69|Figure 30. Unlimited Length Packet Format .................................................................................................................69|
|Figure 31. Manchester Encoding/Decoding .................................................................................................................73|Figure 31. Manchester Encoding/Decoding .................................................................................................................73|Figure 31. Manchester Encoding/Decoding .................................................................................................................73|
|Figure 32. Data Whitening Polynomial .........................................................................................................................74|Figure 32. Data Whitening Polynomial .........................................................................................................................74|Figure 32. Data Whitening Polynomial .........................................................................................................................74|
|Figure 33. SPI Timing Diagram (single access) ...........................................................................................................75|Figure 33. SPI Timing Diagram (single access) ...........................................................................................................75|Figure 33. SPI Timing Diagram (single access) ...........................................................................................................75|
|Figure 34. TCXO Connection .......................................................................................................................................76|Figure 34. TCXO Connection .......................................................................................................................................76|Figure 34. TCXO Connection .......................................................................................................................................76|
|Figure 35. RF Front-end Architecture Shows the Internal PA Configuration. ...............................................................78|Figure 35. RF Front-end Architecture Shows the Internal PA Configuration. ...............................................................78|Figure 35. RF Front-end Architecture Shows the Internal PA Configuration. ...............................................................78|
|Figure 36. Temperature Sensor Response ..................................................................................................................83|Figure 36. Temperature Sensor Response ..................................................................................................................83|Figure 36. Temperature Sensor Response ..................................................................................................................83|
|Figure 37. POR Timing Diagram ................................................................................................................................108|Figure 37. POR Timing Diagram ................................................................................................................................108|Figure 37. POR Timing Diagram ................................................................................................................................108|
|Figure 38. Manual Reset Timing Diagram ..................................................................................................................109|Figure 38. Manual Reset Timing Diagram ..................................................................................................................109|Figure 38. Manual Reset Timing Diagram ..................................................................................................................109|
|Figure 39. Listen Mode: Principle ...............................................................................................................................109|Figure 39. Listen Mode: Principle ...............................................................................................................................109|Figure 39. Listen Mode: Principle ...............................................................................................................................109|
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**RFM95/96/97/98(W)**
## **Section Page**
|Figure 40. Listen Mode with No Preamble Received .................................................................................................110|Figure 40. Listen Mode with No Preamble Received .................................................................................................110|Figure 40. Listen Mode with No Preamble Received .................................................................................................110|
|---|---|---|
|Figure 41. Listen Mode with Preamble Received .......................................................................................................110|Figure 41. Listen Mode with Preamble Received .......................................................................................................110|Figure 41. Listen Mode with Preamble Received .......................................................................................................110|
|Figure 42. Wake On PreambleDetect State Machine .................................................................................................111|Figure 42. Wake On PreambleDetect State Machine .................................................................................................111|Figure 42. Wake On PreambleDetect State Machine .................................................................................................111|
|Figure 43. Listen Mode with no SyncAddress Detected .............................................................................................112|Figure 43. Listen Mode with no SyncAddress Detected .............................................................................................112|Figure 43. Listen Mode with no SyncAddress Detected .............................................................................................112|
|Figure 44. Listen Mode with Preamble Received and no SyncAddress .....................................................................112|Figure 44. Listen Mode with Preamble Received and no SyncAddress .....................................................................112|Figure 44. Listen Mode with Preamble Received and no SyncAddress .....................................................................112|
|Figure 45. Listen Mode with Preamble Received & Valid SyncAddress ....................................................................113|Figure 45. Listen Mode with Preamble Received & Valid SyncAddress ....................................................................113|Figure 45. Listen Mode with Preamble Received & Valid SyncAddress ....................................................................113|
|Figure 46. Wake On SyncAddress State Machine .....................................................................................................113|Figure 46. Wake On SyncAddress State Machine .....................................................................................................113|Figure 46. Wake On SyncAddress State Machine .....................................................................................................113|
|Figure 47. Beacon Mode Timing Diagram ..................................................................................................................115|Figure 47. Beacon Mode Timing Diagram ..................................................................................................................115|Figure 47. Beacon Mode Timing Diagram ..................................................................................................................115|
|Figure 48. Beacon Mode State Machine ....................................................................................................................115|Figure 48. Beacon Mode State Machine ....................................................................................................................115|Figure 48. Beacon Mode State Machine ....................................................................................................................115|
|Figure 49. Example CRC Code ..................................................................................................................................117|Figure 49. Example CRC Code ..................................................................................................................................117|Figure 49. Example CRC Code ..................................................................................................................................117|
|Figure 50. Example Temperature Reading ................................................................................................................118|Figure 50. Example Temperature Reading ................................................................................................................118|Figure 50. Example Temperature Reading ................................................................................................................118|
|Figure 51. Package Outline Drawing ..........................................................................................................................119|Figure 51. Package Outline Drawing ..........................................................................................................................119|Figure 51. Package Outline Drawing ..........................................................................................................................119|
|Figure 52. Recommended Land Pattern ....................................................................................................................120|Figure 52. Recommended Land Pattern ....................................................................................................................120|Figure 52. Recommended Land Pattern ....................................................................................................................120|
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**RFM95/96/97/98(W)**
## **1. General Description**
The RFM95/96/97/98(W) incorporates the LoRa[TM ] spread spectrum modem which is capable of achieving significantly longer range than existing systems based on FSK or OOK modulation. With this new modulation scheme sensitivities 8 dB better than FSK can be achieved with a low-cost, low-tolerance, crystal reference. This increase in link budget provides
much longer range and robustness without the need for external amplification. LoRa[TM ] also provides significant advances in selectivity and blocking performance, further improving communication reliability. For maximum flexibility the user may decide on the spread spectrum modulation bandwidth (BW), spreading factor (SF) and error correction rate (CR). Another benefit of the spread modulation is that each spreading factor is orthogonal - thus multiple transmitted signals can occupy the same channel without interfering. This also permits simple coexistence with existing FSK based systems. Standard GFSK, FSK, OOK, and GMSK modulation is also provided to allow compatibility with existing systems or standards such as wireless MBUS and IEEE 802.15.4g.
The RFM97 offers bandwidth options ranging from 7.8 kHz to 500 kHz with spreading factors ranging from 6 to 12, and covering all available frequency bands. The RFM97 offers the same bandwidth and frequency band options with spreading factors from 6 to 9. The RFM98 offers bandwidths and spreading factor options, but only covers the lower UHF bands.
## **1.1. Simplified Block Diagram**
_Figure 1. Block Diagram_
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**RFM95/96/97/98(W)**
## **1.2. Product Versions**
The features of the three product variants are detailed in the following table.
_Table 48 RFM95/96/97/98(W) Device Variants and Key Parameters_
|**Part Number**|**Frequency Range**|**Spreading Factor**|**Bandwidth**|**Effective Bitrate**|**Est. Sensitivity**|
|---|---|---|---|---|---|
|RFM95W|868/915 MHz|6 - 12|7.8 - 500 kHz|.018 - 37.5 kbps|-111 to -148 dBm|
|RFM97W|868/915 MHz|6 - 9|7.8 - 500 kHz|0.11 - 37.5 kbps|-111 to -139 dBm|
|RFM96W/RFM98W|433/470MHz|6- 12|7.8 - 500 kHz|.018 - 37.5 kbps|-111 to -148 dBm|
## **1.3. Pin Diagram**
The following diagram shows the pin arrangement , top view.
_Figure 2. Pin Diagrams_
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**RFM95/96/97/98(W)**
## **1.4. Pin Description**
|**Number**|**Name**|**Type**|**Description**<br>**Description Stand Alone Mode**|
|---|---|---|---|
|1<br>~~a~~|GND|-|Ground|
|2<br>~~a~~<br>~~a~~|MISO|I|SPI Data output|
|3<br>~~a~~|MOSI|O|SPI Data input|
|4<br>~~a~~|SCK|I|SPI Clock input|
|5<br>~~a~~|NSS|I|SPI Chip select input|
|6<br>~~a~~|RESET|I/O|Reset trigger input|
|7<br>~~a~~|DIO5<br>~~a~~|I/O|Digital I/O, software configured|
|8<br>~~a~~<br>~~a~~|GND<br>~~a~~|-|Ground|
|9<br>~~a~~<br>~~a~~|ANT|-|RF signal output/input.|
|10<br>~~a~~|GND|-|Ground|
|11<br>~~a~~|DIO3|I/O|Digital I/O, software configured|
|12<br>~~a~~|DIO4|I/O|Digital I/O, software configured|
|13<br>~~a~~|3.3V<br>~~a~~|-|Supply voltage|
|14<br>~~a~~|DIO0|I/O|Digital I/O, software configured|
|15<br>~~a~~|DIO1|I/O|Digital I/O, software configured|
|16<br>~~a~~|DIO2|I/O|Digital I/O, software configured|
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**RFM95/96/97/98(W)**
## **2. Electrical Characteristics**
## **2.1. ESD Notice**
The RFM95/96/97/98(W) is a high performance radio frequency device. It satisfies:
Class 2 of the JEDEC standard JESD22-A114-B (Human Body Model) on all pins.
Class III of the JEDEC standard JESD22-C101C (Charged Device Model) on all pins
It should thus be handled with all the necessary ESD precautions to avoid any permanent damage.
## **2.2. Absolute Maximum Ratings**
Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for extended periods may affect device reliability.
## _Table 49 Absolute Maximum Ratings_
|**Symbol**|**Description**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|VDDmr|Supply Voltage|-0.5|3.9|V|
|Tmr|Temperature|-55|+115|° C|
|Tj|Junction temperature|-|+125|° C|
|Pmr|RF Input Level|-|+10|dBm|
_Note Specific ratings apply to +20 dBm operation (see Section 5.4.3)._
## **2.3. Operating Range**
## _Table 50 Operating Range_
|**Symbol**|**Description**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|VDDop|Supply voltage|1.8|3.7|V|
|Top|Operational temperature range|-20|+70|°C|
|Clop|Load capacitance on digital ports|-|25|pF|
|ML|RF Input Level|-|+10|dBm|
_Note A specific supply voltage range applies to +20 dBm operation (see Section 5.4.3)._
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**RFM95/96/97/98(W)**
## **2.4. Chip Specification**
The tables below give the electrical specifications of the transceiver under the following conditions: Supply voltage VDD=3.3 V, temperature = 25 °C, _FXOSC_ = 32 MHz, _F_ RF = 169/434/868/915 MHz (see specific indication), Pout = +13dBm, 2-level FSK modulation without pre-filtering, FDA = 5 kHz, Bit Rate = 4.8 kb/s and terminated in a matched 50 Ohm impedance, shared Rx and Tx path matching., unless otherwise specified.
## **2.4.1. Power Consumption**
_Table 51 Power Consumption Specification_
|**Symbol**<br>~~a~~|**Description**<br>~~ee~~|**Conditions**<br>~~ee~~|**Min**<br>~~ee~~|**Typ**<br>~~ee~~|**Max**<br>~~ee~~|**Unit**<br>~~ee~~|
|---|---|---|---|---|---|---|
|IDDSL<br>~~a~~|Supply current in Sleep mode||-|0.2|1|uA|
|IDDIDLE<br>~~a~~|Supply current in Idle mode|RC oscillator enabled|-|1.5|-|uA|
|IDDST<br>~~a~~<br>~~ee~~|Supply current in Standby mode<br>~~ee~~|Crystal oscillator enabled<br>~~ee~~|-<br>~~ee~~|1.6<br>~~ee~~<br>~~ee~~|1.8<br>~~ee~~<br>~~ee~~|mA<br>~~ee~~<br>~~ee~~|
|IDDFS<br>~~ee~~|Supply current in Synthesizer<br>mode<br>~~ee~~|FSRx<br>~~ee~~|-<br>~~ee~~|5.8<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|mA<br>~~ee~~<br>~~ee~~|
|IDDR<br>~~ee~~|Supply current in Receive mode<br>~~ee~~|_LnaBoost_Off, higher bands<br>_LnaBoost_On, higher bands<br>Lower bands<br>~~ee~~|-<br>-<br>-<br>~~ee~~|10.8<br>11.5<br>12.1<br>~~ee~~<br>~~ee~~|-<br>-<br>-<br>~~ee~~<br>~~ee~~|mA<br>~~ee~~<br>~~ee~~|
|IDDT|Supply current in Transmit mode<br>with impedance matching|RFOP = +20 dBm, on PA_BOOST<br>RFOP = +17 dBm, on PA_BOOST<br>RFOP = +13 dBm, on RFO_LF/HF pin<br>RFOP = + 7 dBm, on RFO_LF/HF pin|-<br>-<br>-<br>-|120<br>87<br>29<br>20|-<br>-<br>-<br>-|mA<br>mA<br>mA<br>mA|
## **2.4.2. Frequency Synthesis**
_Table 52 Frequency Synthesizer Specification_
|**Symbol**<br>~~a~~|**Description**<br>~~ee~~|**Conditions**<br>~~ee~~|**Min**<br>~~ee~~|**Typ**<br>~~ee~~|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|FR<br>~~a~~<br>~~Pr~~<br>~~a~~|Synthesizer frequency range<br>~~ee~~<br>~~Pr~~<br>~~ee~~|Programmable<br>~~ee~~<br>~~Pr~~<br>~~ee~~|137<br>410<br>862<br>~~ee~~<br>~~Pr~~<br>~~ee~~|-<br>-<br>-<br>~~ee~~<br>~~Pr~~<br>~~ee~~|175<br>525<br>1020<br>~~Pr~~|MHz<br>~~Pr~~|
|FXOSC<br>~~a~~|Crystal oscillator frequency<br>~~ee~~|~~ee~~|-<br>~~ee~~<br>~~ee~~|32<br>~~ee~~<br>~~ee~~|-<br>~~ee~~|MHz<br>~~ee~~|
|TS_OSC<br>~~a~~<br>~~a ee~~|Crystal oscillator wake-up time<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~<br>~~ee~~|250<br>~~ee~~<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|us<br>~~ee~~<br>~~ee~~|
|TS_FS|Frequency synthesizer wake-up<br>time to PllLock signal|From Standby mode|-<br>~~ee~~|60<br>~~ee~~|-<br>~~ee~~|us<br>~~ee~~|
|TS_HOP|Frequency synthesizer hop time<br>at most 10 kHz away from the tar-<br>get frequency|200 kHz step<br>1 MHz step<br>5 MHz step<br>7 MHz step<br>12 MHz step<br>20 MHz step<br>25 MHz step|-<br>-<br>-<br>-<br>-<br>-<br>-|20<br>20<br>50<br>50<br>50<br>50<br>50|-<br>-<br>-<br>-<br>-<br>-<br>-|us<br>us<br>us<br>us<br>us<br>us<br>us|
|FSTEP<br>~~a~~|Frequency synthesizer step|FSTEP = FXOSC/219|-|61.0|-|Hz|
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**RFM95/96/97/98(W)**
|FRC|RC Oscillator frequency|After calibration|-|62.5|-|kHz|
|---|---|---|---|---|---|---|
|BRF|Bit rate, FSK|Programmable values (1)|1.2|-|300|kbps|
|BRO|Bit rate, OOK|Programmable|1.2|-|32.768|kbps|
|BRA|Bit Rate Accuracy|ABS(wanted BR - available BR)|-|-|250|ppm|
|FDA|Frequency deviation, FSK (1)|Programmable<br>FDA + BRF/2 =< 250 kHz|0.6|-|200|kHz|
_Note For Maximum Bit rate the maximum modulation index is 0.5._
## **2.4.3. FSK/OOK Mode Receiver**
All receiver tests are performed with RxBw = 10 kHz (Single Side Bandwidth) as programmed in _RegRxBw_ , receiving a PN15 sequence. Sensitivities are reported for a 0.1% BER (with Bit Synchronizer enabled), unless otherwise specified. Blocking tests are performed with an unmodulated interferer. The wanted signal power for the Blocking Immunity, ACR, IIP2, IIP3 and AMR tests is set 3 dB above the receiver sensitivity level.
_Table 53 FSK/OOK Receiver Specification_
|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|RFS_F_LF|Direct tie of RFI and RFO pins,<br>shared Rx, Tx paths FSK sensitiv-<br>ity, highest LNA gain.<br>Lower frequency bands|FDA = 5 kHz, BR = 1.2 kb/s<br>FDA = 5 kHz, BR = 4.8 kb/s<br>FDA = 40 kHz, BR = 38.4 kb/s*<br>FDA = 20 kHz, BR = 38.4 kb/s**<br>FDA = 62.5 kHz, BR = 250 kb/s***|-<br>-<br>-<br>-<br>-|-121<br>-117<br>-107<br>-108<br>-95|-<br>-<br>-<br>-<br>-|dBm<br>dBm<br>dBm<br>dBm<br>dBm|
||Split RF paths, the RF switch<br>insertion loss is not accounted for.<br>Lower frequency bands|FDA = 5 kHz, BR = 1.2 kb/s<br>FDA = 5 kHz, BR = 4.8 kb/s<br>FDA = 40 kHz, BR = 38.4 kb/s*<br>FDA = 20 kHz, BR = 38.4 kb/s**<br>FDA = 62.5 kHz, BR = 250 kb/s***|-<br>-<br>-<br>-<br>-|-123<br>-119<br>-109<br>-110<br>-97|-<br>-<br>-<br>-<br>-|dBm<br>dBm<br>dBm<br>dBm<br>dBm|
|RFS_F_HF|Direct tie of RFI and RFO pins,<br>shared Rx, Tx paths FSK sensitiv-<br>ity, highest LNA gain.<br>Higher frequency bands|FDA = 5 kHz, BR = 1.2 kb/s<br>FDA = 5 kHz, BR = 4.8 kb/s<br>FDA = 40 kHz, BR = 38.4 kb/s*<br>FDA = 20 kHz, BR = 38.4 kb/s**<br>FDA = 62.5 kHz, BR = 250 kb/s***|-<br>-<br>-<br>-<br>-|-119<br>-115<br>-105<br>-105<br>-92|-<br>-<br>-<br>-<br>-|dBm<br>dBm<br>dBm<br>dBm<br>dBm|
||Split RF paths, LnaBoost is turned<br>on, the RF switch insertion loss is<br>not accounted for.<br>Higher frequency bands|FDA = 5 kHz, BR = 1.2 kb/s<br>FDA = 5 kHz, BR = 4.8 kb/s<br>FDA = 40 kHz, BR = 38.4 kb/s*<br>FDA = 20 kHz, BR = 38.4 kb/s**<br>FDA = 62.5 kHz, BR = 250 kb/s***|-<br>-<br>-<br>-<br>-|-123<br>-119<br>-109<br>-109<br>-96|-<br>-<br>-<br>-<br>-|dBm<br>dBm<br>dBm<br>dBm<br>dBm|
|RFS_O<br>~~ee~~|OOK sensitivity, highest LNA gain<br>shared Rx, Tx paths<br>~~ee~~|BR = 4.8 kb/s<br>BR = 32 kb/s<br>~~ee~~|-<br>-<br>~~ee~~|-117<br>-108<br>~~ee~~|-<br>-<br>~~ee~~|dBm<br>dBm<br>~~ee~~|
|CCR<br>~~a~~|Co-Channel Rejection||-|-9|-|dB|
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**RFM95/96/97/98(W)**
|ACR|Adjacent Channel Rejection|FDA = 5 kHz, BR=4.8kb/s<br>Offset = +/- 25 kHz or +/- 50kHz<br>169MHz Band<br>434 MHz Band<br>8-900 MHz Band|-<br>-<br>-|59<br>56<br>50|-<br>-<br>-|dB<br>dB<br>dB|
|---|---|---|---|---|---|---|
|BI_HF|Blocking Immunity, higher bands|Offset = +/- 1 MHz<br>Offset = +/- 2 MHz<br>Offset = +/- 10 MHz|-<br>-<br>-|71<br>76<br>84|-<br>-<br>-|dB<br>dB<br>dB|
|BI_LF|Blocking Immunity, lower bands|Offset = +/- 1 MHz<br>Offset = +/- 2 MHz<br>Offset = +/- 10 MHz|-<br>-<br>-|71<br>72<br>78|-<br>-<br>-|dB<br>dB<br>dB|
|IIP2|2nd order Input Intercept Point<br>Unwanted tones are 20 MHz<br>above the LO|Highest LNA gain|-|+55|-|dBm|
|IIP3_HF|3rd order Input Intercept point<br>Unwanted tones are 1MHz and<br>1.995 MHz above the LO|Higher bands<br>Highest LNA gain G1<br>LNA gain G2, 4dB sensitivity hit|-<br>-|-12.5<br>-8.5|-<br>-|dBm<br>dBm|
|IIP3_LF|3rd order Input Intercept point<br>Unwanted tones are 1MHz and<br>1.995 MHz above the LO|Lower bands<br>Highest LNA gain G1<br>LNA gain G2, 2.5dB sensitivity hit|-<br>-|-22<br>-16|-<br>-|dBm<br>dBm|
|BW_SSB|Single Side channel filter BW|Programmable|2.7|-|250|kHz|
|IMR<br>~~a~~|Image Rejection|Wanted signal 3dB over sensitivity<br>BER=0.1%|-|48|-|dB|
|IMA<br>~~a~~|Image Attenuation||-|57|-|dB|
|DR_RSSI<br>~~a~~|RSSI Dynamic Range|AGC enabled<br>Min<br>Max|-<br>-|-127<br>0|-<br>-|dBm<br>dBm|
_* RxBw = 83 kHz (Single Side Bandwidth)_
_** RxBw = 50 kHz (Single Side Bandwidth)_
_*** RxBw = 250 kHz (Single Side Bandwidth)_
## **2.4.4. FSK/OOK Mode Transmitter**
_Table 54 Transmitter Specification_
|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|RF_OP|RF output power in 50 ohms<br>on RFO pin (High efficiency PA).|Programmable with steps<br>Max<br>Min|+11<br>-|+14<br>-1|-<br>-|dBm<br>dBm|
|ΔRF_<br>OP_V|RF output power stability on RFO<br>pin versus voltage supply.|VDD = 2.5 V to 3.3 V<br>VDD = 1.8 V to 3.7 V|-<br>-|3<br>8|-<br>-|dB<br>dB|
|RF_OPH|RF output power in 50 ohms, on<br>PA_BOOST pin (Regulated PA).|Programmable with 1dB steps<br>Max<br>Min|-<br>-|+17<br>+2|-<br>-|dBm<br>dBm|
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**RFM95/96/97/98(W)**
|RF_OPH_<br>MAX|Max RF output power, on<br>PA_BOOST pin|High power mode|-|+20|-|dBm|
|---|---|---|---|---|---|---|
|ΔRF_<br>OPH_V|RF output power stability on PA_-<br>BOOST pin versus voltage supply.|VDD = 2.4 V to 3.7 V|-|+/-1|-|dB|
|ΔRF_T|RF output power stability versus<br>temperature on PA_BOOST pin.|From T = -40 °C to +85 °C|-|+/-1|-|dB|
|PHN|Transmitter Phase Noise|169 MHz band<br>10kHz Offset<br>50kHz Offset<br>400kHz Offset<br>1MHz Offset|-<br>-<br>-<br>-|-118<br>-118<br>-128<br>-132|-<br>-<br>-<br>-|dBc/<br>Hz|
|||433 MHz band<br>10kHz Offset<br>50kHz Offset<br>400kHz Offset<br>1MHz Offset|-<br>-<br>-<br>-|-109<br>-109<br>-121<br>-128|-<br>-<br>-<br>-|dBc/<br>Hz|
|||868/915 MHz band<br>10kHz Offset<br>50kHz Offset<br>400kHz Offset<br>1MHz Offset|-<br>-<br>-<br>-|-103<br>-103<br>-115<br>-122|-<br>-<br>-<br>-|dBc/<br>Hz|
|ACP|Transmitter adjacent channel<br>power (measured at 25 kHz offset)|BT=1. Measurement conditions as<br>defined by EN 300 220-1 V2.3.1|-|-|-37|dBm|
|TS_TR|Transmitter wake up time, to the<br>first rising edge of DCLK|Frequency Synthesizer enabled,_PaR-_<br>_amp_= 10us, BR = 4.8 kb/s|-|120|-|us|
## **2.4.5. Electrical specification for** Lora[TM ] **modulation**
The table below gives the electrical specifications for the transceiver operating with Lora[TM ] modulation. Following conditions apply unless otherwise specified:
Supply voltage = 3.3 V.
Temperature = 25° C.
fXOSC = 32 MHz.
Lower bands: 169 MHz and 433 MHz, higher bands: 868 and 915 MHz
bandwidth (BW) = 125 kHz.
Spreading Factor (SF) = 12.
Error Correction Code (EC) = 4/6.
Packet Error Rate (PER)= 1%
CRC on payload enabled.
Output power = 13 dBm in transmission.
Payload length = 64 bytes.
Preamble Length = 12 symbols (programmed register _PreambleLength=8_ )
With matched impedances
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**RFM95/96/97/98(W)**
_Table 55 LoRa Receiver Specification._
|**Symbol**|**Description**|**Conditions**|**Min.**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|IDDR_L|Supply current in receiverLoraTM<br>mode, LnaBoost off|Lower Bands, Lower BW<br>Lower Bands, BW = 125 kHz<br>Lower Bands, BW = 250 kHz<br>Lower Bands, BW = 500 kHz|Lower Bands, Lower BW<br>Lower Bands, BW = 125 kHz<br>Lower Bands, BW = 250 kHz<br>-<br>-<br>-<br>-|TBC<br>11.5<br>12.4<br>13.8|-<br>-<br>-<br>-|mA<br>mA<br>mA<br>mA|
|||Higher Bands, Lower BW<br>Higher Bands, BW = 125 kHz<br>Higher Bands, BW = 250 kHz<br>Higher Bands, BW = 500 kHz|Higher Bands, Lower BW<br>Higher Bands, BW = 125 kHz<br>Higher Bands, BW = 250 kHz<br>-<br>-<br>-<br>-|TBC<br>10.3<br>11.1<br>12.6|-<br>-<br>-<br>-|mA<br>mA<br>mA<br>mA|
|IDDT_L<br>~~se~~|Supply current in transmitter mode<br>~~se~~|RFOP = 13 dBm<br>RFOP = 7 dBm<br>~~se~~|-<br>-<br>~~se~~|28<br>20<br>~~se~~|-<br>-<br>~~se~~|mA<br>mA<br>~~se~~|
|IDDT_H_L<br>~~se~~|Supply current in transmitter mode<br>with an external impedance<br>transformation<br>~~se~~|Using PA_BOOST pin<br>RFOP = 17 dBm<br>~~se~~|-<br>~~se~~|90<br>~~se~~|-<br>~~se~~|mA<br>~~se~~|
|BI_L<br>~~eee~~|Blocking immunity, FRF=868 MHz<br>CW interferer<br>~~eee~~|offset = +/- 1 MHz<br>offset = +/- 2 MHz<br>offset = +/- 10 MHz<br>~~eee~~|-<br>~~eee~~|TBC<br>TBC<br>TBC<br>~~eee~~|~~eee~~|dB<br>dB<br>dB<br>~~eee~~|
|IIP3_L_HF<br>~~ee~~|3rd order Input Intercept point<br>Unwanted tones are 1MHz and 1.995<br>MHz above the LO<br>~~ee~~|Higher bands<br>Highest LNA gain G1<br>LNA gain G2, 4dB sensitivity hit<br>~~ee~~|-<br>-<br>~~ee~~|-12.5<br>-8.5<br>~~ee~~|-<br>-<br>~~ee~~|dBm<br>dBm<br>~~ee~~|
|IIP3_L_LF<br>~~ee~~|3rd order Input Intercept point<br>Unwanted tones are 1MHz and 1.995<br>MHz above the LO<br>~~ee~~|Lower bands<br>Highest LNA gain G1<br>LNA gain G2, 2.5dB sensitivity<br>hit<br>~~ee~~|-<br>-<br>~~ee~~|-22<br>-16<br>~~ee~~|-<br>-<br>~~ee~~|dBm<br>dBm<br>~~ee~~|
|IIP2_L<br>~~eee~~|2nd order input intercept point,<br>highest LNA gain, FRF=868 MHz,<br>CW interferer.<br>~~eee~~|F1 = FRF + 20 MHz<br>F2 = FRF+ 20 MHz +Δf<br>~~eee~~|-<br>~~eee~~|+55<br>~~eee~~|-<br>~~eee~~|dBm<br>~~eee~~|
|BR_L|Bit rate, Long-Range Mode|From SF6, BW=500kHz to<br>SF12, BW=7.8kHz|0.018|-|37.5|kbps|
|RFS_L10|RF sensitivity, Long-Range Mode,<br>highest LNA gain, LNA boost for<br>higher bands, using split Rx/Tx path<br>10.4 kHz bandwidth|SF = 6<br>SF = 7<br>SF = 8<br>SF = 9<br>SF = 10<br>SF = 11<br>SF = 12|-<br>-<br>-<br>-<br>-<br>-<br>-|TBC<br>-134<br>TBC<br>TBC<br>TBC<br>TBC<br>TBC|-<br>-<br>-<br>-<br>-<br>-<br>-|dBm<br>dBm<br>dBm<br>dBm<br>dBm<br>dBm<br>dBm|
|RFS_L62|RF sensitivity, Long-Range Mode,<br>highest LNA gain, LNA boost for<br>higher bands, using split Rx/Tx path<br>62.5 kHz bandwidth|SF = 6<br>SF = 7<br>SF = 8<br>SF = 9<br>SF = 10<br>SF = 11<br>SF = 12|-<br>-<br>-<br>-<br>-<br>-<br>-|-121<br>-126<br>-129<br>-132<br>-135<br>-137<br>-139|-<br>-<br>-<br>-<br>-<br>-<br>-|dBm<br>dBm<br>dBm<br>dBm<br>dBm<br>dBm<br>dBm|
_Table 56. Electrical specifications:_ Lora[TM ] _mode_
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|**Symbol**<br>~~PT~~|**Description**<br>~~PT~~|**Conditions**<br>~~PT~~|**Min.**<br>~~PT~~|**Typ**<br>~~PT~~|**Max**<br>~~PT~~|**Unit**<br>~~PT~~|
|---|---|---|---|---|---|---|
|RFS_L125<br>~~PT~~|RF sensitivity, Long-Range Mode,<br>highest LNA gain, LNA boost for<br>higher bands, using split Rx/Tx path<br>125 kHz bandwidth<br>~~PT~~|SF = 6<br>SF = 7<br>SF = 8<br>SF = 9<br>SF = 10<br>SF = 11<br>SF = 12<br>~~PT~~|-<br>-<br>-<br>-<br>-<br>-<br>-<br>~~PT~~|-118<br>-123<br>-126<br>-129<br>-132<br>-133<br>-136<br>~~PT~~|-<br>-<br>-<br>-<br>-<br>-<br>-<br>~~PT~~|dBm<br>dBm<br>dBm<br>dBm<br>dBm<br>dBm<br>dBm<br>~~PT~~|
|RFS_L250<br>~~PT~~|RF sensitivity, Long-Range Mode,<br>highest LNA gain, LNA boost for<br>higher bands, using split Rx/Tx path<br>250 kHz bandwidth<br>~~PT~~|SF = 6<br>SF = 7<br>SF = 8<br>SF = 9<br>SF = 10<br>SF = 11<br>SF = 12<br>~~PT~~|-<br>-<br>-<br>-<br>-<br>-<br>-<br>~~PT~~|-115<br>-120<br>-123<br>-125<br>-128<br>-130<br>-133<br>~~PT~~|-<br>-<br>-<br>-<br>-<br>-<br>-<br>~~PT~~|dBm<br>dBm<br>dBm<br>dBm<br>dBm<br>dBm<br>dBm<br>~~PT~~|
|RFS_L500|RF sensitivity, Long-Range Mode,<br>highest LNA gain, LNA boost for<br>higher bands, using split Rx/Tx path<br>500 kHz bandwidth|SF = 6<br>SF = 7<br>SF = 8<br>SF = 9<br>SF = 10<br>SF = 11<br>SF = 12|-<br>-<br>-<br>-<br>-<br>-<br>-|-111<br>-116<br>-119<br>-122<br>-125<br>TBC<br>TBC|-<br>-<br>-<br>-<br>-<br>-<br>-|dBm<br>dBm<br>dBm<br>dBm<br>dBm<br>dBm<br>dBm|
|CCR_LCW|Co-channel rejection<br>Single CW tone = Sens +6 dB<br>1% PER|SF = 7<br>SF = 8<br>SF = 9<br>SF = 10<br>SF = 11<br>SF = 12|-<br>-<br>-<br>-<br>-<br>-|5<br>9.5<br>12<br>14.4<br>17<br>19.5|-<br>-<br>-<br>-<br>-<br>-|dB<br>dB<br>dB<br>dB<br>dB<br>dB|
|CCR_LL|Co-channel rejection|Interferer is aLoRaTMsignal<br>using same BW and same SF.<br>Pw = Sensitivity + 3 dB||-6||dB|
|ACR_LCW|Adjacent channel rejection|Interferer is 1.5*BW_L from the<br>wanted signal center frequency<br>1% PER, Single CW tone =<br>Sens + 3 dB<br>SF = 7<br>SF = 12|-<br>-|60<br>72|-<br>-|dB<br>dB|
|IMR_LCW<br>~~pL.~~|Image rejection after calibration.<br>~~pL.~~|1% PER, Single CW tone =<br>Sens +3 dB<br>~~+HH~~|-<br>~~HH~~|66<br>~~HH~~|-<br>~~HH~~|dB<br>~~HH~~|
|FERR_L<br>~~pL.~~|Maximum tolerated frequency offset<br>between transmitter and receiver, no<br>sensitivity degradation, SF6 thru 9<br>~~pL.~~|BW_L = 10.4 kHz<br>BW_L = 62.5 kHz<br>BW_L = 125 kHz<br>BW_L = 250 kHz<br>BW_L = 500 kHz<br>~~+HH~~|-2.5<br>-15<br>-30<br>-60<br>-120<br>~~HH~~|-<br>-<br>-<br>-<br>-<br>~~HH~~|2.5<br>15<br>30<br>60<br>120<br>~~HH~~|kHz<br>kHz<br>kHz<br>kHz<br>kHz<br>~~HH~~|
||Maximum tolerated frequency offset<br>between transmitter and receiver, no<br>sensitivity degradation, SF10 thru 11<br>~~pL.~~|SF = 12<br>SF = 11<br>SF = 10<br>~~+HH~~|-50<br>-100<br>-200<br>~~HH~~|-<br>-<br>-<br>~~HH~~|50<br>100<br>200<br>~~HH~~|ppm<br>ppm<br>ppm<br>~~HH~~|
_Table 56. Electrical specifications:_ Lora[TM ] _mode_
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**RFM95/96/97/98(W)**
## **2.4.6. Digital Specification**
Conditions: Temp = 25° C, VDD = 3.3 V, FXOSC = 32 MHz, unless otherwise specified.
_Table 57 Digital Specification_
|**Symbol**<br>~~a A~~|**Description**<br>~~A~~|**Conditions**<br>~~OO~~|**Min**<br>~~OO~~|**Typ**<br>~~OO~~|**Max**<br>~~OO~~|**Unit**<br>~~OO~~|
|---|---|---|---|---|---|---|
|VIH<br>~~a~~|Digital input level high<br>~~a~~<br>~~a~~|~~a~~<br>~~a~~|0.8<br>~~a~~<br>~~a~~|-<br>~~a~~<br>~~a~~|-<br>~~a~~<br>~~a~~|VDD<br>~~a~~<br>~~a~~|
|VIL<br>~~a~~<br>~~a~~|Digital input level low<br>~~a~~<br>~~a~~<br>~~a~~|~~a~~<br>~~a~~<br>~~a~~|-<br>~~a~~<br>~~a~~<br>~~a~~|-<br>~~a~~<br>~~a~~<br>~~a~~|0.2<br>~~a~~<br>~~a~~<br>~~a~~|VDD<br>~~a~~<br>~~a~~<br>~~a~~|
|VOH<br>~~a~~|Digital output level high<br>~~a~~|Imax = 1 mA<br>~~a~~|0.9<br>~~a~~|-<br>~~a~~|-<br>~~a~~|VDD<br>~~a~~|
|VOL<br>~~a~~|Digital output level low<br>~~a~~|Imax = -1 mA<br>~~a~~|-<br>~~a~~|-<br>~~a~~|0.1<br>~~a~~|VDD<br>~~a~~|
|FSCK<br>~~a~~<br>~~a~~|SCK frequency<br>~~a~~<br>~~a~~|~~a~~<br>~~a~~|-<br>~~a~~<br>~~a~~|-<br>~~a~~<br>~~a~~|10<br>~~a~~<br>~~a~~|MHz<br>~~a~~<br>~~a~~|
|tch<br>~~a~~|SCK high time<br>~~a~~|~~a~~|50<br>~~a~~|-<br>~~a~~|-<br>~~a~~|ns<br>~~a~~|
|tcl<br>~~a~~|SCK low time<br>~~a~~|~~a~~|50<br>~~a~~|-<br>~~a~~|-<br>~~a~~|ns<br>~~a~~|
|trise<br>~~a~~|SCK rise time<br>~~a~~|~~a~~|-<br>~~a~~|5<br>~~a~~|-<br>~~a~~|ns<br>~~a~~|
|tfall<br>~~a~~|SCK fall time<br>~~a~~|~~a~~|-<br>~~a~~|5<br>~~a~~|-<br>~~a~~|ns<br>~~a~~|
|tsetup<br>~~a~~|MOSI setup time<br>~~a~~<br>~~ee~~|From MOSI change to SCK rising<br>edge.<br>~~a~~<br>~~ee ~~|30<br>~~a~~<br> ~~ee~~|-<br>~~a~~<br>~~ee~~|-<br>~~a~~<br>~~ee~~|ns<br>~~a~~<br>~~ee~~|
|thold<br>~~a~~|MOSI hold time<br>~~ee~~|From SCK rising edge to MOSI<br>change.<br>~~ee ~~|20<br> ~~ee~~|-<br>~~ee~~|-<br>~~ee~~|ns<br>~~ee~~|
|tnsetup<br>~~a~~|NSS setup time<br>~~ee~~|From NSS falling edge to SCK rising<br>edge.<br>~~ee ~~|30<br> ~~ee~~|-<br>~~ee~~|-<br>~~ee~~|ns<br>~~ee~~|
|tnhold<br>~~a~~|NSS hold time<br>~~ee~~|From SCK falling edge to NSS rising<br>edge, normal mode.<br>~~ee ~~|100<br> ~~ee~~|-<br>~~ee~~|-<br>~~ee~~|ns<br>~~ee~~|
|tnhigh<br>~~a~~|NSS high time between SPI<br>accesses<br>~~ee~~|~~ee ~~|20<br> ~~ee~~|-<br>~~ee~~|-<br>~~ee~~|ns<br>~~ee~~|
|T_DATA<br>~~DG~~|DATA hold and setup time<br>~~DG~~|~~DG~~|250<br>~~DG~~|-<br>~~DG~~|-<br>~~DG~~|ns<br>~~DG~~|
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**RFM95/96/97/98(W)**
## **3. RFM95/96/97/98(W) Features**
This section gives a high-level overview of the functionality of the RFM95/96/97/98(W) low-power, highly integrated transceiver. The following figure shows a simplified block diagram of the RFM95/96/97/98(W).
_Figure 3. RFM95/96/97/98(W) Block Schematic Diagram_
RFM95/96/97/98(W) is a half-duplex, low-IF transceiver. Here the received RF signal is first amplified by the LNA. The LNA inputs are single ended to minimise the external BoM and for ease of design. Following the LNA inputs, the conversion to differential is made to improve the second order linearity and harmonic rejection. The signal is then downconverted to in- phase and quadrature (I&Q) components at the intermediate frequency (IF) by the mixer stage. A pair of sigma delta ADCs then perform data conversion, with all subsequent signal processing and demodulation performed in the digital domain. The digital state machine also controls the automatic frequency correction (AFC), received signal strength indicator (RSSI) and automatic gain control (AGC). It also features the higher-level packet and protocol level functionality of the top level sequencer (TLS).
The frequency synthesisers generate the local oscillator (LO) frequency for both receiver and transmitter, one covering the lower UHF bands (up to 525 MHz), and the other one covering the upper UHF bands (from 860 MHz). The PLLs are optimized for user-transparent low lock time and fast auto-calibrating operation. In transmission, frequency modulation is performed digitally within the PLL bandwidth. The PLL also features optional pre-filtering of the bit stream to improve spectral purity.
RFM95/96/97/98(W) feature three distinct RF power amplifiers. Two of those, connected to RFO_LF and RFO_HF, can deliver up to +14 dBm, are unregulated for high power efficiency and can be connected directly to their respective RF receiver inputs via a pair of passive components to form a single antenna port high efficiency transceiver. The third PA, connected to the PA_BOOST pin and can deliver up to +20 dBm via a dedicated matching network. Unlike the high efficiency PAs, this high- stability PA covers all frequency bands that the frequency synthesizer addresses.
RFM95/96/97/98(W) also include two timing references, an RC oscillator and a 32 MHz crystal oscillator.
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**RFM95/96/97/98(W)**
All major parameters of the RF front end and digital state machine are fully configurable via an SPI interface which gives access to RFM95/96/97/98(W)’s configuration registers. This includes a mode auto sequencer that oversees the transition and calibration of the RFM95/96/97/98(W) between intermediate modes of operation in the fastest time possible.
The RFM95/96/97/98(W) are equipped with both standard FSK and long range spread spectrum (LoRa[TM] ) modems. Depending upon the mode selected either conventional OOK or FSK modulation may be employed or the LoRa[TM ] spread spectrum modem.
## **3.1. LoRa[TM ] Modem**
The LoRa[TM ] modem uses a proprietary spread spectrum modulation technique. This modulation, in contrast to legacy modulation techniques, permits an increase in link budget and increased immunity to in-band interference. At the same time the frequency tolerance requirement of the crystal reference oscillator is relaxed - allowing a performance increase for a reduction in system cost. For a fuller description of the design trade-offs and operation of the RFM95/96/97/98(W) please consult Section 4.1 of the datasheet.
## **3.2. FSK/OOK Modem**
In FSK/OOK mode the RFM95/96/97/98(W) supports standard modulation techniques including OOK, FSK, GFSK, MSK and GMSK. The RFM95/96/97/98(W) is especially suited to narrow band communication thanks the low-IF architecture employed and the built-in AFC functionality. For full information on the FSK/OOK modem please consult Section 4.2 of this document.
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**RFM95/96/97/98(W)**
## **4. RFM95/96/97/98(W) Digital Electronics**
## **4.1. The LoRa[TM ] Modem**
The LoRa[TM ] modem uses spread spectrum modulation and forward error correction techniques to increase the range and robustness of radio communication links compared to traditional FSK or OOK based modulation. Examples of the performance improvement possible, for several possible settings, are summarised in the table below. Here the spreading factor and error correction rate are design variables that allow the designer to optimise the trade-off between occupied bandwidth, data rate, link budget improvement and immunity to interference.
_Table 58 Example LoRa[TM ] Modem Performances_
|**Bandwidth**<br>**(kHz)**|**Spreading Factor**|**Coding rate**|**Nominal Rb**<br>**(bps)**|**Sensitivity**<br>**indication**<br>**(dBm)**|**Frequency**<br>**Reference**|
|---|---|---|---|---|---|
|10.4|6|4/5|782|TBC|TCXO|
||12|4/5|24|TBC||
|20.8|6|4/5|1562|TBC||
||12|4/5|49|TBC||
|62.5|6|4/5|4688|-121|XTAL|
||12|4/5|146|-139||
|125|6|4/5|9380|-118||
||12|4/5|293|-136||
For European operation the range of crystal tolerances acceptable for each sub-band (of the ERC 70-03) is given in the specifications table. For US based operation a frequency hopping mode is available that automates both the LoRa[TM ] spread spectrum and frequency hopping spread spectrum processes.
Another important facet of the LoRa[TM ] modem is its increased immunity to interference. The LoRa[TM ] modem is capable of co-channel GMSK rejection of up to 25 dB. This immunity to interference permits the simple coexistence of LoRa[TM ] modulated systems either in bands of heavy spectral usage or in hybrid communication networks that use LoRa[TM ] to extend range when legacy modulation schemes fail.
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## **4.1.1. Link Design Using the LoRa[TM ] Modem**
## _4.1.1.1. Overview_
The LoRa[TM ] modem is setup as shown in the following figure. This configuration permits the simple replacement of the FSK modem with the LoRa[TM ] modem via the configuration register setting _RegOpMode._ This change can be performed on the fly (in Sleep operating mode) thus permitting the use of both standard FSK or OOK in conjunction with the long range capability. The LoRa[TM ] modulation and demodulation process is proprietary, it uses a form of spread spectrum modulation combined with cyclic error correction coding. The combined influence of these two factors is an increase in link budget and enhanced immunity to interference.
> _Figure 4. LoRa[TM ] Modem Connectivity_
A simplified outline of the transmit and receive processes is also shown above. Here we see that the LoRa[TM ] modem has an independent dual port data buffer FIFO that is accessed through an SPI interface common to all modes. Upon selection of LoRa[TM ] mode, the configuration register mapping of the RFM95/96/97/98(W) changes. For full details of this change please consult the register description of Section 6.
So that it is possible to optimise the LoRa[TM ] modulation for a given application, access is given to the designer to three critical design parameters. Each one permitting a trade off between link budget, immunity to interference, spectral occupancy and nominal data rate. These parameters are spreading factor, modulation bandwidth and error coding rate.
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## _4.1.1.2. Spreading Factor_
The spread spectrum LoRa[TM ] modulation is performed by representing each bit of payload information by multiple chips of information. The rate at which the spread information is sent is referred to as the symbol rate (Rs), the ratio between the nominal symbol rate and chip rate is the spreading factor and represents the number of symbols sent per bit of information. The range of values accessible with the LoRa[TM ] modem are shown in the following table.
## _Table 59 Range of Spreading Factors_
|**_SpreadingFactor_**<br>**(RegModulationCfg)**|**Spreading Factor**<br>**(Chips / symbol)**|**LoRa Demodulator**<br>**SNR**|
|---|---|---|
|6|64|-5 dB|
|7|128|-7.5 dB|
|8|256|-10 dB|
|9|512|-12.5 dB|
|10|1024|-15 dB|
|11|2048|-17.5 dB|
|12|4096|-20 dB|
Note that the spreading factor, _SpreadingFactor_ , must be known in advance on both transmit and receive sides of the link as different spreading factors are orthogonal to each other. Note also the resulting signal to noise ratio (SNR) required at the receiver input. It is the capability to receive signals with negative SNR that increases the sensitivity, so link budget and range, of the LoRa receiver.
## **Spreading Factor 6**
SF = 6 Is a special use case for the highest data rate transmission possible with the LoRa modem. To this end several settings must be activated in the RFM95/96/97/98(W) registers when it is in use:
Set _SpreadingFactor_ = 6 in _RegModemConfig2_
The header must be set to Implicit mode
Write bits 2-0 of register address 0x31 to value "0b101"
Write register address 0x37 to value 0x0C
## _4.1.1.3. Coding Rate_
To further improve the robustness of the link the LoRa[TM ] modem employs cyclic error coding to perform forward error detection and correction. Such error coding incurs a transmission overhead - the resultant additional data overhead per transmission is shown in the table below.
## _Table 60 Cyclic Coding Overhead_
|**_CodingRate_**<br>**(RegTxCfg1)**|**Cyclic Coding**<br>**Rate**|**Overhead Ratio**|
|---|---|---|
|1|4/5|1.25|
|2|4/6|1.5|
|3|4/7|1.75|
|4|4/8|2|
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**RFM95/96/97/98(W)**
Forward error correction is particularly efficient in improving the reliability of the link in the presence of interference. So that the coding rate (and so robustness to interference) can be changed in response to channel conditions - the coding rate can optionally be included in the packet header for use by the receiver. Please consult Section 4.1.1.6 for more information on the LoRa[TM ] packet and header.
## _4.1.1.4. Signal Bandwidth_
An increase in signal bandwidth permits the use of a higher effective data rate, thus reducing transmission time at the expense of reduced sensitivity improvement. There are of course regulatory constraints in most countries on the permissible occupied bandwidth. Contrary to the FSK modem which is described in terms of the single sideband bandwidth, the LoRa[TM ] modem bandwidth refers to the double sideband bandwidth (or total channel bandwidth). The range of bandwidths relevant to most regulatory situations is given in the LoRa[TM ] modem specifications table (see Section 2.4.5).
|**Bandwidth**<br>**(kHz)**|**Spreading Factor**|**Coding rate**|**Nominal Rb**<br>**(bps)**|
|---|---|---|---|
|7.8|12|4/5|18|
|10.4|12|4/5|24|
|15.6|12|4/5|37|
|20.8|12|4/5|49|
|31.2|12|4/5|73|
|41.7|12|4/5|98|
|62.5|12|4/5|146|
|125|12|4/5|293|
|250|12|4/5|586|
|500|12|4/5|1172|
## _Note In the lower band (169 MHz), the 250 kHz and 500 kHz bandwidths are not supported._
## _4.1.1.5. LoRa[TM ] Transmission Parameter Relationship_
With a knowledge of the key parameters that can be controlled by the user we define the LoRa[TM ] symbol rate as:
**==> picture [41 x 19] intentionally omitted <==**
where BW is the programmed bandwidth and SF is the spreading factor. The transmitted signal is a constant envelope signal. Equivalently, one chip is sent per second per Hz of bandwidth.
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**RFM95/96/97/98(W)**
## _4.1.1.6. LoRa[TM ] Packet Structure_
The LoRa[TM ] modem employs two types of packet format, explicit and implicit. The explicit packet includes a short header that contains information about the number of bytes, coding rate and whether a CRC is used in the packet. The packet format is shown in the following figure.
The LoRa[TM ] packet comprises three elements:
- A preamble.
- An optional header.
- The data payload.
## _Figure 5._ LoRa[TM ] _Packet Structure_
## **Preamble**
The preamble is used to synchronize receiver with the incoming data flow. By default the packet is configured with a 12 symbol long sequence. This is a programmable variable so the preamble length may be extended, for example in the interest of reducing to receiver duty cycle in receive intensive applications. However, the minimum length suffices for all communication. The transmitted preamble length may be changed by setting the register _PreambleLength_ from 6 to 65535, yielding total preamble lengths of 6+4 to 65535+4 symbols, once the fixed overhead of the preamble data is considered. This permits the transmission of a near arbitrarily long preamble sequence.
The receiver undertakes a preamble detection process that periodically restarts. For this reason the preamble length should be configured identical to the transmitter preamble length. Where the preamble length is not known, or can vary, the maximum preamble length should be programmed on the receiver side.
## **Header**
Depending upon the chosen mode of operation two types of header are available. The header type is selected by the _ImplictHeaderMode_ bit found within the _RegSymbTimeoutMsb_ register.
## _**Explicit Header Mode**_
This is the default mode of operation. Here the header provides information on the payload, namely:
- The payload length in bytes.
- The forward error correction code rate
The presence of an optional 16-bits CRC for the payload.
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The header is transmitted with maximum error correction code (4/8). It also has its own CRC to allow the receiver to discard invalid headers.
## I **mplicit Header Mode**
In certain scenarios, where the payload, coding rate and CRC presence are fixed or known in advance, it may be advantageous to reduce transmission time by invoking implicit header mode. In this mode the header is removed from the packet. In this case the payload length, error coding rate and presence of the payload CRC must be manually configured on both sides of the radio link.
_Note With SF = 6 selected, implicit header mode is the only mode of operation possible._
## **Payload**
The packet payload is a variable-length field that contains the actual data coded at the error rate either as specified in the header in explicit mode or in the register settings in implicit mode. An optional CRC may be appended. For more information on the payload and how it is loaded from the data buffer FIFO please see Section 4.1.2.3.
## _4.1.1.7. Time on air_
For a given combination of spreading factor (SF), coding rate (CR) and signal bandwidth (BW) the total on-the-air transmission time of a LoRa[TM ] packet can be calculated as follows. From the definition of the symbol rate it is convenient to define the symbol rate:
**==> picture [33 x 17] intentionally omitted <==**
The LoRa packet duration is the sum of the duration of the preamble and the transmitted packet. The preamble length is calculated as follows:
**==> picture [135 x 13] intentionally omitted <==**
where _npreamble_ is the programmed preamble length, _PreambleLength_ .The payload duration depends upon the header mode that is enabled. The following formulae give the payload duration in implicit (headerless) and explicit (with header) modes.
**==> picture [376 x 58] intentionally omitted <==**
Addition of these two durations gives the total packet on -air time.
**==> picture [119 x 10] intentionally omitted <==**
## _4.1.1.8. Frequency Hopping with LoRa[TM]_
Frequency hopping spread spectrum (FHSS) is typically employed when the duration of a single packet could exceed regulatory requirements relating to the maximum permittable channel dwell time. This is most notably the case in US operation where the 902 to 928 MHz ISM band can be used ina frequency hopping mode. To ease implementation of FHSS systems the frequency hopping mode of the LoRa[TM ] modem can be enabled (see _FhssMode_ of register _RegTxCfg1_ ).
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**RFM95/96/97/98(W)**
## **Principle of Operation**
The principle behind the FHSS scheme is that a portion of each LoRa[TM ] packet is transmitted on each hopping channel from a look up table of frequencies managed by the host microcontroller. After a predetermined hopping period the transmitter and receiver change to the next channel in a predefined list of hopping frequencies to continue transmission and reception of the next portion of the packet. The time which the transmission will dwell in any given channel is determined by _HoppingPeriod_ which is an integer multiple of symbol periods:
_HoppingPeriod_ = _Ts_ × _F reqHoppingPeriod_
The frequency hopping transmission and reception process starts at channel 0. The preamble and header are transmitted first on channel 0. At the beginning of each transmission the interrupt the channel counter _FhssPresentChannel_ is incremented and the interrupt signal _FhssChangeChannel_ is generated. The new frequency must then be programmed within the hopping period to ensure it is taken into account for the next hop, the interrupt _FhssChangeChannel_ is then to be cleared by writing a logical ‘1’.
FHSS Reception always starts on channel 0. The receiver waits for a valid preamble detection before starting the frequency hopping process as described above. Note that in the eventuality of header CRC corruption, the receiver will automatically request channel 0 and recommence the valid preamble detection process.
## **Timing of Channel Updates**
The interrupt requesting the channel change, _FhssChannelChange,_ is generated upon transition to the new frequency. The frequency hopping process is recapitulated in the diagram below:
_Figure 6. Interrupts generated in the case of successful frequency hopping communication._
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## **4.1.2. LoRa[TM ] Digital Interface**
The LoRa[TM ] modem comprises three types of digital interface, static configuration registers, status registers and a FIFO data buffer. All are accessed through the RFM95/96/97/98(W)’s SPI interface - full details of each type of register are given below. Full listings of the register addresses used for SPI access are given in Section 6.4.
## _4.1.2.1. LoRa[TM ] Configuration Registers_
Configuration registers are accessed through the SPI interface. Registers are readable in all device mode including Sleep. However, they should be **written only in Sleep and Stand-by modes** . Please note that **the automatic top level sequencer (TLS modes) are not available in** LoRa[TM ] **mode** and **the configuration register mapping changes as shown in Table** 85 **.** The content of the LoRa[TM ] configuration registers is retained in FSK/OOK mode. For the functionality of mode registers common to both FSK/OOK and LoRa[TM ] mode, please consult the Analog and RF Front End section of this document (Section 5).
## _4.1.2.2. Status Registers_
Status registers provide status information during receiver operation.
## _4.1.2.3. LoRa[TM ] Mode FIFO Data Buffer_
## **Overview**
The RFM95/96/97/98(W) is equipped with a 256 byte RAM data buffer which is uniquely accessible in LoRa mode. This RAM area, thereafter reffered to as the FIFO Data buffer, is fully customizable by the user and allows access to the received, or to be transmitted, data. All access to the LoRa[TM ] FIFO data buffer is done via the SPI interface. A diagram of the user defined memory mapping of the FIFO data buffer is shown below. These FIFO data buffer can be read in all operating modes except sleep and store data related to the last receive operation performed. It is automatically cleared of old content upon each new transition to receive mode.
> _Figure 7._ LoRa[TM ] _data buffer_
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## **Principle of Operation**
Thanks to its dual port configuration, it is possible to simultaneously store both transmit and receive information in the FIFO data buffer. The register _FifoTxBaseAddr_ specifies the point in memory where the transmit information is stored. Similarly, for receiver operation, the register _FifoRxBaseAddr_ indicates the point in the data buffer where information will be written to in event of a receive operation.
By default, the device is configured at power-up so that half of the available memory is dedicated to Rx ( _FifoRxBaseAddr_ initialized at address 0x00) and the other half is dedicated for Tx ( _FifoTxBaseAddr_ initialized at address 0x80).
However, due to the contiguous nature of the FIFO data buffer, the base addresses for Tx and Rx are fully configurable across the 256 byte memory area. Each pointer can be set independently anywhere within the FIFO. To exploit the maximum FIFO data buffer size in transmit or receive mode, the whole FIFO data buffer can be used in each mode by setting the base addresses _FifoTxBaseAddr_ and _FifoRxBaseAddr_ at the bottom of the memory (0x00).
The FIFO data buffer is cleared when the device is put in SLEEP mode, consequently no access to the FIFO data buffer is possible in sleep mode. However, the data in the FIFO data buffer are retained when switching across the other LoRa modes of operation, so that a received packet can be retransmitted with minimum data handling on the controller side. The FIFO data buffer is not self-clearing (unless if the device is put in sleep mode) and the data will only be “erased” when a new set of data is written into the occupied memory location.
The actual location to be read from, or written to, over the SPI interface is defined by the address pointer _FifoAddrPtr_ . Before any read or write operation it is hence necessary to initialise this pointer to the corresponding base value. Upon reading or writing to the FIFO data buffer ( _RegFifo_ ) the address pointer will then increment automatically.
The register _FifoRxBytesNb_ defines the size of the memory location to be written in the event of a successful receive operation. On the other hand _PayloadLength_ indicates the size of the memory location to be transmitted. In implicit header mode, the _FifoRxBytesNb_ is not used as the number of payload bytes is known. Otherwise, in explicit header mode, the initial size of the receive buffer is set to the packet length in the received header. The variable _FifoRxCurrentAddr_ indicates the location of the last packet received in the FIFO so that the last packet received can be easily read by pointing the _FifoAddrPtr_ to this register.
It is important to notice that all the received data will be written to the FIFO data buffer even if the CRC is invalid. This allows for post-processing of received data for debug purposes for instance. It is also imporant to note that when receiving, if the packet size exceeds the buffer memory allocated for the Rx it will overwrite the transmit portion of the data buffer.
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## **4.1.3. Operation of the LoRa[TM ] Modem**
## _4.1.3.1. Operating Mode Control_
The operating modes of the LoRa[TM ] modem are accessed by enabling LoRa[TM ] mode (setting the _LongRangeMode_ bit of _RegOpMode_ ). Depending upon the operating mode selected the range of functionality and register access is given by the following table:
## _Table 61 LoRa[TM ] Operating Mode Functionality_
|**Operating Mode**|**Description**|
|---|---|
|**SLEEP**|Low-power mode. In this mode only SPI and configuration registers are accessible.LoraFIFO is not<br>accessible.<br>Note that this is the only mode permissible to switch between FSK/OOK mode andLoRamode.|
|**STAND-BY**|both Crystal oscillator andLorabaseband blocks are turned on.RF part and PLLs are disabled|
|**FSTX**|This is a frequency synthesis mode for transmission. The PLL selected for transmission is locked and active<br>at the transmit frequency. The RF part is off.|
|**FSRX**|This is a frequency synthesis mode for reception. The PLL selected for reception is locked and active at the<br>receive frequency. The RF part is off.|
|**TX**|When activated the RFM95/96/97/98(W) powers all remaining blocks required for transmit, ramps the PA,<br>transmits the packet and returns to Stand-by mode.|
|**RXCONTINUOUS**|When activated the RFM95/96/97/98(W) powers all remaining blocks required for reception,<br>processing all received data until a new user request is made to change operating mode.|
|**RXSINGLE**|When activated the RFM95/96/97/98(W) powers all remaining blocks required for reception, remains in<br>this state until a valid packet has been received and then returns to Stand-by mode.|
|**CAD**|When in CAD mode, the device will check a given channel to detect LoRa preamble signal|
It is possible to access any mode from any other mode by changing the value in the _RegOpMode_ register.
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## **4.1.4. Frequency Settings**
Recalling that the frequency step is given by:
**==> picture [66 x 24] intentionally omitted <==**
In order to set LO frequency values following registers are available.
Frf is a 24-bit register which defines carrier frequency. The carrier frequency relates to the register contents by following formula:
**==> picture [100 x 11] intentionally omitted <==**
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## **4.1.5. LoRa[TM ] Modem State Machine Sequences**
The sequence for transmission and reception of data to and from the LoRa[TM ] modem, together with flow charts of typical sequences of operation, are detailed below.
## **Data Transmission Sequence**
In transmit mode power consumption is optimized by enabling RF, PLL and PA blocks only when packet data needs to be transmitted. Figure 8 shows a typical LoRa[TM ] transmit sequence.
## _Figure 8._ LoRa[TM ] _modulation transmission sequence._
Static configuration registers can only be accessed in Sleep mode, Stand-by mode or FSTX mode.
The LoRa[TM ] FIFO can only be filled in Stand-by mode.
Data transmission is initiated by sending TX mode request.
Upon completion the _TxDone_ interrupt is issued and the radio returns to Stand-by mode.
Following transmission the radio can be manually placed in Sleep mode or the FIFO refilled for a subsequent Tx operation.
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## **LoRa[TM ] Transmit Data FIFO Filling**
In order to write packet data into FIFO user should:
- 1 Set _FifoPtrAddr_ to _FifoTxPtrBase_ .
- 2 Write _PayloadLength_ bytes to the FIFO ( _RegFifo_ )
## **Data Reception Sequence**
Figure 9 shows typical LoRa[TM ] receive sequences for both single and continuous receiver modes of operation.
_Figure 9. LoRa[TM ] receive sequence._
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The LORA receive modem can work in two distinct mode
1. Single receive mode
2. Continuous receive mode
Those two modes correspond to different use cases and it is important to understand the subtle differences between them.
## _**Single Reception Operating Mode**_
In this mode, the modem searches for a preamble during a given time window. If a preamble hasn’t been found at the end of the time window, the chip generates the RxTimeout interrupt and goes back to stand-by mode . The length of the window (in symbols) is defined by the RegSymbTimeout register and should be in the range of 4 (minimum time for the modem to acquire lock on a preamble) up to 1023 symbols. (The default value being 5). If no preamble is detected during this window the RxTimeout interrupt is generated and the radio goes back to stand-by mode.
At the end of the payload, the RxDone interrupt is generated together with the interrupt PayloadCrcError if the payload CRC is not valid. However, even when the CRC is not valid, the data are written in the FIFO data buffer for post processing. Following the RxDone interrupt the radio goes to stand-by mode.
The modem will also automatically return in stand-by mode when the interrupts RxDone or RxTimeout are generated. Therefore, this mode should only be used when the time window of arrival of the packet is known . In other cases, the RX continuous mode should be used.
In Rx single mode low-power is achieved by turning off PLL and RF blocks as soon as a packet has been received. The flow is as follows:
- 1 _Set FifoPtrAddr_ to _FifoRxPtrBase_ .
- 2 Static configuration register device can be written in either Sleep mode, Stand-by mode or FSRX mode.
3 A single packet receive operation is initiated by selecting the operating mode RXSINGLE.
4 The receiver will then await the reception of a valid preamble. Once received, the gain of the receive chain is set. Following the ensuing reception of a valid header, indicated by the ValidHeader interrupt in explicit mode. The packet reception process commences. Once the reception process is complete the RxDone interrupt is set. The radio then returns automatically to Stand-by mode to reduce power consumption.
5 The receiver status register PayloadCrcError should be checked for packet payload integrity.
6 If a valid packet payload has been received then the FIFO should be read (See Payload Data Extraction below). Should a subsequent single packet reception need to be triggered, then the RXSINGLE operating mode must be re-selected to launch the receive process again - taking care to reset the SPI pointer (FifoPtrAddr) to the base location in memory (FifoRxPtrBase).
## _**Continuous Reception Operating Mode**_
In continuous receive mode the modem scans the channel continuously for a preamble. Each time a preamble is detected the modem detects and tracks it until the packet is received and then carries on waiting for the next preamble.
If the preamble length exceeds the anticipated value set by the registers RegPreambleMsb and RegPreambleLsb (measured in symbol unit), the preamble will be dropped and the search for a preamble restarted. However, this scenario will not be flagged by an interrupt. In continous RX mode, opposite to the single RX mode, when a timeout interrupt is generated, the device will not go in standby mode. In this case, the user must simply clear the interrupt while the device carry on waiting for a valid preamble.
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It is also important to note that the demodulated bytes are written in the data buffer memory in the order received. Meaning, the first byte of a new packet is written just after the last byte of the preceding packet. The RX modem address pointer is never reseted as long as this mode is enabled. It is therefore necessary for the controller to handle the address pointer to make sure the FIFO data buffer is never full.
In continuous mode the received packet processing sequence is given below.
- 1 Whilst in Sleep or Stand-by mode select RXCONT mode.
- 2 Upon reception of a valid header CRC the _RxDone i_ nterrupt is set. The radio remains in RXCONT mode waiting for the next RX LoRa[TM ] packet.
- 3 The _PayloadCrcError_ flag should be checked for packet integrity.
- 4 If packet has been correctly received the FIFO data buffer can be read (see below).
- 5 The reception process (steps 2 - 4) can be repeated or receiver operating mode exited as desired.
In continuous mode status information are available only for the last packet received, i.e. the corresponding registers should be read before the next RxDone arrives.
## **Payload Data Extraction from FIFO**
In order to retrieve received data from FIFO the user must ensure that _ValidHeader_ , _PayloadCrcError, RxDone_ and _RxTimeout_ interrupts in the status register RegIrqFlags are not asserted to ensure that packet reception has terminated successfully (i.e. no flags should be set).
In case of errors the steps below should be skipped and the packet discarded. In order to retrieve valid received data from the FIFO the user must:
- _FifoNbRxBytes_ Indicates the number of bytes that have been received thus far.
_RegRxDataAddr_ Is a dynamic pointer that indicates precisely where the Lora modem received data has been written up to.
Set _FifoPtrAddr_ to _FifoRxCurrentAddr_ . This sets the FIFO pointer to the the location of the last packet received in the FIFO. The payload can then be extracted by reading the _RegFifo_ address _RegNbRxBytes_ times. Alternatively, it is possible to manually point to the location of the last packet received from the start of the current packet by setting _FifoPtrAddr_ to _RegRxDataAddr_ - _FifoNbRxBytes_ . In the same way, packet bytes can then be extracted from FIFO by reading the _RegFifo_ address _RegNbRxBytes_ times.
## **Packet Filtering based on Preamble Start**
The LoRa modem does automatically filter received packets based upon any addressing. However the RFM95/96/97/98(W) permit software filtering of the received packets based on the contents of the first few bytes of payload. A brief example is given below for a 4 byte address, however, the address length can be selected by the designer.
The objective of the packet filtering process is to determine the presence, or otherwise, of a valid packet designed for the receiver. If the packet is not for the receiver then the radio returns to sleep mode in order to improve battery life.
The software packet filtering process follows the steps below:
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Each time the RxDone interrupt is received, latch the RegFifoRxByteAddr[7:0] register content in a variable , this variable will be called start_address. The RegFifoRxByteAddr[7:0] register of the RFM95/96/97/98(W) gives in real time the address of the last byte written in the data buffer + 1 (or the address at which the next byte will be written) by the receive LoRa modem . So by doing this , we make sure that the variable start_address always contains the start address of the next packet.
Upon reception of the interrupt ValidHeader, start polling the RegFifoRxByteAddr[7:0] register until it begins to increment. The speed at which this register will increment depends on the Spreading factor, the error correction code and the modulation bandwidth. (Note that this interrupt is still generated in implicit mode).
As soon as RegFifoRxByteAddr[7:0] >= start address + 4, the first 4 bytes (address) are stored in the FIFO data buffer. These can be read and tested to see if the packet is destined for the radio and either remaining in Rx mode to receive the packet or returning to sleep mode if not.
## **Receiver Timeout Operation**
In either single or continuous LoRa[TM ] reception modes, a receiver timeout functionality is available that permits the receiver to listen for a pre-determined period of time before generating an interrupt signal to indicate that no valid packets have been received. The timer is absolute and commences as soon as the radio is placed in either single or continuous receive mode. The interrupt itself, _RxTimeout_ , can be found in the interrupt register _RegIrqFlags_ . In Rx Single mode, the device will return in Stanby mode as soon as the interrupt occurs and the interrupt needs to be cleared before to return in Rx Single mode. In Rx Continuous mode, the interrupt will interrupt will simply be raised but the device will stay in Rx Continous mode. It is therefore the responsability on the controller to clear the interrupt while still in Rx Continuous mode. The programmed timeout value is expressed as a multiple of the symbol period and is given by:
_TimeOut_ = _LoraRxTimeout_ · _Ts_
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## **Channel Activity Detection**
The use of a spread spectrum modulation technique presents challenges in determining whether the channel is already in use by a signal that may be below the noise floor of the receiver. The use of the RSSI in this situation would clearly be impracticable. To this end the channel activity detector is used to detect the presence of other LoRa[TM ] signals. Figure 10 shows the channel activity detection (CAD) process:
_Figure 10._ LoRa[TM ] _CAD flow_
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## **Principle of Operation**
The channel activity detection mode is designed to detect a LoRa preamble on the radio channel with the best possible power efficiency. Once in CAD mode, the RFM95/96/97/98(W) will perform a very quick scan of the band to detect a LoRa packet preamble.
During a CAD the following operations take place:
## The PLL locks
The radio receiver captures LoRa preamble symbol of data from the channel. The radio current consumption during that phase corresponds to the specified Rx mode current
The radio receiver and the PLL turn off, and the modem digital processing starts.
The modem searches for a correlation between the radio captured samples and the ideal preamble waveform. This correlation process takes a little bit less than a symbol period to perform. The radio current consumption during that phase is greatly reduced.
Once the calculation is finished the modem generates the CadDone interrupt. If the correlation was successful, CadDetected is generated simultaneously.
The chip goes back to stand-by mode.
If a preamble was detected, clear the interrupt, then initiate the reception by putting the radio in RX single mode or RX continuous mode.
The time taken for the channel activity detection is dependent upon the LoRa modulation settings used. For a given configuration the typical CAD detection time is shown in the graph below, expressed as a multiple of the LoRa symbol period. Of this period the radio is in receiver mode for (2[SF ] + 32) / BW seconds. For the remainder of the CAD cycle the radio is in a reduced consumption state.
_Figure 11. Channel activity detection (CAD) time as a function of spreading factor_
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To illustrate this process and the respective consumption in each mode, the CAD process follows the sequence of events outlined below:
_Figure 12. Consumption Profile of the LoRa CAD Process_
The receiver is then in full receiver mode for just over half of the activity detection, followed by a reduced consumption processing phase where the consumption varies with the LoRa bandwidth as shown in the table below.
## _Table 62 LoRa CAD Consumption Figures_
|**Bandwidth**<br>**(kHz)**|**Full Rx, IDDR_L**<br>**(mA)**|**Processing, IDDC_L**<br>**(mA)**|
|---|---|---|
|7.8|To be<br>confirmed||
|10.4|||
|15.6|||
|20.8|||
|31.2|||
|41.7|||
|62.5|||
|125|10.8|5.6|
|250|11.6|6.5|
|500|13|8|
## _4.1.5.1. Digital IO Pin Mapping_
Six of RFM95/96/97/98(W)’s general purpose IO pins are available used in LoRa[TM ] mode. Their mapping is shown below and depends upon the configuration of registers _RegDioMapping1_ and _RegDioMapping2._
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_Table 63 DIO Mapping_ LoRa[TM ] _Mode_
|**Operating**<br>**Mode**|**DIOx**<br>**Mapping**|**DIO5**|**DIO4**|**DIO3**|**DIO2**|**DIO1**|**DIO0**|
|---|---|---|---|---|---|---|---|
|ALL|00|ModeReady|CadDetected|CadDone|FhssChangeChannel|RxTimeout|RxDone|
||01|ClkOut|PllLock|ValidHeader|FhssChangeChannel|FhssChangeChannel|TxDone|
||10|ClkOut|PllLock|PayloadCrcError|FhssChangeChannel|CadDetected|CadDone|
||11|-|-|-|-|-|-|
## **4.2. FSK/OOK Modem**
## **4.2.1. Bit Rate Setting**
The bitrate setting is referenced to the crystal oscillator and provides a precise means of setting the bit rate (or equivalently chip) rate of the radio. In continuous transmit mode (Section 3.2.2) the data stream to be transmitted can be input directly to the modulator via pin 9 (DIO2/DATA) in an asynchronous manner, unless Gaussian filtering is used, in which case the DCLK signal on pin 10 (DIO1/DCLK) is used to synchronize the data stream. See section 4.2.2.3 for details on the Gaussian filter.
In Packet mode or in Continuous mode with Gaussian filtering enabled, the Bit Rate (BR) is controlled by bits _Bitrate_ in _RegBitrateMsb and RegBitrateLsb_
**==> picture [155 x 30] intentionally omitted <==**
## _Note: BitrateFrac bits have_ _**no effect** (i.e may be considered equal to 0)_ _**in OOK** modulation mode._
The quantity _BitrateFrac_ is hence designed to allow very high precision (max. 250 ppm programing resolution) for any bitrate in the programmable range. Table 64 below shows a range of standard bitrates and the accuracy to within which they may be reached.
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## _Table 64 Bit Rate Examples_
|**Type**|**BitRate**<br>**(15:8)**|**BitRate**<br>**(7:0)**|**(G)FSK**<br>**(G)MSK**|**OOK**|**Actual BR**<br>**(b/s)**|
|---|---|---|---|---|---|
|Classical modem baud rates<br>(multiples of 1.2 kbps)|0x68<br>~~a~~<br>~~a~~|0x2B<br>|1.2 kbps<br>|1.2 kbps<br>|1200.015<br>~~ee~~<br>|
||0x34<br>~~a~~<br>~~a~~|0x15<br>~~ee~~<br>|2.4 kbps<br>~~ee~~<br>|2.4 kbps<br>~~ee~~<br>|2400.060<br>~~ee~~<br>~~ee~~<br>|
||0x1A<br>~~a ee~~|0x0B<br>~~ee~~|4.8 kbps<br>~~ee~~|4.8 kbps<br>~~ee~~|4799.760<br>~~ee~~<br>~~ee~~|
||0x0D<br>~~a~~|0x05|9.6 kbps|9.6 kbps|9600.960|
||0x06<br>~~a~~|0x83<br>~~ee~~|19.2 kbps<br>~~ee~~|19.2 kbps<br>~~ee~~|19196.16<br>~~ee~~|
||0x03<br>~~a ee~~|0x41<br>~~ee~~|38.4 kbps<br>~~ee~~|~~ee~~|38415.36<br>~~ee~~|
||0x01<br>~~a~~|0xA1|76.8 kbps||76738.60|
||0x00<br>~~a~~|0xD0|153.6 kbps||153846.1|
|Classical modem baud rates<br>(multiples of 0.9 kbps)<br>~~SS~~|0x02<br>~~SS~~|0x2C<br>~~SS~~|57.6 kbps<br>~~a~~||57553.95|
||0x01<br>~~SS~~<br>~~a~~|0x16<br>~~SS~~<br>~~ee~~|115.2 kbps<br>~~a~~<br>~~ee~~|~~ee~~|115107.9<br>~~ee~~|
|Round bit rates<br>(multiples of 12.5, 25 and<br>50 kbps)<br>~~SS~~|0x0A<br>~~SS~~<br>~~a~~<br>~~a~~|0x00<br>~~SS ~~<br>~~ee~~|12.5 kbps<br> ~~a~~<br>~~ee~~|12.5 kbps<br>~~ee~~|12500.00<br>~~ee~~|
||0x05<br>~~a~~|0x00|25 kbps|25 kbps|25000.00|
||0x80<br>~~a~~|0x00|50 kbps||50000.00|
||0x01<br>~~a~~|0x40|100 kbps||100000.0|
||0x00<br>~~a~~|0xD5|150 kbps||150234.7|
||0x00<br>~~a~~|0xA0|200 kbps||200000.0|
||0x00<br>~~a~~|0x80|250 kbps||250000.0|
||0x00<br>~~a~~|0x6B|300 kbps||299065.4|
|Watch Xtal frequency<br>~~a~~|0x03|0xD1|32.768 kbps|32.768 kbps|32753.32|
## **4.2.2. FSK/OOK Transmission**
## _4.2.2.1. FSK Modulation_
FSK modulation is performed inside the PLL bandwidth, by changing the fractional divider ratio in the feedback loop of the PLL. The high resolution of the sigma-delta modulator, allows for very narrow frequency deviation. The frequency deviation FDEV is given by:
**==> picture [107 x 10] intentionally omitted <==**
To ensure correct modulation, the following limit applies:
**==> picture [88 x 18] intentionally omitted <==**
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_Note No constraint applies to the modulation index of the transmitter, but the frequency deviation must be set between 600 Hz and 200 kHz._
## _4.2.2.2. OOK Modulation_
OOK modulation is applied by switching on and off the power amplifier. Digital control and ramping are available to improve the transient power response of the OOK transmitter.
## _4.2.2.3. Modulation Shaping_
Modulation shaping can be applied in both OOK and FSK modulation modes, to improve the narrowband response of the transmitter. Both shaping features are controlled with _PaRamp_ bits in _RegPaRamp_ .
In FSK mode, a Gaussian filter with BT = 0.5 or 1 is used to filter the modulation stream, at the input of the sigma-delta modulator. If the Gaussian filter is enabled when the RFM95/96/97/98(W) is in Continuous mode, DCLK signal on pin 10 (DIO1/DCLK) will trigger an interrupt on the uC each time a new bit has to be transmitted. Please refer to section 5.4.2 for details.
When OOK modulation is used, the PA bias voltages are ramped up and down smoothly when the PA is turned on and off, to reduce spectral splatter.
_Note The transmitter must be restarted if the ModulationShaping setting is changed, in order to recalibrate the built-in filter._
## **4.2.3. FSK/OOK Reception**
## _4.2.3.1. FSK Demodulator_
The FSK demodulator of the RFM95/96/97/98(W) is designed to demodulate FSK, GFSK, MSK and GMSK modulated signals. It is most efficient when the modulation index of the signal is greater than 0.5 and below 10:
**==> picture [92 x 23] intentionally omitted <==**
The output of the FSK demodulator can be fed to the Bit Synchronizer to provide the companion processor with a synchronous data stream in Continuous mode.
## _4.2.3.2. OOK Demodulator_
The OOK demodulator performs a comparison of the RSSI output and a threshold value. Three different threshold modes are available, configured through bits _OokThreshType_ in _RegOokPeak_ .
The recommended mode of operation is the “Peak” threshold mode, illustrated in Figure 13:
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**==> picture [499 x 286] intentionally omitted <==**
**----- Start of picture text -----**<br>
RSSI<br>[dBm]<br>‘’Peak -6dB’’ Threshold<br>‘’Floor’’ threshold defined by<br>OokFixedThresh<br>Noise floor of<br>receiver<br>Time<br>SN<br>Zoom<br>Decay in dB as defined in<br>OokPeakThreshStep Fixed 6dB difference<br>Period as defined in<br>OokPeakThreshDec<br>al<br>**----- End of picture text -----**<br>
_Figure 13. OOK Peak Demodulator Description_
In peak threshold mode the comparison threshold level is the peak value of the RSSI, reduced by 6dB. In the absence of an input signal, or during the reception of a logical ‘0’, the acquired peak value is decremented by one _OokPeakThreshStep_ every _OokPeakThreshDec_ period.
When the RSSI output is null for a long time (for instance after a long string of “0” received, or if no transmitter is present), the peak threshold level will continue falling until it reaches the “Floor Threshold”, programmed in _OokFixedThresh_ .
The default settings of the OOK demodulator lead to the performance stated in the electrical specification. However, in applications in which sudden signal drops are awaited during a reception, the three parameters should be optimized accordingly.
## **Optimizing the Floor Threshold**
_OokFixedThresh_ determines the sensitivity of the OOK receiver, as it sets the comparison threshold for weak input signals (i.e. those close to the noise floor). Significant sensitivity improvements can be generated if configured correctly. Note that the noise floor of the receiver at the demodulator input depends on:
The noise figure of the receiver.
The gain of the receive chain from antenna to base band.
The matching - including SAW filter if any.
The bandwidth of the channel filters.
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It is therefore important to note that the setting of _OokFixedThresh_ will be application dependant. The following procedure is recommended to optimize _OokFixedThresh_ .
**==> picture [181 x 196] intentionally omitted <==**
**----- Start of picture text -----**<br>
Set RFM96/7/8 in OOK Rx mode<br>Adjust Bit Rate, Channel filter BW<br>Default OokFixedThresh setting<br>No input signal<br>Continuous Mode<br>Monitor DIO2/DATA pin<br>Increment<br>OokFixedThresh<br>Glitch activity<br>on DATA ?<br>Optimization complete<br>**----- End of picture text -----**<br>
_Figure 14. Floor Threshold Optimization_
The new floor threshold value found during this test should be used for OOK reception with those receiver settings.
## **Optimizing OOK Demodulator for Fast Fading Signals**
A sudden drop in signal strength can cause the bit error rate to increase. For applications where the expected signal drop can be estimated, the following OOK demodulator parameters _OokPeakThreshStep_ and _OokPeakThreshDec_ can be optimized as described below for a given number of threshold decrements per bit. Refer to _RegOokPeak_ to access those settings.
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## **Alternative OOK Demodulator Threshold Modes**
In addition to the Peak OOK threshold mode, the user can alternatively select two other types of threshold detectors:
- 4 Fixed Threshold: The value is selected through _OokFixedThresh_
- 4 Average Threshold: Data supplied by the RSSI block is averaged, and this operation mode should only be used with DC-free encoded data.
## _4.2.3.3. Bit Synchronizer_
The bit synchronizer provides a clean and synchronized digital output based upon timing recovery information gleaned from the received data edge transitions. Its output is made available on pin DIO1/DCLK in Continuous mode and can be disabled through register settings. However, for optimum receiver performance, especially in Continuous receive mode, its use is strongly advised.
The Bit Synchronizer is automatically activated in Packet mode. Its bit rate is controlled by _BitRateMsb_ and _BitRateLsb_ in _RegBitrate._
**==> picture [113 x 144] intentionally omitted <==**
**----- Start of picture text -----**<br>
Raw demodulator<br>output<br>(FSK or OOK)<br>DATA<br>BitSync Output To<br>pin DATA and<br>DCLK in continuous<br>mode<br>DCLK<br>**----- End of picture text -----**<br>
_Figure 15. Bit Synchronizer Description_
To ensure correct operation of the Bit Synchronizer, the following conditions have to be satisfied:
- A preamble (0x55 or 0xAA) of at least 12 bits is required for synchronization, the longer the synchronization phase is the better the ensuing packet detection rate will be.
The subsequent payload bit stream must have at least one edge transition (either rising or falling) every 16 bits during data transmission.
The absolute error between transmitted and received bit rate must not exceed 6.5%.
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## _4.2.3.4. Frequency Error Indicator_
This frequency error indicator measures the frequency error between the programmed RF centre frequency and the carrier frequency of the modulated input signal to the receiver. When the FEI is performed, the frequency error is measured and the signed result is loaded in _FeiValue_ in _RegFei_ , in 2’s complement format. The time required for an FEI evaluation is 4 bit periods.
To ensure correct operation of the FEI:
The measurement must be launched during the reception of preamble.
The sum of the frequency offset and the 20 dB signal bandwidth must be lower than the base band filter bandwidth. i.e. The whole modulated spectrum must be received.
The 20 dB bandwidth of the signal can be evaluated as follows (double-side bandwidth):
_BW_ 20 _dB_ = 2 × ⎝[⎛ ] _FDEV_ + -------2[⎠ ][⎞ ]
The frequency error, in Hz, can be calculated with the following formula:
**==> picture [121 x 277] intentionally omitted <==**
**----- Start of picture text -----**<br>
FEI = FSTEP × Fe iV alue<br>RFM96/7/8 in Rx mode<br>Preamble-modulated input signal<br>Signal level > Sensitivity<br>Set FeiStart<br>= 1<br>FeiDone No<br>= 1<br>Yes<br>Read<br>FeiValue<br>**----- End of picture text -----**<br>
_Figure 16. FEI Process_
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## _4.2.3.5. AFC_
The AFC is based on the FEI measurement, therefore the same input signal and receiver setting conditions apply. When the AFC procedure is performed the _AfcValue_ is directly subtracted from the register that defines the frequency of operation of the chip, FRF. The AFC is executed each time the receiver is enabled, if _AfcAutoOn_ = 1.
When the AFC is enabled ( _AfcAutoOn_ = 1), the user has the option to:
Clear the former AFC correction value, if _AfcAutoClearOn_ = 1. Allowing the next frequency correction to be performed from the initial centre frequency.
Start the AFC evaluation from the previously corrected frequency. This may be useful in systems in which the centre frequency experiences cumulative drift - such as the ageing of a crystal reference.
The RFM95/96/97/98(W) offers an alternate receiver bandwidth setting during the AFC phase allowing the accommodation of larger frequency errors. The setting _RegAfcBw_ sets the receive bandwidth during the AFC process. In a typical receiver application the, once the AFC is performed, the radio will revert to the receiver communication or channel bandwidth ( _RegRxBw_ ) for the ensuing communication phase.
Note that the FEI measurement is valid only during the reception of preamble. The provision of the _PreambleDetect_ flag can hence be used to detect this condition and allow a reliable AFC or FEI operation to be triggered. This process can be performed automatically by using the appropriate options in _StartDemodOnPreamble_ found in the _RegRxConfig_ register.
A detailed description of the receiver setup to enable the AFC is provided in section 4.2.6.
## _4.2.3.6. Preamble Detector_
The Preamble Detector indicates the reception of a carrier modulated with a 0101...sequence. It is insensitive to the frequency offset, as long as the receiver bandwidth is large enough. The size of detection can be programmed from 1 to 3 bytes with _PreambleDetectorSize_ in _RegPreambleDetect_ as defined in the next table.
## _Table 65 Preamble Detector Settings_
|**_PreambleDetectorSize_**|**# of Bytes**|
|---|---|
|00|1|
|01|2 (recommended)|
|10|3|
|11|reserved|
For normal operation, _PreambleDetectTol_ should be set to be set to 10 (0x0A), with a qualifying preamble size of 2 bytes.
The _PreambleDetect_ interrupt (either in _RegIrqFlags1_ or mapped to a specific DIO) then goes high every time a valid preamble is detected, assuming _PreambleDetectorOn_ =1.
The preamble detector can also be used as a gate to ensure that AFC and AGC are performed on valid preamble. See section 4.2.6. for details.
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## _4.2.3.7. Image Rejection Mixer_
The RFM95/96/97/98(W) employs an image rejection mixer (IRM) which, uncalibrated, 35 dB image rejection. A low phase noise
PLL is used to perform calibration of the receiver chain. This increases the typical image rejection to 48 dB.
## _4.2.3.8. Image and RSSI Calibration_
An automatic calibration process is used to calibrate the phase and gain of both I and Q receive paths. This calibration allows enhanced image frequency rejection and improves the RSSI precision. This Calibration process is launched under the following circumstances:
Automatically at Power On Reset or after a Manual Reset of the chip (refer to section 7.2). For applications where the temperature remains stable, or if the Image Rejection is not a major concern, this single calibration will suffice.
Automatically when a pre-defined temperature change is observed.
Upon User request, by setting bit _ImageCalStart_ in _RegImageCal_ , when the device is in Standby mode. Note that in LoRa[TM ] mode the calibration command is inaccessible. To perform the calibration, the radio must be returned temporarily to FSK/OOK mode for the calibration process.
A selectable temperature change, set with _TempThreshold_ (5, 10, 15 or 20°C), is detected and reported in _TempChange_ , if the temperature monitoring is turned On with _TempMonitorOff_ =0 _._
This interrupt flag can be used by the application to launch a new image calibration at a convenient time if _AutoImageCalOn_ =0, or immediately when this temperature variation is detected, if _AutoImageCalOn_ =1.
The calibration process takes approximately 10ms.
## _4.2.3.9. Timeout Function_
The RFM95/96/97/98(W) includes a Timeout function, which allows it to automatically shut-down the receiver after a receive sequence and therefore save energy.
_Timeout_ interrupt is generated _TimeoutRxRssi x 16 x Tbit_ after switching to Rx mode if the _Rssi_ flag does not raise within this time frame ( _RssiValue_ > _RssiThreshold_ )
_Timeout_ interrupt is generated _TimeoutRxPreamble x 16 x Tbit_ after switching to Rx mode if the _PreambleDetect_ flag does not raise within this time frame
_Timeout_ interrupt is generated _TimeoutSignalSync x 16 x Tbit_ after switching to Rx mode if the _SyncAddress_ flag does not raise within this time frame
This timeout interrupt can be used to warn the companion processor to shut down the receiver and return to a lower power mode. To become active, these timeouts must also be enabled by setting the correct _RxTrigger_ parameters in _RegRxConfig:_
## _Table 66 RxTrigger Settings to Enable Timeout Interrupts_
|**_Receiver_**<br>**_Triggering Event_**|**_RxTrigger_**<br>**_(2:0)_**|**_Timeout on_**<br>**_Rssi_**|**_Timeout on_**<br>**_Preamble_**|**_Timeout on_**<br>**_SyncAddress_**|
|---|---|---|---|---|
|None|000|Off|Off|Active|
|_Rssi_Interrupt|001|Active|Off||
|_PreambleDetect_|110|Off|Active||
|_Rssi_Interrupt &_PreambleDetect_|111|Active|Active||
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## **4.2.4. Operating Modes in FSK/OOK Mode**
The RFM95/96/97/98(W) has several working modes, manually programmed in _RegOpMode_ . Fully automated mode selection, packet transmission and reception is also possible using the Top Level Sequencer described in Section 4.2.8. _Table 67 Basic Transceiver Modes_
|**Mode**|**Selected mode**|**Symbol**|**Enabled blocks**|
|---|---|---|---|
|000|Sleep mode|Sleep|None|
|001|Standby mode|Stdby|Top regulator and crystal oscillator|
|010|Frequency synthesiser to Tx<br>frequency|FSTx|Frequency synthesizer at Tx frequency (Frf)|
|011|Transmit mode|Tx|Frequency synthesizer and transmitter|
|100|Frequency synthesiser to Rx<br>frequency|FSRx|Frequency synthesizer at frequency for reception (Frf-IF)|
|101|Receive mode|Rx|Frequency synthesizer and receiver|
When switching from a mode to another the sub-blocks are woken up according to a pre-defined optimized sequence.
## **4.2.5. Startup Times**
The startup time of the transmitter or the receiver is dependant upon which mode the transceiver was in at the beginning. For a complete description, Figure 17 below shows a complete startup process, from the lower power mode “Sleep”.
**==> picture [406 x 205] intentionally omitted <==**
**----- Start of picture text -----**<br>
Current<br>Drain<br>IDDR (Rx) or IDDT (Tx)<br>IDDFS<br>IDDST<br>IDDSL Timeline<br>0 TS_OSC TS_OSC TS_OSC TS_OSC<br>+TS_FS +TS_FS +TS_FS<br>+TS_TR +TS_RE<br>FSTx Transmit<br>Sleep Stdby<br>mode mode<br>FSRx Receive<br>**----- End of picture text -----**<br>
_Figure 17. Startup Process_
TS_OSC is the startup time of the crystal oscillator which depends on the electrical characteristics of the crystal. TS_FS is the startup time of the PLL including systematic calibration of the VCO.
Typical values of TS_OSC and TS_FS are given in Section 2.3.
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## _4.2.5.1. Transmitter Startup Time_
The transmitter startup time, TS_TR, is calculated as follows in FSK mode:
**==> picture [214 x 30] intentionally omitted <==**
where _PaRamp_ is the ramp-up time programmed in _RegPaRamp_ and _Tbit_ is the bit time.
In OOK mode, this equation can be simplified to the following:
**==> picture [114 x 26] intentionally omitted <==**
## _4.2.5.2. Receiver Startup Time_
The receiver startup time, TS_RE, only depends upon the receiver bandwidth effective at the time of startup. When AFC is enabled ( _AfcAutoOn_ =1), _AfcBw_ should be used instead of _RxBw_ to extract the receiver startup time:
## _Table 68 Receiver Startup Time Summary_
|_Table 68 Receiver Startup Time Summary_||
|---|---|
|**_RxBw_if****_AfcAutoOn=0_**<br>**_RxBwAfc_if****_AfcAutoOn=1_**|**TS_RE**<br>**(+/-5%)**|
|2.6 kHz|2.33 ms|
|3.1 kHz|1.94 ms|
|3.9 kHz|1.56 ms|
|5.2 kHz|1.18 ms|
|6.3 kHz|984 us|
|7.8 kHz|791 us|
|10.4 kHz|601 us|
|12.5 kHz|504 us|
|15.6 kHz|407 us|
|20.8 kHz|313 us|
|25.0 kHz|264 us|
|31.3 kHz|215 us|
|41.7 kHz|169 us|
|50.0 kHz|144 us|
|62.5 kHz|119 us|
|83.3 kHz|97 us|
|100.0 kHz|84 us|
|125.0 kHz|71 us|
|166.7 kHz|85 us|
|200.0 kHz|74 us|
|250.0 kHz|63 us|
TS_RE or later after setting the device in Receive mode, any incoming packet will be detected and demodulated by the transceiver.
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## _4.2.5.3. Time to RSSI Evaluation_
The first RSSI sample will be available TS_RSSI after the receiver is ready, in other words TS_RE + TS_RSSI after the receiver was requested to turn on.
**==> picture [244 x 106] intentionally omitted <==**
**----- Start of picture text -----**<br>
Timeline<br>0 TS_RE TS_RE<br>+TS_RSSI<br>| | |<br>Rssi IRQ<br>FSRx Rx Rssi sample<br>ready<br>@-a-CD<br>Figure 18. Time to Rssi Sample<br>**----- End of picture text -----**<br>
TS_RSSI depends on the receiver bandwidth, as well as the _RssiSmoothing_ option that was selected. The formula used to calculate TS_RSSI is provided in section 2.5.4.
## _4.2.5.4. Tx to Rx Turnaround Time_
**==> picture [228 x 96] intentionally omitted <==**
**----- Start of picture text -----**<br>
Timeline<br>0 TS_HOP<br>+TS_RE<br>1. set new Frf (*)<br>Tx Mode Rx Mode<br>2. set Rx mode<br>@- -@<br>(*) Optional<br>**----- End of picture text -----**<br>
_Figure 19. Tx to Rx Turnaround_
_Note The SPI instruction times are omitted, as they can generally be very small as compared to other timings (up to 10MHz SPI clock)._
## _4.2.5.5. Rx to Tx_
**==> picture [228 x 96] intentionally omitted <==**
**----- Start of picture text -----**<br>
Timeline<br>0 TS_HOP<br>+TS_TR<br>1. set new Frf (*)<br>Rx Mode Tx Mode<br>2. set Tx mode<br>@- -+@<br>(*) Optional<br>**----- End of picture text -----**<br>
_Figure 20. Rx to Tx Turnaround_
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## _4.2.5.6. Receiver Hopping, Rx to Rx_
Two methods are possible:
**==> picture [277 x 237] intentionally omitted <==**
**----- Start of picture text -----**<br>
First method<br>Timeline<br>0 TS_HOP<br>+TS_RE<br>Rx Mode, 1. set new Frf Rx Mode,<br>Channel A 2. set RestartRxWithPllLock Channel B<br>Cy} =C)D<br>Second method<br>Timeline<br>0 ~TS_HOP<br>Rx M ode, 1. set FastHopOn =1 Rx Mode,<br>2. set new Frf (*)<br>Channel A Channel B<br>3. wait for TS_HOP<br>Cc )- —@»<br>(*) RegFrfLsb must be written to<br>trigger a frequency change<br>**----- End of picture text -----**<br>
_Figure 21. Receiver Hopping_
The second method is quicker, and should be used if a very quick RF sniffing mechanism is to be implemented.
## _4.2.5.7. Tx to Tx_
**==> picture [300 x 66] intentionally omitted <==**
**----- Start of picture text -----**<br>
Timeline<br>0 ~ PaRamp ~PaRamp<br>+TS_HOP +TS_HOP<br>+TS_TR<br>Tx Mode, 1. set new Frf (*) FSTx Set Tx mode Tx Mode,<br>Channel A 2. set FSTx mode Channel B<br>**----- End of picture text -----**<br>
_Figure 22. Transmitter Hopping_
## **4.2.6. Receiver Startup Options**
The RFM95/96/97/98(W) receiver can automatically control the gain of the receive chain (AGC) and adjust the receiver LO
frequency (AFC). Those processes are carried out on a packet-by-packet basis. They occur:
When the receiver is turned On.
When the Receiver is restarted upon user request, through the use of trigger bits _RestartRxWithoutPllLock_ or _RestartRxWithPllLock_ , in _RegRxConfig._
When the receiver is automatically restarted after the reception of a valid packet, or after a packet collision.
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Automatic restart capabilities are detailed in Section 4.2.7.
The receiver startup options available in RFM95/96/97/98(W) are described in Table 69.
## _Table 69 Receiver Startup Options_
|_Table 69 Receiver Startup Options_|||||
|---|---|---|---|---|
|**_Triggering Event_**|**Realized Function**|**_AgcAutoOn_**|**_AfcAutoOn_**|**_RxTrigger_**<br>**_(2:0)_**|
|None|None|0|0|000|
|_Rssi_Interrupt|AGC|1|0|001|
||AGC & AFC|1|1|001|
|_PreambleDetect_|AGC|1|0|110|
||AGC & AFC|1|1|110|
|_Rssi_Interrupt<br>&<br>_PreambleDetect_|AGC|1|0|111|
||AGC & AFC|1|1|111|
When _AgcAutoOn_ =0, the LNA gain is manually selected by choosing _LnaGain_ bits in _RegLna._
## **4.2.7. Receiver Restart Methods**
The options for restart of the receiver are covered below. This is typically of use to prepare for the reception of a new signal whose strength or carrier frequency is different from the preceding packet to allow the AGC or AFC to be re-evaluated.
## _4.2.7.1. Restart Upon User Request_
In Receive mode the user can request a receiver restart - this can be useful in conjunction with the use of a Timeout interrupt following a period of inactivity in the channel of interest. Two options are available:
No change in the Local Oscillator upon restart: the AFC is disabled, and the _Frf_ register has not been changed through SPI before the restart instruction: set bit _RestartRxWithoutPllLock_ in _RegRxConfig_ to 1.
Local Oscillator change upon restart: if AFC is enabled ( _AfcAutoOn_ =1), and/or the _Frf_ register had been changed during the last Rx period: set bit _RestartRxWithPllLock_ in _RegRxConfig_ to 1.
_Note ModeReady must be at logic level 1 for a new RestartRx command to be taken into account._
## _4.2.7.2. Automatic Restart after valid Packet Reception_
The bits _AutoRestartRxMode_ in _RegSyncConfig_ control the automatic restart feature of the RFM95/96/97/98(W) receiver, when a valid packet has been received:
If _AutoRestartRxMode_ = 00, the function is off, and the user should manually restart the receiver upon valid packet reception (see section 4.2.7.1 _)._
If _AutoRestartRxMode_ = 01, after the user has emptied the FIFO following a _PayloadReady_ interrupt, the receiver will automatically restart itself after a delay of _InterPacketRxDelay_ , allowing for the distant transmitter to ramp down, hence avoiding a false RSSI detection on the ‘tail’ of the previous packet.
If _AutoRestartRxMode_ = 10 should be used if the next reception is expected on a new frequency, i.e. _Frf_ is changed after the reception of the previous packet. An additional delay is systematically added, in order for the PLL to lock at a new frequency.
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## _4.2.7.3. Automatic Restart when Packet Collision is Detected_
In receive mode the RFM95/96/97/98(W) is able to detect packet collision and restart the receiver. Collisions are detected by a sudden rise in received signal strength, detected by the RSSI. This functionality can be useful in network configurations where many asynchronous slaves attempt periodic communication with a single a master node.
The collision detector is enabled by setting bit _RestartRxOnCollision_ to 1.
The decision to restart the receiver is based on the detection of RSSI change. The sensitivity of the system can be adjusted in 1 dB steps by using register _RssiCollisionThreshold_ in _RegRxConfig_ .
## **4.2.8. Top Level Sequencer**
Depending on the application, it is desirable to be able to change the mode of the circuit according to a predefined sequence without access to the serial interface. In order to define different sequences or scenarios, a user-programmable state machine, called Top Level Sequencer (Sequencer in short), can automatically control the chip modes.
## _**NOTE THAT THIS FUNCTIONALITY IS ONLY AVAILABLE IN FSK/OOK MODE.**_
The Sequencer is activated by setting the _SequencerStart_ bit in _RegSeqConfig1_ to 1 in Sleep or Standby mode (called initial mode).
It is also possible to force the Sequencer off by setting the _Stop_ bit in _RegSeqConfig1_ to 1 at any time.
## _Note SequencerStart and Stop bit must never be set at the same time._
## _4.2.8.1. Sequencer States_
As shown in the table below, with the aid of a pair of interrupt timers (T1 and T2), the sequencer can take control of the chip operation in all modes.
## _Table 70 Sequencer States_
|**_Sequencer_**<br>**_State_**|**Description**|
|---|---|
|**SequencerOff State**|The Sequencer is not activated. Sending a_SequencerStart_command will launch it.<br>When coming from**LowPowerSelection**state, the Sequencer will be Off, whilst the chip will<br>return to its initial mode (either Sleep or Standby mode).|
|**Idle State**|The chip is in low-power mode, either_Standby_or_Sleep_, as defined by_IdleMode_in<br>_RegSeqConfig1_. The Sequencer waits only for the_T1_interrupt.|
|**Transmit State**|The transmitter in on.|
|**Receive State**|The receiver in on.|
|**PacketReceived**|The receiver is on and a packet has been received. It is stored in the FIFO.|
|**LowPowerSelection**|Selects low power state (**SequencerOff**or**Idle**State)|
|**RxTimeout**|Defines the action to be taken on a RxTimeout interrupt.<br>RxTimeout interrupt can be a_TimeoutRxRssi_,_TimeoutRxPreamble_or_TimeoutSignalSync_<br>interrupt.|
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## _4.2.8.2. Sequencer Transitions_
The transitions between sequencer states are listed in the forthcoming table.
## _Table 71 Sequencer Transition Options_
|**_Variable_**|**Transition**|
|---|---|
|_IdleMode_|Selects the chip mode during**Idle**state:<br>0:_Standby_mode<br>1:_Sleep_mode|
|_FromStart_|Controls the Sequencer transition when the_SequencerStart_bit is set to 1 in_Sleep_or_Standby_mode:<br>00: to**LowPowerSelection**<br>01: to**Receive**state<br>10: to**Transmit**state<br>11: to**Transmit**state on a_FifoThreshold_interrupt|
|_LowPowerSelection_|Selects Sequencer LowPower state after a_to LowPowerSelection_transition<br>0:**SequencerOff**state with chip on Initial mode<br>1:**Idle**state with chip on_Standby_or_Sleep_mode depending on**IdleMode**<br>Note: Initial mode is the chip LowPower mode at Sequencer start.|
|_FromIdle_|Controls the Sequencer transition from the**Idle**state on a_T1_interrupt:<br>0: to**Transmit**state<br>1: to**Receive**state|
|_FromTransmit_|Controls the Sequencer transition from the**Transmit**state:<br>0: to**LowPowerSelection**on a_PacketSent_interrupt<br>1: to**Receive**state on a_PacketSent_interrupt|
|_FromReceive_|Controls the Sequencer transition from the**Receive**state:<br>000 and 111: unused<br>001: to**PacketReceived**state on a_PayloadReady_interrupt<br>010: to**LowPowerSelection**on a_PayloadReady_interrupt<br>011: to**PacketReceived**state on a_CrcOk_interrupt. If CRC is wrong (corrupted packet, with CRC on but<br>CrcAutoClearOn is off), the PayloadReady interrupt will drive the sequencer to RxTimeout state.<br>100: to**SequencerOff**state on a_Rssi_interrupt<br>101: to**SequencerOff**state on a_SyncAddress_interrupt<br>110: to**SequencerOff**state on a_PreambleDetect_interrupt<br>Irrespective of this setting, transition to**LowPowerSelection**on a_T2_interrupt|
|_FromRxTimeout_|Controls the state-machine transition from the**Receive**state on a_RxTimeout_interrupt (and on<br>_PayloadReady_if**FromReceive**= 011):<br>00: to**Receive**state via_ReceiveRestart_<br>01: to**Transmit**state<br>10: to**LowPowerSelection**<br>11: to**SequencerOff**state<br>Note: RxTimeout interrupt is a_TimeoutRxRssi_,_TimeoutRxPreamble_or_TimeoutSignalSync_interrupt.|
|_FromPacketReceived_|Controls the state-machine transition from the**PacketReceived**state:<br>000: to**SequencerOff**state<br>001: to**Transmit**on a_FifoEmpty_interrupt<br>010: to**LowPowerSelection**<br>011: to**Receive**via_FS_mode, if frequency was changed<br>100: to**Receive**state (no frequency change)|
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## _4.2.8.3. Timers_
Two timers (Timer1 and Timer2) are also available in order to define periodic sequences. These timers are used to generate interrupts, which can trigger transitions of the Sequencer.
_T1_ interrupt is generated (Timer1Resolution * Timer1Coefficient) after _**T2**_ **interrupt** or _**SequencerStart**_ . command. _T2_ interrupt is generated (Timer2Resolution * Timer2Coefficient) after _**T1**_ **interrupt** .
The timers’ mechanism is summarized on the following diagram.
**==> picture [242 x 116] intentionally omitted <==**
**----- Start of picture text -----**<br>
Sequencer Start<br>T2<br>interrupt<br>Timer2 Timer1<br>T1<br>interrupt<br>**----- End of picture text -----**<br>
_Figure 23. Timer1 and Timer2 Mechanism_
_Note The timer sequence is completed independently of the actual Sequencer state. Thus, both timers need to be on to achieve periodic cycling._
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**RFM95/96/97/98(W)**
## _Table 72 Sequencer Timer Settings_
|**_Variable_**|**Description**|
|---|---|
|Timer1Resolution|Resolution of Timer1<br>00: disabled<br>01: 64 us<br>10: 4.1 ms<br>11: 262 ms|
|Timer2Resolution|Resolution of Timer2<br>00: disabled<br>01: 64 us<br>10: 4.1 ms<br>11: 262 ms|
|Timer1Coefficient|Multiplying coefficient for Timer1|
|Timer2Coefficient|Multiplying coefficient for Timer2|
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**RFM95/96/97/98(W)**
## _4.2.8.4. Sequencer State Machine_
The following graphs summarize every possible transition between each Sequencer state. The Sequencer states are highlighted in grey. The transitions are represented by arrows. The condition activating them is described over the transition arrow. For better readability, the start transitions are separated from the rest of the graph.
Transitory states are highlighted in light grey, and exit states are represented in red. It is also possible to force the Sequencer off by setting the _Stop_ bit in _RegSeqConfig1_ to 1 at any time.
**==> picture [471 x 441] intentionally omitted <==**
**----- Start of picture text -----**<br>
Sequen cer: Start transition s<br>Sequencer Off<br>&<br>—— Initial mode = Sleep or Standby<br>On SequencerStart bit rising edge<br>Start<br>If FromStart = 00 On FifoThreshold<br>if FromStart = 11<br>If FromStart = 01 If FromStart = 10<br>LowPower<br>Selection Receive Transmit<br>© @ @<br>Sequen cer: State mach ine<br>Standby if IdleMode = 0<br>Sleep if IdleMode = 1<br>If LowPowerSelection = 1<br>LowPower If LowPowerSelection = 0<br>Selection ( Mode Initial mode ) Sequencer Off Idle<br>On T1 if FromIdle = 0<br>If FromPacketReceived = 000<br>If FromPacketReceived = 010 On T1 if FromIdle = 1<br>Packet<br>Received<br>On PayloadReady If FromPacketReceived = 100<br>if FromReceive = 010 Via FS mode if FromPacketReceived = 011<br>On PayloadReady if FromReceive = 001<br>On CrcOk if FromReceive = 011<br>On T2<br>On PayloadReady if FromReceive = 011 Receive<br>(CRC failed and CrcAutoClearOn =0)<br>On Rssi if FromReceive = 100<br>On SyncAdress if FromReceive = 101<br>On RxTimeout On Preamble if FromReceive = 110 On PacketSent<br>if FromTransmit = 1 On PacketSent<br>If FromRxTimeout = 10 if FromRxTimeout Via ReceiveRestart= 00 Transmit if FromTransmit = 0<br>RxTimeout If FromRxTimeout = 11 Sequencer Off<br>If FromRxTimeout = 01<br>**----- End of picture text -----**<br>
_Figure 24. Sequencer State Machine_
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**RFM95/96/97/98(W)**
## **4.2.9. Data Processing in FSK/OOK Mode**
## _4.2.9.1. Block Diagram_
Figure below illustrates the RFM95/96/97/98(W) data processing circuit. Its role is to interface the data to/from the modulator/demodulator and the uC access points (SPI and DIO pins). It also controls all the configuration registers.
The circuit contains several control blocks which are described in the following paragraphs.
**==> picture [465 x 174] intentionally omitted <==**
**----- Start of picture text -----**<br>
Tx/Rx me: DIO0DIO1<br>DIO2<br>CONTROL<br>DIO3<br>DIO4<br>DIO5<br>j mm:<br>fo .<br>fo :<br>Data Rx SYNC<br>RECOG.<br>e e wnsbes ae<br>PACKET FIFO SPI<br>HANDLER (+SR)<br>Tx NSS<br>SCK<br>MOSI<br>i on xX MISO<br>**----- End of picture text -----**<br>
Potential datapaths (data operation mode dependant)
## _Figure 25. RFM95/96/97/98(W) Data Processing Conceptual View_
The RFM95/96/97/98(W) implements several data operation modes, each with their own data path through the data processing section. Depending on the data operation mode selected, some control blocks are active whilst others remain disabled.
## _4.2.9.2. Data Operation Modes_
The RFM95/96/97/98(W) has two different data operation modes selectable by the user:
> ° ~~ood~~ Continuous mode: each bit transmitted or received is accessed in real time at the DIO2/DATA pin. This mode may be used if adequate external signal processing is available.
Packet mode (recommended): user only provides/retrieves payload bytes to/from the FIFO. The packet is automatically built with preamble, Sync word, and optional CRC and DC-free encoding schemes The reverse operation is performed in reception. The uC processing overhead is hence significantly reduced compared to Continuous mode. Depending on the optional features activated (CRC, etc) the maximum payload length is limited to 255, 2047 bytes or unlimited.
Each of these data operation modes is fully described in the following sections.
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**RFM95/96/97/98(W)**
## **4.2.10. FIFO**
## **Overview and Shift Register (SR)**
In packet mode of operation, both data to be transmitted and that has been received are stored in a configurable FIFO (First In First Out) device. It is accessed via the SPI interface and provides several interrupts for transfer management.
The FIFO is 1 byte wide hence it only performs byte (parallel) operations, whereas the demodulator functions serially. A shift register is therefore employed to interface the two devices. In transmit mode it takes bytes from the FIFO and outputs them serially (MSB first) at the programmed bit rate to the modulator. Similarly, in Rx the shift register gets bit by bit data from the demodulator and writes them byte by byte to the FIFO. This is illustrated in figure below.
**==> picture [226 x 85] intentionally omitted <==**
**----- Start of picture text -----**<br>
FIFO<br>byte1<br>byte0<br>8<br>Data Tx/Rx<br>SR (8bits)<br>1<br>MSB LSB<br>**----- End of picture text -----**<br>
_Figure 26. FIFO and Shift Register (SR)_
_Note When switching to Sleep mode, the FIFO can only be used once the ModeReady flag is set (quasi immediate from all modes except from Tx)_
The FIFO size is fixed to 64 bytes.
## **Interrupt Sources and Flags**
_FifoEmpty_ : _FifoEmpty_ interrupt source is high when byte 0, i.e. whole FIFO, is empty. Otherwise it is low. Note that when retrieving data from the FIFO, _FifoEmpty_ is updated on NSS falling edge, i.e. when _FifoEmpty_ is updated to low state the currently started read operation must be completed. In other words, _FifoEmpty_ state must be checked after each read operation for a decision on the next one ( _FifoEmpty_ = 0: more byte(s) to read; _FifoEmpty_ = 1: no more byte to read).
_FifoFull_ : _FifoFull_ interrupt source is high when the last FIFO byte, i.e. the whole FIFO, is full. Otherwise it is low.
_FifoOverrunFlag_ : _FifoOverrunFlag_ is set when a new byte is written by the user (in Tx or Standby modes) or the SR (in Rx mode) while the FIFO is already full. Data is lost and the flag should be cleared by writing a 1, note that the FIFO will also be cleared.
_PacketSent_ : _PacketSent_ interrupt source goes high when the SR's last bit has been sent.
_FifoLevel_ : Threshold can be programmed by _FifoThreshold_ in _RegFifoThresh_ . Its behavior is illustrated in figure below.
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**==> picture [349 x 202] intentionally omitted <==**
**----- Start of picture text -----**<br>
FifoLevel<br>1<br>0 B B+1 # of bytes in FIFO<br>**----- End of picture text -----**<br>
_Figure 27. FifoLevel IRQ Source Behavior_
_Notes - FifoLevel interrupt is updated only after a read or write operation on the FIFO. Thus the interrupt cannot be dynamically updated by only changing the FifoThreshold parameter_
- _FifoLevel interrupt is valid as long as FifoFull does not occur. An empty FIFO will restore its normal operation_
## **FIFO Clearing**
Table below summarizes the status of the FIFO when switching between different modes
_Table 73 Status of FIFO when Switching Between Different Modes of the Chip_
|**From**|**To**|**FIFO status**|**Comments**|
|---|---|---|---|
|Stdby|Sleep|Not cleared||
|Sleep|Stdby|Not cleared||
|Stdby/Sleep|Tx|Not cleared|To allow the user to write the FIFO in Stdby/Sleep before Tx|
|Stdby/Sleep|Rx|Cleared||
|Rx|Tx|Cleared||
|Rx|Stdby/Sleep|Not cleared|To allow the user to read FIFO in Stdby/Sleep mode after Rx|
|Tx|Any|Cleared||
## _4.2.10.1. Sync Word Recognition_
## **Overview**
Sync word recognition (also called Pattern recognition) is activated by setting _SyncOn_ in _RegSyncConfig_ . The bit synchronizer must also be activated in Continuous mode (automatically done in Packet mode).
The block behaves like a shift register; it continuously compares the incoming data with its internally programmed Sync word and sets _SyncAddressMatch_ when a match is detected. This is illustrated in Figure 28 below.
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**==> picture [410 x 116] intentionally omitted <==**
**----- Start of picture text -----**<br>
Rx DATA<br>Bit N-x = Bit N-1 = Bit N =<br>(NRZ)<br>Sync_value[x] Sync_value[1] Sync_value[0]<br>ae ee Gee ee ee<br>DCLK<br>SyncAddressMatch<br>**----- End of picture text -----**<br>
## _Figure 28. Sync Word Recognition_
During the comparison of the demodulated data, the first bit received is compared with bit 7 (MSB) of _RegSyncValue1_ and the last bit received is compared with bit 0 (LSB) of the last byte whose address is determined by the length of the Sync word.
When the programmed Sync word is detected the user can assume that this incoming packet is for the node and can be processed accordingly.
_SyncAddressMatch_ is cleared when leaving Rx or FIFO is emptied.
## **Configuration**
Size: Sync word size can be set from 1 to 8 bytes (i.e. 8 to 64 bits) via _SyncSize_ in _RegSyncConfig_ . In Packet mode this field is also used for Sync word generation in Tx mode.
Value: The Sync word value is configured in _SyncValue(63:0)_ . In Packet mode this field is also used for Sync word generation in Tx mode.
_Note SyncValue choices containing 0x00 bytes are not allowed_
## **Packet Handler**
The packet handler is the block used in Packet mode. Its functionality is fully described in section 4.2.13.
## **Control**
The control block configures and controls the full chip's behavior according to the settings programmed in the configuration registers.
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**RFM95/96/97/98(W)**
## **4.2.11. Digital IO Pins Mapping**
Six general purpose IO pins are available on the RFM95/96/97/98(W), and their configuration in Continuous or Packet mode is controlled through _RegDioMapping1_ and _RegDioMapping2._
_Table 74 DIO Mapping, Continuous Mode_
||**DIOxMapping**|**Sleep**|**Standby**|**FSRx/Tx**<br>~~(~~|**Rx**<br>~~(~~|**Tx**|
|---|---|---|---|---|---|---|
|DIO0<br>~~SS~~|00<br>~~SS~~|-<br>~~SS~~|||SyncAddress<br>~~SS~~|TxReady<br>~~SS~~|
||01<br>~~SS~~|-<br>~~SS~~|||Rssi / PreambleDetect<br>~~SS~~|-<br>~~SS~~|
||10<br>~~SS~~|-<br>~~SS~~|||RxReady<br>~~SS~~|TxReady<br>~~SS~~|
||11<br>~~SS~~|-<br>~~SS~~|||||
|DIO1<br>~~SS~~|00<br>~~SS~~|-<br>~~aS~~|||Dclk<br>~~aS~~||
||01<br>~~SS~~|-<br>~~aS~~|||Rssi / PreambleDetect<br>~~aS~~|-<br>~~aS~~|
||10<br>~~SS~~|-<br>~~aS~~|||||
||11<br>~~SS~~|-<br>~~aS~~|||||
|DIO2<br>~~**E**~~<br>~~|.~~|00<br>~~**E**~~|-<br>~~**E**SS~~|||Data<br>~~SS~~||
||01<br>~~**E**~~|-<br>~~**E**SS~~|||Data<br>~~SS~~||
||10<br>~~**E**~~|-<br>~~**E**SS~~|||Data<br>~~SS~~||
||11<br>~~**E**~~|-<br>~~**E**SS~~|||Data<br>~~SS~~||
|DIO3<br>~~**E**~~<br>~~|.~~|00<br>~~**E**~~<br>~~aSsSSSSSSS==~~|-<br>~~**E**SS~~<br>~~aSsSSSSSSS==~~|||Timeout<br>~~SS~~<br>~~aSsSSSSSSS==~~|-<br>~~SS~~<br>~~aSsSSSSSSS==~~|
||01<br>~~**E**~~<br>~~aSsSSSSSSS==~~|-<br>~~**E**SS~~<br>~~aSsSSSSSSS==~~|||Rssi / PreambleDetect<br>~~SS~~<br>~~aSsSSSSSSS==~~|-<br>~~SS~~<br>~~aSsSSSSSSS==~~|
||10<br>~~**E**~~<br>~~aSsSSSSSSS==~~|-<br>~~**E**SS~~<br>~~aSsSSSSSSS==~~|||||
||11<br>~~**E**~~<br>~~aSsSSSSSSS==~~|-<br>~~**E**SS~~<br>~~aSsSSSSSSS==~~|TempChange / LowBat<br>TempChange / LowBat<br>~~SS~~<br>~~aSsSSSSSSS==~~||||
|DIO4<br>~~**E**~~<br>~~|.~~<br>~~SS~~|00<br>~~**E**~~<br>~~aSsSSSSSSS==~~<br>~~SS~~|-<br>~~**E**SS~~<br>~~aSsSSSSSSS==~~||TempChange /LowBat<br>~~SS~~<br>~~aSsSSSSSSS==~~|||
||01<br>~~**E**~~<br>~~SS~~|-<br>~~**E**SS~~||PllLock<br>~~SS~~|||
||10<br>~~SS~~|-|||TimeOut|-|
||11<br>~~SS~~|-|ModeReady<br>ModeReady||||
|DIO5<br>~~SS~~<br>~~SS~~|00<br>~~SS~~<br>~~SS~~|ClkOut if RC<br>~~SS~~|ClkOut<br>ClkOut<br>~~SS~~||||
||01<br>~~SS~~|-<br>~~SS~~||PllLock<br>~~SS~~|||
||10<br>~~SS~~|-<br>~~SS~~|||Rssi / PreambleDetect<br>~~SS~~|-<br>~~SS~~|
||11<br>~~SS~~|-<br>~~SS~~|ModeReady<br>ModeReady<br>~~SS~~||||
_Table 75 DIO Mapping, Packet Mode_
||**DIOxMapping**<br>~~es~~|**Sleep**|**Standby**|**FSRx/Tx**|**Rx**|**Tx**|
|---|---|---|---|---|---|---|
|DIO0<br>~~sss~~|00<br>~~es~~<br>~~sss~~|-<br>~~sss~~|||PayloadReady<br>~~sss~~|PacketSent<br>~~sss~~|
||01<br>~~sss~~|-<br>~~sss~~|||CrcOk<br>~~sss~~|-<br>~~sss~~|
||10<br>~~sss~~|-<br>~~sss~~|||||
||11<br>~~sss~~|-<br>~~sss~~|TempChange / LowBat<br>TempChange / LowBat<br>~~sss~~||||
|DIO1<br>~~2~~|00<br>~~=~~|FifoLevel<br>FifoLevel<br>FifoLevel<br>~~=~~|||||
||01<br>~~=~~|FifoEmpty<br>FifoEmpty<br>FifoEmpty<br>~~=~~|||||
||10<br>~~=~~|FifoFull<br>FifoFull<br>FifoFull<br>~~=~~|||||
||11<br>~~=~~|-<br>~~=~~|||||
|DIO2<br>~~—ELLEEE—QS-S—-=~~|00<br>~~—ELLEEE—QS-S—-=~~|FifoFull<br>FifoFull<br>FifoFull<br>~~—ELLEEE—QS-S—-=~~|||||
||01<br>~~—ELLEEE—QS-S—-=~~|-<br>~~—ELLEEE—QS-S—-=~~|||RxReady<br>~~—ELLEEE—QS-S—-=~~|-<br>~~—ELLEEE—QS-S—-=~~|
||10<br>~~—ELLEEE—QS-S—-=~~|FifoFull<br>~~—ELLEEE—QS-S—-=~~|||TimeOut<br>~~—ELLEEE—QS-S—-=~~|FifoFull<br>~~—ELLEEE—QS-S—-=~~|
||11<br>~~—ELLEEE—QS-S—-=~~|FifoFull<br>~~—ELLEEE—QS-S—-=~~|||SyncAddress<br>~~—ELLEEE—QS-S—-=~~|FifoFull<br>~~—ELLEEE—QS-S—-=~~|
|DIO3<br>~~ee~~|00<br>~~ee~~|FifoEmpty<br>FifoEmpty<br>FifoEmpty<br>~~ee~~|||||
||01<br>~~ee~~|-<br>~~ee~~||||TxReady<br>~~ee~~|
||10<br>~~ee~~|FifoEmpty<br>FifoEmpty<br>FifoEmpty<br>~~ee~~|||||
||11<br>~~ee~~|FifoEmpty<br>FifoEmpty<br>FifoEmpty<br>~~ee~~|||||
|DIO4<br>~~eS~~|00<br>~~eS~~|-<br>~~eS~~|TempChange / LowBat<br>TempChange / LowBat<br>~~eS~~||||
||01<br>~~eS~~|-<br>~~eS~~||PllLock<br>~~eS~~|||
||10<br>~~eS~~|-<br>~~eS~~|||TimeOut<br>~~eS~~|-<br>~~eS~~|
||11<br>~~eS~~|-<br>~~eS~~|||Rssi / PreambleDetect<br>~~eS~~|-<br>~~eS~~|
|DIO5|00<br>~~————————————————————~~|ClkOut if RC<br>~~————————————————————~~|ClkOut<br>~~————————————————————~~||ClkOut<br>~~————————————————————~~||
||01<br>~~————————————————————~~|-<br>~~————————————————————~~||PllLock<br>~~————————————————————~~|||
||10<br>~~————————————————————~~|-<br>~~————————————————————~~|||Data<br>~~————————————————————~~||
||11<br>~~————————————————————~~|-<br>~~————————————————————~~|ModeReady<br>ModeReady<br>~~————————————————————~~||||
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## **4.2.12. Continuous Mode**
## _4.2.12.1. General Description_
**==> picture [541 x 269] intentionally omitted <==**
**----- Start of picture text -----**<br>
As illustrated in Figure 29, in Continuous mode the NRZ data to (from) the (de)modulator is directly accessed by the uC on<br>the bidirectional DIO2/DATA pin. The FIFO and packet handler are thus inactive.<br>~<br>\ Tx/Rx DIO0<br>\me: DIO1/DCLK<br>DIO2/DATA<br>CONTROL<br>x] DIO3<br>ma DIO4<br>| DIO5<br>Data Rx<br>SYNC<br>; RECOG.<br>q<br>SPI<br>f ; NSS<br>SCK<br>3 MOSI<br>MISO<br>**----- End of picture text -----**<br>
_Figure 29. Continuous Mode Conceptual View_
## _4.2.12.2. Tx Processing_
In Tx mode, a synchronous data clock for an external uC is provided on DIO1/DCLK pin. Clock timing with respect to the data is illustrated in Figure 30. DATA is internally sampled on the rising edge of DCLK so the uC can change logic state anytime outside the grayed out setup/hold zone.
**==> picture [202 x 91] intentionally omitted <==**
**----- Start of picture text -----**<br>
T_DATA T_DATA<br>DATA<br>(NRZ)<br>DCLK<br>**----- End of picture text -----**<br>
_Figure 30. Tx Processing in Continuous Mode_
_Note the use of DCLK is required when the modulation shaping is enabled (see section 3.4.5)._
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**RFM95/96/97/98(W)**
## _4.2.12.3. Rx Processing_
If the bit synchronizer is disabled, the raw demodulator output is made directly available on DATA pin and no DCLK signal is provided.
Conversely, if the bit synchronizer is enabled, synchronous cleaned data and clock are made available respectively on DIO2/DATA and DIO1/DCLK pins. DATA is sampled on the rising edge of DCLK and updated on the falling edge as illustrated below.
**==> picture [66 x 12] intentionally omitted <==**
**----- Start of picture text -----**<br>
DATA (NRZ)<br>**----- End of picture text -----**<br>
**==> picture [33 x 9] intentionally omitted <==**
**----- Start of picture text -----**<br>
DCLK<br>**----- End of picture text -----**<br>
_Figure 31. Rx Processing in Continuous Mode_
_Note In Continuous mode it is always recommended to enable the bit synchronizer to clean the DATA signal even if the DCLK signal is not used by the uC (bit synchronizer is automatically enabled in Packet mode)._
## **4.2.13. Packet Mode**
## _4.2.13.1. General Description_
In Packet mode the NRZ data to (from) the (de)modulator is not directly accessed by the uC but stored in the FIFO and accessed via the SPI interface.
In addition, the RFM95/96/97/98(W) packet handler performs several packet oriented tasks such as Preamble and Sync word generation, CRC calculation/check, whitening/dewhitening of data, Manchester encoding/decoding, address filtering, etc. This simplifies software and reduces uC overhead by performing these repetitive tasks within the RF chip itself.
Another important feature is ability to fill and empty the FIFO in Sleep/Stdby mode, ensuring optimum power consumption and adding more flexibility for the software.
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**RFM95/96/97/98(W)**
**==> picture [462 x 200] intentionally omitted <==**
**----- Start of picture text -----**<br>
54 DIO0<br>a: DIO1<br>a. DIO2<br>CONTROL<br>1 ae. DIO3<br>| ac. DIO4<br>DIO5<br>/ | [as]<br>i<br>/<br>Data Rx<br>SYNC<br>RECOG.<br>PACKET FIFO<br>SPI<br>HANDLER (+SR)<br>NSS<br>Tx<br>SCK<br>MOSI<br>MISO<br>**----- End of picture text -----**<br>
_Figure 32. Packet Mode Conceptual View_
_Note The Bit Synchronizer is automatically enabled in Packet mode._
## _4.2.13.2. Packet Format_
## **Fixed Length Packet Format**
Fixed length packet format is selected when bit _PacketFormat_ is set to 0 and _PayloadLength_ is set to any value greater than 0.
In applications where the packet length is fixed in advance, this mode of operation may be of interest to minimize RF overhead (no length byte field is required). All nodes, whether Tx only, Rx only, or Tx/Rx should be programmed with the same packet length value.
The length of the payload is limited to 2047 bytes.
The length programmed in _PayloadLength_ relates only to the payload which includes the message and the optional address byte. In this mode, the payload must contain at least one byte, i.e. address or message byte.
An illustration of a fixed length packet is shown below. It contains the following fields:
- Preamble (1010...)
- Sync word (Network ID)
- Optional Address byte (Node ID)
- Message data
- Optional 2-bytes CRC checksum
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**==> picture [292 x 152] intentionally omitted <==**
**----- Start of picture text -----**<br>
Optional DC free data coding<br>CRC checksum calculation<br>Preamble Sync Word Address Message CRC<br>0 to 65536 bytes 0 to 8 bytes byte Up to 2047 bytes 2-bytes<br>Payload<br>(min 1 byte)<br>Fields added by the packet handler in Tx and processed and removed in Rx<br>Optional User provided fields which are part of the payload<br>Message part of the payload<br>**----- End of picture text -----**<br>
## _Figure 33. Fixed Length Packet Format_
## **Variable Length Packet Format**
Variable length packet format is selected when bit _PacketFormat_ is set to 1.
This mode is useful in applications where the length of the packet is not known in advance and can vary over time. It is then necessary for the transmitter to send the length information together with each packet in order for the receiver to operate properly.
In this mode the length of the payload, indicated by the length byte, is given by the first byte of the FIFO and is limited to 255 bytes. Note that the length byte itself is not included in its calculation. In this mode, the payload must contain at least 2 bytes, i.e. length + address or message byte.
An illustration of a variable length packet is shown below. It contains the following fields:
Preamble (1010...)
Sync word (Network ID)
Length byte
Optional Address byte (Node ID)
Message data
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Optional 2-bytes CRC checksum
**==> picture [334 x 152] intentionally omitted <==**
**----- Start of picture text -----**<br>
Optional DC free data coding<br>CRC checksum calculation<br>Preamble Sync Word Length Address Message CRC<br>0 to 65536 bytes 0 to 8 bytes byte byte Up to 255 bytes 2-bytes<br>Payload<br>(min 2 bytes)<br>Fields added by the packet handler in Tx and processed and removed in Rx<br>Optional User provided fields which are part of the payload<br>Message part of the payload<br>**----- End of picture text -----**<br>
_Figure 34. Variable Length Packet Format_
## **Unlimited Length Packet Format**
Unlimited length packet format is selected when bit _PacketFormat_ is set to 0 and _PayloadLength_ is set to 0. The user can then transmit and receive packet of arbitrary length and _PayloadLength_ register is not used in Tx/Rx modes for counting the length of the bytes transmitted/received.
In Tx the data is transmitted depending on the _TxStartCondition_ bit. On the Rx side the data processing features like Address filtering, Manchester encoding and data whitening are not available if the sync pattern length is set to zero ( _SyncOn = 0_ ). The filling of the FIFO in this case can be controlled by the bit _FifoFillCondition_ . The CRC detection in Rx is also not supported in this mode of the packet handler, however CRC generation in Tx is operational. The interrupts like _CrcOk_ & _PayloadReady_ are not available either.
An unlimited length packet shown below is made up of the following fields:
Preamble (1010...).
Sync word (Network ID).
Optional Address byte (Node ID).
Message data
Optional 2-bytes CRC checksum (Tx only)
**==> picture [214 x 72] intentionally omitted <==**
**----- Start of picture text -----**<br>
DC free Data encoding<br>Preamble<br>Sync Word Address Message<br>0 to 65535<br>bytes 0 to 8 bytes byte unlimited length<br>Payload<br>**----- End of picture text -----**<br>
Fields added by the packet handler in Tx and processed and removed in Rx Message part of the payload
Optional User provided fields which are part of the payload
_Figure 35. Unlimited Length Packet Format_
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## _4.2.13.3. Tx Processing_
In Tx mode the packet handler dynamically builds the packet by performing the following operations on the payload available in the FIFO:
Add a programmable number of preamble bytes
Add a programmable Sync word
Optionally calculating CRC over complete payload field (optional length byte + optional address byte + message) and appending the 2 bytes checksum.
Optional DC-free encoding of the data (Manchester or whitening)
Only the payload (including optional address and length fields) is required to be provided by the user in the FIFO.
The transmission of packet data is initiated by the Packet Handler only if the chip is in Tx mode and the transmission condition defined by _TxStartCondition_ is fulfilled. If transmission condition is not fulfilled then the packet handler transmits a preamble sequence until the condition is met. This happens only if the preamble length /= 0, otherwise it transmits a zero or one until the condition is met to transmit the packet data.
The transmission condition itself is defined as:
- if _TxStartCondition_ = 1, the packet handler waits until the first byte is written into the FIFO, then it starts sending the preamble followed by the sync word and user payload
If _TxStartCondition_ = 0, the packet handler waits until the number of bytes written in the FIFO is equal to the number defined in _RegFifoThresh_ + 1
If the condition for transmission was already fulfilled i.e. the FIFO was filled in Sleep/Stdby then the transmission of packet starts immediately on enabling Tx
## _4.2.13.4. Rx Processing_
In Rx mode the packet handler extracts the user payload to the FIFO by performing the following operations:
- Receiving the preamble and stripping it off
Detecting the Sync word and stripping it off
- Optional DC-free decoding of data
- Optionally checking the address byte
- Optionally checking CRC and reflecting the result on _CrcOk._
Only the payload (including optional address and length fields) is made available in the FIFO.
When the Rx mode is enabled the demodulator receives the preamble followed by the detection of sync word. If fixed length packet format is enabled then the number of bytes received as the payload is given by the _PayloadLength_ parameter.
In variable length mode the first byte received after the sync word is interpreted as the length of the received packet. The internal length counter is initialized to this received length. The _PayloadLength_ register is set to a value which is greater than the maximum expected length of the received packet. If the received length is greater than the maximum length stored in _PayloadLength_ register the packet is discarded otherwise the complete packet is received.
If the address check is enabled then the second byte received in case of variable length and first byte in case of fixed length is the address byte. If the address matches to the one in the _NodeAddress_ field, reception of the data continues otherwise it's stopped. The CRC check is performed if _CrcOn_ = 1 and the result is available in _CrcOk_ indicating that the
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CRC was successful. An interrupt ( _PayloadReady_ ) is also generated on DIO0 as soon as the payload is available in the FIFO. The payload available in the FIFO can also be read in Sleep/Standby mode.
If the CRC fails the _PayloadReady_ interrupt is not generated and the FIFO is cleared. This function can be overridden by setting _CrcAutoClearOff_ = 1, forcing the availability of _PayloadReady_ interrupt and the payload in the FIFO even if the CRC fails.
## _4.2.13.5. Handling Large Packets_
When _PayloadLength_ exceeds FIFO size (64 bytes) whether in fixed, variable or unlimited length packet format, in addition to _PacketSent_ in Tx and _PayloadReady_ or _CrcOk_ in Rx, the FIFO interrupts/flags can be used as described below:
## For Tx:
FIFO can be prefilled in Sleep/Standby but must be refilled “on-the-fly” during Tx with the rest of the payload.
1) Pre-fill FIFO (in Sleep/Standby first or directly in Tx mode) until _FifoThreshold_ or _FifoFull_ is set
- 2) In Tx, wait for _FifoThreshold_ or _FifoEmpty_ to be set (i.e. FIFO is nearly empty)
- 3) Write bytes into the FIFO until _FifoThreshold_ or _FifoFull_ is set.
- 4) Continue to step 2 until the entire message has been written to the FIFO ( _PacketSent_ will fire when the last bit of the packet has been sent).
## For Rx:
FIFO must be unfilled “on-the-fly” during Rx to prevent FIFO overrun.
1) Start reading bytes from the FIFO when _FifoEmpty_ is cleared or _FifoThreshold_ becomes set.
2) Suspend reading from the FIFO if _FifoEmpty_ fires before all bytes of the message have been read
3) Continue to step 1 until _PayloadReady_ or _CrcOk_ fires
- 4) Read all remaining bytes from the FIFO either in Rx or Sleep/Standby mode
## _4.2.13.6. Packet Filtering_
The RFM95/96/97/98(W) packet handler offers several mechanisms for packet filtering, ensuring that only useful packets are made available to the uC, reducing significantly system power consumption and software complexity.
## **Sync Word Based**
Sync word filtering/recognition is used for identifying the start of the payload and also for network identification. As previously described, the Sync word recognition block is configured (size, value) in _RegSyncConfig_ and _RegSyncValue(i)_ registers. This information is used, both for appending Sync word in Tx, and filtering packets in Rx.
Every received packet which does not start with this locally configured Sync word is automatically discarded and no interrupt is generated.
When the Sync word is detected, payload reception automatically starts and _SyncAddressMatch_ is asserted.
_Note Sync Word values containing 0x00 byte(s) are forbidden_
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## **Address Based**
Address filtering can be enabled via the _AddressFiltering_ bits. It adds another level of filtering, above Sync word (i.e. Sync must match first), typically useful in a multi-node networks where a network ID is shared between all nodes (Sync word) and each node has its own ID (address).
Two address based filtering options are available:
_AddressFiltering = 01_ : Received address field is compared with internal register _NodeAddress_ . If they match then the packet is accepted and processed, otherwise it is discarded.
_AddressFiltering = 10_ : Received address field is compared with internal registers _NodeAddress_ and _BroadcastAddress_ . If either is a match, the received packet is accepted and processed, otherwise it is discarded. This additional check with a constant is useful for implementing broadcast in a multi-node networks
Please note that the received address byte, as part of the payload, is not stripped off the packet and is made available in the FIFO. In addition, _NodeAddress_ and _AddressFiltering_ only apply to Rx. On Tx side, if address filtering is expected, the address byte should simply be put into the FIFO like any other byte of the payload.
As address filtering requires a Sync word match, both features share the same interrupt flag _SyncAddressMatch_ .
## **Length Based**
In variable length Packet mode, _PayloadLength_ must be programmed with the maximum payload length permitted. If received length byte is smaller than this maximum then the packet is accepted and processed, otherwise it is discarded.
Please note that the received length byte, as part of the payload, is not stripped off the packet and is made available in the FIFO.
To disable this function the user should set the value of the _PayloadLength_ to 2047.
## **CRC Based**
The CRC check is enabled by setting bit _CrcOn_ in _RegPacketConfig1_ . It is used for checking the integrity of the message.
On Tx side a two byte CRC checksum is calculated on the payload part of the packet and appended to the end of the message
On Rx side the checksum is calculated on the received payload and compared with the two checksum bytes received. The result of the comparison is stored in bit _CrcOk._
By default, if the CRC check fails then the FIFO is automatically cleared and no interrupt is generated. This filtering function can be disabled via _CrcAutoClearOff_ bit and in this case, even if CRC fails, the FIFO is not cleared and only _PayloadReady_ interrupt goes high. Please note that in both cases, the two CRC checksum bytes are stripped off by the packet handler and only the payload is made available in the FIFO. Two CRC implementations are selected with bit _CrcWhiteningType_ .
## _Table 76 CRC Description_
|_Table 76 CRC Description_|||||
|---|---|---|---|---|
|**Crc Type**|**_CrcWhiteningType_**|**Polynomial**|**Seed Value**|**Complemented**|
|**CCITT**|0 (default)|X16+ X12+ X5+ 1|0x1D0F|Yes|
|**IBM**|1|X16+ X15+ X2+ 1|0xFFFF|No|
A C code implementation of each CRC type is proposed in Application Section 7.
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## _4.2.13.7. DC-Free Data Mechanisms_
The payload to be transmitted may contain long sequences of 1's and 0's, which introduces a DC bias in the transmitted signal. The radio signal thus produced has a non uniform power distribution over the occupied channel bandwidth. It also introduces data dependencies in the normal operation of the demodulator. Thus it is useful if the transmitted data is random and DC free.
For such purposes, two techniques are made available in the packet handler: Manchester encoding and data whitening.
## _Note Only one of the two methods can be enabled at a time._
## **Manchester Encoding**
Manchester encoding/decoding is enabled if _DcFree = 01_ and can only be used in Packet mode.
The NRZ data is converted to Manchester code by coding '1' as “10” and '0' as “01”.
In this case, the maximum chip rate is the maximum bit rate given in the specifications section and the actual bit rate is half the chip rate.
Manchester encoding and decoding is only applied to the payload and CRC checksum while preamble and Sync word are kept NRZ. However, the chip rate from preamble to CRC is the same and defined by _BitRate_ in _RegBitRate_ (Chip Rate = Bit Rate NRZ = 2 x Bit Rate Manchester).
Manchester encoding/decoding is thus made transparent for the user, who still provides/retrieves NRZ data to/from the FIFO.
**==> picture [545 x 151] intentionally omitted <==**
**----- Start of picture text -----**<br>
1/BR ...Sync 1/BR Payload...<br>a RF chips @ BR ... 1 1 1 0 1 0 0 1 0 0 1 0 1 1 0 1 0 ...<br>User/NRZ bits t<br>... 1 1 1 0 1 0 0 1 0 0 1 0 1 1 0 1 0<br>eee Manchester OFF ...<br>User/NRZ bits<br>... 1 1 1 0 1 0 0 1 0 0 1 1<br>eee Manchester ON ee eee ...<br>Figure 36. Manchester Encoding/Decoding<br>Data Whitening<br>Another technique called whitening or scrambling is widely used for randomizing the user data before radio transmission.<br>The data is whitened using a random sequence on the Tx side and de-whitened on the Rx side using the same sequence.<br>Comparing to Manchester technique it has the advantage of keeping NRZ data rate i.e. actual bit rate is not halved.<br>**----- End of picture text -----**<br>
The whitening/de-whitening process is enabled if _DcFree = 10_ . A 9-bit LFSR is used to generate a random sequence. The payload and 2-byte CRC checksum is then XORed with this random sequence as shown below. The data is de-whitened on the receiver side by XORing with the same random sequence.
Payload whitening/de-whitening is thus made transparent for the user, who still provides/retrieves NRZ data to/from the FIFO.
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**==> picture [443 x 147] intentionally omitted <==**
**----- Start of picture text -----**<br>
LFS R P o ly nom ia l =X [9 ] + X [5 ] + 1<br>X [8 ] X [7 ] X [6 ] X [5 ] X [4 ] X [3 ] X [2 ] X [1 ] X [0]<br>Tra n s m it d a ta W h iten ed da ta<br>**----- End of picture text -----**<br>
_Figure 37. Data Whitening Polynomial_
## _4.2.13.8. Beacon Tx Mode_
In some short range wireless network topologies a repetitive message, also known as beacon, is transmitted periodically by a transmitter. The Beacon Tx mode allows for the re-transmission of the same packet without having to fill the FIFO multiple times with the same data.
When _BeaconOn_ in _RegPacketConfig2_ is set to 1, the FIFO can be filled only once in Sleep or Stdby mode with the required payload. After a first transmission, _FifoEmpty_ will go high as usual, but the FIFO content will be restored when the chip exits Transmit mode. _FifoEmpty_ , _FifoFull_ and _FifoLevel_ flags are also restored.
This feature is only available in Fixed packet format, with the Payload Length smaller than the FIFO size. The control of the chip modes (Tx-Sleep-Tx....) can either be undertaken by the microcontroller, or be automated in the Top Sequencer. See example in section 4.2.13.8.
The Beacon Tx mode is exited by setting _BeaconOn_ to 0, and clearing the FIFO by setting _FifoOverrun_ to 1.
## **4.2.14. io-homecontrol[® ] Compatibility Mode**
The RFM95/96/97/98(W) features a io-homecontrol **[® ]** compatibility mode. Please contact your local Hope RF representative for details on its implementation.
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## **4.3. SPI Interface**
The SPI interface gives access to the configuration register via a synchronous full-duplex protocol corresponding to CPOL = 0 and CPHA = 0 in Motorola/Freescale nomenclature. Only the slave side is implemented.
Three access modes to the registers are provided:
SINGLE access: an address byte followed by a data byte is sent for a write access whereas an address byte is sent and a read byte is received for the read access. The NSS pin goes low at the beginning of the frame and goes high after the data byte.
BURST access: the address byte is followed by several data bytes. The address is automatically incremented internally between each data byte. This mode is available for both read and write accesses. The NSS pin goes low at the beginning of the frame and stay low between each byte. It goes high only after the last byte transfer.
FIFO access: if the address byte corresponds to the address of the FIFO, then succeeding data byte will address the FIFO. The address is not automatically incremented but is memorized and does not need to be sent between each data byte. The NSS pin goes low at the beginning of the frame and stay low between each byte. It goes high only after the last byte transfer.
The figure below shows a typical SPI single access to a register.
## _Figure 38. SPI Timing Diagram (single access)_
MOSI is generated by the master on the falling edge of SCK and is sampled by the slave (i.e. this SPI interface) on the rising edge of SCK. MISO is generated by the slave on the falling edge of SCK.
A transfer is always started by the NSS pin going low. MISO is high impedance when NSS is high.
The first byte is the address byte. It is comprises:
A wnr bit, which is 1 for write access and 0 for read access.
Then 7 bits of address, MSB first.
The second byte is a data byte, either sent on MOSI by the master in case of a write access or received by the master on MISO in case of read access. The data byte is transmitted MSB first.
Proceeding bytes may be sent on MOSI (for write access) or received on MISO (for read access) without a rising NSS edge and re-sending the address. In FIFO mode, if the address was the FIFO address then the bytes will be written / read at the FIFO address. In Burst mode, if the address was not the FIFO address, then it is automatically incremented for each new byte received.
The frame ends when NSS goes high. The next frame must start with an address byte. The SINGLE access mode is therefore a special case of FIFO / BURST mode with only 1 data byte transferred.
During the write access, the byte transferred from the slave to the master on the MISO line is the value of the written register before the write operation.
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## **5. RFM95/96/97/98(W) Analog & RF Frontend Electronics**
## **5.1. Power Supply Strategy**
The RFM95/96/97/98(W) employs an internal voltage regulation scheme which provides stable operating voltage, and hence device characteristics, over the full industrial temperature and operating voltage range of operation. This includes up to
+17 dBm of RF output power which is maintained from 1.8 V to 3.7 V and +20 dBm from 2.4 V to 3.7 V.
The RFM95/96/97/98(W) can be powered from any low-noise voltage source via pins VBAT_ANA, VBAT_RF and VBAT_DIG. Decoupling capacitors should be connected, as suggested in the reference design of the applications section of this document, on VR_PA, VR_DIG and VR_ANA pins to ensure correct operation of the built-in voltage regulators.
## **5.2. Low Battery Detector**
A low battery detector is also included allowing the generation of an interrupt signal in response to the supply voltage dropping below a programmable threshold that is adjustable through the register _RegLowBat_ . The interrupt signal can be mapped to any of the DIO pins by programming _RegDioMapping_ .
## **5.3. Frequency Synthesis**
## **5.3.1. Crystal Oscillator**
The crystal oscillator is the main timing reference of the RFM95/96/97/98(W). It is used as the reference for the PLL’s frequency synthesis and as the clock signal for all digital processing.
The crystal oscillator startup time, TS_OSC, depends on the electrical characteristics of the crystal reference used, for more information on the electrical specification of the crystal see Section 2.3. The crystal connects to the Pierce oscillator on pins XTA and XTB. The RFM95/96/97/98(W) optimizes the startup time and automatically triggers the PLL when the oscillator signal is stable.
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## **5.3.2. CLKOUT Output**
The reference frequency, or a fraction of it, can be provided on DIO5 (pin 13) by modifying bits _ClkOut_ in _RegDioMapping2_ . Two typical applications of the CLKOUT output include:
To provide a clock output for a companion processor, thus saving the cost of an additional oscillator. CLKOUT can be made available in any operation mode except Sleep mode and is automatically enabled at power on reset.
To provide an oscillator reference output. Measurement of the CLKOUT signal enables simple software trimming of the initial crystal tolerance.
_Note To minimize the current consumption of the RFM95/96/97/98(W), please ensure that the CLKOUT signal is disabled when not required._
## **5.3.3. PLL**
The local oscillator of the RFM95/96/97/98(W) is derived from two almost identical fractional-N PLLs that are referenced to the crystal oscillator circuit. Both PLLs feature a programmable bandwidth setting where one of four discrete preset bandwidths may be accessed.
The RFM95/96/97/98(W) PLL uses a 19-bit sigma-delta modulator whose frequency resolution, constant over the whole frequency range, is given by:
**==> picture [66 x 23] intentionally omitted <==**
The carrier frequency is programmed through _RegFrf_ , split across addresses 0x06 to 0x08:
**==> picture [100 x 11] intentionally omitted <==**
_Note The Frf setting is split across 3 bytes. A change in the center frequency will only be taken into account when the least significant byte FrfLsb in RegFrfLsb is written. This allows the potential for user generation of m-ary FSK at very low bit rates. This is possible where frequency modulation is achieved by direct programming of the programmed RF centre frequency. To enable this functionality set the FastHopOn bit of register RegPllHop._
## **5.3.4. RC Oscillator**
All timing operations in the low-power Sleep state of the Top Level Sequencer rely on the accuracy of the internal lowpower RC oscillator. This oscillator is automatically calibrated at the device power-up not requiring any user input.
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## **5.4. Transmitter Description**
The transmitter of RFM95/96/97/98(W) comprises the frequency synthesizer, modulator (both LoRa[TM ] and FSK/OOK) and power amplifier blocks, together with the DC biasing and ramping functionality that is provided through the VR_PA block.
## **5.4.1. Architecture Description**
The architecture of the RF front end is shown in the following diagram.
Figure 40. RF Front-end Architecture Shows the Internal PA Configuration.
## **5.4.2. RF Power Amplifiers**
PA_HF and PA_LF are high efficiency amplifiers capable of yielding RF power programmable in 1 dB steps from -4 to +14dBm directly into a 50 ohm load with low current consumption. PA_LF covers the lower bands (up to 525 MHz), whilst PA_HF will cover the upper bands (from 860 MHz). The output power is sensitive to the power supply voltage, and typically their performance is expressed at 3.3V.
PA_HP (High Power), connected to the PA_BOOST pin, covers all frequency bands that the chip addresses. It permits continuous operation at up to +17 dBm and duty cycled operation at up to +20dBm. For full details of operation at +20dBm please consult Section 5.4.3
## _Table 77 Power Amplifier Mode Selection Truth Table_
|**_PaSelect_**|**Mode**|**Power Range**|**Pout Formula**|
|---|---|---|---|
|0|PA_HF or PA_LF on RFO_HF or RFO_LF|-4 to +15dBm|Pout=Pmax-(15-OutputPower)<br>Pmax=10.8+0.6*MaxPower [dBm]|
|1|PA_HP on PA_BOOST, any frequency|+2 to +17dBm|Pout=17-(15-OutputPower) [dBm]|
_Notes - For +20 dBm restrictions on operation please consult the following section._
_- To ensure correct operation at the highest power levels ensure that the current limiter OcpTrim is adjusted to permit delivery of the requisite supply current._
- _If the PA_BOOST pin is not used it may be left floating._
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## **5.4.3. High Power +20 dBm Operation**
The RFM95/96/97/98(W) have a high power +20 dBm capability on PA_BOOST pin, with the following settings:
## _Table 78 High Power Settings_
|**_Register_**|**_Address_**|**_Value for_**<br>**_High Power_**|**_Default value_**<br>**_PA_HF/LF or_**<br>**_+17dBm_**|**Description**|
|---|---|---|---|---|
|_RegPaDac_|0x4d|0x87|0x84|Set Pmax to +20dBm for PA_HP|
_Notes - High Power settings must be turned off when using PA_LF or PA_HF_
_- The Over Current Protection limit should be adapted to the actual power level, in RegOcp_
Specific Absolute Maximum Ratings and Operating Range restrictions apply to the +20 dBm operation. They are listed in Table 79 and Table 80.
## _Table 79 Operating Range, +20dBm Operation_
|**Symbol**|**Description**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|DC_20dBm|Duty Cycle of transmission at +20 dBm output|-|1|%|
|VSWR_20dBm|Maximum VSWR at antenna port, +20 dBm output|-|3:1|-|
## _Table 80 Operating Range, +20dBm Operation_
|**Symbol**|**Description**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|VDDop_20dBm|Supply voltage, +20 dBm output|2.4|3.7|V|
The duty cycle of transmission at +20 dBm is limited to 1%, with a maximum VSWR of 3:1 at antenna port, over the standard operating range [-40;+85°C]. For any other operating condition, contact your Hope RF representative.
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**RFM95/96/97/98(W)**
## **5.4.4. Over Current Protection**
The power amplifiers of RFM95/96/97/98(W) are protected against current over supply in adverse RF load conditions by the over current protection block. This has the added benefit of protecting battery chemistries with limited peak current capability and minimising worst case PA consumption in battery life calculation. The current limiter value is controlled by the _OcpTrim_ bits in _RegOcp_ , and is calculated according to the following formulae:
## _Table 81 Trimming of the OCP Current_
|**_OcpTrim_**|**IMAX**|**Imax Formula**|
|---|---|---|
|0 to 15|45 to 120 mA|45 + 5*_OcpTrim_[mA]|
|16 to 27|130 to 240 mA|-30 + 10*_OcpTrim_[mA]|
|27+|240 mA|_240 mA_|
_Note Imax sets a limit on the current drain of the Power Amplifier only, hence the maximum current drain of the_ RFM96/ 77/78 _is equal to Imax + IFS_ .
## **5.5. Receiver Description**
## **5.5.1. Overview**
The RFM95/96/97/98(W) features a digital receiver with the analog to digital conversion process being performed directly following the LNA-Mixers block. In addition to the LoRa[TM ] modulation scheme the low-IF receiver is able to demodulate ASK, OOK, (G)FSK and (G)MSK modulation. All filtering, demodulation, gain control, synchronization and packet handling is performed digitally allowing a high degree of programmable flexibility. The receiver also has automatic gain calibration, this improves the precision of RSSI measurement and enhances image rejection.
## **5.5.2. Receiver Enabled and Receiver Active States**
In the receiver operating mode two states of functionality are defined. Upon initial transition to receiver operating mode the receiver is in the ‘receiver-enabled’ state. In this state the receiver awaits for either the user defined valid preamble or RSSI detection criterion to be fulfilled. Once met the receiver enters ‘receiver-active’ state. In this second state the received signal is processed by the packet engine and top level sequencer. For a complete description of the digital functions of the RFM95/96/97/98(W) receiver please see Section 4 of the datasheet.
## **5.5.3. Automatic Gain Control In FSK/OOK Mode**
The AGC feature allows receiver to handle a wide Rx input dynamic range from the sensitivity level up to maximum input level of 0dBm or more, whilst optimizing the system linearity.
The following table shows typical NF and IIP3 performances for the RFM95/96/97/98(W) LNA gains available.
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## _Table 82 LNA Gain Control and Performances_
|**_RX input level (Pin)_**|**_Gain_**<br>**_Setting_**|**_LnaGain_**|**_Relative LNA_**<br>**_Gain [dB]_**|**NF**<br>**Lower/Higher**<br>**band**<br>**[dB]**|**IIP3**<br>**Lower/Higher**<br>**band [dBm]**|
|---|---|---|---|---|---|
|**Pin <= AgcThresh1**|G1|‘001’|0 dB|5/7|-22/-12|
|**AgcThresh1 < Pin <= AgcThresh2**|G2|‘010’|-6 dB|9/11|-15/-8|
|**AgcThresh2 < Pin <= AgcThresh3**|G3|‘011’|-12 dB|TBC||
|**AgcThresh3 < Pin <= AgcThresh4**|G4|‘100’|-24 dB|||
|**AgcThresh4 < Pin <= AgcThresh5**|G5|‘110’|-26 dB|||
|**AgcThresh5 < Pin**|G6|‘111’|-48 dB|||
## **5.5.4. RSSI in FSK/OOK Mode**
The RSSI provides a measure of the incoming signal power at RF input port, measured within the receiver bandwidth. The signal power is available in _RssiValue_ . This value is absolute in units of dBm and with a resolution of 0.5 dB. The formula below relates the register value to the absolute input signal level at the RF input port:
## _RssiValue_ = −2 · _RF level_ [ _dBm_ ]+ _RssiOffset_ [ _dB_ ]
The RSSI value can be compensated to take into account the loss in the matching network or even the gain of an additional LNA by using _RssiOffset_ . The offset can be chosen in 1 dB steps from -16 to +15 dB. When compensation is applied, the effective signal strength is read as follows:
## _RSSI_ [ _dBm_ ] = − _[RssiValue]_
**==> picture [10 x 10] intentionally omitted <==**
The RSSI value is smoothed on a user defined number of measured RSSI samples. The precision of the RSSI value is related to the number of RSSI samples used. _RssiSmoothing_ selects the number of RSSI samples from a minimum of 2 samples up to 256 samples in increments of power of 2. Table 83 gives the estimation of the RSSI accuracy for a 10 dB SNR and response time versus the number of RSSI samples programmed in _RssiSmoothing_ .
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**RFM95/96/97/98(W)**
_Table 83 RssiSmoothing Options_
|**_RssiSmoothing_**|**Number of Samples**|**Estimated Accuracy**|**Response Time**|
|---|---|---|---|
|‘000’|2|± 6 dB|2 (_RssiSmoothing_+1)<br>4 · _RxBw_~~[~~_kHz_~~] ~~[_ms_]|
|‘001’|4|± 5 dB||
|‘010’|8|± 4 dB||
|‘011’|16|± 3 dB||
|‘100’|32|± 2 dB||
|‘101’|64|± 1.5 dB||
|‘110’|128|± 1.2 dB||
|‘111’|256|± 1.1 dB||
The RSSI is calibrated when the image and RSSI calibration process is launched.
## **5.5.5. RSSI in** LoRa[TM ] **Mode**
The RSSI values reported by the LoRa[TM ] modem differ from those expressed by the FSK/OOK modem. The following formula shows the method used to interpret the LoRa[TM ] RSSI values.
**==> picture [107 x 9] intentionally omitted <==**
## **5.5.6. Channel Filter**
The role of the channel filter is to reject noise and interference outside of the wanted channel. The RFM95/96/97/98(W) channel filtering is implemented with a 16-tap finite impulse response (FIR) filter. Rejection of the filter is high enough that the filter stop-band performance is not the dominant influence on adjacent channel rejection performance. This is instead limited by the RFM95/96/97/98(W) PLL phase noise.
_Note To respect sampling criterion in the decimation chain of the receiver, the communication bit rate cannot be set at a higher than twice the single side receiver bandwidth (BitRate < 2 x RxBw)_
The programmed single side bandwidth _RxBw_ of the channel filter is determined by the parameters _RxBwMant_ and _RxBwExp_ in _RegRxBw:_
_RxBw_ = ------------------------ _[F]_ ---- _[X]_ ---- _[O]_ ---- _[S]_ ---- _[C]_ ------------------------- _[x][ p ]_[+ 2] _RxB wMant_ × 2 _[RxBwE]_
The following channel filter bandwidths are hence accessible in the case of a 32 MHz reference oscillator.
## _Table 84 Available RxBw Settings_
|_Table 84 Available RxBw Settings_|||
|---|---|---|
|**_RxBwMant_**<br>**(binary/value)**|**_RxBwExp_**<br>**(decimal)**|**_RxBw (kHz)_**|
|||**FSK / OOK**|
|10b / 24|7|2.6|
|01b / 20|7|3.1|
|00b / 16|7|3.9|
|10b / 24|6|5.2|
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|01b / 20|6|6.3|
|---|---|---|
|00b / 16|6|7.8|
|10b / 24|5|10.4|
|01b / 20|5|12.5|
|00b / 16|5|15.6|
|10b / 24|4|20.8|
|01b / 20|4|25.0|
|00b / 16|4|31.3|
|10b / 24|3|41.7|
|01b / 20|3|50.0|
|00b / 16|3|62.5|
|10b / 24|2|83.3|
|01b / 20|2|100.0|
|00b / 16|2|125.0|
|10b / 24|1|166.7|
|01b / 20|1|200.0|
|00b / 16|1|250.0|
|Other settings||reserved|
## **5.5.7. Temperature Measurement**
A stand alone temperature measurement block is used in order to measure the temperature in any mode except Sleep and Standby. It is enabled by default, and can be stopped by setting _TempMonitorOff_ to 1. The result of the measurement is stored in _TempValue_ in _RegTemp_ .
Due to process variations, the absolute accuracy of the result is +/- 10 °C. Higher precision requires a calibration procedure at a known temperature. The figure below shows the influence of just such a calibration process. For more information, including source code, please consult the applications Section of this document.
_Figure 41. Temperature Sensor Response_
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**RFM95/96/97/98(W)**
## **6. Description of the Registers**
The register mapping depends upon whether FSK/OOK or LoRa[TM ] mode has been selected. The following table summarises the location and function of each register and gives an overview of the changes in register mapping between both modes of operation.
## **6.1. Register Table Summary**
## _Table 85 Registers Summary_
|**Address**<br>~~po~~|**Register Name**<br>~~po~~|**Register Name**<br>~~po~~|**Reset**<br>**(POR)**|**Default**<br>**(FSK)**|**Description**<br>~~po~~|**Description**<br>~~po~~|
|---|---|---|---|---|---|---|
||**FSK/OOK Mode**<br>~~po~~|**LoRaTMMode**<br>~~po~~|||**FSK Mode**<br>~~po~~|**LoRaTMMode**<br>~~po~~|
|0x00<br>~~po~~|RegFifo<br>~~po~~||0x00<br>~~a~~||FIFO read/write access||
|0x01<br>~~po~~|RegOpMode<br>~~a~~<br>~~po~~||0x01<br>~~a~~<br>~~a~~||Operating mode &LoRaTM/ FSK selection<br>~~a~~||
|0x02<br>~~po~~<br>~~po~~|RegBitrateMsb<br>~~a~~<br>~~po~~<br>~~po~~<br>~~=~~|Unused<br>~~a~~<br>~~SS~~<br>~~o~~|0x1A<br>~~a~~<br>~~a~~<br>~~a~~<br>~~SS~~||Bit Rate setting, Most Significant Bits<br>~~a~~<br>~~SS~~||
|0x03<br>~~po~~<br>~~po~~|RegBitrateLsb<br>~~po~~<br>~~po~~<br>~~=~~||0x0B<br>~~a~~<br>~~a~~<br>~~a~~<br>~~SS~~||Bit Rate setting, Least Significant Bits<br>~~SS~~||
|0x04<br>~~po~~<br>~~fo~~|RegFdevMsb<br>~~po~~<br>~~=~~<br>~~fo~~||0x00<br>~~a~~<br>~~SS~~<br>~~a~~||Frequency Deviation setting, Most Significant Bits<br>~~SS~~||
|0x05<br>~~fo~~<br>~~**p**~~|RegFdevLsb<br>~~=~~<br>~~fo~~<br>~~**p**o~~||0x52<br>~~SS~~<br>~~a~~||Frequency Deviation setting, Least Significant Bits<br>~~SS~~||
|0x06<br>~~fo~~<br>~~**p**~~|RegFrfMsb<br>~~fo~~<br>~~**p**o~~||0xE4<br>~~a~~||RF Carrier Frequency, Most Significant Bits||
|0x07<br>~~**p**~~|RegFrfMid<br>~~**p**o~~<br>~~es~~||0xC0<br>~~o~~<br>~~eG~~||RF Carrier Frequency, Intermediate Bits<br>~~o~~<br>~~eG~~||
|0x08|RegFrfLsb<br>~~es~~||0x00<br>~~eG~~<br>~~ee~~||RF Carrier Frequency, Least Significant Bits<br>~~eG~~||
|0x09|RegPaConfig<br>~~es~~<br>~~as~~||0x0F<br>~~eG~~<br>~~as~~<br>~~ee~~<br>~~ee~~||PA selection and Output Power control<br>~~eG~~<br>~~as~~||
|0x0A|RegPaRamp<br>~~as~~||0x19<br>~~ee~~<br>~~as~~<br>~~ee~~||Control of PA ramp time, low phase noise PLL<br>~~as~~||
|0x0B|RegOcp<br>~~es~~||0x2B<br>~~ee~~<br>~~es~~||Over Current Protection control<br>~~es~~||
|0x0C|RegLna<br>~~pf~~||0x20<br>~~pf~~||LNA settings<br>~~pf~~||
|0x0D|RegRxConfig<br>~~a~~|RegFifoAddrPtr<br>~~a~~<br>~~a~~|0x08<br>~~a~~<br>~~a~~<br>~~a~~|0x0E<br>~~a~~<br>~~a~~<br>~~a~~|AFC, AGC, ctrl<br>~~a~~<br>~~a~~<br>~~a~~|FIFO SPI pointer<br>~~a~~<br>~~a~~<br>~~a~~|
|0x0E|RegRssiConfig<br>~~a~~|RegFifoTxBa-<br>seAddr<br>~~a~~|0x02<br>~~a~~||RSSI<br>~~a~~|Start Tx data<br>~~a~~|
|0x0F|RegRssiCollision<br>~~a~~<br>~~a~~|RegFifoRxBa-<br>seAddr<br>~~a~~<br>~~a~~|0x0A<br>~~a~~<br>~~a~~||RSSI Collision detector<br>~~a~~<br>~~a~~|Start Rx data<br>~~a~~<br>~~a~~|
|0x10|RegRssiThresh<br>~~a~~<br>~~a~~<br>~~a~~|RegIrqFlags<br>~~a~~<br>~~a~~|0xFF<br>~~a~~<br>~~a~~<br>~~**a**~~||RSSI Threshold control<br>~~a~~<br>~~a~~|LoRaTMstate flags<br>~~a~~<br>~~a~~|
|0x11|RegRssiValue<br>~~a~~|RegIrqFlagsMask<br>~~a~~|-<br>~~**a**~~||RSSI value in dBm|Optional flag mask|
|0x12|RegRxBw<br>~~—~~|RegFreqIfMsb<br>~~a~~|0x15<br>~~ee~~||Channel Filter BW Control|IF Frequency<br>|
|0x13|RegAfcBw<br>~~a~~<br>~~eS~~|RegFreqIFLsb<br>~~a~~<br>|0x0B<br>~~ee~~<br>||AFC Channel Filter BW<br>~~ee~~<br>||
|0x14|RegOokPeak<br>~~ee~~<br>~~eS~~|RegSymbTime-<br>outMsb<br>~~a~~<br>~~ee~~<br>|0x28<br>~~ee~~<br>~~ee~~<br>||OOK demodulator<br>~~ee~~<br>~~ee~~<br>|Receiver timeout value<br>~~ee~~<br>|
|0x15|RegOokFix<br>~~ee~~<br>~~eS~~|RegSymbTime-<br>outLsb<br>~~ee~~<br>|0x0C<br>~~ee~~<br>||Threshold of the OOK demod<br>~~ee~~<br>~~ee~~<br>||
|0x16|RegOokAvg<br>~~ee~~<br>~~eSfr”~~|RegTxCfg<br>~~ee~~<br>~~fr”~~|0x12<br>~~ee~~<br>~~fr”~~||Average of the OOK demod<br>~~ee~~<br>~~ee~~<br>~~fr”~~|LoRaTMtransmit<br>parameters<br>~~ee~~<br>~~fr”~~|
|0x17|Reserved17<br>~~eSfr”~~<br>~~a~~|RegPay-<br>loadLength<br>~~fr”~~<br>~~a~~|0x47<br>~~fr”~~<br>~~a~~||-<br>~~ee~~<br>~~fr”~~||
|0x18|Reserved18<br>~~fr”~~<br>~~a ~~<br>~~SS~~|RegPreambleMsb<br>~~fr”~~<br> ~~a~~<br>~~S~~|0x32<br>~~fr”~~<br>~~a~~<br>~~a~~||-<br>~~fr”~~<br>~~ee~~|Size of preamble<br>~~fr”~~<br>~~eee~~<br>|
|0x19|Reserved19<br>~~SS~~<br>~~I~~|RegPreambleLsb<br>~~S~~<br>|0x3E<br>~~a~~<br>||-<br>~~ee~~<br>||
|0x1A|RegAfcFei<br>~~SS~~<br>~~SS~~|RegModulation-<br>Cfg<br>~~S~~<br>~~SS~~|0x00<br>~~a ~~<br>~~SS~~||AFC and FEI control<br> ~~ee ~~<br>~~SS~~|Modem PHY config<br> ~~eee~~<br>~~SS~~|
|0x1B<br>~~$a}~~|RegAfcMsb<br>~~SS~~<br>~~$a}~~|RegRfMode<br>~~SS~~<br>~~$a}at~~|0x00<br>~~SS~~<br>~~at~~<br>~~i~~||Frequency correction value of<br>the AFC<br>~~SS~~<br>~~—SSHEAR~~|Test register<br>~~SS~~<br>~~—SSHEAR~~|
|0x1C<br>~~$a}~~|RegAfcLsb<br>~~$a}~~|RegHopPeriod<br>~~$a}at~~|0x00<br>~~at~~<br>~~i~~|||FHSS Hop period<br>~~—SSHEAR~~|
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**RFM95/96/97/98(W)**
|**Address**<br>~~Po~~|**Register Name**<br>~~Po~~|**Register Name**<br>~~Po~~|**Reset**<br>**(POR)**|**Default**<br>**(FSK)**<br>~~en~~|**Description**<br>~~ee~~|**Description**<br>~~ee~~|
|---|---|---|---|---|---|---|
||**FSK/OOK Mode**<br>~~Po~~<br>~~See~~|**LoRaTMMode**<br>~~Po~~<br>~~See~~|||**FSK Mode**<br>~~ee~~<br>~~en~~|**LoRaTMMode**<br>~~ee~~<br>~~en~~|
|0x1D|RegFeiMsb<br>~~See~~<br>~~a~~|RegNbRxBytes<br>~~See~~<br>~~es~~|0x00<br>~~en~~<br>~~ee~~<br>~~aeee~~||Value of the calculated<br>frequency error<br>~~en~~<br>~~ee~~|Number of received bytes<br>~~en~~<br>~~Po~~|
|0x1E|RegFeiLsb<br>~~See~~<br>~~a~~|RegRxHeaderInfo<br>~~See~~<br>~~es~~|0x00<br>~~en~~<br>~~ee~~<br>~~aeee~~|||Info from last header<br>~~en~~<br>~~Po~~|
|0x1F|RegPreambleDe-<br>tect<br>~~See~~<br>~~a~~<br>~~ss~~<br>~~a~~|RegRx-<br>HeaderCntValue<br>~~See~~<br>~~es~~<br>~~ss~~|0x40<br>~~ee~~<br>~~ss~~<br>~~ae~~<br>~~a~~|0xAA<br>~~en~~<br>~~ee~~<br>~~ss~~<br>~~ee~~<br>~~a~~|Settings of the Preamble<br>Detector<br>~~en~~<br>~~ss~~<br>~~ee~~|Number of valid headers<br>received<br>~~en~~<br>~~Po~~<br>~~ss~~|
|0x20|RegRxTimeout1<br>~~ss~~<br>~~ss~~<br>~~a~~|RegRxPacketCnt-<br>Value<br>~~ss~~<br>~~ss~~|0x00<br>~~ss~~<br>~~ae ee ~~<br>~~ss~~<br>~~a~~||Timeout Rx request and RSSI<br>~~ss~~<br> ~~ee~~<br>~~ss~~|Number of valid packets<br>received<br>~~ss~~<br>~~ss~~|
|0x21|RegRxTimeout2<br>~~ss~~<br>~~a~~<br>~~es~~|RegModemStat<br>~~ss~~|0x00<br>~~ss~~<br>~~a~~||Timeout RSSI and_Pay-_<br>_loadReady_<br>~~ss~~|LiveLoRaTMmodem sta-<br>tus<br>~~ss~~|
|0x22<br>~~Po~~|RegRxTimeout3<br>~~es~~<br>~~Po~~<br>~~rrrrt—SY~~<br>~~es~~|RegPktSnrValue<br>~~rrrrt—SYeee~~<br>~~ee~~|0x00<br>~~ee~~<br>~~eeec~~||Timeout RSSI and_SyncAd-_<br>_dress_<br>~~ee~~<br>~~ee~~<br>~~ec~~|Espimation of last packet<br>SNR<br>~~ee~~<br>~~ec~~|
|0x23<br>~~Po~~|RegRxDelay<br>~~es~~<br>~~Po~~<br>~~rrrrt—SY~~<br>~~es~~|RegRssiValue<br>~~rrrrt—SYeee~~<br>~~ee~~|0x00<br>~~ee~~<br>~~eeec~~||Delay between Rx cycles<br>~~ee~~<br>~~ee~~<br>~~ec~~|Current RSSI<br>~~ee~~<br>~~ec~~|
|0x24<br>~~Po~~<br>~~PO~~|RegOsc<br>~~Po~~<br>~~rrrrt—SY~~<br>~~es~~<br>~~PO~~<br>~~rr—S~~|RegPktRssiValue<br>~~rrrrt—SY eee~~<br>~~ee~~<br>~~ee~~|0x05<br>~~ee~~<br>~~ee~~<br>~~ee~~|0x07<br>~~ee~~<br>~~ec~~|RC Oscillators Settings, CLK-<br>OUT frequency<br>~~ee~~<br>~~ee~~<br>~~ec~~<br>~~ee~~|RSSi of last packet<br>~~ee~~<br>~~ec~~|
|0x25<br>~~PO~~<br>~~|~~|RegPreambleMsb<br>~~es~~<br>~~PO~~<br>~~rr—S~~<br>~~|~~|RegHopChannel<br>~~ee~~<br>~~ee~~|0x00<br>~~eeec~~<br>~~ee~~<br>~~ee~~||Preamble length, MSB<br>~~ec~~<br>~~ee~~<br>~~nn~~|FHSS start channel<br>~~ec~~|
|0x26<br>~~PO~~<br>~~|~~|RegPreambleLsb<br>~~PO~~<br>~~rr—S~~<br>~~re~~<br>~~|~~<br>~~—|~~|RegRxDataAddr<br>~~ee~~<br>~~re~~<br>~~—|~~|0x03<br>~~ee~~<br>~~re~~<br>~~ee~~<br>~~ee~~<br>||Preamble length, LSB<br>~~ee~~<br>~~re~~<br>~~nn~~<br>~~ee~~<br>|LoRaTMrx data pointer<br>~~re~~<br>|
|0x27<br>~~|~~<br>~~Po~~|RegSyncConfig<br>~~|~~<br>~~—|~~<br>~~Po~~|RESERVED<br>~~—| ~~<br>~~ss~~|0x93<br>~~ee~~<br>~~ee~~<br>~~==~~||Sync Word Recognition control<br>~~nn~~<br>~~ee~~<br>~~==~~|RESERVED<br>~~==~~|
|0x28-<br>0x2F<br>~~|~~<br>~~Po~~|RegSyncValue1-8<br>~~|~~<br>~~—|~~<br>~~Po~~||0x55<br>~~ee~~<br>~~ee~~<br>~~==~~|0x01<br>~~ee~~<br>~~ee~~<br>~~==~~|Sync Word bytes, 1 through 8<br>~~nn~~<br>~~ee~~<br>~~==~~||
|0x30<br>~~Po~~<br>~~Ps~~|RegPacketConfig1<br>~~—|~~<br>~~Po~~<br>~~Ps~~||0x90<br>~~ee~~<br>~~==~~<br>~~**es**~~||Packet mode settings<br>~~ee~~<br>~~==~~<br>~~**es**~~||
|0x31<br>~~Po~~<br>~~Ps~~|RegPacketConfig2<br>~~—|~~<br>~~Po~~<br>~~Ps~~||0x40<br>~~ee~~<br>~~==~~<br>~~**es**~~||Packet mode settings<br>~~ee~~<br>~~==~~<br>~~**es**~~||
|0x32<br>~~Po~~<br>~~Ps~~<br>~~|~~|RegPayloadLength<br>~~—|~~<br>~~Po~~<br>~~Ps~~<br>~~|~~<br>~~ss~~||0x40<br>~~ee~~<br> ~~==~~<br>~~**es**~~<br>~~es~~||Payload length setting<br>~~ee~~<br>~~==~~<br>~~**es**~~<br>~~es~~||
|0x33<br>~~|~~<br>~~|~~<br>~~-—~~|RegNodeAdrs<br>~~—|~~<br>~~|~~<br>~~ss~~<br>~~|~~<br>~~ss~~<br>~~-—~~|RESERVED<br>~~—| ~~<br>~~ss~~<br>~~ss~~<br>~~ssid~~<br>~~ss~~<br>~~eee~~<br>|0x00<br>~~ee~~<br> <br>~~es~~<br>~~es~~<br>~~ee~~||Node address<br>~~ee~~<br><br>~~es~~<br>~~es~~<br>~~ee~~|RESERVED<br><br>|
|0x34<br>~~|~~<br>~~|~~<br>~~-—~~|RegBroadcastAdrs<br>~~|~~<br>~~ss~~<br>~~|~~<br>~~ss~~<br>~~-—~~||0x00<br>~~es~~<br>~~es~~<br>~~ee~~||Broadcast address<br>~~es~~<br>~~es~~<br>~~ee~~||
|0x35<br>~~|~~<br>~~-—~~<br>~~|~~|RegFifoThresh<br>~~|~~<br>~~ss~~<br>~~-—~~<br>~~|~~<br>~~ssid~~||0x0F<br>~~es~~<br>~~ee~~<br>~~es~~|0x8F<br>~~es~~<br>~~ee~~<br>~~es~~|Fifo threshold, Tx start condi-<br>tion<br>~~es~~<br>~~ee~~<br>~~es~~||
|0x36<br>~~-—~~<br>~~|~~<br>~~|~~|RegSeqConfig1<br>~~-—~~<br>~~|~~<br>~~ssid~~<br>~~|~~<br>~~ss~~||0x00<br>~~ee~~<br>~~es~~<br>~~es~~||Top level Sequencer settings<br>~~ee~~<br>~~es~~<br>~~es~~||
|0x37<br>~~|~~<br>~~|~~<br>~~fs~~|RegSeqConfig2<br>~~|~~<br>~~ssid~~<br>~~|~~<br>~~ss~~<br>~~fs~~||0x00<br>~~es~~<br>~~es~~<br>~~es~~||Top level Sequencer settings<br>~~es~~<br>~~es~~<br>~~es~~||
|0x38<br>~~|~~<br>~~fs~~<br>~~|~~|RegTimerResol<br>~~|~~<br>~~ss~~<br>~~fs~~<br>~~|~~||0x00<br>~~es~~<br>~~es~~<br>~~ee~~||Timer 1 and 2 resolution control<br>~~es~~<br>~~es~~<br>~~ee~~||
|0x39<br>~~fs~~<br>~~|~~<br>~~fs~~<br>~~-—~~|RegTimer1Coef<br>~~fs~~<br>~~|~~<br>~~fs~~<br>~~-—~~||0xF5<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~||Timer 1 setting<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~||
|0x3A<br>~~|~~<br>~~fs~~<br>~~-—~~|RegTimer2Coef<br>~~|~~<br>~~fs~~<br>~~-—~~||0x20<br>~~ee~~<br>~~es~~<br>~~ee~~||Timer 2 setting<br>~~ee~~<br>~~es~~<br>~~ee~~||
|0x3B<br>~~fs~~<br>~~-—~~<br>~~Po~~|RegImageCal<br>~~fs~~<br>~~-—~~<br>~~Po~~||0x82<br>~~es~~<br>~~ee~~<br>~~es~~|0x02<br>~~es~~<br>~~ee~~<br>~~es~~|Image calibration engine con-<br>trol<br>~~es~~<br>~~ee~~<br>~~es~~||
|0x3C<br>~~-—~~<br>~~Po~~<br>~~-—~~|RegTemp<br>~~-—~~<br>~~Po~~<br>~~eee~~<br>~~-—~~||-<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~es~~||Temperature Sensor value<br>~~ee~~<br>~~es~~<br>~~ee~~<br>~~es~~||
|0x3D<br>~~Po~~<br>~~-—~~|RegLowBat<br>~~Po~~<br>~~eee~~<br>~~-—~~||0x02<br>~~es~~<br>~~ee~~<br>~~es~~||Low Battery Indicator Settings<br>~~es~~<br>~~ee~~<br>~~es~~||
|0x3E<br>~~-—~~|RegIrqFlags1<br>~~eee~~<br>~~-—~~||0x80<br>~~ee~~<br>~~es~~||Status register: PLL Lock state,<br>Timeout, RSSI<br>~~ee~~<br>~~es~~||
|0x3F<br>~~-—~~<br>~~PO~~<br>~~PC~~|RegIrqFlags2<br>~~-—~~<br>~~a~~<br>~~PO~~<br>~~PC~~||0x40<br>~~es~~<br>~~es~~<br><br>~~ee~~||Status register: FIFO handling<br>flags, Low Battery<br>~~es~~<br>~~es~~<br><br>~~ee~~||
|0x40<br>~~PO~~<br>~~PC~~<br>~~PC~~|RegDioMapping1<br>~~PO——(—i‘“‘“‘<‘iw;'~~<br>~~PC~~<br>~~**——**“—i—‘“‘“‘“~~~~**‘<‘iwwi**~~<br>~~PC~~||0x00<br>~~——(—i‘“‘“‘<‘iw;'~~<br>~~ee~~<br>~~**‘<‘iwwi**~~||Mapping of pins DIO0 to DIO3<br>~~——(—i‘“‘“‘<‘iw;'~~<br>~~ee~~||
|0x41<br>~~PO~~<br>~~PC~~<br>~~PC~~|RegDioMapping2<br>~~PO~~<br>~~PC~~<br>~~**——**“—i—‘“‘“‘“~~~~**‘<‘iwwi**~~<br>~~PC~~<br>~~—“—i—‘“‘“‘“~~<br>~~eS~~<br>~~a~~||0x00<br><br>~~ee~~<br>~~**‘<‘iwwi**~~<br>~~a~~||Mapping of pins DIO4 and DIO5, ClkOut frequency<br><br>~~ee~~<br>~~cc~~||
|0x42<br>~~PC~~<br>~~PC~~|RegVersion<br>~~PC~~<br>~~**——**“—i—‘“‘“‘“~~~~**‘<‘iwwi**~~<br>~~PC~~<br>~~—“—i—‘“‘“‘“~~<br>~~eS~~<br>~~a~~||0x11<br>~~ee~~<br>~~**‘<‘iwwi**~~<br>~~a~~||Hope RF ID relating the silicon revision<br>~~ee~~<br>~~cc~~||
|0x44<br>~~PC~~|RegPllHop<br>~~**——**“—i—‘“‘“‘“~~<br>~~PC~~<br>~~—“—i—‘“‘“‘“~~<br>~~eS~~|Unused<br>~~“—i—‘“‘“‘“~~~~**‘<‘iwwi**~~<br>~~—“—i—‘“‘“‘“~~<br>~~a~~|0x2D<br>~~**‘<‘iwwi**~~<br>~~a~~||Control the fast frequency hop-<br>ping mode<br>~~cc~~|Unused|
|0x4B|RegTcxo<br>~~eS~~<br>~~a~~||0x09<br>~~a~~||TCXO or XTAL input setting<br>~~cc~~||
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**RFM95/96/97/98(W)**
|**Address**|**Register Name**|**Register Name**|**Reset**<br>**(POR)**|**Default**<br>**(FSK)**|**Description**|**Description**|
|---|---|---|---|---|---|---|
||**FSK/OOK Mode**|**LoRaTMMode**|||**FSK Mode**|**LoRaTMMode**|
|0x4D|RegPaDac||0x84||Higher power settings of the PA||
|0x5B|RegFormerTemp||-||Stored temperature during the former IQ Calibration||
|0x5D|RegBitRateFrac|Unused|0x00||Fractional part in the Bit Rate<br>division ratio|Unused|
|0x61|RegAgcRef||0x13||Adjustment of the AGC thresholds||
|0x62|RegAgcThresh1||0x0E||||
|0x63|RegAgcThresh2||0x5B||||
|0x64|RegAgcThresh3||0xDB||||
|others|RegTest||-||Internal test registers. Do not overwrite||
## _Note - Reset values are automatically refreshed in the chip at Power On Reset_
- _Default values are the Hope RF recommended register values, optimizing the device operation_
- _Registers for which the Default value differs from the Reset value are denoted by a * in the tables of section 6.2_
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**RFM95/96/97/98(W)**
## **6.2. FSK/OOK Mode Register Map**
This section details the RFM95/96/97/98(W) register mapping and the precise contents of each register in FSK/OOK
mode. Convention: r: read, w: write, t:trigger, c: clear
_Table 86 Register Map_
|**Name**<br>**(Address)**<br>~~a eee~~|**Bits**<br>~~eee~~<br>~~a~~|**Variable Name**<br>~~eee~~<br>~~a~~|**Mode**<br>~~eee~~|**Default**<br>**value**<br>~~eee~~|**FSK/OOK Description**<br>~~eee~~<br>~~ee~~|
|---|---|---|---|---|---|
|RegFifo<br>(0x00)|7-0<br>~~a~~|Fifo<br>~~a~~|rw|0x00|FIFO data input/output<br>~~ee~~|
|Registers for Common settings<br>~~a~~<br>~~ee~~||||||
|RegOpMode<br>(0x01)|7|LongRangeMode|r|0x00|0<br> FSK/OOK Mode<br>1<br> LoRaTMMode<br>This bit can be modified only in Sleep mode. A write operation on<br>other device modes is ignored.|
||6-5<br>~~Mi~~|ModulationType<br>~~Mi~~|rw<br>~~Mi~~|0x00<br>~~Mi~~|Modulation scheme:<br>00<br> FSK<br>01<br> OOK<br>10<br> 11<br> reserved<br>~~Mi~~|
||4<br>~~Mi~~|reserved<br>~~Mi~~|r<br>~~Mi~~|0x0<br>~~Mi~~|reserved<br>~~Mi~~|
||3|LowFrequencyModeOn|rw|0x01|Access Low Frequency Mode registers (from address 0x61 on)<br>0<br> High Frequency Mode (access to HF test registers)<br>1<br> Low Frequency Mode (access to LF test registers)|
||2-0<br>~~—~~|Mode<br>~~—~~|rw<br>~~—~~|0x01<br>~~—~~|Transceiver modes<br>000<br> Sleep mode<br>001<br> Stdby mode<br>010<br> FS mode TX (FSTx)<br>011<br> Transmitter mode (Tx)<br>100<br> FS mode RX (FSRx)<br>101<br> Receiver mode (Rx)<br>110<br> reserved<br>111<br> reserved<br>~~—~~|
|RegBitrateMsb<br>(0x02)|7-0<br>~~—~~|BitRate(15:8)<br>~~—~~|rw<br>~~—~~|0x1a<br>~~—~~|MSB of Bit Rate (chip rate if Manchester encoding is enabled)<br>~~—~~|
|RegBitrateLsb<br>(0x03)|7-0<br>~~—~~<br>~~Pf~~|BitRate(7:0)<br>~~—~~<br>~~Pf~~<br>~~r—“—i—i~~|rw<br>~~—~~<br>~~r—“—i—i~~|0x0b<br>~~—~~|LSB of bit rate (chip rate if Manchester encoding is enabled)<br>_BitRate_= ---------------------------_F_----_X_----_O_-----_S_---_C_----------------------------**-**<br>_Bi tR ate_(15,0) + -_B_----_i_--_t_--_r_--_a_----_t_--_e_---_F_----_r_--_a_----_c_-<br>16<br>Default value: 4.8 kb/s<br>~~—~~|
|RegFdevMsb<br>(0x04)|7-6<br>~~Pf~~|reserved<br>~~Pf~~<br>~~r—“—i—i~~|rw<br>~~r—“—i—i~~|0x00|reserved|
||5-0<br>~~Pf~~<br>~~To.~~|Fdev(13:8)<br>~~Pf~~<br>~~r—“—i—i~~<br>~~To.~~|rw<br>~~r—“—i—i~~<br>~~To.~~|0x00<br>~~To.~~|MSB of the frequency deviation<br>~~To.~~|
|RegFdevLsb<br>(0x05)|7-0<br>~~To.~~|Fdev(7:0)<br>~~To.~~|rw<br>~~To.~~|0x52<br>~~To.~~|LSB of the frequency deviation<br>_Fdev_=_Fste p_×_Fdev_(15,0)<br>Default value: 5 kHz<br>~~To.~~|
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**RFM95/96/97/98(W)**
|**Name**<br>**(Address)**|**Bits**|**Variable Name**|**Mode**|**Default**<br>**value**|**FSK/OOK Description**|
|---|---|---|---|---|---|
|RegFrfMsb<br>(0x06)|7-0|Frf(23:16)|rw|0x6c|MSB of the RF carrier frequency|
|RegFrfMid<br>(0x07)|7-0|Frf(15:8)|rw|0x80|MSB of the RF carrier frequency|
|RegFrfLsb<br>(0x08)|7-0|Frf(7:0)|rw|0x00|LSB of RF carrier frequency<br>_Frf_=_F ste p_×_Frf_(23;0)<br>Default value: 434.000 MHz<br>The RF frequency is taken into account internally only when:<br>- entering FSRX/FSTX modes<br>- re-starting the receiver|
|Registers for the Transmitter||||||
|RegPaConfig<br>(0x09)|7|PaSelect|rw|0x00|Selects PA output pin<br>0<br> RFO pin. Maximum power of +14 dBm<br>1<br> PA_BOOST pin. Maximum power of +20 dBm<br>><br>>|
||6-4<br>~~Se~~|MaxPower<br>~~Se A~~|rw<br>~~A~~|0x04|Select max output power: Pmax=10.8+0.6*MaxPower [dBm]|
||3-0<br>~~Se~~|OutputPower<br>~~Se A~~|rw<br>~~A~~<br>~~ee~~|0x0f<br>~~ee~~|Pout=Pmax-(15-OutputPower) if PaSelect = 0 (RFO pins)<br>Pout=17-(15-OutputPower)<br>if PaSelect = 1 (PA_BOOST pin)|
|RegPaRamp<br>(0x0A)|7<br>~~re~~|unused<br>~~re~~|r<br>~~re~~<br>~~ee~~|0x00<br>~~re~~<br>~~ee~~|unused<br>~~re~~|
||6-5|ModulationShaping|rw<br>~~ee ~~<br>~~ee~~|0x00<br> ~~ee~~<br>~~ee~~|Data shaping:<br>In FSK:<br>00<br> no shaping<br>01<br> gaussian filter BT = 1.0<br>10<br> gaussian filter BT = 0.5<br>11<br> gaussian filter BT = 0.3<br>In OOK:<br>00<br> no shaping<br>01<br> filtering with fcutoff= bit_rate<br>10<br> filtering with fcutoff= 2*bit_rate (for bit_rate < 125 kb/s)<br>11<br> reserved<br>><br>><br>><br>><br>><br>><br>><br>>|
||4<br>~~re~~|reserved<br>~~re~~|rw<br>~~re~~<br>~~ee~~|0x00<br>~~re~~<br>~~ee~~|reserved<br>~~re~~|
||3-0|PaRamp|rw<br>~~ee ~~|0x09<br> ~~ee~~|Rise/Fall time of ramp up/down in FSK<br>0000<br> 3.4 ms<br>0001<br> 2 ms<br>0010<br> 1 ms<br>0011<br> 500 us<br>0100<br> 250 us<br>0101<br> 125 us<br>0110<br> 100 us<br>0111<br> 62 us<br>1000<br> 50 us<br>1001<br> 40 us (d)<br>1010<br> 31 us<br>1011<br> 25 us<br>1100<br> 20 us<br>1101<br> 15 us<br>1110<br> 12 us<br>1111<br> 10 us<br>><br>><br>><br>><br>><br>><br>><br>><br>><br>><br>><br>><br>><br>><br>><br>>|
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**RFM95/96/97/98(W)**
|**Name**<br>**(Address)**<br>~~a~~|**Bits**<br>|**Variable Name**<br>|**Mode**<br><br>~~a~~|**Default**<br>**value**<br><br>~~a ae~~|**FSK/OOK Description**<br><br>~~ae~~|
|---|---|---|---|---|---|
|RegOcp<br>(0x0B)<br>|7-6<br>~~a~~|unused<br>~~a~~|r<br>~~a~~<br>~~a~~|0x00<br>~~a~~<br>~~a ae~~|unused<br>~~a~~<br>~~ae~~|
||5<br>~~a~~|OcpOn<br>~~a~~|rw<br>~~a ~~<br>~~a~~|0x01<br> ~~a ae~~<br>~~a~~|Enables overload current protection (OCP) for the PA:<br>0<br> OCP disabled<br>1<br> OCP enabled<br>~~ae~~<br>~~a~~|
||4-0<br>~~a~~|OcpTrim<br>~~a~~|rw<br>~~a~~|0x0b<br>~~a~~|Trimming of OCP current:<br>Imax= 45+5*OcpTrim [mA] if OcpTrim <= 15 (120 mA) /<br>Imax= -30+10*OcpTrim [mA] if 15 < OcpTrim <= 27 (130 to 240<br>mA)<br>Imax= 240mA for higher settings<br>Default Imax= 100mA<br>~~a~~|
|Registers for the Receiver||||||
|RegLna<br>(0x0C)|7-5|LnaGain|rw|0x01|LNA gain setting:<br>000<br> reserved<br>001<br> G1 = highest gain<br>010<br> G2 = highest gain – 6 dB<br>011<br> G3 = highest gain – 12 dB<br>100<br> G4 = highest gain – 24 dB<br>101<br> G5 = highest gain – 36 dB<br>110<br> G6 = highest gain – 48 dB<br>111<br> reserved<br>Note:<br>Reading this address always returns the current LNA gain (which<br>may be different from what had been previously selected if AGC<br>is enabled.|
||4-3<br>~~Se~~|LnaBoostLf<br>~~Se~~|rw<br>~~Se~~|0x00<br>~~Se~~|Low Frequency (RFI_LF) LNA current adjustment<br>00<br> Default LNA current<br>Other<br> Reserved<br>~~Se~~|
||2<br>~~a~~|reserved<br>~~a~~|rw<br>~~a~~|0x00<br>~~a~~<br>~~is~~|reserved<br>~~a~~<br>~~is~~|
||1-0<br>~~pe~~|LnaBoostHf<br>~~pe~~|rw<br>~~pe~~|0x00<br>~~pe~~<br>~~is~~|High Frequency (RFI_HF) LNA current adjustment<br>00<br> Default LNA current<br>11<br> Boost on, 150% LNA current<br>~~pe~~<br>~~is~~|
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**RFM95/96/97/98(W)**
|**Name**<br>**(Address)**|**Bits**|**Variable Name**|**Mode**|**Default**<br>**value**|**FSK/OOK Description**|
|---|---|---|---|---|---|
|RegRxConfig<br>(0x0d)<br>~~Os~~|7|RestartRxOnCollision|rw|0x00|Turns on the mechanism restarting the receiver automatically if it<br>gets saturated or a packet collision is detected<br>0<br> No automatic Restart<br>1<br> Automatic restart On|
||6<br>~~fo~~|RestartRxWithoutPllLock<br>~~fo~~|wt<br>~~fo~~|0x00<br>~~fo~~|Triggers a manual Restart of the Receiver chain when set to 1.<br>Use this bit when there is no frequency change,<br>RestartRxWithPllLock otherwise.<br>~~fo~~|
||5<br>~~fo~~<br>~~Os~~|RestartRxWithPllLock<br>~~fo~~<br>|wt<br>~~fo~~<br>|0x00<br>~~fo~~<br>|Triggers a manual Restart of the Receiver chain when set to 1.<br>Use this bit when there is a frequency change, requiring some<br>time for the PLL to re-lock.<br>~~fo~~<br>|
||4<br>~~Os~~|AfcAutoOn<br>|rw<br>|0x00<br>|0<br> No AFC performed at receiver startup<br>1<br> AFC is performed at each receiver startup<br>|
||3<br>~~OsTe~~|AgcAutoOn<br>~~Te~~|rw<br>~~Te~~|0x01<br>~~Te~~|0<br> LNA gain forced by the LnaGain Setting<br>1<br> LNA gain is controlled by the AGC<br>~~Te~~|
||2-0<br>~~ee~~|RxTrigger<br>~~ee~~|rw|0x06<br>*|Selects the event triggering AGC and/or AFC at receiver startup.<br>See Table 18 for a description.|
|RegRssiConfig<br>(0x0e)|7-3|RssiOffset|rw|0x00|Signed RSSI offset, to compensate for the possible losses/gains<br>in the front-end (LNA, SAW filter...)<br>1dB / LSB, 2’s complement format|
||2-0|RssiSmoothing|rw|0x02|Defines the number of samples taken to average the RSSI result:<br>000<br> 2 samples used<br>001<br> 4 samples used<br>010<br> 8 samples used<br>011<br> 16 samples used<br>100<br> 32 samples used<br>101<br> 64 samples used<br>110<br> 128 samples used<br>111<br> 256 samples used|
|RegRssiCollision<br>(0x0f)|7-0<br>~~fo~~|RssiCollisionThreshold<br>~~fo~~|rw<br>~~fo~~|0x0a<br>~~fo~~|Sets the threshold used to consider that an interferer is detected,<br>witnessing a packet collision. 1dB/LSB (only RSSI increase)<br>Default: 10dB<br>~~fo~~|
|RegRssiThresh<br>(0x10)<br>~~OS~~|7-0<br>~~ee~~<br>~~OS~~|RssiThreshold<br>~~ee~~<br>|rw<br>~~ee~~|0xff<br>~~ee~~|RSSI trigger level for the Rssi interrupt:<br>- RssiThreshold / 2 [dBm]<br>~~ee~~|
|RegRssiValue<br>(0x11)<br>~~OS~~|7-0<br>~~OS~~~~**a**~~|RssiValue<br>~~**a**~~|r|-|Absolute value of the RSSI in dBm, 0.5dB steps.<br>RSSI = - RssiValue/2 [dBm]<br>~~ee~~|
|RegRxBw<br>(0x12)<br>~~OS~~|7<br>~~OS~~~~**a**~~|unused<br>~~**a**~~|r<br>~~a~~|-<br>~~a~~|unused<br>~~ee~~<br>~~ee~~|
||6-5<br>~~**a**~~|reserved<br>~~**a**~~|rw<br>~~a~~|0x00<br>~~a~~|reserved<br>~~ee~~<br>~~ee~~|
||4-3|RxBwMant|rw<br>~~a~~|0x02<br>~~a~~|Channel filter bandwidth control:<br>00<br> RxBwMant = 16<br>10<br> RxBwMant = 24<br>01<br> RxBwMant = 20<br>11<br> reserved<br>~~ee~~|
||2-0|RxBwExp|rw|0x05|Channel filter bandwidth control:<br>FSK Mode:<br>_RxB w_= ------------------------_F_----_X_----_O_----_S_----_C_-------------------------<br>_Rx BwMant_×2_RxBwExp_+ 2|
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**RFM95/96/97/98(W)**
|**Name**<br>**(Address)**|**Bits**<br>~~a~~|**Variable Name**|**Mode**<br>~~ae~~|**Default**<br>**value**<br>~~ee~~|**FSK/OOK Description**|
|---|---|---|---|---|---|
|RegAfcBw<br>(0x13)|7-5<br>~~a~~|reserved|rw<br>~~ae~~|0x00<br>~~ee~~|reserved|
||4-3<br>~~a~~<br>~~PE~~<br>~~a~~|RxBwMantAfc<br>~~PE~~<br>~~a~~|rw<br>~~ae ~~<br>~~PE~~<br>~~ae~~|0x01<br> ~~ee~~<br>~~PE~~<br>~~ee~~|RxBwMant parameter used during the AFC<br>~~PE~~|
||2-0<br>~~a~~<br>~~a~~|RxBwExpAfc<br>~~a~~<br>~~a~~|rw<br>~~a~~<br>~~ae~~<br>~~ae~~|0x03<br>~~a~~<br>~~ee~~<br>~~ee~~|RxBwExp parameter used during the AFC<br>~~a~~<br>~~ee~~|
|RegOokPeak<br>(0x14)|7-6<br>~~a~~<br>~~a~~|reserved<br>~~a~~<br>~~a~~|rw<br>~~a~~<br>~~ae ~~<br>~~ae~~|0x00<br>~~a~~<br> ~~ee~~<br>~~ee~~|reserved<br>~~a~~<br>~~ee~~|
||5<br>~~tos~~<br>~~To~~|BitSyncOn<br>~~tos~~<br>~~To~~|rw<br>~~ae ~~<br>~~tos~~|0x01<br> ~~ee~~<br>~~tos~~<br>~~ts~~|Enables the Bit Synchronizer.<br>0<br> Bit Sync disabled (not possible in Packet mode)<br>1<br> Bit Sync enabled<br>~~ee~~<br>~~tos~~<br>~~ts~~|
||4-3<br>~~To~~|OokThreshType<br>~~To~~|rw|0x01<br>~~ts~~|Selects the type of threshold in the OOK data slicer:<br>00<br> fixed threshold<br>10<br> average mode<br>01<br> peak mode (default)<br>11<br> reserved<br>~~ts~~>>|
||2-0<br>~~To~~|OokPeakTheshStep<br>~~To~~|rw|0x00<br>~~ts~~|Size of each decrement of the RSSI threshold in the OOK<br>demodulator:<br>000<br> 0.5 dB<br>001<br> 1.0 dB<br>010<br> 1.5 dB<br>011<br> 2.0 dB<br>100<br> 3.0 dB<br>101<br> 4.0 dB<br>110<br> 5.0 dB<br>111<br> 6.0 dB<br>~~ts~~<br>><br>><br>>><br>><br>>|
|RegOokFix<br>(0x15)|7-0|OokFixedThreshold|rw|0x0C|Fixed threshold for the Data Slicer in OOK mode<br>Floor threshold for the Data Slicer in OOK when Peak mode is<br>used|
|RegOokAvg<br>(0x16)|7-5|OokPeakThreshDec|rw<br>~~ae~~|0x00<br>~~ee~~|Period of decrement of the RSSI threshold in the OOK<br>demodulator:<br>000<br> once per chip<br>001<br> once every 2 chips<br>010<br> once every 4 chips<br>011<br> once every 8 chips<br>100<br> twice in each chip<br>101<br> 4 times in each chip<br>110<br> 8 times in each chip 111<br> 16 times in each chip<br>>><br>><br>><br>><br>><br>~~ee~~|
||4<br>~~a~~|reserved<br>~~a~~|rw<br>~~a~~<br>~~ae~~|0x01<br>~~a~~<br>~~ee~~|reserved<br>~~a~~<br>~~ee~~|
||3-2|OokAverageOffset|rw<br>~~ae ~~|0x00<br> ~~ee~~|Static offset added to the threshold in average mode in order to<br>reduce glitching activity (OOK only):<br>00<br> 0.0 dB<br>10<br> 4.0 dB<br>01<br> 2.0 dB<br>11<br> 6.0 dB<br>~~ee~~<br>>>|
||1-0|OokAverageThreshFilt|rw|0x02|Filter coefficients in average mode of the OOK demodulator:<br>00<br> fC≈ chip rate / 32.π<br>01<br> fC≈ chip rate / 8.π<br>10<br> fC≈ chip rate / 4.π<br>11<br>fC≈ chip rate / 2.π<br>>>|
|RegRes17<br>to<br>RegRes19|7-0|reserved|rw|0x47<br>0x32<br>0x3E|reserved. Keep the Reset values.|
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**RFM95/96/97/98(W)**
|**Name**<br>**(Address)**<br>~~a ee~~|**Bits**<br>~~ee~~<br>~~Po~~|**Variable Name**<br>~~ee~~<br>~~Po~~<br>~~rrrtt—sSS~~|**Mode**<br>~~ee~~<br>~~rrrtt—sSS~~|**Default**<br>**value**<br>~~ee~~<br>~~Se~~|**FSK/OOK Description**<br>~~ee~~|
|---|---|---|---|---|---|
|RegAfcFei<br>(0x1a)|7-5<br>~~Po~~|unused<br>~~Po~~<br>~~rrrtt—sSS~~|r<br>~~rrrtt—sSS~~|-<br>~~Se~~|unused|
||4<br>~~Po~~|AgcStart<br>~~Po~~<br>~~rrrtt—sSS~~|wt<br>~~rrrtt—sSS ~~|0x00<br> ~~Se~~|Triggers an AGC sequence when set to 1.|
||3|reserved|rw|0x00|reserved|
||2<br>~~oi:~~|unused<br>~~oi:~~|-<br>~~oi:~~|-<br>~~oi:~~|unused<br>~~oi:~~|
||1<br>~~oi:~~|AfcClear<br>~~oi:~~|wc<br>~~oi:~~|0x00<br>~~oi:~~|Clear AFC register set in Rx mode. Always reads 0.<br>~~oi:~~|
||0<br>~~oi:~~<br>~~a~~|AfcAutoClearOn<br>~~oi:~~<br>~~a~~|rw<br>~~oi:~~|0x00<br>~~oi:~~|Only valid if AfcAutoOn is set<br>0<br> AFC register is not cleared at the beginning of the automatic<br>AFC phase<br>1<br> AFC register is cleared at the beginning of the automatic<br>AFC phase<br>~~oi:~~<br>~~eee~~|
|RegAfcMsb<br>(0x1b)|7-0<br>~~a~~|AfcValue(15:8)<br>~~a~~|rw|0x00|MSB of the AfcValue, 2’s complement format. Can be used to<br>overwrite the current AFC value<br>~~eee~~|
|RegAfcLsb<br>(0x1c)|7-0<br>~~a~~<br>~~rn~~<br>~~a~~|AfcValue(7:0)<br>~~a~~<br>~~rn~~<br>~~a~~|rw<br>~~rn~~|0x00<br>~~rn~~|LSB of the AfcValue, 2’s complement format. Can be used to<br>overwrite the current AFC value<br>~~eee~~<br>~~rn~~<br>~~eee~~|
|RegFeiMsb<br>(0x1d)|7-0<br>~~a~~|FeiValue(15:8)<br>~~a~~|rw|-|MSB of the measured frequency offset, 2’s complement. Must be<br>read before RegFeiLsb.<br>~~eee~~|
|RegFeiLsb<br>(0x1e)|7-0<br>~~a~~<br>~~foi:~~|FeiValue(7:0)<br>~~a~~<br>~~foi:~~|rw<br>~~foi:~~|-<br>~~foi:~~|LSB of the measured frequency offset, 2’s complement<br>_Frequency error =_FeiValue x Fstep<br>~~eee~~<br>~~foi:~~|
|RegPreambleDetect<br>(0x1f)|7<br>~~foi:~~<br>~~WO~~|PreambleDetectorOn<br>~~foi:~~<br>~~WO~~|rw<br>~~foi:~~|0x01<br>*<br>~~foi:~~<br>~~ie~~|Enables Preamble detector when set to 1. The AGC settings<br>supersede this bit during the startup / AGC phase.<br>0<br> Turned off<br>1<br> Turned on<br>~~foi:~~<br>~~ie~~|
||6-5<br>~~WO~~|PreambleDetectorSize<br>~~WO~~|rw|0x01<br>*<br>~~ie~~|Number of Preamble bytes to detect to trigger an interrupt<br>00<br> 1 byte<br>10<br> 3 bytes<br>01<br> 2 bytes<br>11<br> Reserved<br>~~ie~~|
||4-0<br>~~WO~~|PreambleDetectorTol<br>~~WO~~|rw|0x0A<br>*<br>~~ie~~|Number or chip errors tolerated over PreambleDetectorSize.<br>4 chips per bit.<br>~~ie~~|
|RegRxTimeout1<br>(0x20)|7-0|TimeoutRxRssi|rw<br>~~ti~~|0x00<br>~~ti~~|_Timeout_interrupt is generated_TimeoutRxRssi_*16*Tbitafter<br>switching to Rx mode if_Rssi_interrupt doesn’t occur (i.e.<br>_RssiValue > RssiThreshold)_<br>0x00:_TimeoutRxRssi_is disabled<br>~~ti~~|
|RegRxTimeout2<br>(0x21)|7-0<br>~~toot~~|TimeoutRxPreamble<br>~~toot~~|rw <br>~~toot~~<br>~~ti~~<br>~~ti~~|0x00<br>~~toot~~<br>~~ti~~<br>~~ti~~|_Timeout_interrupt is generated_TimeoutRxPreamble_*16*Tbitafter<br>switching to Rx mode if_Preamble_interrupt doesn’t occur<br>0x00:_TimeoutRxPreamble_is disabled<br>~~toot~~<br>~~ti~~<br>~~ti~~|
|RegRxTimeout3<br>(0x22)|7-0<br>~~toot~~|TimeoutSignalSync<br>~~toot~~|rw <br>~~ti~~<br>~~toot~~<br>~~ti~~<br>~~rn~~|0x00<br>~~ti~~<br>~~toot~~<br>~~ti~~<br>~~rn~~|_Timeout_interrupt is generated_TimeoutSignalSync_*16*Tbitafter<br>the Rx mode is programmed, if_SyncAddress_doesn’t occur<br>0x00:_TimeoutSignalSync_is disabled<br>~~ti~~<br>~~toot~~<br>~~ti~~<br>~~ee~~|
|RegRxDelay<br>(0x23)|7-0<br>~~a~~|InterPacketRxDelay<br>~~a~~|rw<br>~~ti~~<br>~~a~~<br>~~rn~~|0x00<br>~~ti~~<br>~~a~~<br>~~rn~~|Additional delay before an automatic receiver restart is launched:<br>Delay = InterPacketRxDelay*4*Tbit<br>~~ti~~<br>~~a~~<br>~~ee~~|
|RC Oscillator registers<br>~~rn~~<br>~~ee~~||||||
Page 92
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**RFM95/96/97/98(W)**
|**Name**<br>**(Address)**<br>~~a ee~~|**Bits**<br>~~ee~~<br>~~a~~|**Variable Name**<br>~~ee~~|**Mode**<br>~~ee~~<br>~~ee~~|**Default**<br>**value**<br>~~ee~~<br>~~ee~~|**FSK/OOK Description**<br>~~ee~~|
|---|---|---|---|---|---|
|RegOsc<br>(0x24)|7-4<br>~~a~~|unused|r<br>~~ee~~|-<br>~~ee~~|unused|
||3<br>~~a~~<br>~~ti~~|RcCalStart<br>~~ti~~|wt<br>~~ee ~~<br>~~ti~~|0x00<br> ~~ee~~<br>~~ti~~|Triggers the calibration of the RC oscillator when set. Always<br>reads 0. RC calibration must be triggered in Standby mode.<br>~~ti~~|
||2-0<br>~~ti~~|ClkOut<br>~~ti~~|rw<br>~~ti~~|0x07<br>*<br>~~ti~~|Selects CLKOUT frequency:<br>000<br> FXOSC<br>001<br> FXOSC / 2<br>010<br> FXOSC / 4<br>011<br> FXOSC / 8<br>100<br> FXOSC / 16<br>101<br> FXOSC / 32<br>110<br> RC (automatically enabled)<br>111<br> OFF<br>~~ti~~|
|Packet Handling registers||||||
|RegPreambleMsb<br>(0x25)|7-0<br>~~nn~~|PreambleSize(15:8)<br>~~nn~~|rw<br>~~nn~~|0x00<br>~~nn~~|Size of the preamble to be sent (from_TxStartCondition_fulfilled).<br>(MSB byte)<br>~~nn~~|
|RegPreambleLsb<br>(0x26)|7-0<br>~~i:~~|PreambleSize(7:0)<br>~~i:~~|rw<br>~~i:~~|0x03<br>~~i:~~|Size of the preamble to be sent (from_TxStartCondition_fulfilled).<br>(LSB byte)<br>~~i:~~|
|RegSyncConfig<br>(0x27)|7-6<br>~~i:~~<br>~~Fo~~|AutoRestartRxMode<br>~~i:~~<br>~~FoUU~~|rw<br>~~i:~~<br>~~UU~~|0x02<br>~~i:~~<br>|Controls the automatic restart of the receiver after the reception of<br>a valid packet (PayloadReady or CrcOk):<br>00<br> Off<br>01<br> On, without waiting for the PLL to re-lock<br>10<br> On, wait for the PLL to lock (frequency changed)<br>11<br> reserved<br>~~i:~~<br>|
||5<br>~~Fo~~|PreamblePolarity<br>~~FoUU~~|rw<br>~~UUtlds~~|0x00<br>~~tlds~~<br>~~is~~|Sets the polarity of the Preamble<br>0<br> 0xAA (default)<br>1<br> 0x55<br>~~tlds~~<br>~~is~~|
||4<br>~~Fo~~<br>~~Too~~|SyncOn<br>~~Fo UU~~<br>~~Too~~|rw<br>~~UU~~<br>~~Too~~|0x01<br><br>~~Too~~<br>~~is~~<br>~~is~~|Enables the Sync word generation and detection:<br>0<br> Off<br>1<br> On<br><br>~~Too~~<br>~~is~~<br>~~is~~|
||3<br>~~To~~|FifoFillCondition<br>~~To~~|rw<br>~~To~~|0x00<br>~~is~~<br>~~To~~<br>~~is~~|FIFO filling condition:<br>0<br> if_SyncAddress_interrupt occurs<br>1<br> as long as_FifoFillCondition_is set<br>~~is~~<br>~~To~~<br>~~is~~|
||2-0<br>~~FU~~|SyncSize<br>~~FU~~|rw<br>~~FU~~|0x03<br>~~is~~<br>~~FU~~|Size of the Sync word:<br>(_SyncSize_+ 1) bytes, (_SyncSize_) bytes if_ioHomeOn_=1<br>~~is~~<br>~~FU~~|
|RegSyncValue1<br>(0x28)|7-0<br>~~a~~|SyncValue(63:56)<br>~~a~~|rw<br>~~a~~|0x01<br>*<br>~~a~~|1stbyte of Sync word. (MSB byte)<br>Used if_SyncOn_is set.<br>~~a~~|
|RegSyncValue2<br>(0x29)|7-0<br>~~a~~|SyncValue(55:48)<br>~~a~~|rw<br>~~a~~|0x01<br>*<br>~~a~~|2ndbyte of Sync word<br>Used if_SyncOn_is set and_(SyncSize +1)_>= 2.<br>~~a~~|
|RegSyncValue3<br>(0x2a)|7-0<br>~~a~~|SyncValue(47:40)<br>~~a~~|rw<br>~~a~~|0x01<br>*<br>~~a~~|3rdbyte of Sync word.<br>Used if_SyncOn_is set and_(SyncSize +1)_>= 3.<br>~~a~~|
|RegSyncValue4<br>(0x2b)|7-0<br>~~a~~|SyncValue(39:32)<br>~~a~~|rw<br>~~a~~|0x01<br>*<br>~~a~~|4thbyte of Sync word.<br>Used if_SyncOn_is set and_(SyncSize +1)_>= 4.<br>~~a~~|
Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com
**RFM95/96/97/98(W)**
|**Name**<br>**(Address)**<br>~~a ee~~|**Bits**<br>~~ee~~|**Variable Name**<br>~~ee~~|**Mode**<br>~~ee~~|**Default**<br>**value**<br>~~ee~~|**FSK/OOK Description**<br>~~ee~~|
|---|---|---|---|---|---|
|RegSyncValue5<br>(0x2c)|7-0<br>~~a~~|SyncValue(31:24)<br>~~a~~|rw<br>~~a~~|0x01<br>*<br>~~a~~|5thbyte of Sync word.<br>Used if_SyncOn_is set and_(SyncSize +1)_>= 5.<br>~~a~~|
|RegSyncValue6<br>(0x2d)|7-0<br>~~ht~~|SyncValue(23:16)<br>~~ht~~|rw<br>~~ht~~|0x01<br>*<br>~~ht~~|6thbyte of Sync word.<br>Used if_SyncOn_is set and_(SyncSize +1)_>= 6.<br>~~ht~~|
|RegSyncValue7<br>(0x2e)|7-0<br>~~a~~|SyncValue(15:8)<br>~~a~~|rw<br>|0x01<br>*<br>|7thbyte of Sync word.<br>Used if_SyncOn_is set and_(SyncSize +1)_>= 7.<br>|
|RegSyncValue8<br>(0x2f)|7-0<br>~~a.~~|SyncValue(7:0)<br>~~a.~~|rw<br>~~a.~~|0x01<br>*<br>~~a.~~|8thbyte of Sync word.<br>Used if_SyncOn_is set and_(SyncSize +1)_= 8.<br>~~a.~~|
|RegPacketConfig1<br>(0x30)|7<br>~~a.~~|PacketFormat<br>~~a.~~|rw<br>~~a.~~|0x01<br>~~a.~~|Defines the packet format used:<br>0<br> Fixed length<br>1<br> Variable length<br>~~a.~~|
||6-5|DcFree|rw|0x00|Defines DC-free encoding/decoding performed:<br>00<br> None (Off)<br>01<br> Manchester<br>10<br> Whitening<br>11<br> reserved|
||4|CrcOn|rw|0x01|Enables CRC calculation/check (Tx/Rx):<br>0<br> Off<br>1<br> On|
||3|CrcAutoClearOff|rw|0x00|Defines the behavior of the packet handler when CRC check fails:<br>0<br> Clear FIFO and restart new packet reception. No<br>_PayloadReady_interrupt issued.<br>1<br> Do not clear FIFO._PayloadReady_interrupt issued.|
||2-1|AddressFiltering|rw|0x00|Defines address based filtering in Rx:<br>00<br> None (Off)<br>01<br> Address field must match_NodeAddress_<br>10<br> Address field must match_NodeAddress_or<br>_BroadcastAddress_<br>11<br> reserved|
||0|CrcWhiteningType|rw|0x00|Selects the CRC and whitening algorithms:<br>0<br> CCITT CRC implementation with standard whitening<br>1<br> IBM CRC implementation with alternate whitening|
|RegPacketConfig2<br>(0x31)|7|unused|r|-|unused|
||6|DataMode|rw|0x01|Data processing mode:<br>0<br> Continuous mode<br>1<br> Packet mode|
||5|IoHomeOn|rw|0x00|Enables the io-homecontrol®compatibility mode<br>0<br> Disabled<br>1<br> Enabled|
||4<br>~~Se~~<br>~~a~~|IoHomePowerFrame<br>~~Se~~|rw<br>~~ae~~|0x00<br>~~ee~~|reserved - Linked to io-homecontrol®compatibility mode<br>~~ee~~|
||3<br>~~a~~<br>~~a~~|BeaconOn|rw<br>~~ae~~<br>~~ae~~|0x00<br>~~ee~~<br>~~ee~~|Enables the Beacon mode in Fixed packet format<br>~~ee~~|
||2-0<br>~~a~~<br>~~a~~|PayloadLength(10:8)|rw<br>~~ae ~~<br>~~ae~~|0x00<br> ~~ee~~<br>~~ee~~|Packet Length Most significant bits<br>~~ee~~|
Page 94 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com
**RFM95/96/97/98(W)**
|**Name**<br>**(Address)**<br>~~a ee~~|**Bits**<br>~~ee~~|**Variable Name**<br>~~ee~~|**Mode**<br>~~ee~~|**Default**<br>**value**<br>~~ee~~|**FSK/OOK Description**<br>~~ee~~|
|---|---|---|---|---|---|
|RegPayloadLength<br>(0x32)|7-0<br>~~i~~|PayloadLength(7:0)<br>~~i~~|rw<br>~~i~~<br>~~i~~|0x40<br>~~i~~<br>~~i~~|If PacketFormat = 0 (fixed), payload length.<br>If PacketFormat = 1 (variable), max length in Rx, not used in Tx.<br>~~i~~|
|RegNodeAdrs<br>(0x33)|7-0<br>~~a~~|NodeAddress<br>~~a~~|rw<br>~~a~~<br>~~i~~|0x00<br>~~a~~<br>~~i~~|Node address used in address filtering.<br>~~a~~|
|RegBroadcastAdrs<br>(0x34)|7-0<br>~~a~~<br>~~foi:~~|BroadcastAddress<br>~~a~~<br>~~foi:~~|rw<br>~~a~~<br>~~i~~<br>~~foi:~~|0x00<br>~~a~~<br>~~i~~<br>~~foi:~~|Broadcast address used in address filtering.<br>~~a~~<br>~~foi:~~|
|RegFifoThresh<br>(0x35)|7<br>~~foi:~~|TxStartCondition<br>~~foi:~~|rw<br>~~foi:~~|0x01<br>*<br>~~foi:~~|Defines the condition to start packet transmission:<br>0<br> _FifoLevel_(i.e. the number of bytes in the FIFO exceeds<br>_FifoThreshold)_<br>1<br> _FifoEmpty goes low_(i.e. at least one byte in the FIFO)<br>~~foi:~~|
||6<br>~~a~~|unused<br>~~a~~|r<br>~~a~~<br>~~a~~<br>~~hi~~|-<br>~~a~~<br>~~a~~<br>~~hi~~|unused<br>~~a~~<br>~~a~~|
||5-0<br>~~a~~|FifoThreshold<br>~~a~~|rw<br>~~a~~<br>~~hi~~|0x0f<br>~~a~~<br>~~hi~~|Used to trigger_FifoLevel_interrupt, when:<br>number of bytes in FIFO >= FifoThreshold + 1<br>~~a~~|
|Sequencer registers<br>~~hi~~||||||
|RegSeqConfig1<br>(0x36)|7|SequencerStart|wt<br>~~En~~|0x00<br>~~En~~|Controls the top level Sequencer<br>When set to ‘1’, executes the “Start” transition.<br>The sequencer can only be enabled when the chip is in Sleep or<br>Standby mode.|
||6<br>~~a~~|SequencerStop<br>~~a~~|wt<br>~~a~~<br>~~En~~|0x00<br>~~a~~<br>~~En~~|Forces the Sequencer Off.<br>Always reads ‘0’<br>~~a~~|
||5|IdleMode|rw<br>~~En~~|0x00<br>~~En~~|Selects chip mode during the state:<br>0: Standby mode<br>1: Sleep mode|
||4-3|FromStart|rw|0x00|Controls the Sequencer transition when_SequencerStart_is set to 1<br>in Sleep or Standby mode:<br>00: to LowPowerSelection<br>01: to Receive state<br>10: to Transmit state<br>11: to Transmit state on a_FifoLevel_interrupt|
||2|LowPowerSelection|rw|0x00|Selects the Sequencer LowPower state after a_to_<br>_LowPowerSelection_transition:<br>0: SequencerOff state with chip on Initial mode<br>1: Idle state with chip on_Standby_or_Sleep_mode depending on<br>_IdleMode_<br>_Note: Initial mode is the chip LowPower mode at_<br>_Sequencer Start._|
||1|FromIdle|rw|0x00|Controls the Sequencer transition from the Idle state on a T1<br>interrupt:<br>0: to Transmit state<br>1: to Receive state|
||0<br>~~Lt~~|FromTransmit<br>~~Lt~~|rw<br>~~Lt~~|0x00<br>~~Lt~~|Controls the Sequencer transition from the Transmit state:<br>0: to LowPowerSelection on a_PacketSent_interrupt<br>1: to Receive state on a_PacketSent_interrupt<br>~~Lt~~|
Page 95
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**RFM95/96/97/98(W)**
|**Name**<br>**(Address)**|**Bits**|**Variable Name**|**Mode**|**Default**<br>**value**|**FSK/OOK Description**|
|---|---|---|---|---|---|
|RegSeqConfig2<br>(0x37)|7-5|FromReceive|rw|0x00|Controls the Sequencer transition from the Receive state<br>000 and 111: unused<br>001: to PacketReceived state on a_PayloadReady_interrupt<br>010: to LowPowerSelection on a_PayloadReady_interrupt<br>011: to PacketReceived state on a_CrcOk_interrupt(1)<br>100: to SequencerOff state on a_Rssi_interrupt<br>101: to SequencerOff state on a_SyncAddress_interrupt<br>110: to SequencerOff state on a_PreambleDetect_interrupt<br>Irrespective of this setting, transition to LowPowerSelection on a<br>T2 interrupt<br>(1)If the CRC is wrong (corrupted packet, with CRC on but<br>_CrcAutoClearOn_=0), the_PayloadReady_interrupt will drive the<br>sequencer to RxTimeout state.|
||4-3|FromRxTimeout|rw|0x00|Controls the state-machine transition from the Receive state on a<br>_RxTimeout_interrupt (and on_PayloadReady_if FromReceive =<br>011):<br>00: to Receive State, via ReceiveRestart<br>01: to Transmit state<br>10: to LowPowerSelection<br>11: to SequencerOff state<br>_Note:_<br>_RxTimeout interrupt is a TimeoutRxRssi,_<br>_TimeoutRxPreamble or TimeoutSignalSync interrupt_|
||2-0|FromPacketReceived|rw|0x00|Controls the state-machine transition from the PacketReceived<br>state:<br>000: to SequencerOff state<br>001: to Transmit state on a_FifoEmpty_interrupt<br>010: to LowPowerSelection<br>011: to Receive via FS mode, if frequency was changed<br>100: to Receive state (no frequency change)|
|RegTimerResol<br>(0x38)|7-4|unused|r|-|unused|
||3-2|Timer1Resolution|rw|0x00|Resolution of Timer 1<br>00: Timer1 disabled<br>01: 64 us<br>10: 4.1 ms<br>11: 262 ms|
||1-0|Timer2Resolution|rw|0x00|Resolution of Timer 2<br>00: Timer2 disabled<br>01: 64 us<br>10: 4.1 ms<br>11: 262 ms|
|RegTimer1Coef<br>(0x39)|7-0<br>~~—~~|Timer1Coefficient<br>~~—~~|rw<br>~~—~~|0xf5<br>~~—~~|Multiplying coefficient for Timer 1<br>~~—~~|
|RegTimer2Coef<br>(0x3a)|7-0<br>~~a~~|Timer2Coefficient<br>~~a~~|rw<br>~~a~~|0x20<br>~~a~~|Multiplying coefficient for Timer 2<br>~~a~~|
Page 96
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**RFM95/96/97/98(W)**
|**Name**<br>**(Address)**<br>~~PL~~|**Bits**<br>~~PL~~|**Variable Name**<br>~~PL~~|**Mode**<br>~~PL~~|**Default**<br>**value**<br>~~PL~~|**FSK/OOK Description**<br>~~PL~~|
|---|---|---|---|---|---|
|Service registers||||||
|RegImageCal<br>(0x3b)|7<br>~~hii~~|AutoImageCalOn<br>~~hii~~|rw<br>~~hii~~|0x00<br>*<br>~~hii~~|Controls the Image calibration mechanism<br>0<br> Calibration of the receiver depending on the temperature is<br>disabled<br>1<br> Calibration of the receiver depending on the temperature<br>enabled.<br>~~hii~~|
||6<br>~~hii~~|ImageCalStart<br>~~hii~~|wt<br>~~hii~~|-<br>~~hii~~|Triggers the IQ and RSSI calibration when set in Standby mode.<br>~~hii~~|
||5<br>~~a~~|ImageCalRunning<br>~~a~~|r<br>~~a~~|0x00<br>~~a~~|Set to 1 while the Image and RSSI calibration are running.<br>Toggles back to 0 when the process is completed<br>~~a~~|
||4<br>~~TI:~~|unused<br>~~TI:~~|r<br>~~TI:~~|-<br>~~TI:~~|unused<br>~~TI:~~|
||3<br>~~TI:~~|TempChange<br>~~TI:~~|r<br>~~TI:~~|0x00<br>~~TI:~~|IRQ flag witnessing a temperature change exceeding<br>TempThreshold since the last Image and RSSI calibration:<br>0<br> Temperature change lower than TempThreshold<br>1<br> Temperature change greater than TempThreshold<br>~~TI:~~|
||2-1|TempThreshold|rw|0x01|Temperature change threshold to trigger a new I/Q calibration<br>00<br> 5 °C<br>01<br> 10 °C<br>10<br> 15 °C<br>11<br> 20 °C|
||0|TempMonitorOff|rw|0x00|Controls the temperature monitor operation:<br>0<br> Temperature monitoring done in all modes except Sleep and<br>Standby<br>1<br> Temperature monitoring stopped.|
|RegTemp<br>(0x3c)|7-0<br>~~tt,~~|TempValue<br>~~tt,~~|r<br>~~tt,~~<br>~~ee~~|-<br>~~tt,~~<br>~~ee~~|Measured temperature<br>-1°C per Lsb<br>Needs calibration for absolute accuracy<br>~~tt,~~|
|RegLowBat<br>(0x3d)|7-4<br>~~re~~|unused<br>~~re~~|r<br>~~re~~<br>~~ee~~|-<br>~~re~~<br>~~ee~~|unused<br>~~re~~|
||3|LowBatOn|rw<br>~~ee ~~|0x00<br> ~~ee~~|Low Battery detector enable signal<br>0<br> LowBat detector disabled<br>1<br> LowBat detector enabled|
||2-0|LowBatTrim|rw|0x02|Trimming of the LowBat threshold:<br>000<br> 1.695 V<br>001<br> 1.764 V<br>010<br> 1.835 V (d)<br>011<br> 1.905 V<br>100<br> 1.976 V<br>101<br> 2.045 V<br>110<br> 2.116 V<br>111<br> 2.185 V|
|Status registers||||||
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**RFM95/96/97/98(W)**
|**Name**<br>**(Address)**|**Bits**|**Variable Name**|**Mode**|**Default**<br>**value**|**FSK/OOK Description**|
|---|---|---|---|---|---|
|RegIrqFlags1<br>(0x3e)|7|ModeReady|r|-|Set when the operation mode requested in_Mode_, is ready<br>- Sleep: Entering Sleep mode<br>- Standby: XO is running<br>- FS: PLL is locked<br>- Rx: RSSI sampling starts<br>- Tx: PA ramp-up completed<br>Cleared when changing the operating mode.|
||6<br>~~A~~|RxReady<br>~~A~~|r<br>~~A~~|-<br>~~A~~|Set in Rx mode, after RSSI, AGC and AFC.<br>Cleared when leaving Rx.<br>~~A~~|
||5<br>~~A~~|TxReady<br>~~A~~|r<br>~~A~~|-<br>~~A~~|Set in Tx mode, after PA ramp-up.<br>Cleared when leaving Tx.<br>~~A~~|
||4<br>~~A~~|PllLock<br>~~A~~|r<br>~~A~~|-<br>~~A~~|Set (in FS, Rx or Tx) when the PLL is locked.<br>Cleared when it is not.<br>~~A~~|
||3<br>~~A~~|Rssi<br>~~A~~|rwc<br>~~A~~|-<br>~~A~~|Set in Rx when the_RssiValue_exceeds_RssiThreshold._<br>Cleared when leaving Rx or setting this bit to 1.<br>~~A~~|
||**2**<br>~~A~~|Timeout<br>~~A~~|r<br>~~A~~|-<br>~~A~~|Set when a timeout occurs<br>Cleared when leaving Rx or FIFO is emptied.<br>~~A~~|
||1<br>~~a~~|PreambleDetect<br>~~a~~|rwc<br>~~a~~|-<br>~~a~~|Set when the Preamble Detector has found valid Preamble.<br>bit clear when set to 1<br>~~a~~|
||0<br>~~Se~~|SyncAddressMatch<br>~~Se~~|rwc<br>~~Se~~<br>~~a~~|-<br>~~Se~~<br>~~a re~~|Set when Sync and Address (if enabled) are detected.<br>Cleared when leaving Rx or FIFO is emptied.<br>This bit is read only in Packet mode, rwc in Continuous mode<br>~~Se~~<br>~~re~~|
|RegIrqFlags2<br>(0x3f)|7<br>~~a~~|FifoFull<br>~~a~~|r<br>~~a~~<br>~~a~~|-<br>~~a~~<br>~~a re~~|Set when FIFO is full (i.e. contains 66 bytes), else cleared.<br>~~a~~<br>~~re~~|
||6<br>~~a~~|FifoEmpty<br>~~a~~|r<br>~~a ~~<br>~~a~~|-<br> ~~a re~~<br>~~a~~|Set when FIFO is empty, and cleared when there is at least 1 byte<br>in the FIFO.<br>~~re~~<br>~~a~~|
||5|FifoLevel|r|-|Set when the number of bytes in the FIFO strictly exceeds<br>_FifoThreshold_, else cleared.|
||4|FifoOverrun|rwc|-|Set when FIFO overrun occurs. (except in Sleep mode)<br>Flag(s) and FIFO are cleared when this bit is set. The FIFO then<br>becomes immediately available for the next transmission /<br>reception.|
||3<br>~~A~~|PacketSent<br>~~A~~|r<br>~~A~~|-<br>~~A~~|Set in Tx when the complete packet has been sent.<br>Cleared when exiting Tx<br>~~A~~|
||2<br>~~Toi},~~|PayloadReady<br>~~Toi},~~|r<br>~~Toi},~~|-<br>~~Toi},~~|Set in Rx when the payload is ready (i.e. last byte received and<br>CRC, if enabled and_CrcAutoClearOff_is cleared_,_is Ok). Cleared<br>when FIFO is empty.<br>~~Toi},~~|
||1<br>~~ee~~|CrcOk<br>~~ee~~|r<br>~~ee~~|-<br>~~ee~~|Set in Rx when the CRC of the payload is Ok. Cleared when FIFO<br>is empty.<br>~~ee~~|
||0<br>~~a~~|LowBat<br>~~a~~|rwc<br>~~a~~|-<br>~~a~~|Set when the battery voltage drops below the Low Battery<br>threshold. Cleared only when set to 1 by the user.<br>~~a~~|
|IO control registers||||||
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**RFM95/96/97/98(W)**
|**Name**<br>**(Address)**<br>~~ee~~|**Bits**<br>~~ee~~|**Variable Name**<br>~~ee~~|**Mode**<br>~~ee~~|**Default**<br>**value**<br>~~ee~~|**FSK/OOK Description**<br>~~ee~~|
|---|---|---|---|---|---|
|RegDioMapping1<br>(0x40)|7-6<br>~~——~~|Dio0Mapping<br>~~—— se~~|rw<br>~~se~~|0x00<br>~~se~~|Mapping of pins DIO0 to DIO5<br>See Table 23 for mapping in LoRa mode<br>See Table 27 for mapping in Continuous mode<br>See table 28 for mapping in Packet mode<br>~~se~~|
||5-4<br>~~——~~<br>~~P|~~|Dio1Mapping<br>~~—— se~~<br>~~P|~~<br>~~{|~~|rw<br>~~se~~<br>~~{||~~|0x00<br>~~se~~<br>~~|~~||
||3-2<br>~~——~~<br>~~P|~~<br>~~P|~~|Dio2Mapping<br>~~—— se~~<br>~~P|~~<br>~~{|~~<br>~~P|~~<br>~~{~~|rw<br>~~se~~<br>~~{||~~<br>~~{|~~|0x00<br>~~se~~<br>~~|~~<br>~~|~~||
||1-0<br>~~——~~<br>~~P|~~<br>~~P|~~<br>~~P|~~|Dio3Mapping<br>~~—— se~~<br>~~P|~~<br>~~{|~~<br>~~P|~~<br>~~{~~<br>~~P|~~<br>~~|{~~|rw<br>~~se~~<br>~~{| |~~<br>~~{|~~<br>~~|{|~~|0x00<br>~~se~~<br>~~|~~<br>~~|~~<br>~~|~~||
|RegDioMapping2<br>(0x41)|7-6<br>~~——~~<br>~~P|~~<br>~~P|~~<br>~~Pt]~~|Dio4Mapping<br>~~—— se~~<br>~~P|~~<br>~~{~~<br>~~P|~~<br>~~|{~~<br>~~Pt]~~<br>~~rt(id~~|rw<br>~~se~~<br>~~{ |~~<br>~~|{|~~<br>~~(id~~|0x00<br>~~se~~<br>~~|~~<br>~~|~~<br>~~(id~~||
||5-4<br>~~——~~<br>~~P|~~<br>~~Pt]~~|Dio5Mapping<br>~~—— se~~<br>~~P|~~<br>~~|{~~<br>~~Pt]~~<br>~~rt(id~~|rw<br>~~se~~<br>~~|{ |~~<br>~~(id~~|0x00<br>~~se~~<br>~~|~~<br>~~(id~~||
||3-1<br>~~Pt]~~|reserved<br>~~Pt]~~<br>~~rt(id~~|rw<br>~~(id~~|0x00<br>~~(id~~|reserved. Retain default value|
||0|MapPreambleDetect|rw|0x00|Allows the mapping of either_Rssi_Or_PreambleDetect_to the DIO<br>pins, as summarized on Table 27 and Table 28<br>0<br> _Rssi_interrupt<br>1<br> _PreambleDetect_interrupt|
|Version register||||||
|RegVersion<br>(0x42)|7-0<br>~~a~~|Version<br>~~a~~|r<br>|0x11<br>|Version code of the chip. Bits 7-4 give the full revision number;<br>bits 3-0 give the metal mask revision number.<br>|
|Additional registers<br>||||||
|RegPllHop<br>(0x44)|7<br>~~Si~~|FastHopOn<br>~~Si~~|rw<br>~~Si~~|0x00<br>~~Si~~|Bypasses the main state machine for a quick frequency hop.<br>Writing RegFrfLsb will trigger the frequency change.<br>0<br> Frf is validated when FSTx or FSRx is requested<br>1<br> Frf is validated triggered when RegFrfLsb is written<br>~~Si~~|
||6-0<br>~~Si~~|reserved<br>~~Si~~|rw<br>~~Si~~<br>~~ee~~|0x2d<br>~~Si~~<br>~~ee~~|reserved<br>~~Si~~|
|RegTcxo<br>(0x4b)|7-5<br>~~re~~|reserved<br>~~re~~|rw<br>~~re~~<br>~~ee~~|0x00<br>~~re~~<br>~~ee~~|reserved. Retain default value<br>~~re~~|
||4<br>~~ti~~<br>~~a~~|TcxoInputOn<br>~~ti~~|rw<br>~~ee ~~<br>~~ti~~<br>~~ae~~|0x00<br> ~~ee~~<br>~~ti~~<br>~~ee~~|Controls the crystal oscillator<br>0<br> Crystal Oscillator with external Crystal<br>1<br> External clipped sine TCXO AC-connected to XTA pin<br>~~ti~~|
||3-0<br>~~a~~<br>~~a~~|reserved|rw<br>~~ae~~<br>~~ee~~|0x09<br>~~ee~~<br>~~ee~~|Reserved. Retain default value.|
|RegPaDac<br>(0x4d)|7-3<br>~~a~~<br>~~a~~|reserved|rw<br>~~ae ~~<br>~~ee~~|0x10<br> ~~ee~~<br>~~ee~~|reserved. Retain default value|
||2-0<br>~~a~~<br>~~th~~|PaDac<br>~~th~~|rw<br>~~ee ~~<br>~~th~~|0x04<br> ~~ee~~<br>~~th~~|Enables the +20dBm option on PA_BOOST pin<br>0x04<br> Default value<br>0x07<br> +20dBm on PA_BOOST when OutputPower=1111<br>~~th~~|
|RegFormerTemp<br>(0x5b)|7-0<br>~~rn~~|FormerTemp<br>~~rn~~|rw<br>~~rn~~|-<br>~~rn~~|Temperature saved during the latest IQ (RSSI and Image)<br>calibrated. Same format as_TempValue_in_RegTemp_.<br>~~rn~~|
|RegBitrateFrac<br>(0x5d)|7-4<br>~~ha~~|unused<br>~~ha~~|r<br>~~ha~~|0x00<br>~~ha~~|unused<br>~~ha~~|
||3-0<br>~~ha~~|BitRateFrac<br>~~ha~~|rw<br>~~ha~~|0x00<br>~~ha~~|Fractional part of the bit rate divider (Only valid for FSK)<br>If_BitRateFrac_> 0 then:<br>_BitRate_= ---------------------------_F_----_X_----_O_-----_S_---_C_----------------------------**-**<br>_Bi tR ate_(15,0) + -_B_----_i_--_t_--_r_--_a_----_t_--_e_---_F_----_r_--_a_----_c_-<br>16<br>~~ha~~|
**RFM95/96/97/98(W)**
|~~Ce~~||||||
|---|---|---|---|---|---|
|**Name**<br>**(Address)**<br>~~Ce~~|**Bits**|**Variable Name**|**Mode**|**Default**<br>**value**|**FSK/OOK Description**|
|RegAgcRef<br>(0x61)<br>~~Ce~~|7-6|unused|r|-|unused|
||5-0|AgcReferenceLevel|rw<br>~~ee~~|0x19<br>~~ee~~|Sets the floor reference for all AGC thresholds:<br>AGC Reference[dBm]=<br>-174dBm+10*log(2*_RxBw_)+SNR+_AgcReferenceLevel_<br>SNR = 8dB, fixed value|
|RegAgcThresh1<br>(0x62)|7-5<br>~~ee~~|unused<br>~~ee~~|r<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|unused<br>~~ee~~|
||4-0<br>~~ee~~|AgcStep1<br>~~ee~~|rw<br>~~ee~~<br>~~ee~~<br>~~ee~~|0x0c<br>~~ee~~<br>~~ee~~<br>~~ee~~|Defines the 1st AGC Threshold<br>~~ee~~|
|RegAgcThresh2<br>(0x63)|7-4<br>~~a~~|AgcStep2<br>~~a~~|rw<br>~~a~~<br>~~ee~~<br>~~ee~~|0x04<br>~~a~~<br>~~ee~~<br>~~ee~~|Defines the 2nd AGC Threshold:<br>~~a~~|
||3-0<br>~~a~~|AgcStep3<br>~~a~~|rw<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~|0x0b<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~|Defines the 3rd AGC Threshold:<br>~~a~~|
|RegAgcThresh3<br>(0x64)|7-4<br>~~a~~|AgcStep4<br>~~a~~|rw<br>~~ee~~<br>~~a~~<br>~~ee~~|0x0c<br>~~ee~~<br>~~a~~<br>~~ee~~|Defines the 4th AGC Threshold:<br>~~a~~|
||3-0<br>~~ee~~|AgcStep5<br>~~ee~~|rw<br>~~ee~~<br>~~ee~~|0x0c<br>~~ee~~<br>~~ee~~|Defines the 5th AGC Threshold:<br>~~ee~~|
## **6.3. Band Specific Additional Registers**
The registers in the address space from 0x61 to 0x73 are specific for operation in the lower frequency bands (below 525 MHz), or in the upper frequency bands (above 860 MHz). Their programmed value may differ, and are retained when switching from lower to high frequency and vice-versa. The access to the band specific registers is granted by enabling or disabling the bit 3 LowFrequencyModeOn of the RegOpMode register. By default, the bit LowFrequencyModeOn is at ‘1’ indicating that the registers are configured for the low frequency band.
_Table 87 Low Frequency Additional Registers_
|**Name**<br>**(Address)**<br>~~a ee~~|**Bits**<br>~~ee~~|**Variable Name**<br>~~ee~~|**Mode**<br>~~ee~~|**Default**<br>**value**<br>~~ee~~|**Low Frequency Additional Registers**<br>~~ee~~|
|---|---|---|---|---|---|
|RegAgcRefLf<br>(0x61)|7-6|unused|r|-|unused|
||5-0<br>~~a~~|AgcReferenceLevel<br>~~a~~|rw<br>~~a~~|0x19<br>~~a~~|Sets the floor reference for all AGC thresholds:<br>AGC Reference[dBm]=<br>-174dBm+10*log(2*_RxBw_)+SNR+_AgcReferenceLevel_<br>SNR = 8dB, fixed value<br>~~a~~|
|RegAgcThresh1Lf<br>(0x62)|7-5<br>~~a~~|unused<br>~~a~~|r<br>~~a~~<br>~~ee~~|-<br>~~a~~<br>~~ee~~|unused<br>~~a~~|
||4-0<br>~~a~~|AgcStep1<br>~~a~~|rw<br>~~a~~<br>~~ee~~<br>~~ee~~|0x0c<br>~~a~~<br>~~ee~~<br>~~ee~~|Defines the 1st AGC Threshold<br>~~a~~|
|RegAgcThresh2Lf<br>(0x63)|7-4<br>~~ee~~|AgcStep2<br>~~ee~~|rw<br>~~ee~~<br>~~ee~~<br>~~ee~~|0x04<br>~~ee~~<br>~~ee~~<br>~~ee~~|Defines the 2nd AGC Threshold:<br>~~ee~~|
||3-0<br>~~ee~~|AgcStep3<br>~~ee~~|rw<br>~~ee~~<br>~~ee~~<br>~~ee~~|0x0b<br>~~ee~~<br>~~ee~~<br>~~ee~~|Defines the 3rd AGC Threshold:<br>~~ee~~|
|RegAgcThresh3Lf<br>(0x64)|7-4<br>~~a~~|AgcStep4<br>~~a~~|rw<br>~~a~~<br>~~ee~~|0x0c<br>~~a~~<br>~~ee~~|Defines the 4th AGC Threshold:<br>~~a~~|
||3-0|AgcStep5|rw<br>~~ee~~|0x0c<br>~~ee~~|Defines the 5th AGC Threshold:|
|RegPllLf<br>(0x70)|7-6<br>~~pt~~|PllBandwidth<br>~~pt~~|rw<br>~~pt~~|0x03<br>~~pt~~|Controls the PLL bandwidth:<br>00<br> 75 kHz<br>10<br> 225 kHz<br>01<br> 150 kHz<br>11<br> 300 kHz|
||5-0<br>~~pt~~|reserved<br>~~pt~~|rw<br>~~pt~~|0x10<br>~~pt~~|reserved. Retain default value|
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**RFM95/96/97/98(W)**
_Table 88 High Frequency Additional Registers_
|~~Ce~~||||||
|---|---|---|---|---|---|
|**Name**<br>**(Address)**<br>~~Ce~~|**Bits**|**Variable Name**|**Mode**|**Default**<br>**value**|**Low Frequency Additional Registers**|
|RegAgcRefHf<br>(0x61)<br>~~Ce~~|7-6|unused|r|-|unused|
||5-0|AgcReferenceLevel|rw|0x1c|Sets the floor reference for all AGC thresholds:<br>AGC Reference[dBm]=<br>-174dBm+10*log(2*_RxBw_)+SNR+_AgcReferenceLevel_<br>SNR = 8dB, fixed value|
|RegAgcThresh1Hf<br>(0x62)|7-5<br>~~ee~~|unused<br>~~ee~~|r<br>~~ee~~|-<br>~~ee~~|unused<br>~~ee~~|
||4-0<br>~~a~~|AgcStep1<br>~~a~~|rw|0x0e|Defines the 1st AGC Threshold|
|RegAgcThresh2Hf<br>(0x63)|7-4<br>~~a~~|AgcStep2<br>~~a~~|rw<br>~~ee~~|0x05<br>~~ee~~|Defines the 2nd AGC Threshold:|
||3-0<br>~~ee~~|AgcStep3<br>~~ee~~|rw<br>~~ee~~|0x0b<br>~~ee~~|Defines the 3rd AGC Threshold:<br>~~ee~~|
|RegAgcThresh3Hf<br>(0x64)|7-4<br>~~a~~|AgcStep4<br>~~a~~|rw|0x0c|Defines the 4th AGC Threshold:|
||3-0|AgcStep5|rw|0x0c|Defines the 5th AGC Threshold:|
|RegPllHf<br>(0x70)|7-6<br>~~pt~~|PllBandwidth<br>~~pt~~|rw<br>~~pt~~|0x03<br>~~pt~~|Controls the PLL bandwidth:<br>00<br> 75 kHz<br>10<br> 225 kHz<br>01<br> 150 kHz<br>11<br> 300 kHz|
||5-0<br>~~pt~~|reserved<br>~~pt~~|rw<br>~~pt~~|0x10<br>~~pt~~|reserved. Retain default value|
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**RFM95/96/97/98(W)**
## **6.4. LoRa[TM ] Mode Register Map**
This section details the RFM95/96/97/98(W) register mapping and the precise contents of each register in LoRa[TM ] mode.
It is essential to understand that the LoRa modem is controlled independently of the FSK modem. Therefore, care should be taken when accessing the registers, especially as some register may have the same name in LoRa or FSK mode.
The LoRa registers are only accessible when the device is set in Lora mode (and, in the same way, the FSK register are only accessible in FSK mode). However, in some cases, it may be necessary to access some of the FSK register while in LoRa mode. To this aim, the _AccesSharedReg_ bit was created in the _RegOpMode_ register. This bit, when set to ‘1’, will grant access to the FSK register 0x0D up to the register 0x3F. Once the setup has been done, it is strongly recommended to clear this bit so that LoRa register can be accessed normally.
Convention: r: read, w: write, c : set to clear and t: trigger.
|**Name**<br>**(Address)**<br>~~re~~|**Bits**<br>~~re~~|**Variable Name**<br>~~re~~|**Mode**<br>~~re~~|**Reset**<br>~~re~~|LoRaTM**Description**<br>~~re~~|
|---|---|---|---|---|---|
|RegFifo<br>(0x00)|7-0<br>~~ee~~|Fifo<br>~~ee~~|rw<br>~~ee~~|0x00<br>~~ee~~|LoRaTMbase-band FIFO data input/output. FIFO is cleared an<br>not accessible when device is in SLEEP mode<br>~~ee~~|
|Common Register Settings||||||
|RegOpMode<br>(0x01)|7|LongRangeMode|rw|0x0|0<br> FSK/OOK Mode<br>1<br> LoRaTMMode<br>This bit can be modified only in Sleep mode. A write operation on<br>other device modes is ignored.|
||6|AccessSharedReg|rw|0x0|This bit operates when device is in Lora mode; if set it allows<br>access to FSK registers page located in address space<br>(0x0D:0x3F) while in LoRa mode<br>0<br> Access LoRa registers page 0x0D: 0x3F<br>1<br> Access FSK registers page (in mode LoRa) 0x0D: 0x3F|
||5-4|reserved|r|0x00|reserved|
||3|LowFrequencyModeOn|rw|0x01|Access Low Frequency Mode registers<br>0<br> High Frequency Mode (access to HF test registers)<br>1<br> Low Frequency Mode (access to LF test registers)|
||2-0|Mode|rwt|0x01|Device modes<br>000<br> SLEEP<br>001<br> STDBY<br>010<br> Frequency synthesis TX (FSTX)<br>011<br> Transmit (TX)<br>100<br> Frequency synthesis RX (FSRX)<br>101<br> Receive continuous (RXCONTINUOUS)<br>110<br> receive single (RXSINGLE)<br>111<br> Channel activity detection (CAD)|
|(0x02)|7-0|reserved|r|0x00|-|
|(0x03)|7-0<br>~~a~~|reserved<br>~~a~~|r<br>~~a~~|0x00<br>~~a~~|-<br>~~a~~|
|(0x04)|7-0<br>~~a~~|reserved<br>~~a~~|rw<br>~~a~~|0x00<br>~~a~~|-<br>~~a~~|
|(0x05)|7-0<br>~~a~~|reserved<br>~~a~~|r<br>~~a~~<br>a|0x00<br>~~a~~|-<br>~~a~~|
|RegFrMsb<br>(0x06)|7-0<br>~~1~~|Frf(23:16)<br>~~1~~|rw|0x6c|MSB of RF carrier frequency|
|RegFrMid<br>(0x07)|7-0<br>~~pp~~|Frf(15:8)<br>~~pp~~|rw<br>~~pp~~|0x80<br>~~pp~~|MSB of RF carrier frequency<br>~~pp~~|
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**RFM95/96/97/98(W)**
|**Name**<br>**(Address)**|**Bits**|**Variable Name**|**Mode**|**Reset**|LoRaTM**Description**|
|---|---|---|---|---|---|
|RegFrLsb<br>(0x08)|7-0|Frf(7:0)|rwt|0x00|LSB of RF carrier frequency<br>_f_<br>= ----(--X----O-----S---C----)---·---_F_----_r_---_f_<br>RF<br>219<br>Resolution is 61.035 Hz if F(XOSC) = 32 MHz. Default value is<br>0x6c8000 = 434 MHz. Register values must be modified only<br>when device is in SLEEP or STAND-BY mode.|
|Registers for RF blocks||||||
|RegPaConfig<br>(0x09)|7<br>~~pps~~|PaSelect<br>~~pps~~|rw<br>~~pps~~|0x00<br>~~pps~~|Selects PA output pin<br>0<br> RFO pin. Output power is limited to +14 dBm.<br>1<br> PA_BOOST pin. Output power is limited to +20 dBm<br>~~pps~~|
||6-4<br>~~a~~|MaxPower<br>~~a~~|rw|0x04|Select max output power: Pmax=10.8+0.6*MaxPower [dBm]|
||3-0<br>~~ee~~|OutputPower<br>~~ee~~|rw<br>~~ee~~|0x0f<br>~~ee~~|Pout=Pmax-(15-OutputPower) if PaSelect = 0 (RFO pin)<br>Pout=17-(15-OutputPower)<br>if PaSelect = 1 (PA_BOOST pin)<br>~~ee~~|
|RegPaRamp<br>(0x0A)|7-5<br>~~a~~|unused<br>~~a~~|r<br>~~a~~|-<br>~~a~~|unused<br>~~a~~|
||4|reserved|rw|0x00|reserved|
||3-0<br>~~pe~~|PaRamp(3:0)<br>~~pe~~|rw<br>~~pe~~|0x09<br>~~pe~~|Rise/Fall time of ramp up/down in FSK<br>0000<br> 3.4 ms<br>0001<br> 2 ms<br>0010<br> 1 ms<br>0011<br> 500 us<br>0100<br> 250 us<br>0101<br> 125 us<br>0110<br> 100 us<br>0111<br> 62 us<br>1000<br> 50 us<br>1001<br> 40 us<br>1010<br> 31 us<br>1011<br> 25 us<br>1100<br> 20 us<br>1101<br> 15 us<br>1110<br> 12 us<br>1111<br> 10 us<br>~~pe~~|
|RegOcp<br>(0x0B|7-6<br>~~pe~~|unused<br>~~pe~~|r<br>~~pe~~|0x00<br>~~pe~~|unused<br>~~pe~~|
||5|OcpOn|rw|0x01|Enables overload current protection (OCP) for PA:<br>0<br> OCP disabled<br>1<br> OCP enabled|
||4-0|OcpTrim|rw|0x0b|Trimming of OCP current:<br>Imax= 45+5*OcpTrim [mA] if OcpTrim <= 15 (120 mA) /<br>Imax= -30+10*OcpTrim [mA] if 15 < OcpTrim <= 27 (130 to<br>240 mA)<br>Imax= 240mA for higher settings<br>Default Imax= 100mA|
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**RFM95/96/97/98(W)**
|**Name**<br>**(Address)**|**Bits**|**Variable Name**|**Mode**|**Reset**|LoRaTM**Description**|
|---|---|---|---|---|---|
|RegLna<br>(0x0C)|7-5|LnaGain|rwx|0x01|LNA gain setting:<br>000<br> not used<br>001<br> G1 = maximum gain<br>010<br> G2<br>011<br> G3<br>100<br> G4<br>101<br> G5<br>110<br> G6 = minimum gain<br>111<br> not used|
||4-3<br>~~Se~~<br>~~Sr~~|LnaBoostLf<br>~~Se~~<br>~~Sr~~|rw<br>a<br>ae|0x00|Low Frequency (RFI_LF) LNA current adjustment<br>00<br> Default LNA current<br>Other<br> Reserved<br>~~ee~~|
||2<br>~~a~~<br>~~Sr~~|reserved<br>~~a~~<br>~~Sr~~|rw<br>~~a~~<br>ae|0x00<br>~~a~~|reserved<br>~~a~~<br>~~ee~~|
||1-0<br>~~Sr~~|LnaBoostHf<br>~~Sr~~|rw<br>ae|0x00|High Frequency (RFI_HF) LNA current adjustment<br>00<br> Default LNA current<br>11<br> Boost on, 150% LNA current<br>~~ee~~|
|Lorapage registers||||||
|RegFifoAddrPtr<br>(0x0D)|7-0<br>~~ee~~|FifoAddrPtr<br>~~ee~~|rw<br>~~ee~~|0x00<br>~~ee~~|SPI interface address pointer in FIFO data buffer.<br>~~ee~~|
|RegFifoTxBaseAd<br>dr<br>(0x0E)|7-0|FifoTxBaseAddr|rw|0x80|write base address in FIFO data buffer for TX modulator|
|RegFifoRxBaseAd<br>dr<br>(0x0F)|7-0<br>~~Cs~~|FifoRxBaseAddr<br>|rw<br>|0x00<br>|read base address in FIFO data buffer for RX demodulator<br>|
|RegFifoRxCurrent<br>Addr<br>(0x10)|7-0<br>~~Cs~~|FifoRxCurrentAddr<br>|r<br>|n/a<br>|Start address (in data buffer) of last packet received<br>|
|RegIrqFlagsMask<br>(0x11)|7<br>~~Csee~~|RxTimeoutMask<br>~~ee~~|rw<br>~~ee~~|0x00<br>~~ee~~|Timeout interrupt mask: setting this bit masks the corresponding<br>IRQ in RegIrqFlags<br>~~ee~~|
||6<br>~~hn~~|RxDoneMask<br>~~hn~~|rw<br>~~hn~~|0x00<br>~~hn~~|Packet reception complete interrupt mask: setting this bit masks<br>the corresponding IRQ in RegIrqFlags<br>~~hn~~|
||5<br>~~ee~~|PayloadCrcErrorMask<br>~~ee~~|rw|0x00|Payload CRC error interrupt mask: setting this bit masks the<br>corresponding IRQ in RegIrqFlags|
||4<br>~~ee~~|ValidHeaderMask<br>~~ee~~|rw<br>~~ee~~|0x00<br>~~ee~~|Valid header received in Rx mask: setting this bit masks the<br>corresponding IRQ in RegIrqFlags<br>~~ee~~|
||3<br>~~ee~~|TxDoneMask<br>~~ee~~|rw|0x00|FIFO Payload transmission complete interrupt mask: setting this<br>bit masks the corresponding IRQ in RegIrqFlags|
||2<br>~~ee~~|CadDoneMask<br>~~ee~~|rw<br>~~ee~~|0x00<br>~~ee~~|CAD complete interrupt mask: setting this bit masks the<br>corresponding IRQ in RegIrqFlags<br>~~ee~~|
||1<br>~~ee~~|FhssChangeChannelM<br>ask<br>~~ee~~|rw<br>~~ee~~|0x00<br>~~ee~~|FHSS change channel interrupt mask: setting this bit masks the<br>corresponding IRQ in RegIrqFlags<br>~~ee~~|
||0<br>~~a~~|CadDetectedMask<br>~~a~~|rw|0x00|Cad Detected Interrupt Mask: setting this bit masks the<br>corresponding IRQ in RegIrqFlags|
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**RFM95/96/97/98(W)**
|**Name**<br>**(Address)**<br>~~a~~|**Bits**<br>|**Variable Name**<br>|**Mode**<br>|**Reset**<br>|LoRaTM**Description**<br>|
|---|---|---|---|---|---|
|RegIrqFlags<br>(0x12)<br>~~a~~|7<br>~~a~~|RxTimeout<br>~~a~~|rc<br>~~a~~|0x00<br>~~a~~|Timeout interrupt: a write operation clears IRQ<br>~~a~~|
||6<br>~~ee~~|RxDone<br>~~ee~~|rc<br>~~ee~~|0x00<br>~~ee~~|Packet reception complete interrupt: a write operation clears IRQ<br>~~ee~~|
||5<br>~~a~~|PayloadCrcError<br>~~a~~|rc|0x00|Payload CRC error interrupt: a write operation clears IRQ|
||4<br>~~ee~~|ValidHeader<br>~~ee~~|rc|0x00|Valid header received in Rx: a write operation clears IRQ|
||3<br>~~a~~|TxDone<br>~~a~~|rc|0x00|FIFO Payload transmission complete interrupt: a write operation<br>clears IRQ|
||2<br>~~a~~|CadDone<br>~~a~~|rc|0x00|CAD complete: write to clear: a write operation clears IRQ|
||1<br>~~a~~|FhssChangeChannel<br>~~a~~|rc<br>|0x00<br>|FHSS change channel interrupt: a write operation clears IRQ<br>|
||0<br>~~ee~~|CadDetected<br>~~ee~~|rc<br>~~ee~~|0x00<br>~~ee~~|Valid Lora signal detected during CAD operation: a write<br>operation clears IRQ<br>~~ee~~|
|RegRxNbBytes<br>(0x13)|7-0<br>~~a~~|FifoRxBytesNb<br>~~a~~|r|n/a|Number of payload bytes of latest packet received|
|RegRxHeaderCnt<br>ValueMsb<br>(0x14)|7-0<br>~~pp~~|ValidHeaderCntMsb(15:<br>8)<br>~~pp~~|r<br>|n/a<br>|Number of valid headers received since last transition into Rx<br>mode, MSB(15:8). Header and packet counters are reseted in<br>Sleep mode.<br>|
|RegRxHeaderCnt<br>ValueLsb<br>(0x15)|7-0<br>~~pp~~|ValidHeaderCntLsb(7:0)<br>~~pp~~|r<br>~~pp~~|n/a<br>~~pp~~|Number of valid headers received since last transition into Rx<br>mode, LSB(7:0). Header and packet counters are reseted in<br>Sleep mode.<br>~~pp~~|
|RegRxPacketCntV<br>alueMsb<br>(0x16)|7-0<br>~~pp~~|ValidPacketCntMsb(15:<br>8)<br>~~pp~~|rc|n/a|Number of valid packets received since last transition into Rx<br>mode, MSB(15:8). Header and packet counters are reseted in<br>Sleep mode.|
|RegRxPacketCntV<br>alueLsb<br>(0x17)|7-0<br>~~pp~~|ValidPacketCntLsb(7:0)<br>~~pp~~|r|n/a|Number of valid packets received since last transition into Rx<br>mode, LSB(7:0). Header and packet counters are reseted in<br>Sleep mode.|
|RegModemStat<br>(0x18)|7-5|RxCodingRate|r|n/a|Coding rate of last header received|
||4<br>~~_d~~<br>~~SS~~|ModemStatus<br>~~SS~~<br>~~a~~|r<br>~~ee~~<br>~~SS~~|‘1’<br>~~ee~~<br>~~SS~~|Modem clear<br>~~ee~~<br>~~SS~~|
||3<br>~~_d~~<br>~~SS~~||r<br>~~ee~~<br>~~SS~~|‘0’<br>~~ee~~<br>~~SS~~|Header info valid<br>~~ee~~<br>~~SS~~|
||2<br>~~_d~~<br>~~SS~~||r<br>~~ee~~<br>~~SS~~|‘0’<br>~~ee~~<br>~~SS~~|RX on-going<br>~~ee~~<br>~~SS~~|
||1<br>~~SS~~<br>~~_~~||r<br>~~SS~~<br>~~ee~~|‘0’<br>~~SS~~<br>~~ee~~|Signal synchronized<br>~~SS~~<br>~~ee~~|
||0<br>~~SS~~<br>~~a~~||r<br>~~SS~~<br>~~a~~|‘0’<br>~~SS~~<br>~~a~~|Signal detected<br>~~SS~~<br>~~a~~|
|RegPktSnrValue<br>(0x19)|7-0<br>~~a~~|PacketSnr<br>~~a~~|r<br>~~a~~|n/a<br>~~a~~|Estimation of SNR on last packet received.In two’s compliment<br>format mutiplied by 4.<br>_SNR_[_dB_]=_P_-----_a_---_c_---_k_---_e_---_t_--_S_---_n_----_r_--[---_t_--_w_----_o_----s---c---o---m-----p---l-i--m-----e--n---t---]<br>4<br>~~a~~|
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**RFM95/96/97/98(W)**
|**Name**<br>**(Address)**|**Bits**|**Variable Name**|**Mode**|**Reset**|LoRaTM**Description**|
|---|---|---|---|---|---|
|RegPktRssiValue<br>(0x1A)|7-0|PacketRssi|r|n/a|RSSI of the latest packet received (dBm)<br>_R SSI_[_dB m_]= – 137 +_Pack et Rssi_|
|RegRssiValue<br>(0x1B)|7-0|Rssi|r|n/a|Current RSSI value (dBm)<br>_RSSI_[_dBm_]= – 137 +_Rssi_|
|RegHopChannel<br>(0x1C)|7|PllTimeout|r|n/a|PLL failed to lock while attempting a TX/RX/CAD operation<br>1<br> PLL did not lock<br>0<br> PLL did lock|
||6|RxPayloadCrcOn|r|n/a|CRC Information extracted from the received packet header<br>0<br> Header indicates CRC off<br>1<br> Header indicates CRC on|
||5-0|FhssPresentChannel|r|n/a|Current value of frequency hopping channel in use.|
|RegModemConfig<br>1<br>(0x1D)|7-4|Bw|rw|0x07|Signal bandwidth:<br>0000<br> 7.8 kHz<br>0001<br> 10.4 kHz<br>0010<br> 15.6 kHz<br>0011<br> 20.8kHz<br>0100<br> 31.25 kHz<br>0101<br> 41.7 kHz<br>0110<br> 62.5 kHz<br>0111<br> 125 kHz<br>1000<br> 250 kHz<br>1001<br> 500 kHz<br>other values<br> reserved<br>In the lower band (169MHz), signal bandwidths 8&9 are not<br>supported)|
||3-1|CodingRate|rw|‘001’|Error coding rate<br>001<br> 4/5<br>010<br> 4/6<br>011<br> 4/7<br>100<br> 4/8<br>All other values<br> reserved<br>In implicit header mode should be set on receiver to determine<br>expected coding rate. See Section 4.1.1.3|
||0<br>~~a~~|ImplicitHeaderModeOn<br>~~a~~|rw<br>~~a~~|0x0<br>~~a~~|0<br> Explicit Header mode<br>1<br> Implicit Header mode<br>~~a~~|
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**RFM95/96/97/98(W)**
|**Name**<br>**(Address)**|**Bits**|**Variable Name**|**Mode**|**Reset**|LoRaTM**Description**|
|---|---|---|---|---|---|
|RegModemConfig<br>2<br>(0x1E)|7-4|SpreadingFactor|rw|0x07|SF rate (expressed as a base-2 logarithm)<br>6<br> 64 chips / symbol<br>7<br> 128 chips / symbol<br>8<br> 256 chips / symbol<br>9<br> 512 chips / symbol<br>10<br> 1024 chips / symbol<br>11<br> 2048 chips / symbol<br>12<br> 4096 chips / symbol<br>other values reserved.|
||3<br>~~FO~~|TxContinuousMode<br>~~FO ~~|rw<br> ~~EP~~<br>~~ii~~|0<br>~~EP~~<br>~~ii~~|0<br> normal mode, a single packet is sent<br>1<br> continuous mode, send multiple packets across the FIFO<br>(used for spectral analysis)<br>~~EP~~<br>~~ii~~|
||2<br>~~toot~~|RxPayloadCrcOn<br>~~toot~~|rw<br>~~toot~~<br>~~ii~~|0x00<br>~~toot~~<br>~~ii~~|CRC Information extracted from the received packet header<br>0<br> Header indicates CRC off<br>1<br> Header indicates CRC on<br>~~toot~~<br>~~ii~~|
||1-0<br>~~Ts...~~|SymbTimeout(9:8)<br>~~Ts...~~|rw<br>~~ii~~<br>~~Ts...~~|0x00<br>~~ii~~<br>~~Ts...~~|RX Time-Out MSB<br>~~ii~~<br>~~Ts...~~|
|RegSymbTimeoutL<br>sb<br>(0x1F)|7-0<br>~~Ts...~~|SymbTimeout(7:0)<br>~~Ts...~~|rw<br>~~Ts...~~|0x64<br>~~Ts...~~|RX Time-Out LSB<br>RX operation time-out value expressed as number of symbols:<br>_TimeOut_=_SymbT imeout_·_Ts_<br>~~Ts...~~|
|RegPreambleMsb<br>(0x20)|7-0<br>~~a~~<br>~~Pio~~|PreambleLength(15:8)<br>~~a~~<br>~~io~~<br>~~UT~~|rw<br>~~a~~<br>~~UTEE~~|0x0<br>~~a~~<br>~~EE~~|Preamble length MSB, = PreambleLength + 4.25 Symbols<br>See Section XX for more details.<br>~~a~~<br>~~EE~~|
|RegPreambleLsb<br>(0x21)|7-0<br>~~Pio~~|PreambleLength(7:0)<br>~~io~~<br>~~UT~~|rw<br>~~UTEE~~|0x8<br>~~EE~~|Preamble Length LSB<br>~~EE~~|
|RegPayloadLength<br>(0x22)|7-0<br>~~Pio~~<br>~~PE~~|PayloadLength(7:0)<br>~~io~~<br>~~UT~~<br>~~PE~~|rw<br>~~UT EE~~<br>~~PE~~|0x1<br>~~EE~~<br>~~PE~~|Payload length in bytes. The register needs to be set in implicit<br>header mode for the expected packet length. A 0 value is not<br>permitted<br>~~EE~~<br>~~PE~~|
|RegMaxPayloadLe<br>ngth<br>(0x23)|7-0<br>~~Eo~~|PayloadMaxLength(7:0) <br>~~Eo~~|rw<br>~~Eo~~|0xff<br>~~Eo~~|Maximum payload length; if header payload length exceeds<br>value a header CRC error is generated. Allows filtering of packet<br>with a bad size.<br>~~Eo~~|
|RegHopPeriod<br>(0x24)|7-0<br>~~a~~|FreqHoppingPeriod(7:0) <br>~~a~~|rw<br>|0x0<br>|Symbol periods between frequency hops. (0 = disabled). 1st hop<br>always happen after the 1st header symbol<br>|
|RegFifoRxByteAdd<br>r<br>(0x25)|7-0<br>~~FE~~|FifoRxByteAddrPtr<br>~~FE~~|r<br>~~FE~~<br>~~ee~~|n/a<br>~~FE~~<br>~~es~~|Current value of RX databuffer pointer (address of last byte<br>written by Lora receiver)<br>~~FE~~|
|RegModemConfig<br>3<br>(0x26)|7-4<br>~~ee~~|Unused<br>~~ee~~|r<br>~~ee~~<br>~~ee~~|0x00 <br>~~ee~~<br>~~es~~|<br>~~ee~~|
||3<br>~~a~~|MobileNode<br>~~a~~|rw<br>~~ee ~~<br>~~a~~|0x00<br> ~~es~~<br>~~a~~<br>~~IR~~|0<br> Use for static node<br>1<br> Use for mobile node<br>~~a~~<br>~~IR~~|
||2<br>~~PFT~~<br>~~a~~|AgcAutoOn<br>~~PFT~~<br>~~a~~|rw<br>~~PFT~~<br>ee|0x00<br>~~PFT~~<br>~~IR~~<br>ee|0<br> LNA gain set by register LnaGain<br>1<br> LNA gain set by the internal AGC loop<br>~~PFT~~<br>~~IR~~|
||1-0<br>~~i~~<br>~~a~~|Reserved<br>~~i~~<br>~~a~~|rw<br>~~i~~<br>ee|0x00<br>~~IR~~<br>~~i~~<br>ee|Reserved<br>~~IR~~<br>~~i~~|
|(0x27) - (0x3F)|-<br>~~a~~|Reserved<br>~~a~~|r<br>ee|n/a<br> ee|Reserved|
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**RFM95/96/97/98(W)**
## **7. Application Information**
## **7.1. Crystal Resonator Specification**
Table 89 shows the crystal resonator specification for the crystal reference oscillator circuit of the RFM95/96/97/98(W). This specification covers the full range of operation of the RFM95/96/97/98(W) and is employed in the reference design.
## _Table 89 Crystal Specification_
|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|FXOSC|XTAL Frequency||-|32|-|MHz|
|RS|XTAL Serial Resistance||-|30|TBC|ohms|
|C0|XTAL Shunt Capacitance||-|2.8|TBC|pF|
|CFOOT|External Foot Capacitance|On each pin XTA and XTB|8|15|22|pF|
|CLOAD|Crystal Load Capacitance||6|-|12|pF|
_Notes - the initial frequency tolerance, temperature stability and ageing performance should be chosen in accordance with the target operating temperature range and the receiver bandwidth selected._
- _the loading capacitance should be applied externally, and adapted to the actual Cload specification of the XTAL._
## **7.2. Reset of the Chip**
A power-on reset of the RFM95/96/97/98(W) is triggered at power up. Additionally, a manual reset can be issued by controlling pin 6.
## **7.2.1. POR**
If the application requires the disconnection of VDD from the RFM95/96/97/98(W), despite of the extremely low Sleep Mode current, the user should wait for 10 ms from of the end of the POR cycle before commencing communications over the SPI bus. Pin 7 (NRESET) should be left floating during the POR sequence.
_Figure 42. POR Timing Diagram_
Please note that any CLKOUT activity can also be used to detect that the chip is ready.
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**RFM95/96/97/98(W)**
## **7.2.2. Manual Reset**
A manual reset of the RFM95/96/97/98(W) is possible even for applications in which VDD cannot be physically disconnected. Pin
7 should be pulled low for a hundred microseconds, and then released. The user should then wait for 5 ms before using the chip.
_Figure 43. Manual Reset Timing Diagram_
_Note whilst pin 7 is driven low, an over current consumption of up to one milliampere can be seen on VDD._
## **7.3. Top Sequencer: Listen Mode Examples**
In this scenario, the circuit spends most of the time in Idle mode, during which only the RC oscillator is on. Periodically the receiver wakes up and looks for incoming signal. If a wanted signal is detected, the receiver is kept on and data are analyzed. Otherwise, if there was no wanted signal for a defined period of time, the receiver is switched off until the next receive period.
During Listen mode, the Radio stays most of the time in a Low Power mode, resulting in very low average power consumption. The general timing diagram of this scenario is given in Figure 44.
|Listenmode :|Listenmode :|ode :|ode :|ode :principle|ciple|ciple|||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|||||||Receive|Idle ( Sleep + RC )|Idle ( Sleep + RC )|Idle ( Sleep + RC )|Idle ( Sleep + RC )|Idle ( Sleep + RC )|Idle ( Sleep + RC )|Receive|Idle|
_Figure 44. Listen Mode: Principle_
An interrupt request is generated on a packet reception. The user can then take appropriate action.
Depending on the application and environment, there are several ways to implement Listen mode:
Wake on a _PreambleDetect_ interrupt Wake on _a SyncAddress_ interrupt Wake on _a PayloadReady_ interrupt
## **7.3.1. Wake on Preamble Interrupt**
In one possible scenario, the sequencer polls for a Preamble detection. If a preamble signal is detected, the sequencer is switched off and the circuit stays in Receive mode until the user switches modes. Otherwise, the receiver is switched off until the next Rx period.
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**RFM95/96/97/98(W)**
## _7.3.1.1. Timing Diagram_
When no signal is received, the circuit wakes every Timer1 + Timer2 and switches to Receive mode for a time defined by Timer2, as shown on the following diagram. If no Preamble is detected, it then switches back to Idle mode, i.e. Sleep mode with RC oscillator on.
No received sign al
**==> picture [539 x 150] intentionally omitted <==**
**----- Start of picture text -----**<br>
Receive Idle ( Sleep + RC ) Receive Idle<br>Timer2 Timer2<br>Timer1 Timer1 Timer1<br>——=—,<br>Figure 45. Listen Mode with No Preamble Received<br>If a Preamble signal is detected, the Sequencer is switched off. The PreambleDetect signal can be mapped to DIO4, in<br>order to request the user's attention. The user can then take appropriate action.<br>**----- End of picture text -----**<br>
**==> picture [440 x 172] intentionally omitted <==**
**----- Start of picture text -----**<br>
Received sign al<br>Sync<br>Preamble ( As long as T1 + 2 * T2 ) Payload Crc<br>Word<br>Idle ( Sleep + RC ) Timer2 Receive<br>Timer2<br>Timer1<br>Preamble<br>Detect<br>**----- End of picture text -----**<br>
_Figure 46. Listen Mode with Preamble Received_
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**RFM95/96/97/98(W)**
## _7.3.1.2. Sequencer Configuration_
The following graph shows Listen mode - Wake on _PreambleDetect_ state machine:
**==> picture [401 x 218] intentionally omitted <==**
**----- Start of picture text -----**<br>
State M ach ine<br>Sequencer Off<br>&<br>Initial mode = Sleep or Standby<br>Start bit set IdleMode = 1 : Sleep<br>LowPower LowPowerSelection = 1<br>Start Idle<br>FromStart = 00 [Selection ]<br>On T1<br>FromIdle = 1<br>On PreambleDetect<br>On T2 Receive FromReceive = 110 Sequencer Off<br>“cs<br>Figure 47. Wake On PreambleDetect State Machine<br>**----- End of picture text -----**<br>
This example configuration is achieved as follows:
_Table 90 Listen Mode with PreambleDetect Condition Settings_
|**Variable**|**Effect**|
|---|---|
|IdleMode|1:**Sleep**mode|
|FromStart|**Sleep**<br>00: To**LowPowerSelection**|
|LowPowerSelection|1: To**Idle**state|
|FromIdle|1: To**Receive**state on_T1_interrupt|
|FromReceive|interrupt<br>110: To**Sequencer Off**on_PreambleDetect_interrupt|
TTimer2 defines the maximum duration the chip stays in Receive mode as long as no Preamble is detected. In order to optimize power consumption, Timer2 must be set just long enough for Preamble detection.
TTimer1 + TTimer2 defines the cycling period, i.e. time between two Preamble polling starts. In order to optimize average power consumption, Timer1 should be relatively long. However, increasing Timer1 also extends packet reception duration.
In order to insure packet detection and optimize the receiver's power consumption, the received packet Preamble should be as long as TTimer1 + 2 x TTimer2.
An example of DIO configuration for this mode is described in the following table:
_Table 91 Listen Mode with PreambleDetect Condition Recommended DIO Mapping_
|**DIO**|**Value**|**Description**|
|---|---|---|
|0|01|**Description**<br>CrcOk|
|1|00|FifoLevel|
|3|00|FifoEmpty|
|4|11|FifoEmpty<br>PreambleDetect–Note:_MapPreambleDetect_bit should be set.|
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**RFM95/96/97/98(W)**
## **7.3.2. Wake on SyncAddress Interrupt**
In another possible scenario, the sequencer polls for a Preamble detection and then for a valid _SyncAddress_ interrupt. If events occur, the sequencer is switched off and the circuit stays in Receive mode until the user switches modes. Otherwise, the receiver is switched off until the next Rx period.
## _7.3.2.1. Timing Diagram_
Most of the sequencer running time is spent while no wanted signal is received. As shown by the timing diagram in Figure 48, the circuit wakes periodically for a short time, defined by RxTimeout. The circuit is in a Low Power mode for the rest of Timer1 + Timer2 (i.e. Timer1 + Timer2 - TrxTimeout)
**==> picture [514 x 98] intentionally omitted <==**
**----- Start of picture text -----**<br>
No wan ted sign al<br>Idle Receive Idle ( Sleep + RC ) Receive Idle<br>Timer2 Timer2<br>Timer1 Timer1 Timer1<br>RxTimeout RxTimeout<br>**----- End of picture text -----**<br>
_Figure 48. Listen Mode with no SyncAddress Detected_
If a preamble is detected before _RxTimeout_ timer ends, the circuit stays in Receive mode and waits for a valid _SyncAddress_ detection. If none is detected by the end of Timer2, Receive mode is deactivated and the polling cycle resumes, without any user intervention.
**==> picture [514 x 173] intentionally omitted <==**
**----- Start of picture text -----**<br>
Unw anted Sign al<br>Wrong<br>Preamble ( Preamble + Sync = T2 ) Payload Crc<br>Word<br>Idle Receive Idle Receive Idle<br>Timer2 Timer2<br>Timer1 RxTimeout Timer1 Timer1<br>RxTimeout<br>Preamble<br>Detect<br>**----- End of picture text -----**<br>
_Figure 49. Listen Mode with Preamble Received and no SyncAddress_
But if a valid Sync Word is detected, a _SyncAddress_ interrupt is fired, the Sequencer is switched off and the circuit stays in Receive mode as long as the user doesn't switch modes.
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**RFM95/96/97/98(W)**
**==> picture [47 x 7] intentionally omitted <==**
**----- Start of picture text -----**<br>
Wan ted Sign al<br>**----- End of picture text -----**<br>
**==> picture [517 x 157] intentionally omitted <==**
**----- Start of picture text -----**<br>
Sync<br>Preamble ( Preamble + Sync = T2 ) Payload Crc<br>Word<br>So<br>Idle Receive<br>Timer2<br>Timer1 RxTimeout<br>Preamble Sync Fifo<br>Detect Address Level<br>**----- End of picture text -----**<br>
_Figure 50. Listen Mode with Preamble Received & Valid SyncAddress_
## _7.3.2.2. Sequencer Configuration_
The following graph shows Listen mode - Wake on SyncAddress state machine:
**==> picture [452 x 370] intentionally omitted <==**
**----- Start of picture text -----**<br>
State M ach ine<br>Sequencer Off<br>&<br>Initial mode = Sleep or Standby<br>a IdleMode = 1 : Sleep<br>Start bit set<br>LowPower LowPowerSelection = 1<br>Start Idle<br>Selection<br>FromStart = 00<br>On T1<br>FromIdle = 1<br>FromRxTimeout = 10<br>On T2 On SyncAdress<br>RxTimeout Receive FromReceive = 101 Sequencer Off<br>On RxTimeout<br><< S<br>Figure 51. Wake On SyncAddress State Machine<br>Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com<br>**----- End of picture text -----**<br>
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**RFM95/96/97/98(W)**
This example configuration is achieved as follows:
_Table 92 Listen Mode with SyncAddress Condition Settings_
|**Variable**|**Effect**|
|---|---|
|IdleMode|1:**Sleep**mode|
|FromStart|**Sleep**<br>00: To**LowPowerSelection**|
|LowPowerSelection|1: To**Idle**state|
|FromIdle|1: To**Receive**state on_T1_interrupt|
|FromReceive|interrupt<br>101: To**Sequencer off**on_SyncAddress_interrupt|
|FromRxTimeout|**Sequencer off**_SyncAddress_interrupt<br>10: To**LowPowerSelection**|
TTimeoutRxPreamble should be set to just long enough to catch a preamble (depends on _PreambleDetectSize_ and _BitRate_ ). TTimer1 should be set to 64 µs (shortest possible duration).
TTimer2 is set so that TTimer1 + TTimer2 defines the time between two start of reception.
In order to insure packet detection and optimize the receiver power consumption, the received packet Preamble should be defined so that TPreamble = TTimer2 - TSyncAddress with TSyncAddress = ( _SyncSize_ + 1 _)_ *8/ _BitRate_ .
An example of DIO configuration for this mode is described in the following table:
_Table 93 Listen Mode with PreambleDetect Condition Recommended DIO Mapping_
|**DIO**|**Value**|**Description**|
|---|---|---|
|0|01|**Description**<br>CrcOk|
|1|00|FifoLevel|
|2|11|SyncAddress|
|3|00|SyncAddress<br>FifoEmpty|
|4|11|FifoEmpty<br>PreambleDetect–Note:_MapPreambleDetect_bit should be set.|
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**RFM95/96/97/98(W)**
## **7.4. Top Sequencer: Beacon Mode**
In this mode, a repetitive message is transmitted periodically. If the Payload being sent is always identical, and _PayloadLength_ is smaller than the FIFO size, the use of the _BeaconOn_ bit in _RegPacketConfig2_ together with the Sequencer permit to achieve periodic beacon without any user intervention.
## **7.4.1. Timing diagram**
In this mode, the Radio is switched to Transmit mode every TTimer1 + TTimer2 and back to Idle mode after _PacketSent_ , as shown in the diagram below. The Sequencer insures minimal time is spent in Transmit mode, and therefore power consumption is optimized.
**==> picture [460 x 142] intentionally omitted <==**
**----- Start of picture text -----**<br>
Beacon m ode<br>Idle Transmit Idle ( Sleep + RC ) Transmit Idle<br>Timer2 Timer2<br>Timer1 Timer1 Timer1<br>Packet Packet<br>Sent Sent<br>**----- End of picture text -----**<br>
_Figure 52. Beacon Mode Timing Diagram_
## **7.4.2. Sequencer Configuration**
The Beacon mode state machine is presented in the following graph. It is noticeable that the sequencer enters an infinite loop and can only be stopped by setting _SequencerStop_ bit in _RegSeqConfig1_ .
**==> picture [344 x 167] intentionally omitted <==**
**----- Start of picture text -----**<br>
State M ach ine<br>Sequencer Off<br>&<br>Initial mode = Sleep or Standby<br>Start bit set oo IdleMode = 1 : Sleep<br>LowPowerSelection = 1<br>LowPower<br>Start Idle<br>Selection<br>FromStart = 00<br>eo - ) @ On T1<br>FromIdle = 0<br>On PacketSent<br>FromTransmit = 0<br>Transmit<br>**----- End of picture text -----**<br>
_Figure 53. Beacon Mode State Machine_
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**RFM95/96/97/98(W)**
This example is achieved by programming the Sequencer as follows:
## _Table 94 Beacon Mode Settings_
|_Table 94 Beacon Mode Settings_||
|---|---|
|**Variable**|**Effect**|
|IdleMode|1:**Sleep**mode|
|FromStart|**Sleep**<br>00: To**LowPowerSelection**|
|LowPowerSelection|1: To**Idle**state|
|FromIdle|0: To**Transmit**state on_T1_interrupt|
|FromTransmit|interrupt<br>0: To**LowPowerSelection**on_PacketSent_interrupt|
TTimer1 + TTimer2 define the time between the start of two transmissions.
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**RFM95/96/97/98(W)**
## **7.5. Example CRC Calculation**
The following routine(s) may be implemented to mimic the CRC calculation of the RFM95/96/97/98(W):
_Figure 54. Example CRC Code_
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**RFM95/96/97/98(W)**
## **7.6. Example Temperature Reading**
The following routine(s) may be implemented to read the temperature and calibrate the sensor:
_Figure 55. Example Temperature Reading_
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**RFM95/96/97/98(W)**
## **7.7. Reference Design**
Please contact your representative for evaluation tools, reference designs and design assistance. Note that all schematics shown in this section are full schematics, listing ALL required components, including decoupling capacitors.
## _Figure 56:+20dBm Schematic_
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**RFM95/96/97/98(W)**
## **8. Packaging Information**
## **8.1. Package Outline Drawing**
The RFM95/96/97/98(W) is available as shown in Figure 56
UNIT ： mm
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**RFM95/96/97/98(W)**
## **15.2. Ordering Information**
— **DRFM95/96/97/98(W) 868 S2** Package ~~} 6~~ Operation Band
## Mode Type
**P/N: RFM95W-868S2 RFM95W module at 868MHz band, SMD Package P/N: RFM95W-915S2 RFM95W module at 915MHz band, SMD Package P/N: RFM96W-315S2 RFM96W module at 315MHz band, SMD Package P/N: RFM96W-433S2 RFM96W module at 433MHz band, SMD Package P/N: RFM97W-868S2 RFM97W module at 868MHz band, SMD Package P/N: RFM97W-915S2 RFM97W module at 915MHz band, SMD Package P/N: RFM98W-315S2 RFM98W module at 315MHz band, SMD Package P/N: RFM98W-433S2 RFM98W module at 433MHz band, SMD Package**
This document may contain preliminary information and is subject to change by Hope Microelectronics without notice. Hope Microelectronics assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or **HOPE MICROELECTRONICS CO.,LTD** implied license or indemnity under the intellectual property rights of Hope Add: 2/F, Building 3, Pingshan Private Microelectronics or third parties. The products described in this document Enterprise Science and Technology are not intended for use in implantation or other direct life support Park, Lishan Road, XiLi Town, Nanshan applications where malfunction may result in the direct physical harm or District, Shenzhen, Guangdong, China injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT Tel: 86-755-82973805 NOT LIMITED TO, THE IMPLIED WARRANTIES OF MECHANTABILITY Fax: 86-755-82973550 OR FITNESS FOR A ARTICULAR PURPOSE, ARE OFFERED IN THIS Email: sales@hoperf.com DOCUMENT. Website: http://www.hoperf.com http://www.hoperf.cn ©2006, HOPE MICROELECTRONICS CO.,LTD. All rights reserved.
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Updated at February 9, 2023
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