RFM69HW-868S2

**RFM69HW** 

## **RFM69HW ISM TRANSCEIVER MODULE V1.3** 

## **GENERAL DESCRIPTION** 

TAL 

ND 

The RFM69HW is a transceiver module capable of operation over a wide frequency range, including the 315,433,868 and 915MHz license-free ISM (Industry Scientific and Medical) frequency bands. All major RF communication parameters are programmable and most of them  can  be  dynamically set.  The  RFM69HW  offers the unique advantage of programmable narrow-band and wide- band communication modes. The RFM69HW is optimized for low power consumption while offering high RF output power and channelized operation. Compliance  ETSI and FCC regulations. 

In order to better use RFM69HW modules, this specification also involves a large number of the parameters and functions of its core chip RF69H's,including those IC pins which are not leaded out. All of these can help customers gain a better understanding of the performance of RFM69HW modules, and enhance the application skills. 

## **RFM69HW** 

## **APPLICATIONS** 

Automated Meter Reading 

## **KEY PRODUCT FEATURES** 

Wireless Sensor Networks 

Home and Building  Automation 

¢¢ +20 dBm - 100 mW Power Output Capability Wireless Alarm and Security Systems ¢ High Sensitivity: down to -120 dBm at 1.2 kbps ¢ Industrial Monitoring and Control 

; High Selectivity: 16-tap FIR Channel Filter Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm,[80 ] dB Blocking Immunity, no Image Frequency response 

Wireless M-BUS 

¢ Low current: Rx = 16 mA, 100nA register retention 

¢ Programmable Pout: -18 to +20 dBm in 1dB steps 

¢ Constant RF performance over voltage range of module 

¢ FSK Bit rates up to 300 kb/s 

¢ Fully integrated synthesizer with a resolution of 61 Hz 

¢ FSK, GFSK, MSK, GMSK and OOK modulations 

¢ Built-in Bit Synchronizer performing Clock Recovery 

¢ Incoming Sync Word Recognition 

¢ 115 dB+ Dynamic Range RSSI 

¢ Automatic RF Sense with ultra-fast AFC ¢ Packet engine with CRC-16, AES-128, 66-byte FIFO Built-in temperature sensor 

¢ Module Size:19.7X16mm 

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**RFM69HW** 

|**Table of Contents**<br>**Page**|**Table of Contents**<br>**Page**|
|---|---|
|1.|1.<br>GeneralDescription ................................................................................................................................................8|
||1.1. Simplified BlockDiagram.............................................................................................................................   8|
||1.2. Pin and MarkingDiagram.................................................................................................................................9|
||1.3.<br>Pin Description ....................................................................................................................................10|
|2.|Electrical Characteristics........................................................................................................................................11|
||2.1.<br>Absolute Maximum Ratings ..................................................................................................................11|
||2.2. Operating Range............................................................................................................................................ 11|
||2.3.<br>Module Specification ...........................................................................................................................12|
||2.3.1. Power Consumption .................................................................................................................................  12|
||2.3.2. Frequency Synthesis ................................................................................................................................  12|
||2.3.3. Receiver .....................................................................................................................................................13|
||2.3.4. Transmitter ...............................................................................................................................................  14|
||2.3.5. Digital Specification .................................................................................................................................   15|
|3.|3.<br>Module Description.................................................................................................................................................16|
||3.1.<br>Power Supply Strategy.............................................................................................................................16|
||3.2.<br>Frequency Synthesis..................................................................................................................................... 16|
||3.2.1. Reference Oscillator .................................................................................................................................   16|
||3.2.2. CLKOUT Output .......................................................................................................................................   17|
||3.2.3. PLL Architecture .......................................................................................................................................   17|
||3.2.4. Lock Time ....................................................................................................................................................18|
||3.2.5. Lock Detect Indicator................................................................................................................................    18|
||3.3.<br>Transmitter Description .................................................................................................................................. 19|
||3.3.1. Architecture Description ...........................................................................................................................   19|
||3.3.2. Bit Rate Setting ........................................................................................................................................   19|
||3.3.3. FSK Modulation .........................................................................................................................................  20|
||3.3.4. OOK Modulation .......................................................................................................................................   20|
||3.3.5. Modulation Shaping....................................................................................................................................  21|
||3.3.6. Power Amplifiers ......................................................................................................................................    21|
||3.3.7. High Power Settings .................................................................................................................................   22|
||3.3.8. Output Power Summary ............................................................................................................................  22|
||3.3.9. Over Current Protection ............................................................................................................................  22|
||3.4.<br>Receiver Description ..............................................................................................................................23|
||3.4.1. Block Diagram .......................................................................................................................................... 23|
||3.4.2. LNA - Single to Differential Buffer ............................................................................................................ 23|
||3.4.3. Automatic Gain Control ............................................................................................................................ 24|
||3.4.4. Continuous-Time DAGC........................................................................................................................... 25|
||3.4.5. Quadrature Mixer - ADCs - Decimators.................................................................................................... 26|
||3.4.6. Channel Filter ........................................................................................................................................... 26|
||3.4.7. DC Cancellation ....................................................................................................................................... 27|



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**RFM69HW** 

||3.4.8. Complex Filter -OOK...............................................................................................................................<br>27|
|---|---|
||3.4.9.RSSI......................................................................................................................................................... 27|
||3.4.10.Cordic..................................................................................................................................................... 28|
||3.4.11. FSK Demodulator ....................................................................................................................................29|
||3.4.12. OOKDemodulator.................................................................................................................................. 29|
||3.4.13. BitSynchronizer..................................................................................................................................... 31|
||3.4.14. Frequency Error Indicator....................................................................................................................... 31|
||3.4.15. Automatic FrequencyCorrection............................................................................................................ 32|
||3.4.16. Optimized Setup for Low Modulation IndexSystems............................................................................. 33|
||3.4.17. Temperature Sensor ............................................................................................................................... 34|
||3.4.18. Timeout Function.................................................................................................................................... 34|
|4.|Operating Modes....................................................................................................................................................35|
||4.1.<br>Basic Modes.................................................................................................................................................. 35|
||4.2.<br>Automatic Sequencer and Wake-UpTimes.................................................................................................. 35|
||4.2.1. Transmitter Startup Time ..........................................................................................................................36|
||4.2.2. Tx Start Procedure ................................................................................................................................... 36|
||4.2.3. Receiver Startup Time.............................................................................................................................. 36|
||4.2.4. Rx StartProcedure................................................................................................................................... 38|
||4.2.5. Optimized Frequency HoppingSequences.............................................................................................. 38|
||4.3.<br>ListenMode.....................................................................................................................................................39|
||4.3.1. Timings..................................................................................................................................................... 39|
||4.3.2. Criteria...................................................................................................................................................... 40|
||4.3.3. End of Cycle Actions ................................................................................................................................ 40|
||4.3.4. Stopping Listen Mode............................................................................................................................... 41|
||4.3.5. RC Timer Accuracy .................................................................................................................................. 41|
||4.4.<br>AutoModes ......................................................................................................................................................42|
|5.|DataProcessing......................................................................................................................................................43|
||5.1.<br>Overview .........................................................................................................................................................43|
||5.1.1. BlockDiagram.......................................................................................................................................... 43|
||5.1.2. Data Operation Modes ............................................................................................................................. 43|
||5.2.<br>Control BlockDescription.............................................................................................................................. 44|
||5.2.1. SPIInterface...............................................................................................................................................44|
||5.2.2. FIFO...........................................................................................................................................................45|
||5.2.3. Sync WordRecognition............................................................................................................................ 46|
||5.2.4. PacketHandler......................................................................................................................................... 47|
||5.2.5.Control ........................................................................................................................................................47|
||5.3.<br>Digital IO Pins Mapping................................................................................................................................. 47|
||5.3.1. DIO Pins Mapping in Continuous Mode ................................................................................................... 48|
||5.3.2. DIO Pins Mapping in Packet Mode .......................................................................................................... 48|
||5.4.<br>Continuous Mode...........................................................................................................................................49|
||5.4.1. GeneralDescription...................................................................................................................................49|
||5.4.2. TxProcessing............................................................................................................................................49|



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**RFM69HW** 

||5.4.3. Rx Processing .......................................................................................................................................... 50|
|---|---|
||5.5.<br>PacketMode ..................................................................................................................................................50|
||5.5.1. GeneralDescription...................................................................................................................................50|
||5.5.2. PacketFormat.......................................................................................................................................... 51|
||5.5.3. Tx Processing (without AES).................................................................................................................... 53|
||5.5.4. Rx Processing (without AES) ................................................................................................................... 54|
||5.5.5. AES...........................................................................................................................................................54|
||5.5.6. Handling Large Packets ........................................................................................................................... 56|
||5.5.7. PacketFiltering..........................................................................................................................................56|
||5.5.8. DC-Free DataMechanisms...................................................................................................................... 58|
|6.|Configuration and StatusRegisters...................................................................................................................... 60|
||6.1.<br>General Description ...................................................................................................................................... 60|
||6.2.<br>Common ConfigurationRegisters................................................................................................................. 63|
||6.3.<br>Transmitter Registers.....................................................................................................................................66|
||6.4.<br>ReceiverRegisters.........................................................................................................................................67|
||6.5.<br>IRQ and Pin Mapping Registers.................................................................................................................... 69|
||6.6.<br>Packet EngineRegisters............................................................................................................................... 71|
||6.7.<br>Temperature SensorRegisters..................................................................................................................... 74|
||6.8.<br>TestRegisters............................................................................................................................................... 74|
|7.|Application Information ......................................................................................................................................... 75|
||7.1.<br>Crystal ResonatorSpecification.................................................................................................................... 75|
||7.2.<br>Reset of the Module ...................................................................................................................................... 75|
||7.2.1.POR.......................................................................................................................................................... ..75|
||7.2.2. Manual Reset..............................................................................................................................................76|
||7.3.<br>Reference Design ......................................................................................................................................... 77|
|8.|PackagingInformation.......................................................................................................................................... 78|
||8.1.<br>Package Outline Drawing.............................................................................................................................. 78|
|9.|OrderingInformation............................................................................................................................................. 79|



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**RFM69HW** 

## **Index of Figures Page** 

|Figure 1.  Block Diagram|Figure 1.  Block Diagram|Figure 1.  Block Diagram................................................................................................................................................8|
|---|---|---|
|Figure 2.  Pin Diagram|Figure 2.  Pin Diagram|Figure 2.  Pin Diagram....................................................................................................................................................9|
|Figure 3.  Marking Diagram|Figure 3.  Marking Diagram|Figure 3.  Marking Diagram............................................................................................................................................9|
|Figure 4.  TCXO Connection|Figure 4.  TCXO Connection|Figure 4.  TCXO Connection........................................................................................................................................16|
|Figure 5.  Transmitter Block Diagram|Figure 5.  Transmitter Block Diagram|Figure 5.  Transmitter Block Diagram...........................................................................................................................19|
|Figure 6.  Output Power Curves|Figure 6.  Output Power Curves|Figure 6.  Output Power Curves...................................................................................................................................22|
|Figure 7.  Receiver Block Diagram|Figure 7.  Receiver Block Diagram|Figure 7.  Receiver Block Diagram...............................................................................................................................23|
|Figure 8.  AGC Thresholds Settings|Figure 8.  AGC Thresholds Settings|Figure 8.  AGC Thresholds Settings.............................................................................................................................24|
|Figure 9.  RSSI Dynamic Curve|Figure 9.  RSSI Dynamic Curve|Figure 9.  RSSI Dynamic Curve....................................................................................................................................28|
|Figure 10.  Cordic Extraction|Figure 10.  Cordic Extraction|Figure 10.  Cordic Extraction........................................................................................................................................28|
|Figure 11.  OOK Peak Demodulator Description|Figure 11.  OOK Peak Demodulator Description|Figure 11.  OOK Peak Demodulator Description..........................................................................................................29|
|Figure 12.  Floor Threshold Optimization|Figure 12.  Floor Threshold Optimization|Figure 12.  Floor Threshold Optimization.....................................................................................................................30|
|Figure 13.  Bit Synchronizer Description|Figure 13.  Bit Synchronizer Description|Figure 13.  Bit Synchronizer Description......................................................................................................................31|
|Figure 14.  FEI Process|Figure 14.  FEI Process|Figure 14.  FEI Process................................................................................................................................................32|
|Figure 15.  Optimized AFC (AfcLowBetaOn=1)|Figure 15.  Optimized AFC (AfcLowBetaOn=1)|Figure 15.  Optimized AFC (AfcLowBetaOn=1)............................................................................................................33|
|Figure 16.  Temperature Sensor Response|Figure 16.  Temperature Sensor Response|Figure 16.  Temperature Sensor Response.................................................................................................................34|
|Figure 17.  Tx Startup, FSK and OOK|Figure 17.  Tx Startup, FSK and OOK|Figure 17.  Tx Startup, FSK and OOK..........................................................................................................................36|
|Figure 18.  Rx Startup - No AGC, no AFC|Figure 18.  Rx Startup - No AGC, no AFC|Figure 18.  Rx Startup - No AGC, no AFC....................................................................................................................37|
|Figure 19.  Rx Startup - AGC, no AFC|Figure 19.  Rx Startup - AGC, no AFC|Figure 19.  Rx Startup - AGC, no AFC.........................................................................................................................37|
|Figure 20.  Rx Startup - AGC and AFC|Figure 20.  Rx Startup - AGC and AFC|Figure 20.  Rx Startup - AGC and AFC........................................................................................................................37|
|Figure 21.  Listen Mode Sequence (no wanted signal is received)|Figure 21.  Listen Mode Sequence (no wanted signal is received)|Figure 21.  Listen Mode Sequence (no wanted signal is received)..............................................................................39|
|Figure 22.  Listen Mode Sequence (wanted signal is received)|Figure 22.  Listen Mode Sequence (wanted signal is received)|Figure 22.  Listen Mode Sequence (wanted signal is received)...................................................................................41|
|Figure 23.  Auto Modes of Packet Handler|Figure 23.  Auto Modes of Packet Handler|Figure 23.  Auto Modes of Packet Handler...................................................................................................................42|
|Figure 24.  RFM69HW Data Processing Conceptual View|Figure 24.  RFM69HW Data Processing Conceptual View|Figure 24.  RFM69HW Data Processing Conceptual View...........................................................................................43|
|Figure 25.  SPI Timing Diagram (single access)|Figure 25.  SPI Timing Diagram (single access)|Figure 25.  SPI Timing Diagram (single access)..........................................................................................................44|
|Figure 26.  FIFO and Shift Register (SR)|Figure 26.  FIFO and Shift Register (SR)|Figure 26.  FIFO and Shift Register (SR).....................................................................................................................45|
|Figure 27.  FifoLevel IRQ Source Behavior|Figure 27.  FifoLevel IRQ Source Behavior|Figure 27.  FifoLevel IRQ Source Behavior..................................................................................................................46|
|Figure 28.  Sync Word Recognition|Figure 28.  Sync Word Recognition|Figure 28.  Sync Word Recognition..............................................................................................................................47|
|Figure 29.  Continuous Mode Conceptual View|Figure 29.  Continuous Mode Conceptual View|Figure 29.  Continuous Mode Conceptual View...........................................................................................................49|
|Figure 30.  Tx Processing in Continuous Mode|Figure 30.  Tx Processing in Continuous Mode|Figure 30.  Tx Processing in Continuous Mode............................................................................................................49|
|Figure 31.  Rx Processing in Continuous Mode|Figure 31.  Rx Processing in Continuous Mode|Figure 31.  Rx Processing in Continuous Mode...........................................................................................................50|
|Figure 32.  Packet Mode Conceptual View|Figure 32.  Packet Mode Conceptual View|Figure 32.  Packet Mode Conceptual View...................................................................................................................51|
|Figure 33.  Fixed Length Packet Format|Figure 33.  Fixed Length Packet Format|Figure 33.  Fixed Length Packet Format......................................................................................................................52|
|Figure 34.  Variable Length Packet Format|Figure 34.  Variable Length Packet Format|Figure 34.  Variable Length Packet Format..................................................................................................................52|
|Figure 35.  Unlimited Length Packet Format|Figure 35.  Unlimited Length Packet Format|Figure 35.  Unlimited Length Packet Format................................................................................................................53|
|Figure 36.  CRC Implementation|Figure 36.  CRC Implementation|Figure 36.  CRC Implementation..................................................................................................................................58|
|Figure 37.  Manchester Encoding/Decoding|Figure 37.  Manchester Encoding/Decoding|Figure 37.  Manchester Encoding/Decoding.................................................................................................................58|
|Figure 38.  Data Whitening|Figure 38.  Data Whitening|Figure 38.  Data Whitening...........................................................................................................................................59|
|Figure 39.  POR Timing Diagram|Figure 39.  POR Timing Diagram|Figure 39.  POR Timing Diagram.................................................................................................................................75|
|Figure 40.  Manual Reset Timing Diagram|Figure 40.  Manual Reset Timing Diagram|Figure 40.  Manual Reset Timing Diagram...................................................................................................................76|



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**RFM69HW** 

Figure 41.  +20dBm Schematic .................................................................................................................................... 77 Figure 42.  Package Outline Drawing ........................................................................................................................... 

**Index of Tables Page** 

**==> picture [527 x 460] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||
|---|---|
|Table 1. RFM69HW Pinouts|........................................................................................................................................ 10|
|Table 2. Absolute Maximum Ratings ............................................................................................................................ 11|
|Table 3. Operating Range|............................................................................................................................................ 11|
|Table 4. Power Consumption Specification .................................................................................................................. 12|
|Table 5. Frequency Synthesizer Specification .............................................................................................................. 12|
|Table 6. Receiver Specification|.................................................................................................................................... 13|
|Table 7. Transmitter Specification|................................................................................................................................ 14|
|Table 8. Digital Specification|........................................................................................................................................ 15|
|Table 9. Bit Rate Examples|.......................................................................................................................................... 20|
|Table 10. Power Amplifier Mode Selection Truth Table|............................................................................................... 21|
|Table 11. High Power Settings|..................................................................................................................................... 22|
|Table 12. LNA Gain Settings|........................................................................................................................................ 23|
|Table 13. Receiver Performance Summary .................................................................................................................. 25|
|Table 14. Available RxBw Settings ............................................................................................................................... 26|
|Table 15. Available DCC Cutoff Frequencies ............................................................................................................... 27|
|Table 16. Basic Transceiver Modes|............................................................................................................................. 35|
|Table 17. Range of Durations in Listen Mode|.............................................................................................................. 39|
|Table 18. Signal Acceptance Criteria in Listen Mode ................................................................................................... 40|
|Table 19. End of Listen Cycle Actions .......................................................................................................................... 40|
|Table 20. Status of FIFO when Switching Between Different Modes of the Module ................................................... . 46|
|Table 21. DIO Mapping, Continuous Mode|.................................................................................................................. 48|
|Table 22. DIO Mapping, Packet Mode|......................................................................................................................... 48|
|Table 23. Registers Summary|...................................................................................................................................... 60|
|Table 24. Common Configuration Registers ................................................................................................................. 63|
|Table 25. Transmitter Registers|................................................................................................................................... 66|
|Table 26. Receiver Registers|....................................................................................................................................... 67|
|Table 27. IRQ and Pin Mapping Registers|................................................................................................................... 69|
|Table 28. Packet Engine Registers|.............................................................................................................................. 71|
|Table 29. Temperature Sensor Registers ..................................................................................................................... 74|
|Table 30. Test Registers|.............................................................................................................................................. 74|
|Table 31. Crystal Specification|..................................................................................................................................... 75|

**----- End of picture text -----**<br>


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**RFM69HW** 

## **Acronyms** 

|BOM|Bill Of Materials|LSB|Least Significant Bit|
|---|---|---|---|
|BR|Bit Rate|MSB|Most Significant Bit|
|BW|Bandwidth|NRZ|Non Return to Zero|
|CCITT|Comité Consultatif International|OOK|On Off Keying|
||Téléphonique et Télégraphique - ITU|||
|CRC|Cyclic Redundancy Check|PA|Power Amplifier|
|DAC|Digital to Analog Converter|PCB|Printed Circuit Board|
|ETSI|European Telecommunications Standards|PLL|Phase-Locked Loop|
||Institute|||
|FCC|Federal Communications Commission|POR|Power On Reset|
|Fdev|Frequency Deviation|RBW|Resolution BandWidth|
|FIFO|First In First Out|RF|Radio Frequency|
|FIR|Finite Impulse Response|RSSI|Received Signal Strength Indicator|
|FS|Frequency Synthesizer|Rx|Receiver|
|FSK|Frequency Shift Keying|SAW|Surface Acoustic Wave|
|GUI|Graphical User Interface|SPI|Serial Peripheral Interface|
|IC|Integrated Circuit|SR|Shift Register|
|ID|IDentificator|Stby|Standby|
|IF|Intermediate Frequency|Tx|Transmitter|
|IRQ|Interrupt ReQuest|uC|Microcontroller|
|ITU|International Telecommunication Union|VCO|Voltage Controlled Oscillator|
|LFSR|Linear Feedback Shift Register|XO|Crystal Oscillator|
|LNA|Low Noise Amplifier|XOR|eXclusive OR|
|LO|Local Oscillator|||



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**RFM69HW** 

This product datasheet contains a detailed description of the RFM69HW performance and functionality. 

## **1. General Description** 

The RFM69HW is a transceiver module ideally suited for today's high performance ISM band RF applications. It is intended for use as high-performance, low-cost FSK and OOK RF transceiver for robust frequency agile, half-duplex bidirectional RF links, and where stable and constant RF performance is required over the full operating range of the device down to 1.8V. 

The RFM69HW is intended for applications over a wide frequency range, including the 315MHz,433 MHz,868 MHz and 915MHz ISM bands. Coupled with a link budget in excess of 140 dB, the advanced system features of the RFM69HW include a 66 byte TX/RX FIFO, configurable automatic packet handler, listen mode, temperature sensor and configurable DIOs which greatly enhance system flexibility whilst at the same time significantly reducing MCU requirements. 

The RFM69HW complies with both ETSI and FCC regulatory requirements and is available 

## **1.1.  Simplified Block Diagram** 

_Figure 1.  Block Diagram_ 

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**RFM69HW** 

## **1.2.  Pin and Marking Diagram** 

The following diagram shows the pin arrangement of the top view. 

DIO1 JO == DIO2 JO | DIO3 JR 108 JO a7 50 3.3v QL 

_Figure 3.  Marking Diagram_ 

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**RFM69HW** 

## **1.3.  Pin Description** 

## _Table 1 RFM69HW Pinouts_ 

|**Number**|**Name**|**Type**|**Description**<br>~~**S**~~|
|---|---|---|---|
|1<br>~~a~~|RESET|I/O|~~**S**~~<br>Reset trigger input|
|2<br>~~a~~|DIO0|I/O|Digital I/O, software configured|
|3<br>~~a~~|DIO1|I/O|Digital I/O, software configured|
|4<br>~~a~~|DIO2|I/O|Digital I/O, software configured|
|5<br>~~a~~|DIO3<br>~~a~~|I/O|Digital I/O, software configured|
|6<br>~~a~~<br>~~a~~|DIO4<br>~~a~~|I/O|Digital I/O, software configured|
|7<br>~~a~~<br>~~a~~|DIO5|I/O|Digital I/O, software configured|
|8<br>~~a~~<br>~~a~~|3.3V|-|Supply voltage|
|9<br>~~a~~|GND|-|Ground|
|10<br>~~a~~|ANA||RF signal output/input.|
|11<br>~~a~~|GND|-|Ground|
|12<br>~~a~~|SCK<br>~~a~~|I|SPI Clock input|
|13<br>~~a~~|MISO|O|SPI Data output|
|14<br>~~a~~|MOSI<br>|I<br>|SPI Data input<br>|
|15<br>~~ee~~|NSS<br>~~ee~~|I<br>~~ee~~|SPI Chip select input<br>~~ee~~|
|16<br>~~a~~|NC|-|Connect to GND|



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**RFM69HW** 

## **2. Electrical Characteristics** 

## **2.1.  Absolute Maximum Ratings** 

Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for extended periods may affect device reliability. 

## _Table 2 Absolute Maximum Ratings_ 

|**Symbol**|**Description**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|VDDmr|Supply Voltage|-0.5|3.9|V|
|Tmr|Temperature|-55|+115|° C|
|Tj|Junction temperature|-|+125|° C|
|Pmr|RF Input Level|-|+6|dBm|
|DC_20dBm|Duty Cycle of transmission at +20dBm output|-|1|%|
|VSWR_20dBm|Maximum VSWR at antenna port|-|3:1|-|



## **2.2.  Operating Range** 

## _Table 3 Operating Range_ 

|**Symbol**|**Description**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|VDDop|Supply voltage(1.8V-2.4V 17dBm, 2.4V- 3.6V  20dBm)|1.8|3.6|V|
|Top|Operational temperature range|-20|+70|°C|
|Clop|Load capacitance on digital ports|-|25|pF|
|ML|RF Input Level|-|0|dBm|



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**RFM69HW** 

## **2.3 Module Specification** 

The tables below give the electrical specifications of the transceiver under the following conditions: Supply voltage VBAT1= VBAT2=VDD=3.3 V, temperature = 25 °C, _F_ RF = 915 MHz, Pout = +20dBm, 2-level FSK modulation without pre-filtering, FDA = 5 kHz, Bit Rate = 4.8 kb/s and terminated in a matched 50 Ohm impedance, unless otherwise specified. 

_Note Unless otherwise specified, the performances in the other frequency bands are similar or better._ 

## **2.3.1. Power Consumption** 

_Table 4 Power Consumption Specification_ 

|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|IDDSL|Supply current in Sleep mode||-|0.1|1|uA|
|IDDIDLE|Supply current in Idle mode|RC oscillator enabled|-|1.2|-|uA|
|IDDST|Supply current in Standby mode|Crystal oscillator enabled|-|1.25|1.5|mA|
|IDDFS|Supply current in Synthesizer<br>mode||-|9|-|mA|
|IDDR|Supply current in Receive mode||-|16|-|mA|
|IDDT|Supply current in Transmit mode<br>with appropriate matching, sta-<br>ble across VDD range|RFOP = +20 dBm, on PA_BOOST<br>RFOP = +17 dBm, on PA_BOOST<br>RFOP = +13 dBm, on RFIO pin<br>RFOP = +10 dBm, on RFIO pin<br>RFOP =  0 dBm, on RFIO pin<br>RFOP = -1 dBm, on RFIO pin|-<br>-<br>-<br>-<br>-<br>-|130<br>95<br>45<br>33<br>20<br>16|-<br>-<br>-<br>-<br>-<br>-|mA<br>mA<br>mA<br>mA<br>mA<br>mA|



## **2.3.2. Frequency Synthesis** 

## _Table 5 Frequency Synthesizer Specification_ 

|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|FR|Synthesizer Frequency Range|315MHz Module<br>433MHz Module<br>868MHz Module<br>915MHz Module|290<br>424<br>862<br>890||340<br>510<br>890<br>1020|MHz<br>MHz<br>MHz<br>MHz|
|FXOSC|Crystal oscillator frequency|For All Module|-|32|-|MHz|
|TS_OSC|Crystal oscillator wake-up time||-|250|500|us|
|TS_FS|Frequency synthesizer wake-up<br>time to PllLock signal|From Standby mode|-|80|150|us|
|TS_HOP|Frequency synthesizer hop time<br>at most 10 kHz away from the<br>target|200 kHz step<br>1 MHz step<br>5 MHz step<br>7 MHz step<br>12 MHz step<br>20 MHz step<br>25 MHz step|-<br>-<br>-<br>-<br>-<br>-<br>-|20<br>20<br>50<br>50<br>80<br>80<br>80|-<br>-<br>-<br>-<br>-<br>-<br>-|us<br>us<br>us<br>us<br>us<br>us<br>us|



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**RFM69HW** 

|FSTEP|Frequency synthesizer step|FSTEP = FXOSC/219|-|61.0|-|Hz|
|---|---|---|---|---|---|---|
|FRC|RC Oscillator frequency|After calibration|-|62.5|-|kHz|
|BRF|Bit rate, FSK|Programmable|1.2|-|300|kbps|
|BRO|Bit rate, OOK|Programmable|1.2|-|32.768|kbps|
|FDA|Frequency deviation, FSK|Programmable<br>FDA + BRF/2 =< 500 kHz|0.6|-|300|kHz|



## **2.3.3. Receiver** 

All receiver tests are performed with _RxBw_ = 10 kHz (Single Side Bandwidth) as programmed in _RegRxBw_ , receiving a PN15 sequence with a BER of 0.1% (Bit Synchronizer is enabled), unless otherwise specified. The LNA impedance is set to 200 Ohms, by setting bit _LnaZin_ in _RegLna_ to 1. Blocking tests are performed with an unmodulated interferer. The wanted signal power for the Blocking Immunity, ACR, IIP2, IIP3 and AMR tests is set 3 dB above the nominal sensitivity level. 

## _Table 6 Receiver Specification_ 

|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|RFS_F<br>~~ee~~|FSK sensitivity, highest LNA gain<br>~~ee~~|FDA = 5 kHz,   BR = 1.2 kb/s<br>FDA = 5 kHz,   BR = 4.8 kb/s<br>FDA = 40 kHz, BR = 38.4 kb/s<br>~~ee~~|-<br>-<br>-<br>~~ee~~<br>~~ee~~|-118<br>-114<br>-105<br>~~ee~~<br>~~ee~~|-<br>-<br>-<br>~~ee~~<br>~~ee~~|dBm<br>dBm<br>dBm<br>~~ee~~<br>~~ee~~|
|||FDA = 5 kHz,   BR = 1.2 kb/s *<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~<br>~~ee~~|-120<br>~~ee~~<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~<br>~~ee~~|dBm<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|RFS_O<br>~~eee~~|OOK sensitivity, highest LNA gain<br>~~eee~~|BR = 4.8 kb/s<br>~~eee~~|-<br>~~ee~~<br>~~eee~~|-112<br>~~ee ~~<br>~~eee~~|-109<br> ~~ee~~<br>~~eee~~|dBm<br>~~ee~~<br>~~eee~~|
|CCR<br>~~eee~~|Co-Channel Rejection<br>~~eee~~|~~eee~~|-13<br>~~eee~~|-10<br>~~eee~~|-<br>~~eee~~|dB<br>~~eee~~|
|ACR<br>~~a~~|Adjacent Channel Rejection<br>|Offset =  +/- 25 kHz<br>Offset =  +/- 50 kHz<br>|-<br>37<br>|42<br>42<br>|-<br>-<br>|dB<br>dB<br>|
|BI<br>|Blocking Immunity<br>~~ee~~|Offset = +/- 1 MHz<br>Offset = +/- 2 MHz<br>Offset = +/- 10 MHz<br>~~ee~~|-<br>-<br>-<br>~~ee~~|66<br>71<br>79<br>~~ee~~|-<br>-<br>-<br>~~ee~~|dB<br>dB<br>dB<br>~~ee~~|
||Blocking Immunity<br>Wanted signal at sensitivity<br>+16dB<br>~~a~~|Offset = +/- 1 MHz<br>Offset = +/- 2 MHz<br>Offset = +/- 10 MHz<br>~~a~~|-<br>-<br>-<br>~~a~~|62<br>65<br>73<br>~~a~~|-<br>-<br>-<br>~~a~~|dB<br>dB<br>dB<br>~~a~~|
|AMR<br>~~ee~~|AM Rejection , AM modulated<br>interferer with 100% modulation<br>depth, fm = 1 kHz, square<br>~~ee~~|Offset = +/- 1 MHz<br>Offset = +/- 2 MHz<br>Offset = +/- 10 MHz<br>~~ee~~<br>~~ee~~|-<br>-<br>-<br>~~ee~~|66<br>71<br>79<br>~~ee~~|-<br>-<br>-<br>~~ee~~|dB<br>dB<br>dB<br>~~ee~~|
|IIP2<br>~~ee~~|2nd order Input Intercept Point<br>Unwanted tones are 20 MHz<br>above the LO<br>~~ee~~|Lowest LNA gain<br>Highest LNA gain<br>~~ee~~<br>~~ee~~|-<br>-<br>~~ee~~|+75<br>+35<br>~~ee~~|-<br>-<br>~~ee~~|dBm<br>dBm<br>~~ee~~|



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**RFM69HW** 

|IIP3<br>~~rr~~|3rd order Input Intercept point<br>Unwanted tones are 1MHz and<br>1.995 MHz above the LO<br>~~rr~~|Lowest LNA gain<br>Highest LNA gain<br>~~ee~~|-<br>-23<br>~~ee~~|+20<br>-18<br>~~ee~~|-<br>-<br>~~ee~~|dBm<br>dBm<br>~~ee~~|
|---|---|---|---|---|---|---|
|BW_SSB<br>~~rr~~<br>~~a~~|Single Side channel filter BW<br>~~rr~~<br>~~a~~|Programmable<br>~~ee~~<br>~~a~~|2.6<br>~~ee~~<br>~~a~~|-<br>~~ee~~<br>~~a~~|500<br>~~ee~~<br>~~a~~|kHz<br>~~ee~~<br>~~a~~|
|IMR_OOK<br>~~a~~|Image rejection in OOK mode<br>~~a~~|Wanted signal level = -106 dBm<br>~~a~~|27<br>~~a~~|30<br>~~a~~|-<br>~~a~~|dB<br>~~a~~|
|TS_RE<br>~~a~~|Receiver wake-up time, from PLL<br>locked state to_RxReady_<br>~~a~~<br>~~ee~~|RxBw= 10 kHz, BR = 4.8 kb/s<br>RxBw= 200 kHz, BR = 100 kb/s<br>~~a~~<br>~~ee~~|-<br>-<br>~~a~~<br>~~ee~~|1.7<br>96<br>~~a~~<br>~~ee~~|-<br>-<br>~~a~~<br>~~ee~~|ms<br>us<br>~~a~~<br>~~ee~~|
|TS_RE_AGC<br>~~a~~<br>~~a~~|Receiver wake-up time, from PLL<br>locked state, AGC enabled<br>~~a~~<br>~~ee~~<br>~~ee~~|RxBw= 10 kHz, BR = 4.8 kb/s<br>RxBw= 200 kHz, BR = 100 kb/s<br>~~a~~<br>~~ee~~<br>~~ee~~|-<br>~~a~~<br>~~ee~~<br>~~ee~~|3.0<br>163<br>~~a~~<br>~~ee~~<br>~~ee~~|~~a~~<br>~~ee~~<br>~~ee~~|ms<br>us<br>~~a~~<br>~~ee~~<br>~~ee~~|
|TS_RE_AGC<br>&AFC<br>~~a~~|Receiver wake-up time, from PLL<br>lock state, AGC and AFC enabled<br>~~ee~~|RxBw= 10 kHz, BR = 4.8 kb/s<br>RxBw= 200 kHz, BR = 100 kb/s<br>~~ee~~|~~ee~~|4.8<br>265<br>~~ee~~|~~ee~~|ms<br>us<br>~~ee~~|
|TS_FEI<br>~~a~~<br>~~a~~<br>~~a~~|FEI sampling time<br>~~ee~~<br>~~ee~~|Receiver is ready<br>~~ee~~|-<br>~~ee~~|4.Tbit<br>~~ee~~|-<br>~~ee~~|-<br>~~ee~~|
|TS_AFC<br>~~a~~<br>~~a~~|AFC Response Time<br>~~ee~~|Receiver is ready|-|4.Tbit|-|-|
|TS_RSSI<br>~~a~~|RSSI Response Time<br>~~ee~~|Receiver is ready|-|2.Tbit|-|-|
|DR_RSSI<br>~~a~~|RSSI Dynamic Range|AGC enabled<br>Min<br>Max|-<br>-|-115<br>0|-<br>-|dBm<br>dBm|



_* Set SensitivityBoost in RegTestLna to 0x2D to reduce the noise floor in the receiver_ 

## **2.3.4. Transmitter** 

## _Table 7 Transmitter Specification_ 

|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|RF_OP|RF output power in 50 ohms<br>On RFIO pin|Programmable with 1dB steps<br>Max<br>Min|-<br>-|+20<br>-18|-<br>-|dBm<br>dBm|
|RF_OPH|Max RF output power, on<br>PA_BOOST pin|With external match to 50 ohms|-|+20|-|dBm|
|ΔRF_OP|RF output power stability|From VDD=2.4V to 3.6V|-|+/-0.3|-|dB|
|PHN|Transmitter Phase Noise|50 kHz Offset from carrier<br>868 / 915 MHz bands<br>434 / 315 MHz bands|-<br>-|-95<br>-99|-<br>-|dBc/<br>Hz|
|ACP|Transmitter adjacent channel<br>power (measured at 25 kHz off-<br>set)|BT=0.5 . Measurement conditions as<br>defined by EN 300 220-1 V2.1.1|-|-|-37|dBm|
|TS_TR|Transmitter wake up time, to the<br>first rising edge of DCLK|Frequency Synthesizer enabled,<br>_PaRamp_= 10 us, BR = 4.8 kb/s.|-|120|-|us|



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**RFM69HW** 

## **2.3.5. Digital Specification** 

Conditions: Temp = 25°C, VDD = 3.3V, unless otherwise specified. 

## _Table 8 Digital Specification_ 

|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VIH<br>~~a~~|Digital input level high<br>~~a~~|~~a~~|0.8<br>~~a~~|-<br>~~a~~|-<br>~~a~~|VDD<br>~~a~~|
|VIL<br>~~a~~|Digital input level low<br>~~a~~|~~a~~|-<br>~~a~~|-<br>~~a~~|0.2<br>~~a~~|VDD<br>~~a~~|
|VOH<br>~~a~~|Digital output level high<br>~~a~~|Imax = 1 mA<br>~~a~~|0.9<br>~~a~~|-<br>~~a~~|-<br>~~a~~|VDD<br>~~a~~|
|VOL<br>~~a~~<br>~~a~~|Digital output level low<br>~~a~~<br>~~a~~|Imax = -1 mA<br>~~a~~<br>~~a~~|-<br>~~a~~<br>~~a~~|-<br>~~a~~<br>~~a~~|0.1<br>~~a~~<br>~~a~~|VDD<br>~~a~~<br>~~a~~|
|FSCK<br>~~a~~|SCK frequency<br>~~a~~|~~a~~|-<br>~~a~~|-<br>~~a~~|10<br>~~a~~|MHz<br>~~a~~|
|tch<br>~~a~~|SCK high time<br>~~a~~|~~a~~|50<br>~~a~~|-<br>~~a~~|-<br>~~a~~|ns<br>~~a~~|
|tcl<br>~~a~~|SCK low time<br>~~a~~|~~a~~|50<br>~~a~~|-<br>~~a~~|-<br>~~a~~|ns<br>~~a~~|
|trise<br>~~a~~<br>~~a~~|SCK rise time<br>~~a~~<br>~~a~~|~~a~~<br>~~a~~|-<br>~~a~~<br>~~a~~|5<br>~~a~~<br>~~a~~|-<br>~~a~~<br>~~a~~|ns<br>~~a~~<br>~~a~~|
|tfall<br>~~a~~|SCK fall time<br>~~a~~|~~a~~|-<br>~~a~~|5<br>~~a~~|-<br>~~a~~|ns<br>~~a~~|
|tsetup<br>~~a~~|MOSI setup time<br>~~a~~|from MOSI change to SCK rising<br>edge<br>~~a~~|30<br>~~a~~|-<br>~~a~~|-<br>~~a~~|ns<br>~~a~~|
|thold<br>~~a~~|MOSI hold time<br>~~a~~|from SCK rising edge to MOSI<br>change<br>~~a~~|60<br>~~a~~|-<br>~~a~~|-<br>~~a~~|ns<br>~~a~~|
|tnsetup<br>~~a~~|NSS setup time<br>~~a~~|from NSS falling edge to SCK rising<br>edge<br>~~a~~|30<br>~~a~~|-<br>~~a~~|-<br>~~a~~|ns<br>~~a~~|
|tnhold<br>~~a~~|NSS hold time<br>~~a~~|from SCK falling edge to NSS rising<br>edge, normal mode<br>~~a~~|30<br>~~a~~|-<br>~~a~~|-<br>~~a~~|ns<br>~~a~~|
|tnhigh<br>~~a~~|NSS high time between SPI<br>accesses<br>~~a~~|~~a~~|20<br>~~a~~|-<br>~~a~~|-<br>~~a~~|ns<br>~~a~~|
|T_DATA<br>~~a~~|DATA hold and setup time<br>~~a~~|~~a~~|250<br>~~a~~|-<br>~~a~~|-<br>~~a~~|ns<br>~~a~~|



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**RFM69HW** 

## **3.  Module Description** 

This section describes in depth the architecture of the RFM69HW low-power, highly integrated transceiver. 

## **3.1.  Power Supply Strategy** 

The RFM69HW employs an advanced power supply scheme, which provides stable operating characteristics over the full temperature and voltage range of operation. This includes the full output power of +20dBm maintained from 2.4 to 3.6V. 

The RFM69HW can be powered from any low-noise voltage source via pins VBAT1 and VBAT2. Decoupling capacitors should be connected, as suggested in the reference design, on VR_PA, VR_DIG and VR_ANA pins to ensure a correct operation of the built-in voltage regulators. 

## **3.2.  Frequency Synthesis** 

The LO generation on the RFM69HW is based on a state-of-the-art fractional-N PLL. The PLL is fully integrated with automatic calibration. 

## **3.2.1. Reference Oscillator** 

The crystal oscillator is the main timing reference of the RFM69HW. It is used as a reference for the frequency synthesizer and as a clock for the digital processing. 

The XO startup time, TS_OSC, depends on the actual XTAL being connected on pins XTA and XTB. When using the builtin sequencer, the RFM69HW optimizes the startup time and automatically triggers the PLL when the XO signal is stable. To manually control the startup time, the user should either wait for TS_OSC max, or monitor the signal CLKOUT which will only be made available on the output buffer when a stable XO oscillation is achieved. 

An external clock can be used to replace the crystal oscillator, for instance a tight tolerance TCXO. To do so, bit 4 at address 0x59 should be set to 1, and the external clock has to be provided on XTA. XTB should be left open. The peakpeak amplitude of the input signal must never exceed 2.4 V. Please consult your TCXO supplier for an appropriate value of decoupling capacitor, CD. 

**==> picture [145 x 106] intentionally omitted <==**

**----- Start of picture text -----**<br>
XTA   XTB<br>NC<br>TCXO<br>OP<br>32 MHz<br>Vcc Vcc<br>GND<br>CD<br>. Lt<br>**----- End of picture text -----**<br>


_Figure 4.  TCXO Connection_ 

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## **3.2.2. CLKOUT Output** 

The reference frequency, or a fraction of it, can be provided on DIO5  by modifying bits _ClkOut_ in _RegDioMapping2_ . Two typical applications of the CLKOUT output include: 

To provide a clock output for a companion processor, thus saving the cost of an additional oscillator. CLKOUT can be made available in any operation mode except Sleep mode and is automatically enabled at power on reset. 

To provide an oscillator reference output. Measurement of the CLKOUT signal enables simple software trimming of the initial crystal tolerance. 

_Note to minimize the current consumption of the RFM69HW, please ensure that the CLKOUT signal is disabled when not required._ 

## **3.2.3. PLL Architecture** 

The frequency synthesizer generating the LO frequency for both the receiver and the transmitter is a fractional-N sigmadelta PLL. The PLL incorporates a third order loop capable of fast auto-calibration, and it has a fast switching-time. The VCO and the loop filter are both fully integrated, removing the need for an external tight-tolerance, high-Q inductor in the VCO tank circuit. 

## _3.2.3.1. VCO_ 

The VCO runs at 2, 4 or 6 times the RF frequency (respectively in the 915, 434 and 315 MHz bands) to reduce any LO leakage in receiver mode, to improve the quadrature precision of the receiver, and to reduce the pulling effects on the VCO during transmission. 

The VCO calibration is fully automated. A coarse adjustment is carried out at power on reset, and a fine tuning is performed each time the RFM69HW PLL is activated. Automatic calibration times are fully transparent to the end-user, as their processing time is included in the _TS_TE_ and _TS_RE_ specifications. 

## _3.2.3.2. PLL Bandwidth_ 

The bandwidth of the RFM69HW Fractional-N PLL is wide enough to allow for: 

High speed FSK modulation, up to 300 kb/s, inside the PLL bandwidth 

Very fast PLL lock times, enabling both short startup and fast hop times required for frequency agile applications 

## _3.2.3.3. Carrier Frequency and Resolution_ 

The RFM69HW PLL embeds a 19-bit sigma-delta modulator and its frequency resolution, constant over the whole frequency range, and is given by: 

**==> picture [66 x 23] intentionally omitted <==**

The carrier frequency is programmed through _RegFrf_ , split across addresses 0x07 to 0x09: 

_FRF_ = _FSTEP_ ⋅ _Frf_ (23,0) 

_Note The Frf setting is split across 3 bytes. A change in the center frequency will only be taken into account when the least significant byte FrfLsb in RegFrfLsb is written. This allows for more complex modulation schemes such as m- ary FSK, where frequency modulation is achieved by changing the programmed RF frequency._ 

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## **3.2.4. Lock Time** 

PLL lock time _TS_FS_ is a function of a number of technical factors, such as synthesized frequency, frequency step, etc. When using the built-in sequencer, the RFM69HW optimizes the startup time and automatically starts the receiver or the transmitter when the PLL has locked. To manually control the startup time, the user should either wait for _TS_FS_ max given in the specification, or monitor the signal PLL lock detect indicator, which is set when the PLL has is within its locking range. 

When performing an AFC, which usually corrects very small frequency errors, the PLL response time is approximately: 

=  ----------- **-** 

“PIEAFC 2~ DEERIF 

In a frequency hopping scheme, the timings _TS_HOP_ given in the table of specifications give an order of magnitude for the expected lock times. 

## **3.2.5. Lock Detect Indicator** 

A lock indication signal can be made available on some of the DIO pins, and is toggled high when the PLL reaches its locking range. Please refer to Table 21 and Table 22 to map this interrupt to the desired pins. 

_Note The lock detect block may indicate an unlock condition (signal toggling low) when the transmitter is FSK modulated with large frequency deviation settings._ 

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## **3.3.  Transmitter Description** 

The transmitter of RFM69HW comprises the frequency synthesizer, modulator and power amplifier blocks. 

## **3.3.1. Architecture Description** 

**==> picture [213 x 163] intentionally omitted <==**

**----- Start of picture text -----**<br>
LNA<br>RFIO  Receiver Chain<br>PA0<br>Local<br>Oscillator<br>PA1<br>PA_BOOST<br>PA2<br>**----- End of picture text -----**<br>


_Figure 5.  Transmitter Block Diagram_ 

## **3.3.2. Bit Rate Setting** 

When using the RFM69HW in Continuous mode, the data stream to be transmitted can be input directly to the modulator via pin DIO2/DATA in an asynchronous manner, unless Gaussian filtering is used, in which case the DCLK signal on pin DIO1/DCLK is used to synchronize the data stream. See section 3.3.5 for details on the Gaussian filter. 

In Packet mode or in Continuous mode with Gaussian filtering enabled (refer to section 5.5 for details), the Bit Rate (BR) is controlled by bits _BitRate_ in _RegBitrate_ : 

**==> picture [59 x 20] intentionally omitted <==**

Amongst others, the following Bit Rates are accessible: 

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## _Table 9 Bit Rate Examples_ 

|**Type**|**BitRate**<br>**(15:8)**|**BitRate**<br>**(7:0)**|**(G)FSK**<br>**(G)MSK**|**OOK**|**Actual BR**<br>**(b/s)**|
|---|---|---|---|---|---|
|Classical modem baud rates<br>(multiples of 1.2 kbps)|0x68|0x2B|1.2 kbps|1.2 kbps|1200.015|
||0x34|0x15|2.4 kbps|2.4 kbps|2400.060|
||0x1A|0x0B|4.8 kbps|4.8 kbps|4799.760|
||0x0D|0x05|9.6 kbps|9.6 kbps|9600.960|
||0x06|0x83|19.2 kbps|19.2 kbps|19196.16|
||0x03|0x41|38.4 kbps||38415.36|
||0x01|0xA1|76.8 kbps||76738.60|
||0x00|0xD0|153.6 kbps||153846.1|
|Classical modem baud rates<br>(multiples of 0.9 kbps)|0x02|0x2C|57.6 kbps||57553.95|
||0x01|0x16|115.2 kbps||115107.9|
|Round bit rates<br>(multiples of 12.5, 25 and<br>50 kbps)|0x0A|0x00|12.5 kbps|12.5 kbps|12500.00|
||0x05|0x00|25 kbps|25 kbps|25000.00|
||0x02|0x80|50 kbps||50000.00|
||0x01|0x40|100 kbps||100000.0|
||0x00|0xD5|150 kbps||150234.7|
||0x00|0xA0|200 kbps||200000.0|
||0x00|0x80|250 kbps||250000.0|
||0x00|0x6B|300 kbps||299065.4|
|Watch Xtal frequency|0x03|0xD1|32.768 kbps|32.768 kbps|32753.32|



## **3.3.3. FSK Modulation** 

FSK modulation is performed inside the PLL bandwidth, by changing the fractional divider ratio in the feedback loop of the PLL. The large resolution of the sigma-delta modulator, allows for very narrow frequency deviation. The frequency deviation FDEV is given by: 

To ensure a proper modulation, the following limit applies: 

_Note no constraint applies to the modulation index of the transmitter, but the frequency deviation must exceed 600 Hz._ 

## **3.3.4. OOK Modulation** 

OOK modulation is applied by switching on and off the Power Amplifier. Digital control and smoothing are available to improve the transient power response of the OOK transmitter. 

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## **3.3.5. Modulation Shaping** 

Modulation shaping can be applied in both OOK and FSK modulation modes, to improve the narrowband response of the transmitter. Both shaping features are controlled with _PaRamp_ bits in _RegPaRamp_ . 

In FSK mode, a Gaussian filter with BT = 0.3, 0.5 or 1 is used to filter the modulation stream, at the input of the sigma-[delta modulator. If the Gaussian filter is enabled when the RFM69HW is in Continuous mode, DCLK signal ] on pin DIO1/DCLK will trigger an interrupt on the uC each time a new bit has to be transmitted. Please refer to section 5.4.2 for details. 

When OOK modulation is used, the PA bias voltages are ramped up and down smoothly when the PA is turned on and[off, to reduce spectral splatter. ] 

_Note the transmitter must be restarted if the PaRamp setting is changed, in order to recalibrate the built-in filter._ 

## **3.3.6. Power Amplifiers** 

A higher power mode, when PA1 and PA2 are combined, providing up to +20 dBm to a matched load. 

When PA1 and PA2 are combined to deliver +20 dBm to the antenna, a specific impedance matching / harmonic filtering design is required to ensure impedance transformation and regulatory compliance. 

All PA settings are controlled by _RegPaLevel_ , and the truth table of settings is given in Table 10. 

## _Table 10  Power Amplifier Mode Selection Truth Table_ 

|**_Pa0On_**|**_Pa1On_**|**_Pa2On_**|**Mode**|**Power Range**|**Pout Formula**|
|---|---|---|---|---|---|
|1|0|0|PA0 output on pin RFIO|-18 to +13 dBm|-18 dBm +_OutputPower_|
|0|1|0|PA1 enabled on pin PA_BOOST|-2 to +13 dBm|-18 dBm +_OutputPower_|
|0|1|1|PA1 and PA2 combined on pin PA_BOOST|+2 to +17 dBm|-14 dBm +_OutputPower_|
|0|1|1|PA1+PA2 on PA_BOOST with high output<br>power +20dBm settings (see 3.3.7)|+5 to +20 dBm|-11 dBm +_OutputPower_|
|Other combinations|||Reserved|||



_Notes   - To ensure correct operation at the highest power levels, please make sure to adjust the Over Current Protection Limit accordingly in RegOcp, except above +18dBm where it must be disabled_ 

- _If PA_BOOST pin is not used (+20dBm applications and less), the pin can be left floating._ 

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## **3.3.7. High Power Settings** 

The RFM69HW has a high power +20 dBm capability on PA_BOOST pin, with the following settings: 

_Table 11  High Power Settings_ 

|**_Register_**|**_Address_**|**_Value for_**<br>**_High Power_**|**_Value for Rx_**<br>**_or PA0 use_**|**Description**|
|---|---|---|---|---|
|_RegOcp_|0x13|0x0F|0x1x|OCP control|
|_RegTestPa1_|0x5A|0x5D|0x55|High power PA control|
|_RegTestPa2_|0x5C|0x7C|0x70|High power PA control|



_Note High Power settings MUST be turned off when using PA0, and in Receive mode_ 

The Duty Cycle of transmission at +20dBm is limited to 1%, with a maximum VSWR of 3:1 at antenna port, over the standard operating range [-40;+85°C]. 

## **3.3.8. Output Power Summary** 

The curves below summarize the possible PA options on the RFM69HW: 

**==> picture [284 x 166] intentionally omitted <==**

**----- Start of picture text -----**<br>
Po ut vs. P rog ram med  Pow er<br>22<br>18 ee eeee<br>14106 aaa ee<br>2 ee a eeeee<br>-2 | | ee|apa e<br>-6 P out on PA0 [dB m ]<br>P out on PA1 [dB m ]<br>-10<br>P out on PA1+PA2 [dBm]<br>-14<br>P  out on  P A 1+ P A 2 with 20dB m  s ettings  [dB m]<br>-18 ramaa4 E |<br>-22<br>-18  -14  -10  -6  -2  2  6  10  14  18<br>Pr ogr am m e d  Po w e r  [d Bm ]<br>[dBm]<br>Pout<br>**----- End of picture text -----**<br>


_Figure 6.  Output Power Curves_ 

## **3.3.9. Over Current Protection** 

An over current protection block is built-in the module. It helps preventing surge currents required when the transmitter is used at its highest power levels, thus protecting the battery that may power the application. The current clamping value is controlled by _OcpTrim_ bits in _RegOcp_ , and is calculated with the following formula: 

_Imax_ = 45 + 5 ⋅ _OcpTrim  mA _ 

_Note Imax sets a limit on the current drain of the Power Amplifier only, hence the maximum current drain of the RFM69HW is equal to Imax + IFS_ 

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## **3.4.  Receiver Description** 

The RFM69HW features a digital receiver with the analog to digital conversion process being performed directly following the LNA-Mixers block. The zero-IF receiver is able to handle (G)FSK and (G)MSK modulation. ASK and OOK modulation is, however, demodulated by a low-IF architecture. All the filtering, demodulation, gain control, synchronization and packet handling is performed digitally, which allows a very wide range of bit rates and frequency deviations to be selected. The receiver is also capable of automatic gain calibration in order to improve precision on RSSI measurements. 

## **3.4.1. Block Diagram** 

**==> picture [526 x 142] intentionally omitted <==**

**----- Start of picture text -----**<br>
Rx  Calibration<br>Reference<br>LNA ©/⊗ CORDIC<br>Single to Mixers Modulators Channel DC  Complex<br>Differential Filter Cancellation Filter Phase FSK<br>RFIO Output Demodulator<br>Module OOK<br>From RSSI<br>PA1 Output Demodulator<br>Bypassed<br>in FSK<br>Local<br>Oscillator AFC<br>—=<br>AGC<br>|<br>imator<br>Dec Processing<br>**----- End of picture text -----**<br>


_Figure 7.  Receiver Block Diagram_ 

The following sections give a brief description of each of the receiver blocks. 

## **3.4.2. LNA - Single to Differential Buffer** 

The LNA uses a common-gate topology, which allows for a flat characteristic over the whole frequency range. It is designed to have an input impedance of 50 Ohms or 200 Ohms (as selected with bit _LnaZin_ in _RegLna)_ , and the parasitic capacitance at the LNA input port is cancelled with the external RF choke. A single to differential buffer is implemented to improve the second order linearity of the receiver. 

The LNA gain, including the single-to-differential buffer, is programmable over a 48 dB dynamic range, and control is either manual or automatic with the embedded AGC function. 

- _Note In the specific case where the LNA gain is manually set by the user, the receiver will not be able to properly handle FSK signals with a modulation index smaller than 2 at an input power greater than the 1dB compression point, tabulated in section 3.4.3._ 

## _Table 12  LNA Gain Settings_ 

|**_LnaGainSelect_**|**LNA Gain**|**Gain Setting**|
|---|---|---|
|000|Any of the below, set by the AGC loop|-|
|001|Max gain|G1|
|010|Max gain - 6 dB|G2|
|011|Max gain - 12 dB|G3|
|100|Max gain - 24 dB|G4|
|101|Max gain - 36 dB|G5|
|110|Max gain - 48 dB|G6|
|111|Reserved|-|



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## **3.4.3. Automatic Gain Control** 

By default ( _LnaGainSelect = 000_ ), the LNA gain is controlled by a digital AGC loop in order to obtain the optimal sensitivity/ linearity trade-off. 

Regardless of the data transfer mode (Packet or Continuous), the following series of events takes place when the receiver is enabled: 

The receiver stays in WAIT mode, until _RssiValue_ exceeds _RssiThreshold_ for two consecutive samples. Its power consumption is the receiver power consumption. 

When this condition is satisfied, the receiver automatically selects the most suitable LNA gain, optimizing the sensitivity/linearity trade-off. 

The programmed LNA gain, read-accessible with _LnaCurrentGain_ in _RegLna_ , is carried on for the whole duration of the packet, until one of the following conditions is fulfilled: 

Packet mode: if _AutoRxRestartOn = 0,_ the LNA gain will remain the same for the reception of the following packet. If _AutoRxRestartOn = 1_ , after the controller has emptied the FIFO the receiver will re-enter the WAIT mode described above, after a delay of _InterPacketRxDelay_ , allowing for the distant transmitter to ramp down, hence avoiding a false RSSI detection. In both cases (AutoRxRestartOn=0 or AutoRxRestartOn=1), the receiver can also re-enter the WAIT mode by setting _RestartRx_ bit to 1. The user can decide to do so, to manually launch a new AGC procedure. 

Continuous mode: upon reception of valid data, the user can decide to either leave the receiver enabled with the same[LNA gain, or][ to restart the procedure, by setting ] _[RestartRx ]_[bit to 1, resuming the WAIT mode of the receiver, ] described above. 

_Notes   - the AGC procedure must be performed while receiving preamble in FSK mode_ 

- _in OOK mode, the AGC will give better results if performed while receiving a constant “1” sequence_ 

The following figure illustrates the AGC behavior: 

**==> picture [504 x 138] intentionally omitted <==**

**----- Start of picture text -----**<br>
Towards<br>-125 dBm<br>16dB   7dB   11dB   9dB   11dB Pin [dBm]<br>ee I cere ee oe<br>G1  G2  G3  G4  G5  G6<br>Higher Sensitivity  Lower Sensitivity<br>C= Lower Linearity  5 Higher Linearity<br>Lower Noise Figure Higher Noise Figure<br>**----- End of picture text -----**<br>


_Figure 8.  AGC Thresholds Settings_ 

The following table summarizes the performance (typical figures) of the complete receiver: 

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_Table 13  Receiver Performance Summary_ 

|**_Input Power_**<br>**_Pin_**|**Gain**<br>**Setting**|**Receiver Performance (typ)**|**Receiver Performance (typ)**|**Receiver Performance (typ)**|**Receiver Performance (typ)**|
|---|---|---|---|---|---|
|||**P-1dB**<br>**[dBm]**|**NF**<br>**[dB]**|**IIP3**<br>**[dBm]**|**IIP2**<br>**[dBm]**|
|Pin < AgcThresh1|G1|-37|7|-18|+35|
|AgcThresh1 < Pin < AgcThresh2|G2|-31|13|-15|+40|
|AgcThresh2 < Pin < AgcThresh3|G3|-26|18|-8|+48|
|AgcThresh3 < Pin < AgcThresh4|G4|-14|27|-1|+62|
|AgcThresh4 < Pin < AgcThresh5|G5|>-6|36|+13|+68|
|AgcThresh5 < Pin|G6|>0|44|+20|+75|



## _3.4.3.1. RssiThreshold Setting_ 

For correct operation of the AGC, _RssiThreshold_ in _RegRssiThresh_ must be set to the sensitivity of the receiver. The receiver will remain in WAIT mode until _RssiThreshold_ is exceeded. 

_Note When AFC is enabled and performed automatically at the receiver startup, the channel filter used by the receiver during the AFC and the AGC is RxBwAfc instead of the standard RxBw setting. This may impact the sensitivity of the receiver, and the setting of RssiThreshold accordingly_ 

## _3.4.3.2. AGC Reference_ 

The AGC reference level is automatically computed in the RFM69HW, according to: 

**AGC Reference [dBm] = -174 + NF + DemodSnr +10.log(2*** _**RxBw**_ **) + FadingMargin  [dBm]** 

With: 

_NF_ = 7dB : LNA’s Noise Figure at maximum gain _DemodSnr_ = 8 dB : SNR needed by the demodulator _RxBw_ : Single sideband channel filter bandwidth _FadingMargin = 5 dB_ : Fading margin 

## **3.4.4. Continuous-Time DAGC** 

In addition to the automatic gain control described in section 3.4.3, the RFM69HW is capable of continuously adjusting its gain in the digital domain, after the analog to digital conversion has occured. This feature, named DAGC, is fully transparent to the end user. The digital gain adjustment is repeated every 2 bits, and has the following benefits: 

Fully transparent to the end user 

Improves the fading margin of the receiver during the reception of a packet, even if the gain of the LNA is frozen 

Improves the receiver robustness in fast fading signal conditions, by quickly adjusting the receiver gain (every 2 bits) 

Works in Continuous, Packet, and unlimited length Packet modes 

The DAGC is enabled by setting _RegTestDagc_ to 0x20 for low modulation index systems (i.e. when _AfcLowBetaOn_ =1, refer to section 3.4.16), and 0x30 for other systems. It is recommended to always enable the DAGC. 

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## **3.4.5. Quadrature Mixer - ADCs - Decimators** 

The mixer is inserted between output of the RF buffer stage and the input of the analog to digital converter (ADC) of the receiver section. This block is designed to translate the spectrum of the input RF signal to base-band, and offer both high IIP2 and IIP3 responses. 

In the lower bands of operation (290 to 510 MHz), the multi-phase mixing architecture with weighted phases improves the rejection of the LO harmonics in receiver mode, hence increasing the receiver immunity to out-of-band interferers. 

The I and Q digitalization is made by two 5[th ] order continuous-time Sigma-Delta Analog to Digital Converters (ADC). Their gain is not constant over temperature, but the whole receiver is calibrated before reception, so that this inaccuracy has no impact on the RSSI precision. The ADC output is one bit per channel. It needs to be decimated and filtered afterwards. This ADC can also be used for temperature measurement, please refer to section 3.4.17 for more details. 

The decimators decrease the sample rate of the incoming signal in order to optimize the area and power consumption of the following receiver blocks. 

## **3.4.6. Channel Filter** 

The role of the channel filter is to filter out the noise and interferers outside of the channel. Channel filtering on the RFM69HW is implemented with a 16-tap Finite Impulse Response (FIR) filter, providing an outstanding Adjacent Channel Rejection performance, even for narrowband applications. 

_Note to respect oversampling rules in the decimation chain of the receiver, the Bit Rate cannot be set at a higher value than 2 times the single-side receiver bandwidth (BitRate < 2 x RxBw)_ 

The single-side channel filter bandwidth _RxBw_ is controlled by the parameters _RxBwMant_ and _RxBwExp_ in _RegRxBw:_ 

When FSK modulation is enabled: 

When OOK modulation is enabled: 

**==> picture [142 x 70] intentionally omitted <==**

The following channel filter bandwidths are accessible (oscillator is mandated at 32 MHz): 

_Table 14  Available RxBw Settings_ 

|**_RxBwMant_**<br>**(binary/value)**|**_RxBwExp_**<br>**(decimal)**|**_RxBw (kHz)_**|**_RxBw (kHz)_**|
|---|---|---|---|
|||**FSK**<br>**_ModulationType=00_**|**OOK**<br>**_ModulationType=01_**|
|10b / 24|7|2.6|1.3|
|01b / 20|7|3.1|1.6|
|00b / 16|7|3.9|2.0|
|10b / 24|6|5.2|2.6|
|01b / 20|6|6.3|3.1|
|00b / 16|6|7.8|3.9|
|10b / 24|5|10.4|5.2|
|01b / 20|5|12.5|6.3|
|00b / 16|5|15.6|7.8|
|10b / 24|4|20.8|10.4|



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**RFM69HW** 

|~~ee~~||||
|---|---|---|---|
|01b / 20<br>~~ee~~<br>~~ee~~|4|25.0|12.5|
|00b / 16<br>~~ee~~<br>~~ee~~<br>~~ee~~|4|31.3|15.6|
|10b / 24<br>~~ee~~<br>~~ee~~<br>~~ee~~|3|41.7|20.8|
|01b / 20<br>~~ee~~<br>~~ee~~<br>~~ee~~|3|50.0|25.0|
|00b / 16<br>~~ee~~<br>~~ee~~<br>~~ee~~|3|62.5|31.3|
|10b / 24<br>~~ee~~<br>~~ee~~|2|83.3|41.7|
|01b / 20<br>~~ee~~<br>~~a~~<br>~~ee~~|2|100.0|50.0|
|00b / 16<br>~~a~~<br>~~ee~~<br>~~ee~~|2|125.0|62.5|
|10b / 24<br>~~ee~~<br>~~ee~~<br>~~ee~~|1|166.7|83.3|
|01b / 20<br>~~ee~~<br>~~ee~~|1|200.0|100.0|
|00b / 16<br>~~ee~~<br>~~a~~<br>~~ee~~|1|250.0|125.0|
|10b / 24<br>~~ee~~<br>~~ee~~|0|333.3|166.7|
|01b / 20<br>~~ee~~<br>~~ee~~<br>~~ee~~|0|400.0|200.0|
|00b / 16<br>~~ee~~<br>~~ee~~|0|500.0|250.0|



## **3.4.7. DC Cancellation** 

DC cancellation is required in zero-IF architecture transceivers to remove any DC offset generated through self-reception. It is built-in the RFM69HW and its adjustable cutoff frequency _fc_ is controlled in _RegRxBw_ : 

## _Table 15  Available DCC Cutoff Frequencies_ 

|**_DccFreq_**<br>**_in RegRxBw_**|**fc in**<br>**% of RxBw**|
|---|---|
|000|16|
|001|8|
|010 (default)|4|
|011|2|
|100|1|
|101|0.5|
|110|0.25|
|111|0.125|



The default value of _DccFreq_ cutoff frequency is typically 4% of the RxBw (channel filter BW). The cutoff frequency of the DCC can however be increased to slightly improve the sensitivity, under wider modulation conditions. It is advised to adjust the DCC setting while monitoring the receiver sensitivity. 

## **3.4.8. Complex Filter - OOK** 

In OOK mode the RFM69HW is modified to a low-IF architecture. The IF frequency is automatically set to half the single side bandwidth of the channel filter (FIF = 0.5 x _RxBw_ ). The Local Oscillator is automatically offset by the IF in the OOK receiver. A complex filter is implemented on the module to attenuate the resulting image frequency by typically 30 dB. 

_Note this filter is automatically bypassed when receiving FSK signals (ModulationType = 00_ in _RegDataModul)._ 

## **3.4.9. RSSI** 

The RSSI block evaluates the amount of energy available within the receiver channel bandwidth. Its resolution is 0.5 dB, and it has a wide dynamic range to accommodate both small and large signal levels that may be present. Its acquisition time is very short, taking only 2 bit periods. The RSSI sampling must occur during the reception of preamble in FSK, and constant “1” reception in OOK. 

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**RFM69HW** 

## _Note - RssiValue can only be read when it exceeds RssiThreshold_ 

_- The receiver is capable of automatic gain calibration, in order to improve the precision of its RSSI measurements. This function injects a known RF signal at the LNA input, and calibrates the receiver gain accordingly. This calibration is automatically performed during the PLL start-up, making it a transparent process to the end-user_ 

_- RSSI accuracy depends on all components located between the antenna port and pin RFIO, and is therefore limited to a few dB. Board-level calibration is advised to further improve accuracy_ 

**==> picture [272 x 175] intentionally omitted <==**

**----- Start of picture text -----**<br>
RSSI Chart - With  AGC<br>0.0<br>-20.0<br>Bea<br>-40.0<br>titty<br>-60.0<br>ttt tt| t erytd<br>-80.0<br>jtiperttt ttt<br>-100.0<br>thettt ttt tt<br>-120.0 Tritt titi tit<br>-120      -110     -100  -90  -80  -70  -60  -50  -40  -30  -20  -10  0<br>Pin [dBm]<br>[dBm]<br>RssiValue<br>**----- End of picture text -----**<br>


_Figure 9.  RSSI Dynamic Curve_ 

## **3.4.10. Cordic** 

The Cordic task is to extract the phase and the amplitude of the modulation vector (I+j.Q). This information, still in the digital domain is used: 

Phase output: used by the FSK demodulator and the AFC blocks. 

Amplitude output: used by the RSSI block, for FSK demodulation, AGC and automatic gain calibration purposes. 

**==> picture [154 x 73] intentionally omitted <==**

**----- Start of picture text -----**<br>
Q(t)<br>Real-time<br>Magnitude<br>\<br>Real-time Phase<br>/ I(t)<br>**----- End of picture text -----**<br>


_Figure 10.  Cordic Extraction_ 

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## **3.4.11. FSK Demodulator** 

The FSK demodulator of the RFM69HW is designed to demodulate FSK, GFSK, MSK and GMSK modulated signals. It is most efficient when the modulation index of the signal is greater than 0.5 and below 10: 

**==> picture [28 x 7] intentionally omitted <==**

The output of the FSK demodulator can be fed to the Bit Synchronizer (described in section 3.4.13), to provide the companion processor with a synchronous data stream in Continuous mode. 

## **3.4.12. OOK Demodulator** 

The OOK demodulator performs a comparison of the RSSI output and a threshold value. Three different threshold modes are available, configured through bits _OokThreshType_ in _RegOokPeak_ . 

The recommended mode of operation is the "Peak" threshold mode, illustrated in Figure 11: 

**==> picture [545 x 338] intentionally omitted <==**

**----- Start of picture text -----**<br>
RSSI<br>[dBm]<br>‘’Peak -6dB’’  Threshold<br>‘’Floor’’ threshold defined  by<br>OokFixedThresh<br>G =<br>Noise floor  of<br>receiver<br>Time<br>Zoom<br>Decay in dB as defined  in<br>OokPeakThreshStep  Fixed 6dB  difference<br>Period as defined  in<br>OokPeakThreshDec<br>a<br>Figure 11.  OOK Peak Demodulator Description<br>In peak threshold mode the comparison threshold level is the peak value of the RSSI, reduced by 6dB. In the absence of<br>an input signal, or during the reception of a logical "0", the acquired peak value is decremented by one<br>OokPeakThreshStep  every  OokPeakThreshDec  period.<br>**----- End of picture text -----**<br>


When the RSSI output is null for a long time (for instance after a long string of "0" received, or if no transmitter is present), the peak threshold level will continue falling until it reaches the "Floor Threshold", programmed in _OokFixedThresh_ . 

The default settings of the OOK demodulator lead to the performance stated in the electrical specification. However, in applications in which sudden signal drops are awaited during a reception, the three parameters should be optimized accordingly. 

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**RFM69HW** 

## _3.4.12.1. Optimizing the Floor Threshold_ 

_OokFixedThresh_ determines the sensitivity of the OOK receiver, as it sets the comparison threshold for weak input signals (i.e. those close to the noise floor). Significant sensitivity improvements can be generated if configured correctly. Note that the noise floor of the receiver at the demodulator input depends on: 

The noise figure of the receiver. 

The gain of the receive chain from antenna to base band. 

The matching - including SAW filter if any. 

The bandwidth of the channel filters. 

It is therefore important to note that the setting of _OokFixedThresh_ will be application dependant. The following procedure is recommended to optimize _OokFixedThresh_ . 

**==> picture [181 x 196] intentionally omitted <==**

**----- Start of picture text -----**<br>
Set RFM69HW in OOK Rx mode<br>Adjust Bit Rate, Channel filter  BW<br>Default  OokFixedThresh  setting<br>No input  signal<br>Continuous  Mode<br>Monitor DIO2/DATA  pin<br>Increment<br>OokFixedThresh<br>Glitch  activity<br>on DATA  ?<br>Optimization  complete<br>**----- End of picture text -----**<br>


_Figure 12.  Floor Threshold Optimization_ 

The new floor threshold value found during this test should be used for OOK reception with those receiver settings. 

## _3.4.12.2. Optimizing OOK Demodulator for Fast Fading Signals_ 

A sudden drop in signal strength can cause the bit error rate to increase. For applications where the expected signal drop can be estimated, the following OOK demodulator parameters _OokPeakThreshStep_ and _OokPeakThreshDec_ can be optimized as described below for a given number of threshold decrements per bit. Refer to _RegOokPeak_ to access those settings. 

## _3.4.12.3. Alternative OOK Demodulator Threshold Modes_ 

In addition to the Peak OOK threshold mode, the user can alternatively select two other types of threshold detectors: 

Fixed Threshold: The value is selected through _OokFixedThresh_ 

Average Threshold: Data supplied by the RSSI block is averaged, and this operation mode should only be used with[DC-free encoded data. ] 

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## **3.4.13. Bit Synchronizer** 

The Bit Synchronizer is a block that provides a clean and synchronized digital output, free of glitches. Its output is made available on pin DIO1/DCLK in Continuous mode and can be disabled through register settings. However, for optimum receiver performance its use when running Continuous mode is strongly advised. 

The Bit Synchronizer is automatically activated in Packet mode. Its bit rate is controlled by _BitRateMsb_ and _BitRateLsb_ in _RegBitrate._ 

**==> picture [113 x 143] intentionally omitted <==**

**----- Start of picture text -----**<br>
Raw demodulator<br>output  oe<br>(FSK or OOK)<br>DATA<br>BitSync Output To<br>pin DATA and<br>DCLK in continuous<br>mode<br>DCLK<br>**----- End of picture text -----**<br>


_Figure 13.  Bit Synchronizer Description_ 

To ensure correct operation of the Bit Synchronizer, the following conditions have to be satisfied: 

A preamble (0x55 or 0xAA) of 12 bits is required for synchronization (from the _RxReady_ interrupt) 

The subsequent payload bit stream must have at least one transition form '0' to '1' or '1' to '0 every 16 bits during data transmission 

The bit rate matching between the transmitter and the receiver must be better than 6.5 %. 

_Notes   - If the Bit Rates of transmitter and receiver are known to be the same, the RFM69HW will be able to receive an infinite unbalanced sequence (all “0s” or all ”1s”) with no restriction._ 

_- If there is a difference in Bit Rate between Tx and Rx, the amount of adjacent bits at the same level that the BitSync can withstand can be estimated as follows:_ 

- _This implies approximately 6 consecutive unbalanced bytes when the Bit Rate precision is 1%, which is easily achievable (crystal tolerance is in the range of 50 to 100 ppm)._ 

## **3.4.14. Frequency Error Indicator** 

This function provides information about the frequency error of the local oscillator (LO) compared with the carrier frequency of a modulated signal at the input of the receiver. When the FEI block is launched, the frequency error is measured and the 

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signed result is loaded in _FeiValue_ in _RegFei_ , in 2’s complement format. The time required for an FEI evaluation is 4 times the bit period. 

To ensure a proper behavior of the FEI: 

The operation must be done during the reception of preamble 

The sum of the frequency offset and the 20 dB signal bandwidth must be lower than the base band filter bandwidth 

The 20 dB bandwidth of the signal can be evaluated as follows (double-side bandwidth): 

= ⋅ - a BW agge = 2™| Foert =) 

The frequency error, in Hz, can be calculated with the following formula: 

**==> picture [109 x 221] intentionally omitted <==**

**----- Start of picture text -----**<br>
SX1239RFM69HW in Rx<br>mode<br>Preamble-modulated input s ignal<br>Signal level > Sensitivity<br>Set  FeiStart<br>= 1<br>FeiDone  No<br>= 1<br>Yes<br>Read<br>FeiValue<br>**----- End of picture text -----**<br>


_Figure 14.  FEI Process_ 

## **3.4.15. Automatic Frequency Correction** 

The AFC is based on the FEI block, and therefore the same input signal and receiver setting conditions apply. When the AFC procedure is done, _AfcValue_ is directly subtracted to the register that defines the frequency of operation of the module, FRF. The AFC can be launched: 

Each time the receiver is enabled, if _AfcAutoOn_ = 1 

Upon user request, by setting bit _AfcStart_ in _RegAfcFei_ , if _AfcAutoOn_ = 0 

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When the AFC is automatically triggered ( _AfcAutoOn_ = 1), the user has the option to: 

Clear the former AFC correction value, if _AfcAutoClearOn_ = 1 

Start the AFC evaluation from the previously corrected frequency. This may be useful in systems in which the LO keeps on drifting in the “same direction”. Ageing compensation is a good example. 

The RFM69HW offers an alternate receiver bandwidth setting during the AFC phase, to accommodate large LO drifts. If the user considers that the received signal may be out of the receiver bandwidth, a higher channel filter bandwidth can be programmed in _RegAfcBw_ , at the expense of the receiver noise floor, which will impact upon sensitivity. 

## **3.4.16. Optimized Setup for Low Modulation Index Systems** 

For wide band systems, where AFC is usually not required (XTAL inaccuracies do not typically impact the sensitivity), it is recommended to offset the LO frequency of the receiver to avoid desensitization. This can be simply done by modifying _Frf_ in _RegFrfLsb_ . A good rule of thumb is to offset the receiver’s LO by 10% of the expected transmitter frequency deviation. 

For narrow band systems, it is recommended to perform AFC. The RFM69HW has a dedicated AFC, enabled when 

_AfcLowBetaOn_ in _RegAfcCtrl_ is set to 1. A frequency offset, programmable through _LowBetaAfcOffset_ in _RegTestAfc_ , is added and is calculated as follows: 

## **Offset =** _**LowBetaAfcOffset**_ **x 488 Hz** 

The user should ensure that the programmed offset exceeds the DC canceller’s cutoff frequency, set through _DccFreqAfc_ in _RegAfcBw._ 

**==> picture [281 x 142] intentionally omitted <==**

**----- Start of picture text -----**<br>
RX TX RX & TX<br>FeiValue Standard AFC AfcValue<br>AfcLowBetaOn = 0<br>f  f<br>RX TX TX  RX<br>FeiValue  Optimized AFC AfcValue LowBetaAfcOffset<br>AfcLowBetaOn = 1<br>f  f<br>Before AFC   After  AFC<br>**----- End of picture text -----**<br>


_Figure 15.  Optimized AFC (AfcLowBetaOn=1)_ 

As shown on Figure 15, a standard AFC sequence uses the result of the FEI to correct the LO frequency and align both local oscillators. When the optimized AFC is enabled ( _AfcLowBetaOn=1_ ), the receiver’s LO is corrected by “ _FeiValue_ + _LowBetaAfcOffset_ ”. 

When the optimized AFC routine is enabled, the receiver startup time can be computed as follows (refer to section 4.2.3): 

## **TS_RE_AGC&AFC (optimized AFC) =** _**Tana + 4.Tcf + 4.Tdcc + 3.Trssi + 2.Tafc + 2.Tpllafc**_ 

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**RFM69HW** 

## **3.4.17. Temperature Sensor** 

When temperature is measured, the receiver ADC is used to digitize the sensor response. Most receiver blocks are disabled, and temperature measurement can only be triggered in Standby or Frequency Synthesizer modes. 

The response of the temperature sensor is -1°C / Lsb. A CMOS temperature sensor is not accurate by nature, therefore it should be calibrated at ambient temperature for precise temperature readings. 

**==> picture [42 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
TempValue<br>**----- End of picture text -----**<br>


**==> picture [316 x 155] intentionally omitted <==**

**----- Start of picture text -----**<br>
-1°C/Lsb<br>TempValue(t)<br>TempValue(t)-1<br>Returns 150d (typ.)<br>Needs calibration<br>we<br>-40°C t  t+1 Ambient  +85°C<br>**----- End of picture text -----**<br>


_Figure 16.  Temperature Sensor Response_ 

It takes less than 100 microseconds for the RFM69HW to evaluate the temperature (from setting _TempMeasStart_ to 1 to _TempMeasRunning_ reset). 

## **3.4.18. Timeout Function** 

The RFM69HW includes a Timeout function, which allows it to automatically shut-down the receiver after a receive sequence and therefore save energy. 

Timeout interrupt is generated _TimeoutRxStart x 16x Tbit_ after switching to RX mode if _RssiThreshold_ flag does not raise within this time frame 

Timeout interrupt is generated _TimeoutRssiThresh x 16 x Tbit_ after _RssiThreshold_ flag has been raised. 

This timeout interrupt can be used to warn the companion processor to shut down the receiver and return to a lower power mode. 

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**RFM69HW** 

## **4. Operating Modes** 

## **4.1.  Basic Modes** 

The circuit can be set in 5 different basic modes which are described in Table 16. 

By default, when switching from a mode to another one, the sub-blocks are woken up according to a pre-defined and optimized sequence. Alternatively, these operating modes can be selected directly by disabling the automatic sequencer ( _SequencerOff_ in _RegOpMode = 1_ ). 

_Table 16  Basic Transceiver Modes_ 

|**_ListenOn_**<br>**in****_RegOpMode_**|**_Mode_**<br>**in****_RegOpMode_**|**Selected mode**|**Enabled blocks**|
|---|---|---|---|
|0|0 0 0|Sleep Mode|None|
|0|0 0 1|Stand-by Mode|Top regulator and crystal oscillator|
|0|0 1 0|FS Mode|Frequency synthesizer|
|0|0 1 1|Transmit Mode|Frequency synthesizer and transmitter|
|0|1 0 0|Receive Mode|Frequency synthesizer and receiver|
|1|x|Listen Mode|See Listen Mode, section 4.3|



## **4.2.  Automatic Sequencer and Wake-Up Times** 

By default, when switching from one operating mode to another, the circuit takes care of the sequence of events in such a way that the transition timing is optimized. For example, when switching from Sleep mode to Transmit mode, the RFM69HW goes first to Standby mode (XO started), then to frequency synthesizer mode, and finally, when the PLL has locked, to transmit mode. Entering transmit mode is also made according to a predefined sequence starting with the wake-up of the PA regulator before applying a ramp-up on the PA and generating the DCLK clock. 

The crystal oscillator wake-up time, TS_OSC, is directly related to the time for the crystal oscillator to reach its steady state. It depends notably on the crystal characteristics. 

The frequency synthesizer wake-up time, TS_FS, is directly related to the time needed by the PLL to reach its steady state. The signal PLL_LOCK, provided on an external pin, gives an indication of the lock status. It goes high when the PLL reaches its locking range. 

Four specific cases can be highlighted: 

|Four specific cases can be highlighted:||
|---|---|
|Transmitter Wake Up time from Sleep mode|_= TS_OSC + TS_FS + TS_TR_|
|Receiver Wake Up time from Sleep mode|_= TS_OSC + TS_FS + TS_RE_|
|Receiver Wake Up time from Sleep mode, AGC enabled|_= TS_OSC + TS_FS + TS_RE_AGC_|
|Receiver Wake Up time from Sleep mode, AGC and AFC enabled|=_TS_OSC + TS_FS + TS_RE_AGC&AFC_|



These timings are detailed in sections 4.2.1 and 4.2.3. 

In applications where the target average power consumption, or the target startup time, do not require setting the RFM69HW in the lowest power modes (Sleep or Standby), the respective timings _TS_OSC_ and _TS_FS_ in the former equations can be omitted. 

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**RFM69HW** 

## **4.2.1. Transmitter Startup Time** 

The transmitter wake-up time, TS_TR, is given by the sequence controlled by the digital part. It is a pure digital delay which depends on the bit rate and the ramp-up time. In FSK mode, this time can be derived from the following equation. 

**==> picture [7 x 4] intentionally omitted <==**

**----- Start of picture text -----**<br>
,<br>**----- End of picture text -----**<br>


where _PaRamp_ is the ramp-up time programmed in _RegPaRamp_ and _Tbit_ is the bit time. 

In OOK mode, this equation can be simplified to the following: 

**==> picture [298 x 97] intentionally omitted <==**

**----- Start of picture text -----**<br>
Tx startup request<br>(sequencer or user) TS_TR<br>— _—_—XK—"—X—__~> S<br>vy<br>1.25 x PaRamp<br>XO Started and PLL is locked  group delay Analog 0.5 x Tbit  (only in mode)FSK  Transmission of Packet<br>5 us<br>ModeReady<br>TxReady<br>**----- End of picture text -----**<br>


_Figure 17.  Tx Startup, FSK and OOK_ 

## **4.2.2. Tx Start Procedure** 

As described in the former section, _ModeReady_ and _TxReady_ interrupts warn the uC that the transmitter is ready to transmit data 

In Continuous mode, the preamble bits preceding the payload can be applied on the DIO2/DATA pin immediately after any of these interrupts have fired. The DCLK signal, activated on pin DIO1/DCLK can also be used to start toggling the DATA pin, as described on Figure 30. 

In Packet mode, the RFM69HW will automatically modulate the RF signal with preamble bytes as soon as _TxReady_ or 

_ModeReady_ happen. The actual packet transmission (starting with the number of preambles specified in _PreambleSize_ ) will start when the _TxStartCondition_ is fulfilled. 

## **4.2.3. Receiver Startup Time** 

It is highly recommended to use the built-in sequencer of the RFM69HW, to optimize the delays when setting the module in receive mode. It guarantees the shortest startup times, hence the lowest possible energy usage, for battery operated systems. 

The startup times of the receiver can be calculated from the following: 

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**RFM69HW** 

**==> picture [527 x 397] intentionally omitted <==**

**----- Start of picture text -----**<br>
Rx startup request<br>(sequencer or user) TS_RE<br>XO Started and PLL is locked  Analog FE’s  Channel Filter’s  DC Cutoff’s  RSSI  RSSI  Reception of Packet<br>group delay  group delay  group delay  sampling  sampling<br>ee<br>Tana Tcf  Tdcc  Trssi  Trssi<br>ModeReady<br>a RxReady<br>Received Packet Preamble may start<br>ee<br>Figure 18.  Rx Startup - No AGC, no AFC<br>The LNA gain is adjusted by<br>Rx startup request  the AGC, according to the<br>(sequencer or user)  TS_RE_AGC | RSSI result<br>XO Started and PLL is locked  Analog FE’s  Channel Filter’s  DC Cutoff’s  RSSI  RSSI  Channel Filter’s  DC Cutoff’s  RSSI  Reception of Packet<br>group delay  group delay  group delay  sampling  sampling  group delay  group delay  sampling<br>Tana Tcf  Tdcc  Trssi  Trssi  Tcf  Tdcc  Trssi<br>ModeReady<br>me<br>RxReady<br>———<br>Received Packet Preamble may start<br>Figure 19.  Rx Startup - AGC, no AFC<br>The LNA gain is adjusted by<br>Rx startup request  the AGC, according to the  Carrier Frequency is adjusted<br>(sequencer or user)  7 TS_RE_AGC&AFC RSSI result by the AFC<br>XO Started and PLL is locked  Analog FE’s group delay  Channel Filter’s group delay  group delay DC Cutoff’s  sampling RSSI  sampling RSSI  Channel Filter’s group delay  group delay DC Cutoff’s  sampling RSSI  AFC  PLL lock  Channel Filter’s group delay  group delay DC Cutoff’s  Reception of Packet<br>Tana Tcf  Tdcc  Trssi  Trssi  Tcf  Tdcc  Trssi  Tafc  Tpllafc  Tcf  Tdcc<br>ModeReady<br>i a<br>RxReady<br>— _— w a<br>**----- End of picture text -----**<br>


Received Packet Preamble may start 

_Figure 20.  Rx Startup - AGC and AFC_ 

The different timings shown above are as follows: 

_Tana = 20 us Tcf = 21 / (4.RxBw) Tcf = 34 / (4.RxBw)_ 

Group delay of the analog front end: _Tana = 20 us_ Channel filter’s group delay in FSK mode: _Tcf = 21 / (4.RxBw)_ Channel filter’s group delay in OOK mode: _Tcf = 34 / (4.RxBw)_ DC Cutoff’s group delay: _Tdcc = max(8 , 2^(round(log2(8.RxBw.Tbit)+1)) / (4.RxBw)_ PLL lock time after AFC adjustment: _Tpllafc = 5 / PLLBW (PLLBW = 300 kHz)_ AFC sample time: _Tafc = 4 x Tbit_ (also denoted TS_AFC in the general specification) RSSI sample time: _Trssi = 2 x int(4.RxBw.Tbit)/(4.RxBw)_ (aka TS_RSSI) 

_Note The above timings represent maximum settling times, and shorter settling times may be observed in real cases_ 

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**RFM69HW** 

## **4.2.4. Rx Start Procedure** 

As described in the former sections, the _RxReady_ interrupt warns the uC that the receiver is ready. 

In Continuous mode with Bit Synchronizer, the receiver will start locking its Bit Synchronizer on a minimum or 12 bits of received preamble (see section 3.4.13 for details), before the reception of correct Data, or Sync Word (if enabled) can occur. 

In Continuous mode without Bit Synchronizer, valid data will be available on DIO2/DATA right after the _RxReady_ interrupt. 

In Packet mode, the receiver will start locking its Bit Synchronizer on a minimum or 12 bits of received preamble (see section 3.4.13 for details), before the reception of correct Data, or Sync Word (if enabled) can occur. 

## **4.2.5. Optimized Frequency Hopping Sequences** 

In a frequency hopping-like application, it is required to turn off the transmitter when hopping from one channel to another, to avoid spectral splatter and obtain the best spectral purity. 

## Transmitter hop from Ch A to Ch B: it is advised to step through the Rx mode: 

   - (0) RFM69HW is in Tx mode in Ch A 

- (1) Program the RFM69HW in Rx mode 

- (2) Change the carrier frequency in the _RegFrf_ registers 

- (3) Turn the transceiver back to Tx mode 

- (4) Respect the Tx start procedure, described in section 4.2.2 

## Receiver hop from Ch A to Ch B: 

   - (0) RFM69HW is in Rx mode in Ch A 

- (1) Change the carrier frequency in the _RegFrf_ registers 

- (2) Program the RFM69HW in FS mode 

- (3) Turn the transceiver back to Rx mode 

- (4) Respect the Rx start procedure, described in section 4.2.4 

_Note all sequences described above are assuming that the sequencer is turned on (SequencerOff=0 in RegOpMode)._ 

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**RFM69HW** 

## **4.3.  Listen Mode** 

The circuit can be set to Listen mode, by setting _ListenOn_ in _RegOpMode_ to 1 while in Standby mode. In this mode, RFM69HW spends most of the time in Idle mode, during which only the RC oscillator runs. Periodically the receiver is woken up and listens for an RF signal. If a wanted signal is detected, the receiver is kept on and the data is demodulated. Otherwise, if a wanted signal hasn't been detected after a pre-defined period of time, the receiver is disabled until the next time period. 

This periodical Rx wake-up requirement is very common in low power applications. On RFM69HW it is handled locally by the 

Listen mode block without using uC resources or energy. 

The simplified timing diagram of this procedure is illustrated in Figure 21. 

**==> picture [365 x 123] intentionally omitted <==**

**----- Start of picture text -----**<br>
tListenIdle<br>Rx  Idle Rx<br>time<br>tListenRx  tListenRx<br>**----- End of picture text -----**<br>


_Figure 21.  Listen Mode Sequence (no wanted signal is received)_ 

## **4.3.1. Timings** 

The duration of the Idle phase is given by tListenIdle. The time during which the receiver is on and waits for a signal is given by tListenRx. tListenRx includes the wake-up time of the receiver, described in section 4.2.3. This duration can be programmed in the configuration registers via the serial interface. 

Both time periods tListenRx and tListenIdle (denoted tListenX in the following text) are fixed by two parameters from the configuration register and are calculated as follows: 

**==> picture [179 x 13] intentionally omitted <==**

where _ListenResolX_ is the Rx or Idle resolution and is independently programmable on three values (64us, 4.1ms or 262ms), whereas _ListenCoefX_ is an integer between 1 and 255. All parameters are located in _RegListen_ registers. 

The timing ranges are tabulated in Table 17 below. 

_Table 17  Range of Durations in Listen Mode_ 

|**_ListenResolX_**|**Min duration**<br>**(****_ListenCoef_= 1 )**|**Max duration**<br>**(****_ListenCoef_= 255 )**|
|---|---|---|
|01|64us|16ms|
|10|4.1ms|1.04s|
|11|0.26s|67s|



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**RFM69HW** 

_Notes   - the accuracy of the typical timings given in Table 17 will depend in the RC oscillator calibration_ 

_- RC oscillator calibration is required, and must be performed at power up. See section 4.3.5 for details_ 

## **4.3.2. Criteria** 

The criteria taken for detecting a wanted signal and hence deciding to maintain the receiver on is defined by _ListenCriteria_ in _RegListen1._ 

_Table 18  Signal Acceptance Criteria in Listen Mode_ 

|**_ListenCriteria_**|**Input Signal Power**<br>**>=****_RssiThreshold_**|**_SyncAddressMatch_**|
|---|---|---|
|0|Required|Not Required|
|1|Required<br>Required|Not Required<br>Required|



## **4.3.3. End of Cycle Actions** 

The action taken after detection of a packet, is defined by _ListenEnd_ in _RegListen3_ , as described in the table below. 

_Table 19  End of Listen Cycle Actions_ 

|**_ListenEnd_**|**Description**|
|---|---|
|00|Module stays in Rx mode. Listen mode stops and must be disabled.|
|01<br>mode defined by|Module stays in Rx mode until_PayloadReady_or_Timeout_interrupt occurs. It then goes to the<br>mode defined by_Mode_. Listen mode stops and must be disabled.|
|10<br>resumes in Idle state. FIFO content is lost at next Rx wakeup.|Module stays in Rx mode until_PayloadReady_or_Timeout_interrupt occurs. Listen mode then<br>resumes in Idle state. FIFO content is lost at next Rx wakeup.|



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Upon detection of a valid packet, the sequencing is altered, as shown below: 

**==> picture [481 x 266] intentionally omitted <==**

**----- Start of picture text -----**<br>
PayloadReady<br>ListenCriteria<br>passed<br>a<br>Idle  Rx<br>ListenEnd = 00<br>Listen Mode<br>a<br>Idle  Rx  Mode<br>ListenEnd = 01<br>Listen Mode<br>ee<br>Idle Rx Idle Rx<br>ListenEnd = 10<br>Listen Mode<br>**----- End of picture text -----**<br>


_Figure 22.  Listen Mode Sequence (wanted signal is received)_ 

## **4.3.4. Stopping Listen Mode** 

To abort Listen mode operation, the following procedure must be respected: 

Program _RegOpMode_ with _ListenOn_ =0, _ListenAbort_ =1, and the desired setting for the _Mode_ bits (Sleep, Stdby, FS, Rx or Tx mode) in a single SPI access 

Program _RegOpMode_ with _ListenOn_ =0, _ListenAbort_ =0, and the desired setting for the _Mode_ bits (Sleep, Stdby, FS, Rx or Tx mode) in a second SPI access 

## **4.3.5. RC Timer Accuracy** 

All timings of the Listen Mode rely on the accuracy of the internal low-power RC oscillator. This oscillator is automatically calibrated at the device power-up, and it is a user-transparent process. 

For applications enduring large temperature variations, and for which the power supply is never removed, RC calibration can be performed upon user request. _RcCalStart_ in _RegOsc1_ can be used to trigger this calibration, and the flag _RcCalDone_ will be set automatically when the calibration is over. 

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**RFM69HW** 

## **4.4.  AutoModes** 

Automatic modes of packet handler can be enabled by configuring the related parameters in _RegAutoModes_ . The intermediate mode of the module is called _IntermediateMode_ and the enter and exit conditions to/from this intermediate mode can be configured through the parameters _EnterCondition_ & _ExitCondition_ . 

The enter and exit conditions cannot be used independently of each other i.e. both should be enabled at the same time. The initial and the final state is the one configured in _Mode_ in _RegOpMode_ . The initial & final states can be different by configuring the modes register while the module is in intermediate mode. The pictorial description of the auto modes is shown 

below. 

**==> picture [248 x 89] intentionally omitted <==**

**----- Start of picture text -----**<br>
Intermediate State<br>defined by  IntermediateMode<br>EnterCondition  ExitCondition<br>Initial  state defined  Final  state defined<br>By M ode  in RegOpMode  By M ode  in RegOpMode<br>**----- End of picture text -----**<br>


## _Figure 23.  Auto Modes of Packet Handler_ 

Some typical examples of AutoModes usage are described below: 

Automatic transmission (AutoTx) : _Mode_ = Sleep, _IntermediateMode_ = Tx, _EnterCondition_ = _FifoLevel_ , _ExitCondition_ = _PacketSent_ 

Automatic reception (AutoRx) : _Mode_ = Rx, _IntermediateMode_ = Sleep, _EnterCondition_ = _CrcOk_ , _ExitCondition_ = falling edge of _FifoNotEmpty_ 

Automatic reception of acknowledge (AutoRxAck): _Mode_ = Tx, _IntermediateMode_ = Rx, _EnterCondition_ = _PacketSent_ , _ExitCondition_ = _CrcOk_ 

... 

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**RFM69HW** 

## **5. Data Processing** 

## **5.1.  Overview** 

## **5.1.1. Block Diagram** 

Figure below illustrates the RFM69HW data processing circuit. Its role is to interface the data to/from the modulator/ demodulator and the uC access points (SPI and DIO pins). It also controls all the configuration registers. 

The circuit contains several control blocks which are described in the following paragraphs. 

**==> picture [468 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
Tx/Rx DIO0<br>| x DIO1<br>DIO2<br>CONTROL<br>. Xx DIO3<br>: me DIO4<br>DIO5<br>i: m<<br>/ . [.]<br>fo i<br>/ Data . [.] Rx  SYNC<br>RECOG.<br>i [7]<br>iZFe [.][.] 1 » PACKET  FIFO  SPI<br>3 [7] 1: HANDLER (+SR)<br>Tx NSS<br>44 Perr rrr ritT . . an ix!x SCK MOSI<br>i on px MISO<br>**----- End of picture text -----**<br>


Potential datapaths (data operation mode dependant) 

_Figure 24.  RFM69HW Data Processing Conceptual_ 

_View_ 

The RFM69HW implements several data operation modes, each with their own data path through the data processing section. Depending on the data operation mode selected, some control blocks are active whilst others remain disabled. 

## **5.1.2. Data Operation Modes** 

The RFM69HW has two different data operation modes selectable by the user: 

~~ee~~ Continuous mode: each bit transmitted or received is accessed in real time at the DIO2/DATA pin. This mode may be used if adequate external signal processing is available. 

~~ee~~ Packet mode (recommended): user only provides/retrieves payload bytes to/from the FIFO. The packet is automatically built with preamble, Sync word, and optional AES, CRC, and DC-free encoding schemes The reverse operation is performed in reception. The uC processing overhead is hence significantly reduced compared to Continuous mode. Depending on the optional features activated (CRC, AES, etc) the maximum payload length is limited to FIFO size, 255 bytes or unlimited. 

Each of these data operation modes is described fully in the following sections. 

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**RFM69HW** 

## **5.2.  Control Block Description** 

## **5.2.1. SPI Interface** 

The SPI interface gives access to the configuration register via a synchronous full-duplex protocol corresponding to CPOL = 0 and CPHA = 0 in Motorola/Freescale nomenclature. Only the slave side is implemented. 

Three access modes to the registers are provided: 

SINGLE access: an address byte followed by a data byte is sent for a write access whereas an address byte is sent and a read byte is received for the read access. The NSS pin goes low at the begin of the frame and goes high after the data byte. 

BURST access: the address byte is followed by several data bytes. The address is automatically incremented internally between each data byte. This mode is available for both read and write accesses. The NSS pin goes low at the beginning of the frame and stay low between each byte. It goes high only after the last byte transfer. 

FIFO access: if the address byte corresponds to the address of the FIFO, then succeeding data byte will address the FIFO. The address is not automatically incremented but is memorized and does not need to be sent between each data byte. The NSS pin goes low at the beginning of the frame and stay low between each byte. It goes high only after the last byte transfer. 

Figure below shows a typical SPI single access to a register. 

_Figure 25.  SPI Timing Diagram (single access)_ 

MOSI is generated by the master on the falling edge of SCK and is sampled by the slave (i.e. this SPI interface) on the rising edge of SCK. MISO is generated by the slave on the falling edge of SCK. 

A transfer always starts by the NSS pin going low. MISO is high impedance when NSS is high. 

The first byte is the address byte. It is made of: 

wnr bit, which is 1 for write access and 0 for read access 

- 7 bits of address, MSB first 

The second byte is a data byte, either sent on MOSI by the master in case of a write access, or received by the master on MISO in case of read access. The data byte is transmitted MSB first. 

Proceeding bytes may be sent on MOSI (for write access) or received on MISO (for read access) without rising NSS and re-sending the address. In FIFO mode, if the address was the FIFO address then the bytes will be written / read at the FIFO address. In Burst mode, if the address was not the FIFO address, then it is automatically incremented at each new byte received. 

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**RFM69HW** 

The frame ends when NSS goes high. The next frame must start with an address byte. The SINGLE access mode is actually a special case of FIFO / BURST mode with only 1 data byte transferred. 

During the write access, the byte transferred from the slave to the master on the MISO line is the value of the written register before the write operation. 

## **5.2.2. FIFO** 

## _5.2.2.1. Overview and Shift Register (SR)_ 

In packet mode of operation, both data to be transmitted and that has been received are stored in a configurable FIFO (First In First Out) device. It is accessed via the SPI interface and provides several interrupts for transfer management. 

The FIFO is 1 byte wide hence it only performs byte (parallel) operations, whereas the demodulator functions serially. A shift register is therefore employed to interface the two devices. In transmit mode it takes bytes from the FIFO and outputs them serially (MSB first) at the programmed bit rate to the modulator. Similarly, in Rx the shift register gets bit by bit data from the demodulator and writes them byte by byte to the FIFO. This is illustrated in figure below. 

**==> picture [226 x 86] intentionally omitted <==**

**----- Start of picture text -----**<br>
FIFO<br>byte1<br>byte0<br>8<br>Data Tx/Rx<br>SR (8bits)<br>1<br>MSB  LSB<br>**----- End of picture text -----**<br>


_Figure 26.  FIFO and Shift Register (SR)_ 

_Note When switching to Sleep mode, the FIFO can only be used once the ModeReady flag is set (quasi immediate from all modes except from Tx)_ 

## _5.2.2.2. Size_ 

The FIFO size is fixed to 66 bytes. 

## _5.2.2.3. Interrupt Sources and Flags_ 

FifoNotEmpty: FifoNotEmpty interrupt source is low when byte 0, i.e. whole FIFO, is empty. Otherwise it is high. Note that when retrieving data from the FIFO, FifoNotEmpty is updated on NSS falling edge, i.e. when FifoNotEmpty is updated to low state the currently started read operation must be completed. In other words, FifoNotEmpty state must be checked after each read operation for a decision on the next one (FifoNotEmpty = 1: more byte(s) to read; FifoNotEmpty = 0: no more byte to read). 

FifoFull: FifoFull interrupt source is high when the last FIFO byte, i.e. the whole FIFO, is full. Otherwise it is low. 

FifoOverrunFlag: FifoOverrunFlag is set when a new byte is written by the user (in Tx or Standby modes) or the SR (inRx mode) while the FIFO is already full. Data is lost and the flag should be cleared by writing a 1, note that the FIFO will also be cleared. 

PacketSent: PacketSent interrupt source goes high when the SR's last bit has been sent. 

FifoLevel: Threshold can be programmed by FifoThreshold in RegFifoThresh. Its behavior is illustrated in figure below. 

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**RFM69HW** 

**==> picture [349 x 203] intentionally omitted <==**

**----- Start of picture text -----**<br>
FifoLevel<br>1<br>0  B  B+1  # of bytes in FIFO<br>**----- End of picture text -----**<br>


_Figure 27.  FifoLevel IRQ Source Behavior_ 

- _Note - FifoLevel interrupt is updated only after a read or write operation on the FIFO. Thus the interrupt cannot be dynamically updated by only changing the FifoThreshold parameter_ 

   - _FifoLevel interrupt is valid as long as FifoFull does not occur. An empty FIFO will restore its normal operation_ 

## _5.2.2.4. FIFO Clearing_ 

Table below summarizes the status of the FIFO when switching between different modes 

_Table 20  Status of FIFO when Switching Between Different Modes of the Module_ 

|**From**|**To**|**FIFO status**|**Comments**|
|---|---|---|---|
|Stdby|Sleep|Not cleared||
|Sleep|Stdby|Not cleared||
|Stdby/Sleep|Tx|Not cleared|To allow the user to write the FIFO in Stdby/Sleep before Tx|
|Stdby/Sleep|Rx|Cleared||
|Rx|Tx|Cleared||
|Rx|Stdby/Sleep|Not cleared|To allow the user to read FIFO in Stdby/Sleep mode after Rx|
|Tx|Any|Cleared||



## **5.2.3. Sync Word Recognition** 

## _5.2.3.1. Overview_ 

Sync word recognition (also called Pattern recognition) is activated by setting _SyncOn_ in _RegSyncConfig_ . The bit synchronizer must also be activated in continuous mode (automatically done in Packet mode) . 

The block behaves like a shift register; it continuously compares the incoming data with its internally programmed Sync word and sets _SyncAddressMatch_ when a match is detected. This is illustrated in Figure 28 below. 

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**==> picture [478 x 120] intentionally omitted <==**

**----- Start of picture text -----**<br>
Rx DATA<br>Bit N-x =  Bit N-1 =  Bit N =<br>(NRZ)<br>Sync_value[x]  7 se Sync_value[1]  Sync_value[0]  ee<br>DCLK<br>SyncAddressMatch<br>**----- End of picture text -----**<br>


_Figure 28.  Sync Word Recognition_ 

During the comparison of the demodulated data, the first bit received is compared with bit 7 (MSB) of _RegSyncValue1_ and the last bit received is compared with bit 0 (LSB) of the last byte whose address is determined by the length of the Sync word. 

When the programmed Sync word is detected the user can assume that this incoming packet is for the node and can be processed accordingly. 

_SyncAddressMatch_ is cleared when leaving Rx or FIFO is emptied. 

## _5.2.3.2. Configuration_ 

- Size: Sync word size can be set from 1 to 8 bytes (i.e. 8 to 64 bits) via SyncSize in RegSyncConfig. In Packet mode this field is also used for Sync word generation in Tx mode. 

- Error tolerance: The number of errors tolerated in the Sync word recognition can be set from 0 to 7 bits to via SyncTol. 

- Value: The Sync word value is configured in SyncValue(63:0). In Packet mode this field is also used for Sync word generation in Tx mode. 

_Note SyncValue choices containing 0x00 bytes are not allowed_ 

## **5.2.4. Packet Handler** 

The packet handler is the block used in Packet mode. Its functionality is fully described in section 5.5. 

## **5.2.5. Control** 

The control block configures and controls the full module's behavior according to the settings programmed in the configuration registers. 

## **5.3.  Digital IO Pins Mapping** 

Six general purpose IO pins are available on the RFM69HW, and their configuration in Continuous or Packet mode is controlled through _RegDioMapping1_ and _RegDioMapping2._ 

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## **5.3.1. DIO Pins Mapping in Continuous Mode** 

_Table 21  DIO Mapping, Continuous Mode_ 

|**_Mode_**|**_Diox_**<br>**_Mapping_**|**DIO5**|**DIO4**|**DIO3**|**DIO2**|**DIO1**|**DIO0**|
|---|---|---|---|---|---|---|---|
|Sleep|00<br>~~CO~~<br>~~**p**O~~|-<br>~~CO~~<br>~~O~~|-<br>~~CO~~|-<br>~~CO~~|-<br>~~CO~~|-<br>~~CO~~|-<br>~~CO~~|
||01<br>~~**p**O~~|-<br>~~O~~|-|-|-|-|-|
||10<br>~~**p**O~~|-<br>~~O~~|-|AutoMode<br>~~f~~|-<br>~~f~~|-<br>~~f~~|-<br>~~f~~|
||11<br>~~po~~<br>~~RS~~|ModeReady<br>~~po~~<br>~~RS~~|-<br>~~po~~<br>~~CO~~|-<br>~~po~~<br>~~CO~~|-<br>~~po~~<br>~~CO~~|-<br>~~po~~<br>~~CO~~|ModeReady<br>~~po~~<br>~~CO~~|
|Stdby|00<br>~~RS~~<br>~~**p**o~~|ClkOut<br>~~RS~~<br>~~o~~|-<br>~~CO~~|-<br>~~CO~~|-<br>~~CO~~|-<br>~~CO~~|-<br>~~CO~~|
||01<br>~~RS~~<br>~~**p**o~~|-<br>~~RS~~<br>~~o~~|-<br>~~CO~~|-<br>~~CO~~|-<br>~~CO~~|-<br>~~CO~~|-<br>~~CO~~|
||10<br>~~**p**o~~|-<br>~~o~~|-|AutoMode<br>~~f~~|-<br>~~f~~|-<br>~~f~~|-<br>~~f~~|
||11<br>~~aRs~~|ModeReady<br>~~Rs~~|-<br>~~Rs~~|-<br>~~Rs~~|-<br>~~Rs~~|-<br>~~Rs~~|ModeReady<br>~~Rs~~|
|FS|00<br>~~pT~~|ClkOut<br>~~pT~~|-<br>~~pT~~|-<br>~~pT~~|-<br>~~pT~~|-<br>~~pT~~|PllLock<br>~~pT~~|
||01<br>~~po~~|-<br>~~po~~|-<br>~~po~~|-<br>~~po~~|-<br>~~po~~|-<br>~~po~~|-<br>~~po~~|
||10<br>~~pf~~|-<br>~~pf~~|-<br>~~pf~~|AutoMode<br>~~pf~~|-<br>~~pf~~|-<br>~~pf~~|-<br>~~pf~~|
||11<br>~~se~~|ModeReady<br>~~se~~|PllLock<br>~~se~~|-<br>~~se~~|-<br>~~se~~|PllLock<br>~~se~~|ModeReady<br>~~se~~|
|Rx|00<br>~~A~~<br>~~po~~|ClkOut<br>~~A~~<br>~~po~~|Timeout<br>~~CO~~|Rssi<br>~~CO~~|Data<br>~~CO~~|Dclk<br>~~CO~~|SyncAddress|
||01<br>~~po~~|Rssi<br>~~po~~|RxReady|RxReady|Data|RxReady|Timeout|
||10<br>~~po~~<br>~~pT~~|-<br>~~po~~<br>~~pT~~|SyncAddress<br>~~pT~~|AutoMode<br>~~pT~~|Data<br>~~pT~~|-<br>~~pT~~|Rssi<br>~~pT~~|
||11<br>~~po~~|ModeReady<br>~~po~~|PllLock<br>~~po~~|Timeout<br>~~po~~|Data<br>~~po~~|SyncAddress<br>~~po~~|ModeReady<br>~~po~~|
|Tx|00<br>~~pf~~<br>~~**p**O~~|ClkOut<br>~~pf~~<br>~~O~~|TxReady<br>~~pf~~|TxReady<br>~~pf~~|Data<br>~~pf~~|Dclk<br>~~pf~~|PllLock<br>~~pf~~|
||01<br>~~**p**O~~|ClkOut<br>~~O~~|TxReady|TxReady|Data|TxReady|TxReady|
||10<br>~~**p**O~~<br>~~Rs~~|-<br>~~O~~<br>~~Rs~~|-<br>~~es~~|AutoMode<br>~~f~~|Data<br>~~f~~|-<br>~~f~~|-<br>~~f~~|
||11<br>~~Rs~~|ModeReady<br>~~Rs~~|PllLock<br>~~es~~|TxReady|Data|PllLock|ModeReady|



## **5.3.2. DIO Pins Mapping in Packet Mode** 

_Table 22  DIO Mapping, Packet Mode_ 

|**_Mode_**|**_Diox_**<br>**_Mapping_**<br>~~SR~~|**DIO5**<br>~~SR~~|**DIO4**<br>~~GO~~|**DIO3**<br>~~GO~~|**DIO2**<br>~~CG~~|**DIO1**<br>~~CG~~|**DIO0**|
|---|---|---|---|---|---|---|---|
|Sleep|00<br>~~SR~~|-<br>~~SR~~|-<br>~~GO~~|FifoFull<br>~~GO~~|FifoNotEmpty<br>~~CG~~|FifoLevel<br>~~CG~~|-|
||01<br>~~SR~~<br>~~pO~~|-<br>~~SR~~<br>~~pO~~|-<br>~~GO~~<br>~~pO~~|-<br>~~GO~~<br>~~pO~~|-<br>~~CG~~<br>~~pO~~|FifoFull<br>~~CG~~<br>~~pO~~|-<br>~~pO~~|
||10<br>~~pT~~|-<br>~~pT~~|-<br>~~pT~~|-<br>~~pT~~|-<br>~~pT~~|FifoNotEmpty<br>~~pT~~|-<br>~~pT~~|
|~~**p**~~|11<br>~~I~~<br>~~**p**O~~|ModeReady<br><br>~~O~~|-<br>|-<br>|AutoMode<br>|-<br><br>~~OO~~|-<br>|
|Stdby<br>~~**p**~~|00<br>~~GC~~<br>~~**p**O~~|ClkOut<br>~~GC~~<br>~~O~~|-<br>~~GC~~|FifoFull<br>~~GC~~|FifoNotEmpty<br>~~GC~~|FifoLevel<br>~~GC~~<br>~~OO~~|-<br>~~GC~~|
|~~**p**~~|01<br>~~**p**O~~|-<br>~~O~~|-|-|-|FifoFull<br>~~OO~~|-|
|~~**p**~~|10<br>~~**p**O~~<br>~~es~~|-<br>~~O~~<br>~~es~~|-<br>~~es~~|-<br>~~T~~|-<br>~~T~~|FifoNotEmpty<br>~~OO~~<br>~~T~~<br>~~(~~|-<br>~~T~~|
||11<br>~~es~~|ModeReady<br>~~es~~|-<br>~~es~~|-|AutoMode|-<br>~~(~~|-|
|FS<br>~~**p**~~|00<br>~~es~~<br>~~pT~~<br>~~**p**o~~|ClkOut<br>~~es~~<br>~~pT~~<br>~~o~~|-<br>~~es~~<br>~~pT~~|FifoFull<br>~~pT~~|FifoNotEmpty<br>~~pT~~|FifoLevel<br>~~(~~<br>~~pT~~|-<br>~~pT~~|
|~~**p**~~|01<br>~~**p**o~~|-<br>~~o~~|-|-|-|FifoFull|-|
|~~**p**~~|10<br>~~**p**o~~<br>~~a~~|-<br>~~o~~<br>~~ee~~|-<br>~~ee~~|-<br>~~O~~<br>~~ss~~|-<br>~~O~~<br>~~ss~~|FifoNotEmpty<br>~~O~~|-<br>~~O~~|
||11<br>~~a~~|ModeReady<br>~~ee~~|PllLock<br>~~ee~~|PllLock<br>~~ss~~|AutoMode<br>~~ss~~|PllLock|PllLock|
|Rx|00<br>~~a~~<br>~~CC~~|ClkOut<br>~~ee~~<br>~~CC~~|Timeout<br>~~ee~~<br>~~CC~~|FifoFull<br>~~ss~~<br>~~CC~~|FifoNotEmpty<br>~~ss~~<br>~~CC~~|FifoLevel<br>~~CC~~|CrcOk<br>~~CC~~|
||01<br>~~pT~~|Data<br>~~pT~~|Rssi<br>~~pT~~|Rssi<br>~~pT~~|Data<br>~~pT~~|FifoFull<br>~~pT~~|PayloadReady<br>~~pT~~|
||10<br>~~pO~~|-<br>~~pO~~|RxReady<br>~~pO~~|SyncAddress<br>~~pO~~|-<br>~~pO~~|FifoNotEmpty<br>~~pO~~|SyncAddress<br>~~pO~~|
||11<br>~~pO~~|ModeReady<br>~~pO~~|PllLock<br>~~pO~~|PllLock<br>~~pO~~|AutoMode<br>~~pO~~|Timeout<br>~~pO~~|Rssi<br>~~pO~~|
|Tx|00<br>~~pT~~|ClkOut<br>~~pT~~|ModeReady<br>~~pT~~|FifoFull<br>~~pT~~|FifoNotEmpty<br>~~pT~~|FifoLevel<br>~~pT~~|PacketSent<br>~~pT~~|
|~~pO~~|01<br>~~pT~~<br>~~pO~~|Data<br>~~pT~~<br>~~pO~~|TxReady<br>~~pT~~|TxReady<br>~~pT~~|Data<br>~~pT~~|FifoFull<br>~~pT~~|TxReady<br>~~pT~~|
|~~pO~~|10<br>~~pO~~|-<br>~~pO~~|-|-|-|FifoNotEmpty|-|
|~~pO~~|11<br>~~pO~~<br>~~po~~|ModeReady<br>~~pO~~<br>~~po~~|PllLock<br>~~po~~|PllLock<br>~~po~~|AutoMode<br>~~po~~|PllLock<br>~~po~~|PllLock<br>~~po~~|



_Note Received Data is only shown on the Data signal between RxReady and PayloadReady’s rising edges_ 

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## **5.4.  Continuous Mode** 

## **5.4.1. General Description** 

As illustrated in Figure 29, in Continuous mode the NRZ data to (from) the (de)modulator is directly accessed by the uC on the bidirectional DIO2/DATA pin. The FIFO and packet handler are thus inactive. 

**==> picture [493 x 194] intentionally omitted <==**

**----- Start of picture text -----**<br>
Tx/Rx DIO0<br>DIO1/DCLK<br>DIO2/DATA<br>CONTROL<br>\ paidx] DIO3<br>DIO4<br>x] DIO5<br>Data Rx<br>i SYNC<br>f<br>RECOG.<br>SPI<br>NSS<br>SCK<br>MOSI<br>\ <—x MISO<br>**----- End of picture text -----**<br>


_Figure 29.  Continuous Mode Conceptual View_ 

## **5.4.2. Tx Processing** 

In Tx mode, a synchronous data clock for an external uC is provided on DIO1/DCLK pin. Clock timing with respect to the data is illustrated in Figure 30. DATA is internally sampled on the rising edge of DCLK so the uC can change logic state anytime outside the grayed out setup/hold zone. 

**==> picture [202 x 90] intentionally omitted <==**

**----- Start of picture text -----**<br>
T_DATA  T_DATA<br>if I<br>DATA<br>(NRZ)<br>DCLK<br>**----- End of picture text -----**<br>


_Figure 30.  Tx Processing in Continuous Mode_ 

_Note the use of DCLK is required when the modulation shaping is enabled (see section 3.3.5)._ 

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## **5.4.3. Rx Processing** 

If the bit synchronizer is disabled, the raw demodulator output is made directly available on DATA pin and no DCLK signal is provided. 

Conversely, if the bit synchronizer is enabled, synchronous cleaned data and clock are made available respectively on DIO2/DATA and DIO1/DCLK pins. DATA is sampled on the rising edge of DCLK and updated on the falling edge as illustrated below. 

**==> picture [66 x 54] intentionally omitted <==**

**----- Start of picture text -----**<br>
DATA (NRZ)<br>DCLK<br>**----- End of picture text -----**<br>


_Figure 31.  Rx Processing in Continuous Mode_ 

_Note in Continuous mode it is always recommended to enable the bit synchronizer to clean the DATA signal even if the DCLK signal is not used by the uC (bit synchronizer is automatically enabled in Packet mode)._ 

## **5.5.  Packet Mode** 

## **5.5.1. General Description** 

In Packet mode the NRZ data to (from) the (de)modulator is not directly accessed by the uC but stored in the FIFO and accessed via the SPI interface. 

In addition, the RFM69HW packet handler performs several packet oriented tasks such as Preamble and Sync word generation, CRC calculation/check, whitening/dewhitening of data, Manchester encoding/decoding, address filtering, AES encryption/decryption, etc. This simplifies software and reduces uC overhead by performing these repetitive tasks within the RF module itself. 

Another important feature is ability to fill and empty the FIFO in Sleep/Stdby mode, ensuring optimum power consumption and adding more flexibility for the software. 

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## **DATASHEET** 

**==> picture [456 x 201] intentionally omitted <==**

**----- Start of picture text -----**<br>
DIO0<br>DIO1<br>DIO2<br>4 CONTROL |<br>DIO3<br>i |<br>| |a DIO4<br>/ DIO5<br>/<br>Data Rx<br>SYNC<br>RECOG.<br>PACKET  FIFO<br>SPI<br>HANDLER (+SR)<br>NSS<br>Tx<br>SCK<br>MOSI<br>x<br>MISO<br>**----- End of picture text -----**<br>


_Figure 32.  Packet Mode Conceptual View_ 

_Note The Bit Synchronizer is automatically enabled in Packet mode._ 

## **5.5.2. Packet Format** 

## _5.5.2.1. Fixed Length Packet Format_ 

Fixed length packet format is selected when bit _PacketFormat_ is set to 0 and _PayloadLength_ is set to any value greater than 0. 

In applications where the packet length is fixed in advance, this mode of operation may be of interest to minimize RF overhead (no length byte field is required). All nodes, whether Tx only, Rx only, or Tx/Rx should be programmed with the same packet length value. 

The length of the payload is limited to 255 bytes if AES is not enabled else the message is limited to 64 bytes (i.e. max 65 bytes payload if Address byte is enabled). 

The length programmed in _PayloadLength_ relates only to the payload which includes the message and the optional address byte. In this mode, the payload must contain at least one byte, i.e. address or message byte. 

An illustration of a fixed length packet is shown below. It contains the following fields: 

- Preamble (1010...) 

- Sync word (Network ID) 

- Optional Address byte (Node ID) 

- Message data 

- Optional 2-bytes CRC checksum 

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**==> picture [279 x 90] intentionally omitted <==**

**----- Start of picture text -----**<br>
DC free Data encoding<br>CRC checksum calculation<br>AES Enc/Dec<br>Preamble<br>0 to 65535  Sync Word  Address  Message CRC<br>0 to 8  bytes byte Up to  255 bytes 2-bytes<br>bytes<br>Payload<br>( min 1 byte )<br>**----- End of picture text -----**<br>


Fields added by the packet handler in Tx and processed and removed in Rx 

Optional User provided fields which are part of the payload Message part of the payload 

_Figure 33.  Fixed Length Packet Format_ 

## _5.5.2.2. Variable Length Packet Format_ 

Variable length packet format is selected when bit _PacketFormat_ is set to 1. 

This mode is useful in applications where the length of the packet is not known in advance and can vary over time. It is then necessary for the transmitter to send the length information together with each packet in order for the receiver to operate properly. 

In this mode the length of the payload, indicated by the length byte, is given by the first byte of the FIFO and is limited to 255 bytes if AES is not enabled else the message is limited to 64 bytes (i.e. max 66 bytes payload if Address byte is enabled). Note that the length byte itself is not included in its calculation. In this mode, the payload must contain at least 2 bytes, i.e. length + address or message byte. 

An illustration of a variable length packet is shown below. It contains the following fields: 

Preamble (1010...) 

Sync word (Network ID) 

Length byte 

Optional Address byte (Node ID) 

Message data 

Optional 2-bytes CRC checksum 

**==> picture [322 x 145] intentionally omitted <==**

**----- Start of picture text -----**<br>
DC free Data encoding<br>CRC checksum calculation<br>AES Enc/Dec<br>Preamble<br>Sync Word  Length  Address  Message CRC<br>0 to 65535<br>0 to 8  bytes byte byte Up  to 255 bytes 2-bytes<br>bytes<br>Payload<br>(min 2 bytes)<br>Fields added by the packet handler in Tx and processed and removed in Rx<br>Optional User provided fields which are part of the payload<br>Message part of the payload<br>**----- End of picture text -----**<br>


_Figure 34.  Variable Length Packet Format_ 

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## _5.5.2.3. Unlimited Length Packet Format_ 

Unlimited length packet format is selected when bit _PacketFormat_ is set to 0 and _PayloadLength_ is set to 0. 

The user can then transmit and receive packet of arbitrary length and _PayloadLength_ register is not used in Tx/Rx modes for counting the length of the bytes transmitted/received. This mode is a replacement for the legacy buffered mode in RF63/RF64 transceivers. 

In Tx the data is transmitted depending on the _TxStartCondition_ bit. On the Rx side the data processing features like Address filtering, Manchester encoding and data whitening are not available if the sync pattern length is set to zero ( _SyncOn = 0_ ). The filling of the FIFO in this case can be controlled by the bit _FifoFillCondition_ . The CRC detection in Rx is also not supported in this mode of the packet handler, however CRC generation in Tx is operational. The interrupts like _CrcOk_ & _PayloadReady_ are not available either. 

An unlimited length packet shown in is made up of the following fields: 

Preamble (1010...). 

Sync word (Network ID). 

Optional Address byte (Node ID). 

Message data 

Optional 2-bytes CRC checksum (Tx only) 

**==> picture [236 x 74] intentionally omitted <==**

**----- Start of picture text -----**<br>
— DC free Data encoding —><br>Preamble<br>Sync Word Address  Message<br>0 to 65535<br>bytes 0 to 8  bytes byte unlimited length<br>———— Payload ——><br>**----- End of picture text -----**<br>


Fields added by the packet handler in Tx and processed and removed in Rx 

Message part of the payload 

Optional User provided fields which are part of the payload 

## _Figure 35.  Unlimited Length Packet Format_ 

## **5.5.3. Tx Processing (without AES)** 

In Tx mode the packet handler dynamically builds the packet by performing the following operations on the payload available in the FIFO: 

Add a programmable number of preamble bytes 

Add a programmable Sync word 

Optionally calculating CRC over complete payload field (optional length byte + optional address byte + message) andappending the 2 bytes checksum. 

Optional DC-free encoding of the data (Manchester or whitening) 

Only the payload (including optional address and length fields) is required to be provided by the user in the FIFO. 

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The transmission of packet data is initiated by the Packet Handler only if the module is in Tx mode and the transmission condition defined by _TxStartCondition_ is fulfilled. If transmission condition is not fulfilled then the packet handler transmits a preamble sequence until the condition is met. This happens only if the preamble length /= 0, otherwise it transmits a zero or one until the condition is met to transmit the packet data. 

The transmission condition itself is defined as: 

if _TxStartCondition_ = 1, the packet handler waits until the first byte is written into the FIFO, then it starts sending the preamble followed by the sync word and user payload 

If _TxStartCondition_ = 0, the packet handler waits until the number of bytes written in the FIFO is equal to the number defined in _RegFifoThresh_ + 1 

If the condition for transmission was already fulfilled i.e. the FIFO was filled in Sleep/Stdby then the transmission of packet starts immediately on enabling Tx 

## **5.5.4. Rx Processing (without AES)** 

In Rx mode the packet handler extracts the user payload to the FIFO by performing the following operations: 

Receiving the preamble and stripping it off 

Detecting the Sync word and stripping it off 

Optional DC-free decoding of data 

Optionally checking the address byte 

Optionally checking CRC and reflecting the result on _CrcOk._ 

Only the payload (including optional address and length fields) is made available in the FIFO. 

When the Rx mode is enabled the demodulator receives the preamble followed by the detection of sync word. If fixed length packet format is enabled then the number of bytes received as the payload is given by the _PayloadLength_ parameter. 

In variable length mode the first byte received after the sync word is interpreted as the length of the received packet. The internal length counter is initialized to this received length. The _PayloadLength_ register is set to a value which is greater than the maximum expected length of the received packet. If the received length is greater than the maximum length stored in _PayloadLength_ register the packet is discarded otherwise the complete packet is received. 

If the address check is enabled then the second byte received in case of variable length and first byte in case of fixed length is the address byte. If the address matches to the one in the _NodeAddress_ field, reception of the data continues otherwise it's stopped. The CRC check is performed if _CrcOn_ = 1 and the result is available in _CrcOk_ indicating that the CRC was successful. An interrupt ( _PayloadReady_ ) is also generated on DIO0 as soon as the payload is available in the FIFO. The payload available in the FIFO can also be read in Sleep/Standby mode. 

If the CRC fails the _PayloadReady_ interrupt is not generated and the FIFO is cleared. This function can be overridden by setting _CrcAutoClearOff_ = 1, forcing the availability of _PayloadReady_ interrupt and the payload in the FIFO even if the CRC fails. 

## **5.5.5. AES** 

AES is the symmetric-key block cipher that provides the cryptographic capabilities to the transceiver. The system proposed can work with 128-bit long fixed keys. The fixed key is stored in a 16-byte write only user configuration register, which retains its value in Sleep mode. 

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**RFM69HW** 

As shown in  Figure 33 and Figure 34 above the message part of the Packet can be encrypted and decrypted with the cipher 128- cipher key stored in the configuration registers. 

## _5.5.5.1. Tx Processing_ 

1. User enters the data to be transmitted in FIFO in Stdby/Sleep mode and gives the transmit command. 

2. On Tx command the Packet handler state machine takes over the control and If encryption is enabled then the message inside the FIFO is read in blocks of 16 bytes (padded with 0s if needed), encrypted and stored back to FIFO. All this processing is done in Tx mode before enabling the packet handling state machine. Only the Message part of the packet is encrypted and preamble, sync word, length byte, address byte and CRC are not encrypted. 

3. Once the encryption is done the Packet handling state machine is enabled to transmit the data. 

## _5.5.5.2. Rx Processing_ 

1. The data received is stored in the FIFO, The address, CRC interrupts are generated as usual because these parameters were not encrypted. 

2. Once the complete packet has been received. The data is read from the FIFO, decrypted and written back to FIFO. The _PayloadReady_ interrupt is issued once the decrypted data is ready in the FIFO for reading via the SPI interface. 

The AES encryption/decryption cannot be used on the fly i.e. while transmitting and receiving data. Thus when AES encryption/decryption is enabled, the FIFO acts as a simple buffer. This buffer is filled before initiating any transmission. The data in the buffer is then encrypted before the transmission can begin. On the receive side the decryption is initiated only once the complete packet has been received in the buffer. 

The encryption/decryption process takes approximately 7.0 us per 16-byte block. Thus for a maximum of 4 blocks (i.e. 64 bytes) it can take up to 28 us for completing the cryptographic operations. 

The receive side sees the AES decryption time as a sequential delay before the _PayloadReady_ interrupt is available. 

The Tx side sees the AES encryption time as a sequential delay in the startup of the Tx chain, thus the startup time of the Tx will increase according to the length of data. 

In Fixed length mode the Message part of the payload that can be encrypted/decrypted can be 64 bytes long. If the address filtering is enabled, the length of the payload should be at max 65 bytes in this case. 

In Variable length mode the Max message size that can be encrypted/decrypted is also 64 bytes when address filtering is disabled, else it is 48 bytes. Thus, including length byte, the length of the payload is max 65 or 50 bytes (the latter when address filtering is enabled). 

If the address filtering is expected then _AddressFiltering_ must be enabled on the transmitter side as well to prevent address byte to be encrypted. 

Crc check being performed on encrypted data, _CrcOk_ interrupt will occur "decryption time" before _PayloadReady_ interrupt. 

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**RFM69HW** 

## **5.5.6. Handling Large Packets** 

When Payload length exceeds FIFO size (66 bytes) whether in fixed, variable or unlimited length packet format, in addition to _PacketSent_ in Tx and _PayloadReady_ or _CrcOk_ in Rx, the FIFO interrupts/flags can be used as described below: 

## For Tx: 

FIFO can be prefilled in Sleep/Standby but must be refilled "on-the-fly" during Tx with the rest of the payload. 

1) Prefill FIFO (in Sleep/Standby first or directly in Tx mode) until _FifoThreshold_ or _FifoFull_ is set 

2) In Tx, wait for _FifoThreshold_ or _FifoNotEmpty_ to be cleared (i.e. FIFO is nearly empty) 

3) Write bytes into the FIFO until _FifoThreshold_ or _FifoFull_ is set. 

4) Continue to step 2 until the entire message has been written to the FIFO ( _PacketSent_ will fire when the last bit of the packet has been sent). 

## For Rx: 

FIFO must be unfilled "on-the-fly" during Rx to prevent FIFO overrun. 

1) Start reading bytes from the FIFO when _FifoNotEmpty_ or _FifoThreshold_ becomes set. 

2) Suspend reading from the FIFO if _FifoNotEmpty_ clears before all bytes of the message have been read 

3) Continue to step 1 until _PayloadReady_ or _CrcOk_ fires 

4) Read all remaining bytes from the FIFO either in Rx or Sleep/Standby mode 

_Note AES encryption is not feasible on large packets, since all Payload bytes need to be in the FIFO at the same time to perform encryption_ 

## **5.5.7. Packet Filtering** 

RFM69HW's packet handler offers several mechanisms for packet filtering, ensuring that only useful packets are made available to the uC, reducing significantly system power consumption and software complexity. 

## _5.5.7.1. Sync Word Based_ 

Sync word filtering/recognition is used for identifying the start of the payload and also for network identification. As previously described, the Sync word recognition block is configured (size, error tolerance, value) in _RegSyncValue_ registers. This information is used, both for appending Sync word in Tx, and filtering packets in Rx. 

Every received packet which does not start with this locally configured Sync word is automatically discarded and no interrupt is generated. 

When the Sync word is detected, payload reception automatically starts and _SyncAddressMatch_ is asserted. 

_Note Sync Word values containing 0x00 byte(s) are forbidden_ 

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## _5.5.7.2. Address Based_ 

Address filtering can be enabled via the _AddressFiltering_ bits. It adds another level of filtering, above Sync word (i.e. Sync must match first), typically useful in a multi-node networks where a network ID is shared between all nodes (Sync word) and each node has its own ID (address). 

Two address based filtering options are available: 

- _AddressFiltering = 01_ : Received address field is compared with internal register _NodeAddress_ . If they match then the[packet is accepted and processed, otherwise it is discarded. ] 

_AddressFiltering = 10: Received address field is compared with internal registers NodeAddress and BroadcastAddress.If either is a match, the received packet is accepted and processed, otherwise it is discarded. This additional check with a constant is useful for implementing broadcast in a multi-node networks_ 

Please note that the received address byte, as part of the payload, is not stripped off the packet and is made available in the FIFO. In addition, _NodeAddress_ and _AddressFiltering_ only apply to Rx. On Tx side, if address filtering is expected, the address byte should simply be put into the FIFO like any other byte of the payload. 

As address filtering requires a Sync word match, both features share the same interrupt flag _SyncAddressMatch_ . 

## _5.5.7.3. Length Based_ 

In variable length Packet mode, _PayloadLength_ must be programmed with the maximum payload length permitted. If received length byte is smaller than this maximum then the packet is accepted and processed, otherwise it is discarded. 

Please note that the received length byte, as part of the payload, is not stripped off the packet and is made available in the FIFO. 

To disable this function the user should set the value of the _PayloadLength_ to 255. 

## _5.5.7.4. CRC Based_ 

The CRC check is enabled by setting bit _CrcOn_ in _RegPacketConfig1_ . It is used for checking the integrity of the message. 

_On Tx side a two byte CRC checksum is calculated on the payload part of the packet and appended to the end of the message_ 

_On Rx side the checksum is calculated on the received payload and compared with the two checksum bytes received.The result of the comparison is stored in bit CrcOk._ 

By default, if the CRC check fails then the FIFO is automatically cleared and no interrupt is generated. This filtering function can be disabled via _CrcAutoClearOff_ bit and in this case, even if CRC fails, the FIFO is not cleared and only _PayloadReady_ interrupt goes high. Please note that in both cases, the two CRC checksum bytes are stripped off by the packet handler and only the payload is made available in the FIFO. 

The CRC is based on the CCITT polynomial as shown below. This implementation also detects errors due to leading and trailing zeros. 

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**RFM69HW** 

**==> picture [545 x 182] intentionally omitted <==**

For such purposes, two techniques are made available in the packet handler: Manchester encoding and data whitening. 

## _Note Only one of the two methods should be enabled at a time._ 

## _5.5.8.1. Manchester Encoding_ 

Manchester encoding/decoding is enabled if _DcFree = 01_ and can only be used in Packet mode. 

The NRZ data is converted to Manchester code by coding '1' as "10" and '0' as "01". 

In this case, the maximum chip rate is the maximum bit rate given in the specifications section and the actual bit rate is half the chip rate. 

Manchester encoding and decoding is only applied to the payload and CRC checksum while preamble and Sync word are kept NRZ. However, the chip rate from preamble to CRC is the same and defined by _BitRate_ in _RegBitRate_ (Chip Rate = Bit Rate NRZ = 2 x Bit Rate Manchester). 

Manchester encoding/decoding is thus made transparent for the user, who still provides/retrieves NRZ data to/from the FIFO 

|~~**RF chips @ BR**~~|~~1/BR~~~~**...Sync**~~<br>~~**1**~~<br>~~**1**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~<br>~~**0**~~|~~1/BR~~~~**...Sync**~~<br>~~**1**~~<br>~~**1**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~<br>~~**0**~~|~~1/BR~~~~**...Sync**~~<br>~~**1**~~<br>~~**1**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~<br>~~**0**~~|~~1/BR~~~~**...Sync**~~<br>~~**1**~~<br>~~**1**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~<br>~~**0**~~|~~1/BR~~~~**...Sync**~~<br>~~**1**~~<br>~~**1**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~<br>~~**0**~~|~~1/BR~~~~**...Sync**~~<br>~~**1**~~<br>~~**1**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~<br>~~**0**~~|~~1/BR~~~~**...Sync**~~<br>~~**1**~~<br>~~**1**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~<br>~~**0**~~|~~1/BR~~~~**...Sync**~~<br>~~**1**~~<br>~~**1**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~<br>~~**0**~~|~~1/BR~~<br>~~**Payload...**~~<br>~~**1**~~<br>~~**0**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~|~~1/BR~~<br>~~**Payload...**~~<br>~~**1**~~<br>~~**0**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~|~~1/BR~~<br>~~**Payload...**~~<br>~~**1**~~<br>~~**0**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~|~~1/BR~~<br>~~**Payload...**~~<br>~~**1**~~<br>~~**0**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~|~~1/BR~~<br>~~**Payload...**~~<br>~~**1**~~<br>~~**0**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~|~~1/BR~~<br>~~**Payload...**~~<br>~~**1**~~<br>~~**0**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~|~~1/BR~~<br>~~**Payload...**~~<br>~~**1**~~<br>~~**0**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~|~~1/BR~~<br>~~**Payload...**~~<br>~~**1**~~<br>~~**0**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~|~~1/BR~~<br>~~**Payload...**~~<br>~~**1**~~<br>~~**0**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~|~~1/BR~~<br>~~**Payload...**~~<br>~~**1**~~<br>~~**0**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~|~~1/BR~~<br>~~**Payload...**~~<br>~~**1**~~<br>~~**0**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**1**~~<br>~~**0**~~<br>~~**1**~~<br>~~**0**~~|**t**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|~~**RF chips @ BR**~~|~~**...**~~|~~**1**~~|~~**1**~~|~~**1**~~|~~**0**~~|~~**1**~~|~~**0**~~|~~**0**~~|~~**1**~~|~~**0**~~|~~**0**~~|~~**1**~~|~~**0**~~|~~**1**~~|~~**1**~~|~~**0**~~|~~**1**~~|~~**0**~~|~~**...**~~||
|~~User/NRZ bits~~<br>Manchester OFF<br>~~So~~|...|1|1<br>~~tt~~|1<br>~~tt~~|0<br>~~tt~~|1<br>~~ye~~|0<br>~~ye~~|0<br>~~ye~~|1|0|0|1|0|1|1|0|1|0|...||
|User/NRZ bits<br>Manchester ON<br>~~So~~|...|1|1<br>~~tt~~|1<br>~~tt~~|0<br>~~tt~~|1<br>~~ye~~|0<br>~~ye~~|0<br>~~ye~~|1||0||0||1||1||...||



_Figure 37.  Manchester Encoding/Decoding_ 

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**RFM69HW** 

## _5.5.8.2. Data Whitening_ 

Another technique called whitening or scrambling is widely used for randomizing the user data before radio transmission. The data is whitened using a random sequence on the Tx side and de-whitened on the Rx side using the same sequence. Comparing to Manchester technique it has the advantage of keeping NRZ data rate i.e. actual bit rate is not halved. 

The whitening/de-whitening process is enabled if _DcFree = 10_ . A 9-bit LFSR is used to generate a random sequence. The payload and 2-byte CRC checksum is then XORed with this random sequence as shown below. The data is de-whitened on the receiver side by XORing with the same random sequence. 

Payload whitening/de-whitening is thus made transparent for the user, who still provides/retrieves NRZ data to/from the FIFO. 

**LFS R P o ly nom ia l =X[9 ] + X[5  ] + 1** 

**==> picture [443 x 80] intentionally omitted <==**

**----- Start of picture text -----**<br>
X [8 ] X [7 ] X [6 ] X  [5 ] X [4 ] X [3 ] X [2 ] X [1 ] X  [0]<br>Tra n s m it  d a ta  W h iten ed  da ta<br>**----- End of picture text -----**<br>


_Figure 38.  Data Whitening_ 

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**RFM69HW** 

## **6. Configuration and Status Registers** 

## **6.1.  General Description** 

_Table 23  Registers Summary_ 

|**Address**|**Register Name**<br>~~Ea~~|**Reset**<br>**(built-in)**|**Default**<br>**(recom**<br>**mended)**|**Description**<br>~~a~~|
|---|---|---|---|---|
|0x00<br>~~EE~~|RegFifo<br>~~Ea~~<br>~~EE~~|0x00||FIFO read/write access<br>~~a~~<br>~~ee~~|
|0x01<br>~~EE~~|RegOpMode<br>~~Ea~~<br>~~EE~~<br>~~Ld~~|0x04||Operating modes of the transceiver<br>~~a~~<br>~~ee~~<br>~~ee~~|
|0x02<br>~~EE~~<br>~~LT~~|RegDataModul<br>~~EE~~<br>~~Ld~~<br>~~LT~~|0x00||Data operation mode and Modulation settings<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|0x03<br>~~LT~~|RegBitrateMsb<br>~~Ld~~<br>~~LT~~<br>~~LT~~|0x1A<br>~~LT~~||Bit Rate setting, Most Significant Bits<br>~~ee~~<br>~~ee~~<br>~~a~~|
|0x04<br>~~LT~~|RegBitrateLsb<br>~~LT~~<br>~~LT~~<br>~~LT~~|0x0B<br>~~LT~~<br>~~LT~~||Bit Rate setting, Least Significant Bits<br>~~ee~~<br>~~a~~<br>~~ee~~|
|0x05<br>~~Lo~~|RegFdevMsb<br>~~LT~~<br>~~LT~~<br>~~Lo~~|0x00<br>~~LT~~<br>~~LT~~||Frequency Deviation setting, Most Significant Bits<br>~~a~~<br>~~ee~~<br>~~ee~~|
|0x06<br>~~Lo~~<br>~~_—_—_~~|RegFdevLsb<br>~~LT~~<br>~~Lo~~<br>~~_—_—_~~|0x52<br>~~LT~~||Frequency Deviation setting, Least Significant Bits<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|0x07<br>~~Lo~~<br>~~_—_—_~~|RegFrfMsb<br>~~Lo~~<br>~~_—_—_~~|0xE4||RF Carrier Frequency, Most Significant Bits<br>~~ee~~<br>~~ee~~|
|0x08<br>~~_—_—_~~|RegFrfMid<br>~~_—_—_~~<br>~~a~~<br>~~Ea~~|0xC0||RF Carrier Frequency, Intermediate Bits<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|0x09<br>~~EE~~|RegFrfLsb<br>~~Ea~~<br>~~EE~~|0x00||RF Carrier Frequency, Least Significant Bits<br>~~ee~~<br>~~ee~~|
|0x0A<br>~~EE~~|RegOsc1<br>~~Ea~~<br>~~EE~~<br>~~Ea~~|0x41||RC Oscillators Settings<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|0x0B<br>~~EE~~<br>~~EE~~|RegAfcCtrl<br>~~EE~~<br>~~Ea~~<br>~~EE~~|0x00||AFC control in low modulation index situations<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|0x0C<br>~~EE~~<br>~~LT~~|Reserved0C<br>~~Ea~~<br>~~EE~~<br>~~LT~~|0x02||-<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|0x0D<br>~~EE~~<br>~~LT~~|RegListen1<br>~~EE~~<br>~~LT~~<br>~~LT~~|0x92<br>~~LT~~||Listen Mode settings<br>~~ee~~<br>~~ee~~<br>~~a~~|
|0x0E<br>~~LT~~|RegListen2<br>~~LT~~<br>~~LT~~<br>~~LT~~|0xF5<br>~~LT~~<br>~~LT~~||Listen Mode Idle duration<br>~~ee~~<br>~~a~~<br>~~a~~|
|0x0F<br>~~Lo~~|RegListen3<br>~~LT~~<br>~~LT~~<br>~~Lo~~|0x20<br>~~LT~~<br>~~LT~~||Listen Mode Rx duration<br>~~a~~<br>~~a~~<br>~~ee~~|
|0x10<br>~~Lo~~<br>~~EE~~|RegVersion<br>~~LT~~<br>~~Lo~~<br>~~EE~~|0x24<br>~~LT~~||~~a~~<br>~~ee~~<br>~~ee~~|
|0x11<br>~~Lo~~<br>~~EE~~|RegPaLevel<br>~~Lo~~<br>~~EE~~|0x9F||PA selection and Output Power control<br>~~ee~~<br>~~ee~~|
|0x12<br>~~EE~~<br>~~EE~~|RegPaRamp<br>~~EE~~<br>~~a~~<br>~~EE~~|0x09||Control of the PA ramp time in FSK mode<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|0x13<br>~~EE~~<br>~~——~~|RegOcp<br>~~EE~~<br>~~——~~|0x1A||Over Current Protection control<br>~~ee~~<br>~~a~~|
|0x14<br>~~EE~~<br>~~——~~<br>~~——~~|Reserved14<br>~~EE~~<br>~~——~~<br>~~——~~|0x40||-<br>~~ee~~<br>~~a~~<br>~~a~~|
|0x15<br>~~——~~<br>~~——~~<br>~~——~~|Reserved15<br>~~——~~<br>~~——~~<br>~~——~~|0xB0||-<br>~~a~~<br>~~a~~<br>~~a~~|
|0x16<br>~~——~~<br>~~——~~<br>~~EE~~|Reserved16<br>~~——~~<br>~~——~~<br>~~EE~~|0x7B||-<br>~~a~~<br>~~a~~<br>~~ee~~|
|0x17<br>~~——~~<br>~~EE~~|Reserved17<br>~~——~~<br>~~EE~~|0x9B||-<br>~~a~~<br>~~ee~~|
|0x18<br>~~EE~~|RegLna<br>~~EE~~<br>~~eee~~|0x08<br>~~eee~~|0x88<br>~~eee~~|LNA settings<br>~~ee~~<br>~~eee~~|
|0x19|RegRxBw<br>~~ee~~|0x86<br>~~ee~~|0x55<br>~~ee~~|Channel Filter BW Control<br>~~ee~~|



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|**Address**|**Register Name**|**Reset**<br>**(built-in)**|**Default**<br>**(recom**<br>**mended)**|**Description**|
|---|---|---|---|---|
|0x1A|RegAfcBw<br>~~CO~~<br>~~Ea~~|0x8A<br>~~CO~~|0x8B<br>~~CO~~|Channel Filter BW control during the AFC routine<br>~~CO~~<br>~~ee~~|
|0x1B<br>~~EE~~|RegOokPeak<br>~~CO~~<br>~~Ea~~<br>~~EE~~|0x40<br>~~CO~~||OOK demodulator selection and control in peak mode<br>~~CO~~<br>~~ee~~<br>~~ee~~|
|0x1C<br>~~EE~~<br>~~EE~~|RegOokAvg<br>~~Ea~~<br>~~EE~~<br>~~EE~~|0x80||Average threshold control of the OOK demodulator<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|0x1D<br>~~EE~~<br>~~EE~~|RegOokFix<br>~~EE~~<br>~~EE~~<br>~~Ld~~|0x06||Fixed threshold control of the OOK demodulator<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|0x1E<br>~~EE~~<br>~~LT~~|RegAfcFei<br>~~EE~~<br>~~Ld~~<br>~~LT~~|0x10||AFC and FEI control and status<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|0x1F<br>~~LT~~|RegAfcMsb<br>~~Ld~~<br>~~LT~~<br>~~LT~~|0x00<br>~~LT~~||MSB of the frequency correction of the AFC<br>~~ee~~<br>~~ee~~<br>~~a~~|
|0x20<br>~~LT~~|RegAfcLsb<br>~~LT~~<br>~~LT~~<br>~~LT~~|0x00<br>~~LT~~<br>~~LT~~||LSB of the frequency correction of the AFC<br>~~ee~~<br>~~a~~<br>~~ee~~|
|0x21<br>~~Lo~~|RegFeiMsb<br>~~LT~~<br>~~LT~~<br>~~Lo~~|0x00<br>~~LT~~<br>~~LT~~||MSB of the calculated frequency error<br>~~a~~<br>~~ee~~<br>~~ee~~|
|0x22<br>~~Lo~~<br>~~_—_—_~~|RegFeiLsb<br>~~LT~~<br>~~Lo~~<br>~~_—_—_~~|0x00<br>~~LT~~||LSB of the calculated frequency error<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|0x23<br>~~Lo~~<br>~~_—_—_~~|RegRssiConfig<br>~~Lo~~<br>~~_—_—_~~|0x02||RSSI-related settings<br>~~ee~~<br>~~ee~~|
|0x24<br>~~_—_—_~~|RegRssiValue<br>~~_—_—_~~<br>~~a~~<br>~~Ea~~|0xFF||RSSI value in dBm<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|0x25|RegDioMapping1<br>~~Ea~~|0x00||Mapping of pins DIO0 to DIO3<br>~~ee~~|
|0x26|RegDioMapping2<br>~~Ea~~<br>~~eee~~<br>~~Ea~~|0x05<br>~~eee~~|0x07<br>~~eee~~|Mapping of pins DIO4 and DIO5, ClkOut frequency<br>~~ee~~<br>~~eee~~<br>~~ee~~|
|0x27<br>~~EE~~|RegIrqFlags1<br>~~Ea~~<br>~~EE~~|0x80||Status register: PLL Lock state, Timeout, RSSI > Threshold...<br>~~ee~~<br>~~ee~~|
|0x28<br>~~EE~~|RegIrqFlags2<br>~~Ea~~<br>~~EE~~|0x00||Status register: FIFO handling flags...<br>~~ee~~<br>~~ee~~|
|0x29<br>~~EE~~<br>~~EE~~|RegRssiThresh<br>~~EE~~<br>~~ee~~<br>~~EE~~|0xFF<br>~~ee~~|0xE4<br>~~ee~~|RSSI Threshold control<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|0x2A<br>~~EE~~|RegRxTimeout1<br>~~EE~~<br>~~Ea~~|0x00||Timeout duration between Rx request and RSSI detection<br>~~ee~~<br>~~ee~~|
|0x2B<br>~~EE~~<br>~~EE~~|RegRxTimeout2<br>~~EE~~<br>~~Ea~~<br>~~EE~~|0x00||Timeout duration between RSSI detection and_PayloadReady_<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|0x2C<br>~~EE~~<br>~~LT~~|RegPreambleMsb<br>~~Ea~~<br>~~EE~~<br>~~LT~~|0x00||Preamble length, MSB<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|0x2D<br>~~EE~~<br>~~LT~~|RegPreambleLsb<br>~~EE~~<br>~~LT~~<br>~~LT~~|0x03<br>~~LT~~||Preamble length, LSB<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|0x2E<br>~~LT~~|RegSyncConfig<br>~~LT~~<br>~~LT~~|0x98<br>~~LT~~||Sync Word Recognition control<br>~~ee~~<br>~~ee~~|
|0x2F-0x36|RegSyncValue1-8<br>~~LT~~<br>~~eee~~<br>~~LT~~|0x00<br>~~LT~~<br>~~eee~~<br>~~LT~~|0x01<br>~~eee~~|Sync Word bytes, 1 through 8<br>~~ee~~<br>~~eee~~<br>~~a~~|
|0x37|RegPacketConfig1<br>~~LT~~<br>~~LT~~|0x10<br>~~LT~~<br>~~LT~~||Packet mode settings<br>~~a~~<br>~~ee~~|
|0x38<br>~~Lo~~|RegPayloadLength<br>~~LT~~<br>~~LT~~<br>~~Lo~~|0x40<br>~~LT~~<br>~~LT~~||Payload length setting<br>~~a~~<br>~~ee~~<br>~~ee~~|
|0x39<br>~~Lo~~<br>~~EE~~|RegNodeAdrs<br>~~LT~~<br>~~Lo~~<br>~~EE~~|0x00<br>~~LT~~||Node address<br>~~ee~~<br>~~ee~~<br>~~ee~~|
|0x3A<br>~~Lo~~<br>~~EE~~|RegBroadcastAdrs<br>~~Lo~~<br>~~EE~~|0x00||Broadcast address<br>~~ee~~<br>~~ee~~|
|0x3B<br>~~EE~~|RegAutoModes<br>~~EE~~<br>~~a~~|0x00||Auto modes settings<br>~~ee~~<br>~~ee~~|
|0x3C<br>~~SS~~|RegFifoThresh<br>~~i~~|0x0F|0x8F|Fifo threshold, Tx start condition|
|0x3D<br>~~SS~~|RegPacketConfig2<br>~~i~~<br>~~#3~~|0x02<br>~~#3~~||Packet mode settings|



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**RFM69HW** 

|**Address**|**Register Name**|**Reset**<br>**(built-in)**|**Default**<br>**(recom**<br>**mended)**|**Description**|
|---|---|---|---|---|
|0x3E-0x4D|RegAesKey1-16|0x00||16 bytes of the cypher key|
|0x4E|RegTemp1|0x01||Temperature Sensor control|
|0x4F|RegTemp2|0x00||Temperature readout|
|0x58|RegTestLna|0x1B||Sensitivity boost|
|0x5A|RegTestPa1|0x55||High Power PA settings|
|0x5C|RegTestPa2|0x70||High Power PA settings|
|0x6F|RegTestDagc|0x00|0x30|Fading Margin Improvement|
|0x71|RegTestAfc|0x00||AFC offset for low modulation index AFC|
|0x50 +|RegTest|-||Internal test registers|



- _Note - Reset values are automatically refreshed in the chip at Power On Reset_ 

   - _Default values are  recommended register values, optimizing the device operation_ 

   - _Registers for which the Default value differs from the Reset value are denoted by a * in the tables of section 6_ 

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**RFM69HW** 

## **6.2.  Common Configuration Registers** 

_Table 24 Common Configuration Registers_ 

|**Name**<br>**(Address)**|**Bits**|**Variable Name**|**Mode**|**Default**<br>**Value**|**Description**|
|---|---|---|---|---|---|
|RegFifo<br>(0x00)|7-0|Fifo|rw|0x00|FIFO data input/output|
|RegOpMode<br>(0x01)|7|SequencerOff|rw|0|Controls the automatic Sequencer (see section 4.2 ):<br>0→Operating mode as selected with Mode bits in<br>RegOpMode is automatically reached with the Sequencer<br>1→Mode is forced by the user|
||6|ListenOn|rw|0|Enables Listen mode, should be enabled whilst in<br>Standby mode:<br>0→Off (see section 4.3)<br>1→On|
||5|ListenAbort|w|0|Aborts Listen mode when set together with ListenOn=0<br>See section 4.3.4 for details<br>Always reads 0.|
||4-2|Mode|rw|001|Transceiver’s operating modes:<br>000→Sleep mode (SLEEP)<br>001→Standby mode (STDBY)<br>010→Frequency Synthesizer mode (FS)<br>011→Transmitter mode (TX)<br>100→Receiver mode (RX)<br>others→reserved;   Reads the value corresponding to<br>the current module mode|
||1-0|-|r|00|unused|
|RegDataModul<br>(0x02)|7|-|r|0|unused|
||6-5|DataMode|rw|00|Data processing mode:<br>00→Packet mode<br>01→reserved<br>10→Continuous mode with bit synchronizer<br>11→Continuous mode without bit synchronizer|
||4-3|ModulationType|rw|00|Modulation scheme:<br>00→FSK<br>01→OOK<br>10 - 11→reserved|
||2|-|r|0|unused|
||1-0|ModulationShaping|rw|00|Data shaping:<br>in FSK:<br>00→no shaping<br>01→Gaussian filter, BT = 1.0<br>10→Gaussian filter, BT = 0.5<br>11→Gaussian filter, BT = 0.3<br>in OOK:<br>00→no shaping<br>01→filtering with fcutoff= BR<br>10→filtering with fcutoff= 2*BR<br>11→reserved|
|RegBitrateMsb<br>(0x03)|7-0|BitRate(15:8)|rw|0x1a|MSB of Bit Rate (Chip Rate when Manchester encoding is<br>enabled)|



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|RegBitrateLsb<br>(0x04)|7-0|BitRate(7:0)|rw|0x0b|LSB of Bit Rate (Chip Rate if Manchester encoding is<br>enabled)<br>_BitRate_=  --------_F_----_X_----_O_-----_S_---_C_----------<br>_BitRate_(15,0)<br>Default value: 4.8 kb/s|
|---|---|---|---|---|---|
|RegFdevMsb<br>(0x05)|7-6|-|r|00|unused|
||5-0|Fdev(13:8)|rw|000000|MSB of the frequency deviation|
|RegFdevLsb<br>(0x06)|7-0|Fdev(7:0)|rw|0x52|LSB of the frequency deviation<br>_Fdev_=_Fstep_⋅ _Fdev_(15,0)<br>Default value: 5 kHz|
|RegFrfMsb<br>(0x07)|7-0|Frf(23:16)|rw|0xe4|MSB of the RF carrier frequency|
|RegFrfMid<br>(0x08)|7-0|Frf(15:8)|rw|0xc0|Middle byte of the RF carrier frequency|
|RegFrfLsb<br>(0x09)|7-0|Frf(7:0)|rw|0x00|LSB of the RF carrier frequency<br>_Frf_=_Fstep_⋅_Frf 23;0 _<br>Default value:  Frf = 915 MHz (32 MHz XO)|
|RegOsc1<br>(0x0A)|7|RcCalStart|w|0|Triggers the calibration of the RC oscillator when set.<br>Always reads 0. RC calibration must be triggered in<br>Standby mode.|
||6|RcCalDone|r|1|0→RC calibration in progress<br>1→RC calibration is over|
||5-0|-|r|000001|unused|
|RegAfcCtrl<br>(0x0B)|7-6|-|r|00|unused|
||5|AfcLowBetaOn|rw|0|Improved AFC routine for signals with modulation index<br>lower than 2. Refer to section 3.4.16 for details<br>0→Standard AFC routine<br>1→Improved AFC routine|
||4-0|-|r|00000|unused|
|Reserved0C<br>(0x0C)|7-0|-|r|0x02|unused|



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|RegListen1<br>(0x0D)|7-6|ListenResolIdle|rw|10|10|Resolution of Listen mode Idle time (calibrated RC osc):<br>00→reserved<br>01→64 us<br>10→4.1 ms<br>11→262 ms|Action taken after acceptance of a packet in Listen mode:<br>chip stays in Rx mode. Listen mode stops and must|
|---|---|---|---|---|---|---|---|
||5-4|ListenResolRx|rw|01||Resolution of Listen mode Rx time (calibrated RC osc):<br>00→reserved<br>01→64 us<br>10→4.1 ms<br>11→262 ms||
||3|ListenCriteria|rw|0||Criteria for packet acceptance in Listen mode:<br>0→signal strength is above_RssiThreshold_<br>1→signal strength is above_RssiThreshold_and<br>_SyncAddress_matched||
||2-1|ListenEnd|rw|01||Action taken after acceptance of a packet in Listen mode:<br>00→chip stays in Rx mode. Listen mode stops and must<br>be disabled (see section 4.3).<br>01→chip stays in Rx mode until_PayloadReady_or<br>_Timeout_interrupt occurs. It then goes to the mode defined<br>by_Mode_. Listen mode stops and must be disabled (see<br>section 4.3).<br>10→chip stays in Rx mode until_PayloadReady_or<br>_Timeout_interrupt occurs. Listen mode then resumes in<br>Idle state. FIFO content is lost at next Rx wakeup.<br>11→Reserved||
||0|-|r|0||unused||
|RegListen2<br>(0x0E)|7-0|ListenCoefIdle<br>~~ListenCoefRx~~|rw|0xf5||Duration of the Idle phase in Listen mode.<br>_tListenIdle_= _ListenCoefIdle _∗ _Listen_Re_solIdle_<br>~~Duration of the Rx phase in Listen mode (startup time~~||
|RegListen3<br>(0x0F)|~~7-0~~|~~ListenCoefRx~~|~~rw~~|~~0x20~~||~~Duration of the Rx phase in Listen mode (startup time~~<br>included, see section 4.2.3)<br>_tListenRx_= _ListenCoefRx _∗ _Listen_Re_solRx_||
|RegVersion<br>(0x10)|7-0|Version|r|0x24||Version code of the chip. Bits 7-4 give the full revision<br>number; bits 3-0 give the metal mask revision number.||
|||||||||



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**RFM69HW** 

## **6.3.  Transmitter Registers** 

## _Table 25  Transmitter Registers_ 

|**Name**<br>**(Address)**|**Bits**|**Variable Name**|**Mode**|**Default**<br>**Value**|**Description**|
|---|---|---|---|---|---|
|RegPaLevel<br>(0x11)|7|Pa0On *|rw|1|Enables PA0, connected to RFIO and LNA|
||6|Pa1On *|rw|0|Enables PA1, on PA_BOOST pin|
||5|Pa2On *|rw|0|Enables PA2, on PA_BOOST pin|
||4-0|OutputPower|rw|11111|Output power setting, with 1 dB steps<br>Pout = -18 +_OutputPower_[dBm] , with PA0<br>Pout = -18 +_OutputPower_[dBm] , with PA1**<br>Pout = -14+_OutputPower_[dBm] , with PA1 and PA2**<br>Pout = -11 +_OutputPower_[dBm] , with PA1 and PA2, and<br>high Power PA settings (refer to section 3.3.7)**|
|RegPaRamp<br>(0x12)|7-4|-|r|0000|unused|
||3-0|PaRamp|rw|1001|Rise/Fall time of ramp up/down in FSK<br>0000→3.4 ms<br>0001→2 ms<br>0010→1 ms<br>0011→500 us<br>0100→250 us<br>0101→125 us<br>0110→100 us<br>0111→62 us<br>1000→50 us<br>1001→40 us<br>1010→31 us<br>1011→25 us<br>1100→20 us<br>1101→15 us<br>1110→12 us<br>1111→10 us|
|RegOcp<br>(0x13)|7-5|-|r|000|unused|
||4|OcpOn|rw|1|Enables overload current protection (OCP) for the PA:<br>0→OCP disabled<br>1→OCP enabled|
||3-0|OcpTrim|rw|1010|Trimming of OCP current:<br>_Imax_=  45 + 5⋅ _OcpTrim mA _<br>95 mA OCP by default|



_Note *Power Amplifier truth table is available in Table 10_ 

_** Only the16 upper values of OutputPower are accessible_ 

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**RFM69HW** 

## **6.4.  Receiver Registers** 

## _Table 26  Receiver Registers_ 

|**Name**<br>**(Address)**|**Bits**|**Variable Name**|**Mode**|**Default**<br>**Value**|**Description**|
|---|---|---|---|---|---|
|Reserved14<br>(0x14)|7-0|-|r|0x40|unused|
|Reserved15<br>(0x15)|7-0|-|r|0xB0|unused|
|Reserved16<br>(0x16)|7-0|-|r|0x7B|unused|
|Reserved17<br>(0x17)|7-0|-|r|0x9B|unused|
|RegLna<br>(0x18)|7|LnaZin<br>~~ee~~|rw<br>~~ee~~|1<br>*<br>~~ee~~|LNA’s input impedance<br>0→50 ohms<br>1→200 ohms<br>~~ee~~|
||6|-|r|0|unused|
||5-3|LnaCurrentGain|r|001|Current LNA gain, set either manually, or by the AGC|
||2-0|LnaGainSelect|rw|000|LNA gain setting:<br>000→gain set by the internal AGC loop<br>001→G1 = highest gain<br>010→G2 = highest gain – 6 dB<br>011→G3 = highest gain – 12 dB<br>100→G4 = highest gain – 24 dB<br>101→G5 = highest gain – 36 dB<br>110→G6 = highest gain – 48 dB<br>111→reserved|
|RegRxBw<br>(0x19)|7-5|DccFreq<br>~~i~~|rw<br>~~i~~|010<br>*<br>~~i~~|Cut-off frequency of the DC offset canceller (DCC):<br>-----<br>-----------------<br>~4% of the RxBw by default<br>~~i~~|
||4-3|RxBwMant<br>~~ee~~|rw<br>~~ee~~|10<br>*<br>~~ee~~|Channel filter bandwidth control:<br>00→RxBwMant = 16<br>10→RxBwMant = 24<br>01→RxBwMant = 20<br>11→reserved<br>~~ee~~|
||2-0|RxBwExp|rw|101<br>*|Channel filter bandwidth control:<br>FSK Mode:<br>_RxBw_=------------------------_F_----_X_----_O_----_S_----_C_-------------------------<br>_RxBwMant_∗2_RxBwExp_+ 2<br>OOK Mode:<br>_RxBw_=------------------------_F_----_X_----_O_----_S_----_C_-------------------------<br>_RxBwMant_∗ 2_RxBwExp_+ 3<br>See Table 14 for tabulated values|
|RegAfcBw<br>(0x1A)|7-5|DccFreqAfc|rw|100|DccFreq parameter used during the AFC|
||4-3|RxBwMantAfc<br>~~po~~|rw<br>~~po~~|01<br>~~po~~|RxBwMant parameter used during the AFC<br>~~po~~|
||2-0|RxBwExpAfc<br>~~a~~|rw|011 *|RxBwExp parameter used during the AFC|



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|RegOokPeak<br>(0x1B)|7-6|OokThreshType|rw|01|Selects type of threshold in the OOK data slicer:<br>00→fixed<br>10→average<br>01→peak<br>11→reserved|
|---|---|---|---|---|---|
||5-3|OokPeakTheshStep|rw|000|Size of each decrement of the RSSI threshold in the OOK<br>demodulator:<br>000→0.5 dB<br>001→1.0 dB<br>010→1.5 dB<br>011→2.0 dB<br>100→3.0 dB<br>101→4.0 dB<br>110→5.0 dB<br>111→6.0 dB|
||2-0|OokPeakThreshDec|rw|000|Period of decrement of the RSSI threshold in the OOK<br>demodulator:<br>000→once per chip<br>001→once every 2 chips<br>010→once every 4 chips<br>011→once every 8 chips<br>100→twice in each chip<br>101→4 times in each chip<br>110→8 times in each chip   111→16 times in each chip|
|RegOokAvg<br>(0x1C)|7-6|OokAverageThreshFilt|rw|10|Filter coefficients in average mode of the OOK<br>demodulator:<br>00→fC≈ chip rate / 32.π<br>01→fC≈ chip rate / 8.π<br>10→fC≈ chip rate / 4.π<br>11→fC≈ chip rate / 2.π|
||5-0|-|r|000000|unused|
|RegOokFix<br>(0x1D)|7-0|OokFixedThresh<br>~~Se~~|rw<br>~~Se~~|0110<br>(6dB)<br>~~Se~~|Fixed threshold value (in dB) in the OOK demodulator.<br>Used when_OokThresType_= 00<br>~~Se~~|
|RegAfcFei<br>(0x1E)|7|-|r|0|unused|
||6|FeiDone<br>~~a~~|r|0|0→FEI is on-going<br>1→FEI finished|
||5|FeiStart<br>~~a~~|w|0|Triggers a FEI measurement when set. Always reads 0.|
||4|AfcDone<br>~~a~~|r|1|0→AFC is on-going<br>1→AFC has finished|
||3|AfcAutoclearOn<br>~~a ~~|rw<br> ~~ee~~|0<br>~~ee~~|Only valid if_AfcAutoOn_is set<br>0→AFC register is not cleared before a new AFC phase<br>1→AFC register is cleared before a new AFC phase<br>~~ee~~|
||2|AfcAutoOn<br>~~a~~|rw|0|0→AFC is performed each time_AfcStart_is set<br>1→AFC is performed each time Rx mode is entered|
||1|AfcClear<br>~~——————~~|w<br>~~——————~~|0<br>~~——————~~|Clears the AfcValue if set in Rx mode. Always reads 0<br>~~——————~~|
||0|AfcStart<br>~~——————~~|w<br>~~——————~~|0<br>~~——————~~|Triggers an AFC when set. Always reads 0.<br>~~——————~~|
|RegAfcMsb<br>(0x1F)|7-0|AfcValue(15:8)<br>~~a~~<br>~~a~~|r<br>~~a~~<br>~~Oa~~|0x00<br>~~a~~|MSB of the AfcValue, 2’s complement format<br>~~a~~|
|RegAfcLsb<br>(0x20)|7-0|AfcValue(7:0)<br>~~a~~<br>~~a~~|r<br>~~a~~<br>~~Oa~~|0x00<br>~~a~~|LSB of the AfcValue, 2’s complement format<br>_Frequency correction =_AfcValue x Fstep<br>~~a~~|
|RegFeiMsb<br>(0x21)|7-0|FeiValue(15:8)<br>~~a~~|r<br>~~Oa~~|-|MSB of the measured frequency offset, 2’s complement|
|RegFeiLsb<br>(0x22)|7-0|FeiValue(7:0)<br>~~a~~|r|-|LSB of the measured frequency offset, 2’s complement<br>_Frequency error =_FeiValue x Fstep|
|RegRssiConfig<br>(0x23)|7-2|-|r|000000|unused|
||1<br>~~a~~|RssiDone<br>~~a~~<br>~~a~~|r|1|0→RSSI is on-going<br>1→RSSI sampling is finished, result available|
||0<br>~~a~~|RssiStart<br>~~a~~|w|0|Trigger a RSSI measurement when set. Always reads 0.|
|RegRssiValue<br>(0x24)|7-0<br>~~a~~|RssiValue<br>~~a~~<br>~~a~~|r|0xFF|Absolute value of the RSSI in dBm, 0.5dB steps.<br>RSSI = -_RssiValue/2 [dBm]_|



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**RFM69HW** 

## **6.5.  IRQ and Pin Mapping Registers** 

_Table 27  IRQ and Pin Mapping Registers_ 

|**Name**<br>**(Address)**|**Bits**|**Variable Name**|**Mode**|**Default**<br>**Value**|**Description**|
|---|---|---|---|---|---|
|RegDioMapping1<br>(0x25)|7-6<br>~~Os~~<br>~~yy~~|Dio0Mapping<br>~~ee~~<br>~~yy~~|rw<br>~~ee~~<br>~~ee~~|00<br>~~ee~~<br>~~ee~~|Mapping of pins DIO0 to DIO5<br>See Table 21 for mapping in Continuous mode<br>See Table 22 for mapping in Packet mode|
||5-4<br>~~Os~~<br>~~yy~~<br>~~Os~~|Dio1Mapping<br>~~ee~~<br>~~yy~~<br>~~t—C—‘“CSSCsSsYSC~~<br>|rw<br>~~ee~~<br>~~ee~~<br>~~t—C—‘“CSSCsSsYSC~~<br>~~ee~~<br>|00<br>~~ee~~<br>~~ee~~<br>~~t—C—‘“CSSCsSsYSC~~<br>~~**ee**~~<br>||
||3-2<br>~~yy~~<br>~~se~~<br>~~Os~~|Dio2Mapping<br>~~yy~~<br>~~se~~<br>|rw<br>~~ee ~~<br>~~se~~<br>~~ee~~<br>|00<br> ~~ee~~<br>~~se~~<br>~~**ee**~~<br>||
||1-0<br>~~Os~~|Dio3Mapping<br>~~ee~~|rw<br>~~ee~~<br>~~ee~~|00<br>~~**ee**~~<br>~~ee~~||
|RegDioMapping2<br>(0x26)|7-6<br>~~Os~~|Dio4Mapping<br>|rw<br>~~ee ~~<br><br>~~ee~~|00<br> ~~**ee**~~<br>||
||5-4<br>~~i~~|Dio5Mapping<br>~~rr~~|rw<br>~~rr~~<br>~~ee~~|00<br>~~rr~~||
||3|-|r<br>~~ee~~|0|unused|
||2-0|ClkOut|rw|111<br>*|Selects CLKOUT frequency:<br>000→FXOSC<br>001→FXOSC / 2<br>010→FXOSC / 4<br>011→FXOSC / 8<br>100→FXOSC / 16<br>101→FXOSC / 32<br>110→RC (automatically enabled)<br>111→OFF|
|RegIrqFlags1<br>(0x27)|7|ModeReady|r|1|Set when the operation mode requested in_Mode_, is ready<br>- Sleep: Entering Sleep mode<br>- Standby: XO is running<br>- FS: PLL is locked<br>- Rx: RSSI sampling starts<br>- Tx: PA ramp-up completed<br>Cleared when changing operating mode.|
||6|RxReady<br>~~a ~~|r<br> ~~ee~~|0<br>~~ee~~|Set in Rx mode, after RSSI, AGC and AFC.<br>Cleared when leaving Rx.<br>~~ee~~|
||5|TxReady<br>~~a ~~|r<br> ~~ee~~|0<br>~~ee~~|Set in Tx mode, after PA ramp-up.<br>Cleared when leaving Tx.<br>~~ee~~|
||4|PllLock<br>~~a ~~|r<br> ~~ee~~|0<br>~~ee~~|Set (in FS, Rx or Tx) when the PLL is locked.<br>Cleared when it is not.<br>~~ee~~|
||3|Rssi<br>~~a ~~|rwc<br> ~~ee~~|0<br>~~ee~~|Set in Rx when the_RssiValue_exceeds_RssiThreshold._<br>Cleared when leaving Rx.<br>~~ee~~|
||2|Timeout|r|0|Set when a timeout occurs (see_TimeoutRxStart_and<br>_TimeoutRssiThresh_)<br>Cleared when leaving Rx or FIFO is emptied.|
||1|AutoMode|r|0|Set when entering Intermediate mode.<br>Cleared when exiting Intermediate mode.<br>Please note that in Sleep mode a small delay can be<br>observed between_AutoMode_interrupt and the<br>corresponding enter/exit condition.|
||0|SyncAddressMatch|r/rwc|0|Set when Sync and Address (if enabled) are detected.<br>Cleared when leaving Rx or FIFO is emptied.<br>This bit is read only in Packet mode, rwc in Continuous<br>mode|



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|RegIrqFlags2<br>(0x28)|7|FifoFull|r|0|Set when FIFO is full (i.e. contains 66 bytes), else<br>cleared.|
|---|---|---|---|---|---|
||6|FifoNotEmpty|r|0|Set when FIFO contains at least one byte, else cleared|
||5|FifoLevel|r|0|Set when the number of bytes in the FIFO strictly exceeds<br>_FifoThreshold_, else cleared.|
||4|FifoOverrun|rwc|0|Set when FIFO overrun occurs. (except in Sleep mode)<br>Flag(s) and FIFO are cleared when this bit is set. The<br>FIFO then becomes immediately available for the next<br>transmission / reception.|
||3|PacketSent|r|0|Set in Tx when the complete packet has been sent.<br>Cleared when exiting Tx.|
||2|PayloadReady|r|0|Set in Rx when the payload is ready (i.e. last byte<br>received and CRC, if enabled and_CrcAutoClearOff_is<br>cleared_,_is Ok). Cleared when FIFO is empty.|
||1|CrcOk|r|0|Set in Rx when the CRC of the payload is Ok. Cleared<br>when FIFO is empty.|
||0|-|r|0|unused|
|RegRssiThresh<br>(0x29)|7-0|RssiThreshold|rw|0xE4<br>*|RSSI trigger level for_Rssi_interrupt :<br>-_RssiThreshold_/ 2 [dBm]|
|RegRxTimeout1<br>(0x2A)|7-0|TimeoutRxStart|rw|0x00|_Timeout_interrupt is generated_TimeoutRxStart_*16*Tbit<br>after switching to Rx mode if_Rssi_interrupt doesn’t occur<br>(i.e._RssiValue > RssiThreshold)_<br>0x00:_TimeoutRxStart_is disabled|
|RegRxTimeout2<br>(0x2B)|7-0|TimeoutRssiThresh|rw|0x00|_Timeout_interrupt is generated_TimeoutRssiThresh_*16*Tbit<br>after_Rssi_interrupt if_PayloadReady_interrupt doesn’t<br>occur.<br>0x00:_TimeoutRssiThresh_is disabled|



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**RFM69HW** 

## **6.6.  Packet Engine Registers** 

_Table 28  Packet Engine Registers_ 

|**Name**<br>**(Address)**|**Bits**|**Variable Name**|**Mode**|**Default**<br>**Value**|**Description**|
|---|---|---|---|---|---|
|RegPreambleMsb<br>(0x2c)|7-0|PreambleSize(15:8)<br>~~a~~<br>~~ee~~|rw<br>~~a~~|0x00<br>~~a~~|Size of the preamble to be sent (from_TxStartCondition_<br>fulfilled). (MSB byte)<br>~~a~~|
|RegPreambleLsb<br>(0x2d)|7-0|PreambleSize(7:0)<br>~~a~~<br>~~ee~~|rw<br>~~a~~|0x03<br>~~a~~|Size of the preamble to be sent (from_TxStartCondition_<br>fulfilled). (LSB byte)<br>~~a~~|
|RegSyncConfig<br>(0x2e)|7|SyncOn<br>~~ee~~<br>~~re~~|rw<br>~~re~~|1<br>~~re~~|Enables the Sync word generation and detection:<br>0→Off<br>1→On<br>~~re~~|
||6|FifoFillCondition<br>~~ee~~|rw<br>~~ee~~|0<br>~~ee~~|FIFO filling condition:<br>0→if_SyncAddress_interrupt occurs<br>1→as long as_FifoFillCondition_is set<br>~~ee~~|
||5-3|SyncSize<br>~~a~~|rw<br>a|011|Size of the Sync word:<br>(_SyncSize_+ 1) bytes|
||2-0|SyncTol<br>~~Oe~~|rw<br>~~Oe~~|000<br>~~Oe~~|Number of tolerated bit errors in Sync word<br>~~Oe~~|
|RegSyncValue1<br>(0x2f)|7-0|SyncValue(63:56)<br>~~ee~~|rw<br>~~ee~~|0x01<br>*<br>~~ee~~|1stbyte of Sync word. (MSB byte)<br>Used if_SyncOn_is set.<br>~~ee~~|
|RegSyncValue2<br>(0x30)|7-0|SyncValue(55:48)<br>~~ee~~<br>~~ee~~|rw<br>~~ee~~<br>~~ee~~|0x01<br>*<br>~~ee~~<br>~~ee~~|2ndbyte of Sync word<br>Used if_SyncOn_is set and_(SyncSize +1)_>= 2.<br>~~ee~~<br>~~ee~~|
|RegSyncValue3<br>(0x31)|7-0|SyncValue(47:40)<br>~~ee~~<br>~~ee~~|rw<br>~~ee~~<br>~~ee~~|0x01<br>*<br>~~ee~~<br>~~ee~~|3rdbyte of Sync word.<br>Used if_SyncOn_is set and_(SyncSize +1)_>= 3.<br>~~ee~~<br>~~ee~~|
|RegSyncValue4<br>(0x32)|7-0|SyncValue(39:32)<br>~~ee~~<br>~~ee~~|rw<br>~~ee~~<br>~~ee~~|0x01<br>*<br>~~ee~~<br>~~ee~~|4thbyte of Sync word.<br>Used if_SyncOn_is set and_(SyncSize +1)_>= 4.<br>~~ee~~<br>~~ee~~|
|RegSyncValue5<br>(0x33)|7-0|SyncValue(31:24)<br>~~ee~~<br>~~ee~~|rw<br>~~ee~~<br>~~ee~~|0x01<br>*<br>~~ee~~<br>~~ee~~|5thbyte of Sync word.<br>Used if_SyncOn_is set and_(SyncSize +1)_>= 5.<br>~~ee~~<br>~~ee~~|
|RegSyncValue6<br>(0x34)|7-0|SyncValue(23:16)<br>~~ee~~<br>~~ee~~|rw<br>~~ee~~<br>~~ee~~|0x01<br>*<br>~~ee~~<br>~~ee~~|6thbyte of Sync word.<br>Used if_SyncOn_is set and_(SyncSize +1)_>= 6.<br>~~ee~~<br>~~ee~~|
|RegSyncValue7<br>(0x35)|7-0|SyncValue(15:8)<br>~~ee~~<br>~~ee~~|rw<br>~~ee~~<br>~~ee~~|0x01<br>*<br>~~ee~~<br>~~ee~~|7thbyte of Sync word.<br>Used if_SyncOn_is set and_(SyncSize +1)_>= 7.<br>~~ee~~<br>~~ee~~|
|RegSyncValue8<br>(0x36)|7-0|SyncValue(7:0)<br>~~ee~~<br>~~a ~~|rw<br>~~ee~~<br> ~~ee~~|0x01<br>*<br>~~ee~~<br>~~ee~~|8thbyte of Sync word.<br>Used if_SyncOn_is set and_(SyncSize +1)_= 8.<br>~~ee~~|



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|RegPacketConfig1<br>(0x37)|7|PacketFormat|rw|0|Defines the packet format used:<br>0→Fixed length<br>1→Variable length|
|---|---|---|---|---|---|
||6-5|DcFree|rw|00|Defines DC-free encoding/decoding performed:<br>00→None (Off)<br>01→Manchester<br>10→Whitening<br>11→reserved|
||4|CrcOn|rw|1|Enables CRC calculation/check (Tx/Rx):<br>0→Off<br>1→On|
||3|CrcAutoClearOff|rw|0|Defines the behavior of the packet handler when CRC<br>check fails:<br>0→Clear FIFO and restart new packet reception. No<br>_PayloadReady_interrupt issued.<br>1→Do not clear FIFO._PayloadReady_interrupt issued.|
||2-1|AddressFiltering|rw|00|Defines address based filtering in Rx:<br>00→None (Off)<br>01→Address field must match_NodeAddress_<br>10→Address field must match_NodeAddress_or<br>_BroadcastAddress_<br>11→reserved|
||0|-|rw|0|unused|
|RegPayloadLength<br>(0x38)|7-0|PayloadLength|rw|0x40|If PacketFormat = 0 (fixed), payload length.<br>If PacketFormat = 1 (variable), max length in Rx, not used<br>in Tx.|
|RegNodeAdrs<br>(0x39)|7-0|NodeAddress|rw|0x00|Node address used in address filtering.|
|RegBroadcastAdrs<br>(0x3A)|7-0|BroadcastAddress|rw|0x00|Broadcast address used in address filtering.|
|RegAutoModes<br>(0x3B)|7-5|EnterCondition|rw|000|Interrupt condition for entering the intermediate mode:<br>000→None (AutoModes Off)<br>001→Rising edge of_FifoNotEmpty_<br>010→Rising edge of_FifoLevel_<br>011→Rising edge of_CrcOk_<br>100→Rising edge of_PayloadReady_<br>101→Rising edge of_SyncAddress_<br>110→Rising edge of_PacketSent_<br>111→Falling edge of_FifoNotEmpty_(i.e. FIFO empty)|
||4-2|ExitCondition|rw|000|Interrupt condition for exiting the intermediate mode:<br>000→None (AutoModes Off)<br>001→Falling edge of_FifoNotEmpty_(i.e. FIFO empty)<br>010→Rising edge of_FifoLevel_or_Timeout_<br>011→Rising edge of_CrcOk_or_Timeout_<br>100→Rising edge of_PayloadReady_or_Timeout_<br>101→Rising edge of_SyncAddress_or_Timeout_<br>110→Rising edge of_PacketSent_<br>111→Rising edge of_Timeout_|
||1-0|IntermediateMode|rw|00|Intermediate mode:<br>00→Sleep mode (SLEEP)<br>01→Standby mode (STDBY)<br>10→Receiver mode (RX)<br>11→Transmitter mode (TX)|



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|RegFifoThresh<br>(0x3C)|7|TxStartCondition|rw|1<br>*|Defines the condition to start packet transmission :<br>0→_FifoLevel_(i.e. the number of bytes in the FIFO<br>exceeds_FifoThreshold)_<br>1→_FifoNotEmpty_(i.e. at least one byte in the FIFO)|
|---|---|---|---|---|---|
||6-0|FifoThreshold|rw|0001111|Used to trigger_FifoLevel_interrupt.|
|RegPacketConfig2<br>(0x3D)|7-4|InterPacketRxDelay|rw|0000|After_PayloadReady_occurred, defines the delay between<br>FIFO empty and the start of a new RSSI phase for next<br>packet. Must match the transmitter’s PA ramp-down time.<br>- Tdelay = 0 if_InterpacketRxDelay_>= 12<br>- Tdelay = (2_InterpacketRxDelay) _/_BitRate_otherwise|
||3|-|rw|0|unused|
||2|RestartRx|w|0|Forces the Receiver in WAIT mode, in Continuous Rx<br>mode.<br>Always reads 0.|
||1|AutoRxRestartOn<br>~~ee~~|rw<br>|1<br>~~eee~~|Enables automatic Rx restart (RSSI phase) after<br>_PayloadReady_occurred and packet has been completely<br>read from FIFO:<br>0→Off._RestartRx_can be used.<br>1→On. Rx automatically restarted after<br>_InterPacketRxDelay_.<br>~~eee~~|
||0|AesOn<br>~~ee~~|rw<br><br>~~ee~~|0<br>~~eee~~<br>~~ee~~|Enable the AES encryption/decryption:<br>0→Off<br>1→On (payload limited to 66 bytes maximum)<br>~~eee~~|
|RegAesKey1<br>(0x3E)|7-0|AesKey(127:120)<br>~~ee ~~<br>~~ee~~|w<br> <br>~~ee~~<br>~~ee~~|0x00<br> ~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|1stbyte of cipher key (MSB byte)<br>~~eee~~<br>~~ee~~|
|RegAesKey2<br>(0x3F)|7-0|AesKey(119:112)<br>~~ee~~<br>~~ee~~|w<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0x00<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|2ndbyte of cipher key<br>~~ee~~<br>~~ee~~|
|RegAesKey3<br>(0x40)|7-0|AesKey(111:104)<br>~~ee~~<br>~~ee~~|w<br>~~ee~~<br>~~ee~~<br>~~ee~~|0x00<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|3rdbyte of cipher key<br>~~ee~~<br>~~ee~~|
|RegAesKey4<br>(0x41)|7-0|AesKey(103:96)<br>~~ee~~<br>~~ee~~|w<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0x00<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|4thbyte of cipher key<br>~~ee~~<br>~~ee~~|
|RegAesKey5<br>(0x42)|7-0|AesKey(95:88)<br>~~ee~~<br>~~ee~~|w<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|0x00<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|5thbyte of cipher key<br>~~ee~~<br>~~ee~~|
|RegAesKey6<br>(0x43)|7-0|AesKey(87:80)<br>~~ee~~<br>~~ee~~|w<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0x00<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|6thbyte of cipher key<br>~~ee~~<br>~~ee~~|
|RegAesKey7<br>(0x44)|7-0|AesKey(79:72)<br>~~ee~~<br>~~ee~~|w<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0x00<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|7thbyte of cipher key<br>~~ee~~<br>~~ee~~|
|RegAesKey8<br>(0x45)|7-0|AesKey(71:64)<br>~~ee~~<br>~~ee~~|w<br>~~ee~~<br>~~ee~~<br>~~ee~~|0x00<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|8thbyte of cipher key<br>~~ee~~<br>~~ee~~|
|RegAesKey9<br>(0x46)|7-0|AesKey(63:56)<br>~~ee~~<br>~~ee~~|w<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0x00<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|9thbyte of cipher key<br>~~ee~~<br>~~ee~~|
|RegAesKey10<br>(0x47)|7-0|AesKey(55:48)<br>~~ee~~<br>~~ee~~|w<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|0x00<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|10thbyte of cipher key<br>~~ee~~<br>~~ee~~|
|RegAesKey11<br>(0x48)|7-0|AesKey(47:40)<br>~~ee~~<br>~~ee~~|w<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0x00<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|11thbyte of cipher key<br>~~ee~~<br>~~ee~~|
|RegAesKey12<br>(0x49)|7-0|AesKey(39:32)<br>~~ee~~<br>~~ee~~|w<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~|0x00<br>~~ee~~<br> ~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|12thbyte of cipher key<br>~~ee~~<br>~~ee~~|
|RegAesKey13<br>(0x4A)|7-0|AesKey(31:24)<br>~~ee~~<br>~~ee~~|w<br>~~ee~~<br>~~ee~~<br>~~ee~~|0x00<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|13thbyte of cipher key<br>~~ee~~<br>~~ee~~|



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|RegAesKey14<br>(0x4B)|7-0|AesKey(23:16)|w|0x00|14thbyte of cipher key|
|---|---|---|---|---|---|
|RegAesKey15<br>(0x4C)|7-0|AesKey(15:8)|w|0x00|15thbyte of cipher key|
|RegAesKey16<br>(0x4D)|7-0|AesKey(7:0)|w|0x00|16thbyte of cipher key (LSB byte)|



## **6.7.  Temperature Sensor Registers** 

_Table 29  Temperature Sensor Registers_ 

|**Name**<br>**(Address)**|**Bits**|**Variable Name**|**Mode**|**Default**<br>**Value**|**Description**|
|---|---|---|---|---|---|
|RegTemp1<br>(0x4E)|7-4<br>~~a~~|-<br>~~ee~~|r<br>~~ee~~|0000<br>~~ee ~~|unused<br> ~~PT~~|
||3|TempMeasStart<br>~~ee~~|w<br>~~ee~~|0<br>~~ee~~|Triggers the temperature measurement when set. Always<br>reads 0.<br>~~ee~~|
||2<br>~~a~~|TempMeasRunning<br>~~ee~~<br>~~ee~~|r<br>~~ee~~<br>~~ee~~|0<br>~~ee~~<br>|Set to 1 while the temperature measurement is running.<br>Toggles back to 0 when the measurement has completed.<br>The receiver can not be used while measuring<br>temperature<br>~~ee~~<br>~~PT~~|
||1-0<br>~~a~~<br>~~Fe~~|-<br>~~ee~~<br>~~ee~~<br>~~Fe~~<br>~~EE~~|r<br>~~ee~~<br>~~ee ~~<br>~~EE~~|01<br>~~ee~~<br> <br>~~EE~~|unused<br>~~ee~~<br> ~~PT~~|
|RegTemp2<br>(0x4F)|7-0 <br>~~Fe~~|TempValue<br>~~Fe~~<br>~~EE~~|r<br>~~EE~~|-<br>~~EE~~|Measured temperature<br>-1°C per Lsb<br>Needs calibration for accuracy|



## **6.8.  Test Registers** 

## _Table 30  Test Registers_ 

|**Name**<br>**(Address)**|**Bits**|**Variable Name**|**Mode**|**Default**<br>**Value**|**Description**|
|---|---|---|---|---|---|
|RegTestLna<br>(0x58)|7-0|SensitivityBoost|rw|0x1B|High sensitivity or normal sensitivity mode:<br>0x1B→Normal mode<br>0x2D→High sensitivity mode|
|RegTestPa1<br>(0x5A)|7-0|Pa20dBm1|rw|0x55|Set to 0x5D for +20 dBm operation on PA_BOOST.<br>0x55→Normal mode and Rx mode<br>0x5D→+20 dBm mode<br>Revert to 0x55 when receiving or using PA0|
|RegTestPa2<br>(0x5C)|7-0|Pa20dBm2|rw|0x70|Set to 0x7C for +20 dBm operation on PA_BOOST<br>0x70→Normal mode and Rx mode<br>0x7C→+20 dBm mode<br>Revert to 0x70 when receiving or using PA0|
|RegTestDagc<br>(0x6F)|7-0|ContinuousDagc|rw|0x30<br>*|Fading Margin Improvement, refer to 3.4.4<br>0x00→Normal mode<br>0x20→Improved margin, use if_AfcLowBetaOn=1_<br>0x30→Improved margin, use if_AfcLowBetaOn=0_|
|RegTestAfc<br>(0x71)|7-0|LowBetaAfcOffset|rw|0x00|AFC offset set for low modulation index systems, used if<br>_AfcLowBetaOn=1_.<br>_Offset = LowBetaAfcOffset x 488 Hz_|



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## **7. Application Information** 

## **7.1.  Crystal Resonator Specification** 

Table 31 shows the crystal resonator specification for the crystal reference oscillator circuit of  the RFM69HW. This specification covers the full range of operation of the RFM69HW and is employed in the reference design. 

## _Table 31  Crystal Specification_ 

|**Symbol**|**Description**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|FXOSC|XTAL Frequency||26|-|32|MHz|
|RS|XTAL Serial Resistance||-|30|140|ohms|
|C0|XTAL Shunt Capacitance||-|2.8|7|pF|
|CLOAD|External Foot Capacitance|On each pin XTA and XTB|8|16|22|pF|



_Notes   - the initial frequency tolerance, temperature stability and ageing performance should be chosen in accordance with the target operating temperature range and the receiver bandwidth selected._ 

_- the loading capacitance should be applied externally, and adapted to the actual Cload specification of the XTAL._ 

_- A minimum XTAL frequency of 28 MHz is required to cover the 863-870 MHz band, 29 MHz for the 902-928 MHz band_ 

## **7.2.  Reset of the Module** 

A power-on reset of the RFM69HW is triggered at power up. Additionally, a manual reset can be issued by controlling pin RESET. 

## **7.2.1. POR** 

If the application requires the disconnection of VDD from the RFM69HW, despite of the extremely low Sleep Mode current, the user should wait for 10 ms from of the end of the POR cycle before commencing communications over the SPI bus. Pin 

6 (Reset) should be left floating during the POR sequence. 

**==> picture [248 x 73] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>Pin Reset<br>Undefined<br>(output)<br>Wait for Module is ready<br>10 ms from this point on<br>**----- End of picture text -----**<br>


## _Figure 39.  POR Timing Diagram_ 

Please note that any CLKOUT activity can also be used to detect that the module is ready. 

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**RFM69HW** 

## **7.2.2. Manual Reset** 

A manual reset of the RFM69HW is possible even for applications in which VDD cannot be physically disconnected. Pin RESET should be pulled high for a hundred microseconds, and then released. The user should then wait for 5 ms before using the module. 

_Figure 40.  Manual Reset Timing Diagram_ 

_Note whilst pin RESET is driven high, an over current consumption of up to ten milliamps can be seen on VDD._ 

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## **7.3.  Reference Design** 

Please contact your representative for evaluation tools, reference designs and design assistance. Note that all schematics shown in this section are full schematics, listing ALL required components, including decoupling capacitors. 

_Figure 41:+20dBm Schematic_ 

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## **8. Packaging Information** 

## **8.1.  Package Outline Drawing** 

_Figure 42.  S 2 Package Outline Drawing_ 

**==> picture [35 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Page 78<br>**----- End of picture text -----**<br>


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**RFM69HW** 

## **9. Ordering Information** 

— **DRFM69HW 433 S2** 

Package Operation Band Mode Type 

**P/N: RFM69HW-315S2 RFM69HW module at 315MHz band, SMD Package P/N: RFM69HW-433S2 RFM69HW module at 433MHz band, SMD Package P/N: RFM69HW-868S2 RFM69HW module at 868MHz band, SMD Package P/N: RFM69HW-915S2 RFM69HW module at 915MHz band, SMD PackageV** 

This document may contain preliminary information and is subject to change by Hope Microelectronics without notice. Hope Microelectronics assumes no responsibility or liability for any use of the information **HOPE MICROELECTRONICS CO.,LTD** contained herein. Nothing in this document shall operate as an express or Add: 2/F, Building 3, Pingshan Private implied license or indemnity under the intellectual property rights of Hope Enterprise Science and Technology Microelectronics or third parties. The products described in this document Park, Lishan Road, XiLi Town, are not intended for use in implantation or other direct life support Nanshan District, Shenzhen, applications where malfunction may result in the direct physical harm or Guangdong, China injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT Tel:  86-755-82973805 NOT LIMITED TO, THE IMPLIED WARRANTIES OF MECHANTABILITY Fax:  86-755-82973550 OR FITNESS FOR A ARTICULAR PURPOSE, ARE OFFERED IN THIS Email:   sales@hoperf.com DOCUMENT. Website:  http://www.hoperf.com http://www.hoperf.cn ©2006, HOPE MICROELECTRONICS CO.,LTD. All rights reserved. 

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