RFD3055LE

_**RFD3055LE, RFD3055LESM**_ 

## _**Data Sheet**_ 

## _**N-Channel Logic Level Power MOSFET 60V, 11A, 107 mΩ**_ 

These N-Channel enhancement-mode power MOSFETs are manufactured using the latest manufacturing process technology. This process, which uses feature sizes approaching those of LSI circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. These transistors can be operated directly from integrated circuits. 

Formerly developmental type TA49158. 

## _**Ordering Information**_ 

|**PART NUMBER**|**PACKAGE**|**BRAND**|
|---|---|---|
|RFD3055LE|TO-251AA|F3055L|
|RFD3055LESM9A|TO-252AA|F3055L|



## _**September 20 13**_ 

## _**Features**_ 

- 11A, 60V 

- r = 0.107Ω **DS(ON)** 

- Temperature Compensating PSPICE[®] Model 

- Peak Current vs Pulse Width Curve 

- UIS Rating Curve 

- Related Literature 

- TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” 

## _**Symbol**_ 

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## _**Packaging**_ 

**JEDEC TO-251AA** 

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SOURCE<br>DRAIN<br>GATE<br>DRAIN (FLANGE)<br>oFs<br>**----- End of picture text -----**<br>


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JEDEC TO-252AA<br>**----- End of picture text -----**<br>


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DRAIN (FLANGE)<br>GATE<br>SOURCE<br>oo<br>**----- End of picture text -----**<br>


©2002 Fairchild Semiconductor Corporation 

RFD3055LE, RFD3055LESM Rev. C0 

_**RFD3055LE, RFD3055LESM**_ 

## **Absolute Maximum Ratings** TC = 25[o] C, Unless Otherwise Specified 

|**Absolute Maximum Ratings **TC = 25C = 25= 25[o]C, Unless Otherwise Specified|||
|---|---|---|
||**RFD3055LE,**||
||**RFD3055LESM9A**|**UNITS**|
|Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS|60|V|
|Drain to Gate Voltage (RGS= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR|60|V|
|Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS|±16|V|
|Continuous Drain Current  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID|11|A|
|Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM|Refer to Peak Current Curve||
|Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS|Refer to UIS Curve||
|Power Dissipation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD|38|W|
|Derate Above 25oC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .|0.25|W/oC|
|Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG|-55 to 175|oC|
|Maximum Temperature for Soldering|||
|Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL|300|oC|
|Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg|260|oC|



_CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied._ 

## NOTE: 

1. TJ = 25[o] C to 150[o] C. 

## **Electrical Specifications** TC = 25[o] C, Unless Otherwise Specified 

|**Electrical Specifications**<br>TC = 25C = 25= 25[o]C, Unless Otherwise Specified|C, Unless Otherwise Specified|C, Unless Otherwise Specified|C, Unless Otherwise Specified||||||
|---|---|---|---|---|---|---|---|---|
|**PARAMETER**||**SYMBOL**|**TEST CONDITIONS**|**MIN**||**TYP**|**MAX**|**UNITS**|
|Drain to Source Breakdown Voltage||BVDSS|ID= 250µA, VGS= 0V|60||-|-|V|
|Gate Threshold Voltage||VGS(TH)|VGS= VDS, ID= 250µA|1||-|3|V|
|Zero Gate Voltage Drain Current||IDSS|VDS= 55V, VGS= 0V|-||-|1|µA|
||||VDS= 50V, VGS= 0V, TC= 150oC|-||-|250|µA|
|Gate to Source Leakage Current||IGSS|VGS=±16V|-||-|±100|nA|
|Drain to Source On Resistance (Note 2)||rDS(ON)|ID= 8A, VGS= 5V (Figure 11)|-||-|0.107|Ω|
|Turn-On Time||tON|VDD ≈30V, ID= 8A,|-||-|170|ns|
|Turn-On Delay Time||td(ON)|VGS= 4.5V, RGS= 32Ω<br>(Figures 10, 18, 19)|-||8|-|ns|
|Rise Time||tr||-||105|-|ns|
|Turn-Off Delay Time||td(OFF)||-||22|-|ns|
|Fall Time||tf||-||39|-|ns|
|Turn-Off Time||tOFF||-||-|92|ns|
|Total Gate Charge<br>Qg(TOT)<br>VGS= 0V to 10V<br>VDD= 30V, ID= 8A,<br>Ig(REF)= 1.0mA<br>(Figures 20, 21)<br>-<br>9.4<br>11.3<br>nC<br>Gate Charge at 5V<br>Qg(5)<br>VGS= 0V to 5V<br>-<br>5.2<br>6.2<br>nC<br>Threshold Gate Charge<br>Qg(TH)<br>VGS= 0V to 1V<br>-<br>0.36<br>0.43<br>nC<br>Input Capacitance<br>CISS<br>VDS= 25V, VGS= 0V, f = 1MHz<br>(Figure 14)<br>-<br>350<br>-<br>pF<br>Output Capacitance<br>COSS<br>-<br>105<br>-<br>pF<br>Reverse Transfer Capacitance<br>CRSS<br>-<br>23<br>-<br>pF<br>Thermal Resistance Junction to Case<br>RθJC<br>-<br>-<br>3.94<br>oC/W<br>Thermal Resistance Junction to Ambient<br>RθJA<br>TO-220AB<br>-<br>-<br>62<br>oC/W<br>TO-251AA, TO-252AA<br>-<br>-<br>100<br>oC/W<br>————$ J<br>——<br>a<br>——|||||||||
|**Source to Drain Diode Specifications**|||||||||
|**PARAMETER**<br>**SYMBOL**<br>**TEST CONDITIONS**<br>**MIN**<br>**TYP**<br>**MAX**<br>**UNITS**<br>Source to Drain Diode Voltage<br>VSD<br>ISD= 8A<br>-<br>1.25<br>V<br>Diode Reverse Recovery Time<br>trr<br>ISD= 8A, dISD/dt = 100A/µs<br>-<br>66<br>ns<br>~~a~~|||||||||
|NOTES:|||||||||



2. Pulse Test: Pulse Width ≤ 300ms, Duty Cycle ≤ 2%. 

3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current Capability Curve (Figure 5). 

©2002 Fairchild Semiconductor Corporation 

RFD3055LE, RFD3055LESM Rev. C0 

_**RFD3055LE, RFD3055LESM**_ 

## _**Typical Performance Curves**_ Unless Otherwise Specified 

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1.2<br>15<br>1.0<br>VGS = 10V<br>0.8 10<br>PIN | tt —<br>0.6 VGS = 4.5V<br>0.4 Ce PA 5<br>aaa Ne NG<br>0.2<br>0<br>0 aaa<br>0 25 50 75 100 125 150 175 25 50 75 100 125 150 175<br>TC, CASE TEMPERATURE ( [o] C) TC, CASE TEMPERATURE ( [o] C)<br>, DRAIN CURRENT (A)<br>ID<br>POWER DISSIPATION MULTIPLIER<br>**----- End of picture text -----**<br>


**FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE CASE TEMPERATURE** 

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2<br>DUTY CYCLE - DESCENDING ORDER<br>1 0.5<br>0.2 l ll<br>|<br>0.1<br>0.05<br>0.02<br>0.01<br>eee PDM<br>0.1<br>t1<br>t2<br>NOTES:<br>SINGLE PULSE DUTY FACTOR: D = t1/t2<br>PEAK TJ = PDM x Z θ JC x R θ JC + TC<br>0.01 atwall t UE LLLHETE<br>10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1]<br>t, RECTANGULAR PULSE DURATION (s)<br>FIGURE 3. NORMALIZED TRANSIENT THERMAL IMPEDANCE<br>100 200<br>TC = 25 [o] C<br>FOR TEMPERATURES<br>ABOVE 25 [o] C DERATE PEAK<br>100<br>CURRENT AS FOLLOWS:<br>10 100 µ s I = I25  175 - TC<br>150<br>a tC HHH |{—]<br>ees OPERATION IN THIS  |S 1ms NTTSLTTM<br>AREA MAY BE<br>1 LIMITED BY rDS(ON)<br>eS A 10ms a r 0 a<br>VGS = 5V<br>SINGLE PULSE<br>TJ = MAX RATED TC = 25 [o] C TRANSCONDUCTANCEMAY LIMIT CURRENT<br>0.1 a eeOLEi 10 IN THIS REGION ceo<br>1 10 100 200<br>10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1]<br>VDS, DRAIN TO SOURCE VOLTAGE (V) t, PULSE WIDTH (s)<br>, NORMALIZED<br>JC<br>θ<br>Z<br>THERMAL IMPEDANCE<br>, DRAIN CURRENT (A) , PEAK CURRENT (A)<br>ID IDM<br>**----- End of picture text -----**<br>


**FIGURE 4. FORWARD BIAS SAFE OPERATING AREA** 

**FIGURE 5. PEAK CURRENT CAPABILITY** 

©2002 Fairchild Semiconductor Corporation 

RFD3055LE, RFD3055LESM Rev. C0 

_**RFD3055LE, RFD3055LESM**_ 

## _**Typical Performance Curves**_ Unless Otherwise Specified **(Continued)** 

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100<br>If R = 0<br>tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)AV = (L)(IAS)/(1.3*RATED BVDSS - VDD) = (L)(IAS)/(1.3*RATED BVDSS - VDD)AS)/(1.3*RATED BVDSS - VDD))/(1.3*RATED BVDSS - VDD)DSS - VDD) - VDD)DD))<br>If R  ≠  0<br>tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]AV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]AS*R)/(1.3*RATED BVDSS - VDD) +1]*R)/(1.3*RATED BVDSS - VDD) +1]DSS - VDD) +1] - VDD) +1]DD) +1]) +1]<br>STARTING TJ = 25J = 25 = 25 [[o]] C<br>10<br>STARTING TJ = 150J = 150 = 150 [[o]] C<br>1<br>ETI ETT ATIITINNO<br>0.001 0.01 0.1 1 10<br>tAV, TIME IN AVALANCHE (ms)AV, TIME IN AVALANCHE (ms), TIME IN AVALANCHE (ms)<br>, AVALANCHE CURRENT (A)<br>IASAS<br>**----- End of picture text -----**<br>


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15<br>If R = 0 VGS = 10V<br>tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)AV = (L)(IAS)/(1.3*RATED BVDSS - VDD) = (L)(IAS)/(1.3*RATED BVDSS - VDD)AS)/(1.3*RATED BVDSS - VDD))/(1.3*RATED BVDSS - VDD)DSS - VDD) - VDD)DD))<br>If R  ≠  0 VGS = 5V<br>tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]AV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]AS*R)/(1.3*RATED BVDSS - VDD) +1]*R)/(1.3*RATED BVDSS - VDD) +1]DSS - VDD) +1] - VDD) +1]DD) +1]) +1] 12 VGS = 4V<br>STARTING TJ = 25J = 25 = 25 [[o]] C 9<br>10 VGS = 3.5V<br>STARTING TJ = 150J = 150 = 150 [[o]] C 6<br>PULSE DURATION = 80 µ s<br>DUTY CYCLE = 0.5% MAX<br>3<br>1  TC = 25 [o] C VGS = 3V<br>ETI ETT ATIITINNO 0 mn<br>0.001 0.01 0.1 1 10<br>0 1 2 3 4<br>tAV, TIME IN AVALANCHE (ms)AV, TIME IN AVALANCHE (ms), TIME IN AVALANCHE (ms) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>NOTE: Refer to Fairchild Application Notes AN9321 and AN9322<br>FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS<br>15 150<br>PULSE DURATION = 80 µ s PULSE DURATION = 80 µ s<br>DUTY CYCLE = 0.5% MAX ID = 3A ID = 11A DUTY CYCLE = 0.5% MAX<br>12 VDD = 15V  TC = 25 [o] C<br>ID = 5A<br>120<br>9<br>6  TJ = 25 [o] C<br>90<br>3 — f~ X K<br> TJ = 175 [o] C<br> TJ = -55 [o] C<br>0<br>>ee ee 60 ee<br>2 3 4 5 2 4 6 8 10<br>VGS, GATE TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V)<br>FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE<br>VOLTAGE AND DRAIN CURRENT<br>150 2.5<br>VGS = 4.5V, VDD = 30V,  ID = 8A  PULSE DURATION = 80 µ s<br>DUTY CYCLE = 0.5% MAX<br>tr<br>2.0<br>100<br>P| ee<br>1.5<br>tf<br>50 Beane<br>td(OFF) 1.0<br>td(ON) VGS = 10V, ID = 11A<br>0 = 0.5<br>-80 -40 0 40 80 120 160 200<br>0 10 20 30 40 50<br>RGS, GATE TO SOURCE RESISTANCE ( Ω ) TJ, JUNCTION TEMPERATURE ( [o] C)<br>, DRAIN CURRENT (A)<br>ID<br>, AVALANCHE CURRENT (A)<br>IASAS<br>) Ω<br>, DRAIN TO SOURCE<br> DRAIN CURRENT (A) ON RESISTANCE (m<br>ID, rDS(ON)<br>ON RESISTANCE<br>SWITCHING TIME (ns)<br>NORMALIZED DRAIN TO SOURCE<br>**----- End of picture text -----**<br>


NOTE: Refer to Fairchild Application Notes AN9321 and AN9322 

**FIGURE 10. SWITCHING TIME vs GATE RESISTANCE** 

**FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE** 

©2002 Fairchild Semiconductor Corporation 

RFD3055LE, RFD3055LESM Rev. C0 

_**RFD3055LE, RFD3055LESM**_ 

## _**Typical Performance Curves**_ Unless Otherwise Specified **(Continued)** 

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1.2<br>VGS = VDS, ID = 250 µ A<br>1.0<br>0.8<br>0.6<br>-80 -40 0 40 80 120 160 200<br>TJ, JUNCTION TEMPERATURE ( [o] C)<br>FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs<br>JUNCTION TEMPERATURE<br>1000<br>CISS  =  CGS + CGD<br>COSS  ≅  CDS + CGD<br>100 SS re<br>VGS = 0V, f = 1MHz CRSS  =  CGD<br>10 ee eae LETT NS ON<br>0.1 1 10 60<br>VDS, DRAIN TO SOURCE VOLTAGE (V)<br>NORMALIZED GATE<br>THRESHOLD VOLTAGE<br>C, CAPACITANCE (pF)<br>**----- End of picture text -----**<br>


**FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE** 

## _**Test Circuits and Waveforms**_ 

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VDS<br>L<br>VARY tP TO OBTAIN +<br>REQUIRED PEAK IAS RG VDD<br>VGS -<br>DUT<br>tP<br>0V IAS<br>0.01 Ω<br>**----- End of picture text -----**<br>


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1.2<br>ID = 250 µ A<br>1.1<br>1.0<br>0.9<br>-80 -40 0 40 80 120 160 200<br>TJ, JUNCTION TEMPERATURE ( [o] C)<br>FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN<br>VOLTAGE vs JUNCTION TEMPERATURE<br>10<br>VDD = 30V<br>8<br>6<br>| | A<br>4<br>WAVEFORMS IN<br>DESCENDING ORDER:<br>2 ID = 11A<br>ID = 5A<br>ID = 3A<br>0 a<br>fo<br>0 2 4 6 8 10<br>Qg, GATE CHARGE (nC)<br>NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.<br>FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR<br>CONSTANT GATE CURRENT<br>BVDSS<br>tP<br>VDS<br>IAS<br>VDD<br>0<br>tAV<br>BREAKDOWN VOLTAGE<br>NORMALIZED DRAIN TO SOURCE<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE** 

**FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT** 

**FIGURE 17. UNCLAMPED ENERGY WAVEFORMS** 

©2002 Fairchild Semiconductor Corporation 

RFD3055LE, RFD3055LESM Rev. C0 

_**RFD3055LE, RFD3055LESM**_ 

## _**Test Circuits and Waveforms**_ **(Continued)** 

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tON tOFF<br>td(ON) td(OFF)<br>VDSDS<br>tr tf<br>VDS<br>90% 90%<br>VGSGS RLL<br>+ 10% 10%<br>VDDDD 0<br>-<br>DUT 90%<br>RGSGS<br>VGS 50% 50%<br>PULSE WIDTH<br>10%<br>0<br>FIGURE 18. SWITCHING TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS<br>VDS<br>RL VDD Qg(TOT)<br>S s<br>VDS<br>VGS = 20V<br>VGS + Qg(10) OR Qg(5)  VL [2] GS  DEVICES= 10V FOR<br>- VDD VGS VVGS GS = 10V= 5V FOR<br>DUT VGS = 2V VGS = 1V FOR L [2]  DEVICES<br>Ig(REF) 0 L [2]  DEVICES<br>_ _ Qg(TH) tS<br>Ig(REF)<br>0 -————————<br>**----- End of picture text -----**<br>


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VDSDS<br>VGSGS RLL<br>+<br>VDDDD<br>-<br>DUT<br>RGSGS<br>VGS<br>**----- End of picture text -----**<br>


**FIGURE 20. GATE CHARGE TEST CIRCUIT** 

**FIGURE 21. GATE CHARGE WAVEFORMS** 

©2002 Fairchild Semiconductor Corporation 

RFD3055LE, RFD3055LESM Rev. C0 

_**RFD3055LE, RFD3055LESM**_ 

## _**PSPICE Electrical Model**_ 

.SUBCKT RFD3055LE 2 1 3 ; rev 1/30/95 

CA  12  8 3.9e-9 CB  15  14 4.9e-9 CIN  6  8 3.25e-10 

DBODY 7 5 DBODYMOD DBREAK 5 11  DBREAKMOD DPLCAP 10 5 DPLCAPMOD 

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LDRAIN<br>DPLCAP 5 DRAIN<br>2<br>10<br>RLDRAIN<br>RSLC1<br>51 DBREAK<br>RSLC2<br>5<br>51 ESLC 11<br>- 50 +<br>6 RDRAIN 17 DBODY<br>ESG EBREAK 18<br>+ 8 EVTHRES 16 -<br>+ 19 - 21 MWEAK<br>LGATE EVTEMP 8<br>GATE RGATE + 18 - 6<br>1 22 MMED<br>9 20<br>MSTRO<br>RLGATE<br>LSOURCE<br>CIN 8 7 SOURCE3<br>RSOURCE<br>RLSOURCE<br>S1A S2A<br>12 13 14 15 RBREAK<br>17 18<br>8 13<br>S1B S2B RVTEMP<br>13 CB 19<br>CA + + 14 IT rn -<br>6 5 VBAT<br>EGS 8 EDS 8 +<br>- - 8<br>22<br>RVTHRES<br>+<br>-<br>**----- End of picture text -----**<br>


EBREAK 11 7 17  18 67.8 EDS  14  8  5  8 1 EGS  13  8  6  8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8  1 EVTEMP 20 6 18 22 1 

IT  8  17  1 

LDRAIN 2 5 1.0e-9 LGATE 1  9 5.42e-9 LSOURCE  3  7 2.57e-9 

MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD 

RBREAK  17  18  RBREAKMOD  1 RDRAIN 50 16 RDRAINMOD 3.7e-2 RGATE  9  20 3.37 RLDRAIN 2 5 10 RLGATE 1 9 54.2 RLSOURCE 3 7 25.7 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE  8  7  RSOURCEMOD 2.50e-2 RVTHRES 22 8 RVTHRESMOD  1 RVTEMP 18 19 RVTEMPMOD 1 

S1A  6  12  13  8  S1AMOD S1B  13  12  13  8  S1BMOD S2A  6  15  14  13  S2AMOD S2B  13  15  14  13  S2BMOD 

VBAT 22 19  DC  1 

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*30),3))} 

.MODEL DBODYMOD D (IS = 1.75e-13 RS = 1.75e-2 TRS1 = 1e-4 TRS2 = 5e-6 CJO = 5.9e-10 TT = 5.45e-8 N = 1.03 M = 0.6) .MODEL DBREAKMOD D (RS = 6.50e-1 TRS1 = 1.25e-4 TRS2 = 1.34e-6) .MODEL DPLCAPMOD D (CJO = 3.21e-10 IS = 1e-30 N = 10 M = 0.81) .MODEL MMEDMOD NMOS (VTO = 2.02 KP = .83 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.37) .MODEL MSTROMOD NMOS (VTO = 2.39 KP = 14 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.78 KP = 0.02 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33.7 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.06e-3 TC2 = 0) .MODEL RDRAINMOD RES (TC1 = 1.23e-2 TC2 = 2.58e-5) .MODEL RSLCMOD RES (TC1 = 0 TC2 = 0) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -2.19e-3 TC2 = -4.97e-6) .MODEL RVTEMPMOD RES (TC1 = -1.6e-3 TC2 = 1e-7) 

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4 VOFF= -2.5) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.5 VOFF= -4) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= 0) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0 VOFF= -0.5) 

## .ENDS 

For further discussion of the PSPICE model, consult **A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options** ; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 

©2002 Fairchild Semiconductor Corporation 

RFD3055LE, RFD3055LESM Rev. C0 

_**RFD3055LE, RFD3055LESM**_ 

## **TRADEMARKS** 

The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 

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|---|---|---|---|---|---|---|---|
|AccuPower™|F-PFS™|Sync-Lock™|
|AX-CAP|[®]|*|FRFET|[®]|tm|[®]|®*|
|BitSiC™|Global Power Resource|[SM]|PowerTrench|[®]|
|E|GENERALSYSTEM|
|Build it Now™|GreenBridge™|PowerXS™|
|CorePLUS™|Green FPS™|Programmable Active Droop™|TinyBoost|[®]|
|CorePOWER™|Green FPS™ e-Series™|QFET|[®]|TinyBuck|[®]|
|CROSSVOLT|™|G|max|™|QS™|TinyCalc™|
|CTL™|GTO™|Quiet Series™|TinyLogic|[®]|
|TINYOPTO™|
|Current Transfer Logic™|IntelliMAX™|RapidConfigure™|
|DEUXPEED|[®]|ISOPLANAR™|™|TinyPower™|
|Dual Cool™|Marking Small Speakers Sound Louder|TinyPWM™|
|EcoSPARK|[®]|and Better™|Saving our world, 1mW/W/kW at a time™|TinyWire™TranSiC™|
|EfficentMax™|MegaBuck™|SignalWise™|TriFault Detect™|
|ESBC™|MICROCOUPLER™|SmartMax™|TRUECURRENT|[®]|*|
|®|MicroFET™MicroPak™|SMART START™Solutions for Your Success™|SerDes™|
|Fairchild|[®]|MicroPak2™|SPM|[®]|
|Fairchild Semiconductor|[®]|MillerDrive™|STEALTH™|WZ...|
|FACT Quiet Series™|MotionMax™|SuperFET|[®]|UHC|[®]|
|FACT|[®]|mWSaver|[®]|SuperSOT™-3|Ultra FRFET™|
|FAST|[®]|OptoHiT™|SuperSOT™-6|UniFET™|
|FastvCore™|OPTOLOGIC|[®]|SuperSOT™-8|VCX™|
|FETBench™|OPTOPLANAR|[®]|SupreMOS|[®]|VisualMax™|
|FPS™|SyncFET™|VoltagePlus™|
|XS™|

**----- End of picture text -----**<br>


*Trademarks of System General Corporation, used under license by Fairchild Semiconductor. 

## **DISCLAIMER** 

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. 

## **LIFE SUPPORT POLICY** 

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. 

As used here in: 

1. Life support devices or systems are devices or systems which, (a) are 2. intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 

A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 

## **ANTI-COUNTERFEITING POLICY** 

Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website, www.Fairchildsemi.com, under Sales Support. 

Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are experiencing counterfeiting of their parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed application, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild’s full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. 

## **PRODUCT STATUS DEFINITIONS Definition of Terms** 

**==> picture [458 x 97] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||
|---|---|---|
|Datasheet Identification|Product Status|Definition|
|Advance Information|Formative / In Design|Datasheet contains the design specifications for product development. Specifications|
|may change in any manner without notice.|
|Datasheet contains preliminary data; supplementary data will be published at a later|
|Preliminary|First Production|date. Fairchild Semiconductor reserves the right to make changes at any time without|
|notice to improve design.|
|No Identification Needed|Full Production|Datasheet contains final specifications. Fairchild Semiconductor reserves the right to|
|make changes at any time without notice to improve the design.|
|Obsolete|Not In Production|Datasheet contains specifications on a product that is discontinued by Fairchild|
|Semiconductor. The datasheet is for reference information only.|

**----- End of picture text -----**<br>


Rev. I66 

©2002 Fairchild Semiconductor Corporation 

RFD3055LE, RFD3055LESM Rev. C0