RFD14N05LSM

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_**RFD14N05L, RFD14N05LSM**_ 

## _**Data Sheet**_ 

## _**N-Channel Logic Level Power MOSFET 50 V, 14 A, 100 mΩ**_ 

These are N-channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers.  This performance is accomplished through a special gate oxide design which provides full rated conductance at gate bias in the 3V-5V range, thereby facilitating true on-off power control directly from logic level (5V) integrated circuits. 

Formerly developmental type TA09870. 

## _**Ordering Information**_ 

|**PART NUMBER**|**PACKAGE**|**BRAND**|
|---|---|---|
|RFD14N05L|TO-251AA|14N05L|
|RFD14N05LSM|TO-252AA|14N05L|
|RFD14N05LSM9A|TO-252AA|14N05L|



NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in the tape and reel, i.e., RFD14N05LSM9A. 

## _**October 2013**_ 

## _**Features**_ 

- 14A,  50V 

- rDS(ON) = 0.100 Ω 

- Temperature Compensating PSPICE[®] Model 

- Can be Driven Directly from CMOS, NMOS, and TTL Circuits 

- Peak Current vs Pulse Width Curve 

- UIS Rating Curve 

- 175[o] C Operating Temperature 

- Related Literature 

- TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” 

## _**Symbol**_ 

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D<br>G<br>. : S<br>**----- End of picture text -----**<br>


## _**Packaging**_ 

## **JEDEC TO-251AA** 

**SOURCE DRAIN GATE DRAIN (FLANGE)** 

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JEDEC TO-252AA<br>**----- End of picture text -----**<br>


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DRAIN (FLANGE)<br>**----- End of picture text -----**<br>


©2004 Fairchild Semiconductor Corporation 

RFD14N05L, RFD14N05LSM Rev. C0 

_**RFD14N05L, RFD14N05LSM**_ 

**Absolute Maximum Ratings** TC = 25[o] C, Unless Otherwise Specified 

|**Absolute Maximum Ratings**<br>TC = 25C = 25= 25[o]C, Unless Otherwise Specified|||
|---|---|---|
||**RFD14N05L, RFD14N05LSM,**||
||**RFD14N05LSM9A**|**UNITS**|
|Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS|50|V|
|Drain to Gate Voltage (RGS= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR|50|V|
|Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS|±10|V|
|Continuous Drain Current  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID|14|A|
|Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM|Refer to Peak Current Curve||
|Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS|Refer to UIS Curve||
|Power Dissipation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD|48|W|
|Derate above 25oC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .|0.32|W/oC|
|Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ,TSTG|-55 to 175|oC|
|Maximum Temperature for Soldering|||
|Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL|300|oC|
|Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg|260|oC|



_CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied._ 

NOTE: 

1. TJ = 25[o] C to 150[o] C. 

## **Electrical Specifications** TC = 25[o] C, Unless Otherwise Specified 

**PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS** Drain to Source Breakdown Voltage BVDSS ID = 250 µ A, VGS = 0V, Figure 13 50 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250 µ A, Figure12 1 - 2 V Zero Gate Voltage Drain Current IDSS VDS = 40V, VGS = 0V - - 1 µ A VDS = 40V, VGS = 0V, TC = 150[o] C - - 50 µ A Gate to Source Leakage Current IGSS VGS = ± 10V - - ± 100 nA Drain to Source On Resistance (Note 2) rDS(ON) ID = 14A, VGS = 5V, Figures 9, 11 - - 0.100 Ω Turn-On Time t(ON) VDD = 25V, ID = 7A, - - 60 ns Turn-On Delay Time td(ON) RRLGS = 3.57 = 0.6 ΩΩ , VGS = 5V, - 13 - ns Rise Time tr - 24 - ns Turn-Off Delay Time td(OFF) - 42 - ns Fall Time tf - 16 - ns Turn-Off Time t(OFF) - - 100 ns ~~SS~~ Total Gate Charge Qg(TOT) VGS = 0V to 10V VDD = 40V, ID = 14A, - - 40 nC Gate Charge at 5V Qg(5) VGS = 0V to 5V RL = 2.86 Ω ~~==~~ - - 25 nC Figures 20, 21 ~~————~~ Threshold Gate Charge Qg(TH) VGS = 0V to 1V - - 1.5 nC Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz - 670 - pF Output Capacitance COSS Figure 14 - 185 - pF Reverse Transfer Capacitance CRSS - 50 - pF ~~——~~ Thermal Resistance Junction to Case R θ JC - - 3.125 oC/W Thermal Resistance Junction to Ambient R θ JA TO-251 - - 100 oC/W ~~a~~ R θ JA TO-252 - - 100 oC/W **Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS** Source to Drain Diode Voltage (Note 2) VSD ISD = 14A - - 1.5 V Diode Reverse Recovery Time trr ISD = 14A, dISD/dt = 100A/ µ s - - 125 ns ~~—_—_——~~ NOTES: 

2. Pulse Test: Pulse Width ≤ 300ms, Duty Cycle ≤ 2%. 

3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current Capability Curve (Figure 5). 

©2004 Fairchild Semiconductor Corporation 

RFD14N05L, RFD14N05LSM Rev. C0 

_**RFD14N05L, RFD14N05LSM**_ 

## _**Typical Performance Curves**_ Unless Otherwise Specified 

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1.2<br>1.0<br>0.8<br>INE<br>0.6 CENaN<br>0.4 aNS<br>0.2<br>0<br>0 pt 25 50 EET 75 100 125 EN 150 175<br>TC, CASE TEMPERATURE ( [o] C)<br>POWER DISSIPATION MULTIPLIER<br>**----- End of picture text -----**<br>


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16<br>12<br>pt<br>8 OLN<br>o\<br>4 eT eeaw \<br>0<br>25 50 75 100 125 150 175<br>TC, CASE TEMPERATURE ( [o] C)<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. TEMPERATURE TEMPERATURE** 

**FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs** 

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2<br>1<br>1<br>0.5<br>0.2 oe<br>P DM<br>0.1 = Ro<br>0.1<br>0.05 t 1<br>0.02 t2<br>0.01<br>NOTES:<br>SINGLE PULSE DUTY FACTOR: D = t1/t2<br>PEAK TJ = PDM x Z θ JC x R θ JC + TC<br>0.01 Fr CCIHR TAT<br>10 [-5] 10 [-4] 10 [-3] CCE 10 [-2] CEE 10 [-1] 10 [0] 10 [1]<br>t, RECTANGULAR PULSE DURATION (s)<br>FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE<br>100 200<br>TC = 25 [o] C TRANSCONDUCTANCE FOR TEMPERATURES<br>Soocsor 335} TJ = MAX. RATED MAY LIMIT CURRENTIN THIS REGION ABOVE 25CURRENT AS FOLLOWS: [o] C DERATE PEAK<br>100<br>I = I 25 175 - TC<br>150<br>100 µ s<br>10 mcs ua Sant = Ly]<br>Se EET<br>etff ONaff Pre NL! i<br>1ms<br>APES ee CUMING rTMETH TTT TT<br>10ms<br>OPERATION IN THIS Sesh CNC SSC ACT<br>1 AREA MAY BE 100ms VGS = 5V<br>LIMITED BY rDS(ON) DC VGS = 10V<br>0.5 HEE EH 10 TC = 25 [o] C (ic c<br>1 10 100 10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1]<br>VDS, DRAIN TO SOURCE VOLTAGE (V) t, PULSE WIDTH (s)<br>, NORMALIZED<br>JC<br>θ<br>Z<br>THERMAL IMPEDANCE<br>, DRAIN CURRENT (A)<br>ID<br>, PEAK CURRENT CAPABILITY (A)<br>IDM<br>**----- End of picture text -----**<br>


**FIGURE 4. FORWARD BIAS SAFE OPERATING AREA** 

**FIGURE 5. PEAK CURRENT CAPABILITY** 

©2004 Fairchild Semiconductor Corporation 

RFD14N05L, RFD14N05LSM Rev. C0 

_**RFD14N05L, RFD14N05LSM**_ 

## _**Typical Performance Curves**_ Unless Otherwise Specified **(Continued)** 

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50<br>SSH<br>STARTING TJ = 25J = 25 = 25 [[o]] C<br>10<br>STARTING T J  = 150 [[o]] C<br>If R = 0<br>tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)AV = (L)(IAS)/(1.3*RATED BVDSS - VDD) = (L)(IAS)/(1.3*RATED BVDSS - VDD)AS)/(1.3*RATED BVDSS - VDD))/(1.3*RATED BVDSS - VDD)DSS - VDD) - VDD)DD))<br>If R  ≠  0<br>tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1]AV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1]= (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1]AS*R)/(1.3*RATED BVDSS-VDD) +1]*R)/(1.3*RATED BVDSS-VDD) +1]DSS-VDD) +1]-VDD) +1]DD) +1]) +1]<br>1 Ni<br>0.01 0.1 1 10<br>tAV, TIME IN AVALANCHE (ms)AV, TIME IN AVALANCHE (ms), TIME IN AVALANCHE (ms)<br>, AVALANCHE CURRENT (A)<br>IASAS<br>**----- End of picture text -----**<br>


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35<br>VGS = 10V VGS = 5V<br>30 V GS  = 4.5V VGS = 4V<br>SSH = 25 yA|} |} —<br>STARTING TJ = 25J = 25 = 25 [[o]] C<br>10 PULSE DURATION = 80 µ s, TC = 25 [o] C<br>20<br>DUTY CYCLE = 0.5% MAX.<br>15<br>STARTING T J  = 150 [[o]] C<br>10 V GS  = 3V<br>If R = 0<br>tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)AV = (L)(IAS)/(1.3*RATED BVDSS - VDD) = (L)(IAS)/(1.3*RATED BVDSS - VDD)AS)/(1.3*RATED BVDSS - VDD))/(1.3*RATED BVDSS - VDD)DSS - VDD) - VDD)DD))<br>If R  ≠  0 5 V GS  = 2.5V<br>tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1]AV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1]= (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1]AS*R)/(1.3*RATED BVDSS-VDD) +1]*R)/(1.3*RATED BVDSS-VDD) +1]DSS-VDD) +1]-VDD) +1]DD) +1]) +1]<br>1 Ni 0 AAR<br>0.01 0.1 1 10 0 1.5 3.0 4.5 6.0 7.5<br>tAV, TIME IN AVALANCHE (ms)AV, TIME IN AVALANCHE (ms), TIME IN AVALANCHE (ms) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.<br>FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS<br>35 250<br>-55 [[o]] C ID = 7A ID = 14A ID = 28A<br>30<br>ey 25 [[o]] C 175 [[o]] C 200 a<br>25 ee 2)<br>20 ——+ Ffae-—fae-—ae-—-— 150 in<br>\<br>15 100 ID = 3.5A<br>10<br>PULSE DURATION = 80 µ s 50<br>5 DUTY CYCLE = 0.5% MAX. PULSE DURATION = 80 µ s<br>VDD = 15VDD = 15V = 15V<br>DUTY CYCLE = 0.5% MAX.<br>0 ee 0 ae a<br>0 1.5 3.0 4.5 6.0 7.5 2.5 3.0 3.5 4.0 4.5 5.0<br>VGS, GATE TO SOURCE VOLTAGE (V)GS, GATE TO SOURCE VOLTAGE (V), GATE TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V)<br>FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE<br>VOLTAGE AND DRAIN CURRENT<br>160 2.5<br>VDD = 25V, ID = 14A, RL = 3.57 Ω td(OFF) PULSE DURATION = 80 µ s<br>Fh, DUTY CYCLE = 0.5% MAX.<br>140<br>VGS = 10V, ID = 14A<br>2.0<br>120 ee ee eee eee<br>100 ee<br>tr 1.5<br>i.<br>80<br>tf<br>1.0<br>60 | |2ALE<br>40 ane<br>td(ON) 0.5<br>20<br>0 se TOC—~dSC—*‘“T _ 0 srtcees<br>0 10 20 30 40 50 -80 -40 0 40 80 120 160 200<br>RGS, GATE TO SOURCE RESISTANCE ( Ω ) TJ, JUNCTION TEMPERATURE ( [o] C)<br>, DRAIN CURRENT (A)<br>, AVALANCHE CURRENT (A) ID<br>IASAS<br>) Ω<br>, DRAIN TO SOURCE<br>ON RESISTANCE (m<br>, DRAIN TO SOURCE CURRENT (A)IDS(ON)IDS(ON)DS(ON) rDS(ON)<br>ON RESISTANCE<br>SWITCHING TIME (ns)<br>NORMALIZED DRAIN TO SOURCE<br>**----- End of picture text -----**<br>


NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. **FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING** 

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35<br>-55 [[o]] C<br>30<br>ey 25 [[o]] C 175 [[o]] C<br>25 ee 2)<br>20 ——+ Ffae-—fae-—ae-—-—<br>15<br>10<br>PULSE DURATION = 80 µ s<br>5 DUTY CYCLE = 0.5% MAX.<br>VDD = 15VDD = 15V = 15V<br>0 ee<br>0 1.5 3.0 4.5 6.0 7.5<br>VGS, GATE TO SOURCE VOLTAGE (V)GS, GATE TO SOURCE VOLTAGE (V), GATE TO SOURCE VOLTAGE (V)<br>, DRAIN TO SOURCE CURRENT (A)IDS(ON)IDS(ON)DS(ON)<br>**----- End of picture text -----**<br>


**FIGURE 10. SWITCHING TIME vs GATE RESISTANCE** 

**FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE** 

©2004 Fairchild Semiconductor Corporation 

RFD14N05L, RFD14N05LSM Rev. C0 

_**RFD14N05L, RFD14N05LSM**_ 

## _**Typical Performance Curves**_ Unless Otherwise Specified **(Continued)** 

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2.0 2.0<br>VGS = VDS, ID = 250 µ A ID = 250 µ A<br>1.5 1.5<br>1.0 1.0<br>0.5 0.5<br>0 0<br>-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200<br>TJ, JUNCTION TEMPERATURE ( [o] C) TJ, JUNCTION TEMPERATURE ( [o] C)<br>FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs  FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN<br>JUNCTION TEMPERATURE VOLTAGE vs JUNCTION TEMPERATURE<br>800 50 5<br>CISS VDD = BVDSS VDD = BVDSS<br>40 4<br>600<br>—=— VGS = 0V, f = 1MHz 30 LA 3<br>CISS = CGS + CGD<br>400 C RSS = C GD<br>COSS ≈  CDS + CGD 20 2<br>0.75 BVDSS<br>0.50 BVDSS<br>COSS 0.25 BVDSS<br>200 renee 10 7 RL = 3.57 Ω Nal 1<br>IG(REF) = 0.4mA<br>CRSS VGS = 5V<br>0 0<br>0 ee<br>0 5 10 15 20 25 20 ------------------------IG ( REF ) t, TIME ( µ s) 80------------------------IG ( REF )<br>VDS, DRAIN TO SOURCE VOLTAGE (V) IG ( ACT ) IG ( ACT )<br>NOTE: Refer to Fairchild Application Notes AN7254 and AN7260,<br>FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 15. TRANSCONDUCTANCE vs DRAIN CURRENT<br>NORMALIZED GATE<br>THRESHOLD VOLTAGE BREAKDOWN VOLTAGE<br>NORMALIZED DRAIN TO SOURCE<br>C, CAPACITANCE (pF)<br>, DRAIN TO SOURCE VOLTAGE (V) , GATE TO SOURCE VOLTAGE (V)<br>DS GS<br>V V<br>**----- End of picture text -----**<br>


**FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN** 

**FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE** 

## _**Test Circuits and Waveforms**_ 

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VDS<br>BVDSS<br>L tP<br>VDS<br>REQUIRED PEAK IVARY tP TO OBTAINAS RG +VDD IAS VDD<br>VGS -<br>DUT<br>tP<br>0V IAS 0<br>0.01 Ω<br>tAV<br>**----- End of picture text -----**<br>


**FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT** 

**FIGURE 17. UNCLAMPED ENERGY WAVEFORMS** 

©2004 Fairchild Semiconductor Corporation 

RFD14N05L, RFD14N05LSM Rev. C0 

_**RFD14N05L, RFD14N05LSM**_ 

## _**Test Circuits and Waveforms**_ **(Continued)** 

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VDS<br>VGS RL<br>+<br>VDD<br>-<br>DUT<br>RGS<br>VGS<br>**----- End of picture text -----**<br>


**FIGURE 18. SWITCHING TIME TEST CIRCUIT** 

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VDS<br>RL<br>VGS +<br>—=— - VDD<br>DUT<br>IG(REF)<br>**----- End of picture text -----**<br>


**FIGURE 20. GATE CHARGE TEST CIRCUIT** 

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—_> tON = —_> tOFF =<br>ee el td(ON) ae l td(OFF)<br>—_> tr = ———_ tf =<br>VDS<br>90% 90%<br>10% 10%<br>0<br>90%<br>VGS 50% 50%<br>PULSE WIDTH<br>10%<br>0<br>**----- End of picture text -----**<br>


**FIGURE 19. RESISTIVE SWITCHING WAVEFORMS** 

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VDD Qg(TOT)<br>-— [C—O] | |<br>N N VDS<br>N N VGS = 10V<br>N<br>|-—- N Qg(5) |<br>N<br>VGS N VGS = 5V<br>———- \ SN<br>VGS = 1V XN N\<br>0 Mee eee eee ee ee Ke<br>Qg(TH)<br>IG(REF)<br>0<br>**----- End of picture text -----**<br>


**FIGURE 21. GATE CHARGE WAVEFORMS** 

©2004 Fairchild Semiconductor Corporation 

RFD14N05L, RFD14N05LSM Rev. C0 

_**RFD14N05L, RFD14N05LSM**_ 

## _**PSPICE Electrical Model**_ 

.SUBCKT  RFP14N05L  2 1 3 ; rev 9/15/94 

CA  12  8  1.464e-9 CB  15  14  1.64e-9 CIN  6  8  6.17e-10 

DBODY  7  5  DBDMOD DBREAK  5 11  DBKMOD DPLCAP 10  5  DPLCAPMOD 

EBREAK  11  7  17  18  65.35 EDS  14  8  5  8  1 EGS  13  8  6  8  1 ESG  6  10  6  8  1 EVTO  20  6  18  8  1 

IT  8  17  1 

LDRAIN  2  5  1e-9 LGATE 1  9  5.68e-9 LSOURCE  3  7  5.35e-9 

MOS1  16  6  8  8  MOSMOD  M = 0.99 MOS2  16  21  8  8  MOSMOD  M = 0.01 

RBREAK  17  18  RBKMOD  1 RDRAIN  50  16  RDSMOD  33.1e-3 RGATE  9  20  5.85 RIN  6  8  1e9 RSCL1  5  51  RSCLMOD 1e-6 RSCL2  5  50  1e3 RSOURCE  8  7  RDSMOD  14.3e-3 RVTO  18  19  RVTOMOD  1 

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**----- Start of picture text -----**<br>
DPLCAP 5<br>DRAIN<br>10<br>LDRAIN 2<br>RSCL1<br>DBREAK<br>RSCL2 + 51<br>5<br>ESCL<br>51<br>50<br>11<br>6 RDRAIN + DBODY<br>ESG +8 16 EBREAK 1718<br>VTO<br>+<br>MOS2<br>EVTO 21<br>GATE<br>9 20 + 6<br>1 18 MOS1<br>LGATE RGATE 8<br>RIN CIN<br>RSOURCE LSOURCE<br>8 | 7 3<br>SOURCE<br>S1A S2A<br>12 13 14 15 RBREAK<br>17 18<br>8 13<br>S1B S2B<br>RVTO<br>13<br>CA CB 19<br>+ + 14 IT<br>VBAT<br>6 5<br>EGS 8 EDS 8 +<br>**----- End of picture text -----**<br>


S1A  6  12  13  8  S1AMOD S1B  13  12  13  8  S1BMOD S2A  6  15  14  13  S2AMOD S2B  13  15  14  13  S2BMOD 

VBAT  8  19  DC  1 VTO  21  6   0.485 

ESCL  51 50  VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/46,7))} 

.MODEL DBDMOD D (IS = 2.23e-13 RS = 1.15e-2 TRS1 = 1.64e-3 TRS2 = 7.89e-6 CJO = 6.83e-10 TT = 3.68e-8) .MODEL DBKMOD D (RS = 3.8e-1 TRS1 = 1.89e-3 TRS2 = 1.13e-5) .MODEL DPLCAPMOD D (CJO = 25.7e-11 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 1.935 KP = 18.89 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 7.18e-4 TC2 = 1.53e-6) .MODEL RDSMOD RES (TC1 = 4.45e-3 TC2 = 2.9e-5) .MODEL RSCLMOD RES (TC1 = 2.8e-3  TC2 = 6.0e-6) .MODEL RVTOMOD RES (TC1 = -1.7e-3 TC2 = -2.0e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.55 VOFF= -1.55) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.55 VOFF= -3.55) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.55 VOFF= 2.45) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.45 VOFF= -2.55) 

.ENDS 

NOTE: For  further discussion of  the PSPICE model, consult **A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options** ; authored by William J. Hepp and C. Frank Wheatley. 

©2004 Fairchild Semiconductor Corporation 

RFD14N05L, RFD14N05LSM Rev. C0 

_**RFD14N05L, RFD14N05LSM**_ 

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