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PSMN8R3-40YS,115
Power MOSFET, N Channel, 40 V, 70 A, 6600 µohm, SOT-669, Surface Mount
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- Manufacturer: NEXPERIA
- Product type: Single MOSFETs
- Transistor Polarity:N Channel; Continuous Drain Current Id:70A; Drain Source Voltage Vds:40V; On Resistance Rds(on):0.0066ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:3V; Power
- MSL: MSL 1 - Unlimited
- SVHC: Lead (25-Jun-2025)
- No. of Pins: 4Pins
- Channel Type: N Channel
- Product Range: -
- Qualification: -
- Power Dissipation: 74W
- Transistor Mounting: Surface Mount
- Rds(on) Test Voltage: 10V
- Transistor Case Style: SOT-669
- Drain Source Voltage Vds: 40V
- Operating Temperature Max: 175°C
- Continuous Drain Current Id: 70A
- Drain Source On State Resistance: 6600µohm
- Gate Source Threshold Voltage Max: 3V
| Delivery and price | |
|---|---|
| Units per pack | 5000 |
| Price | 0.326 € |
| Current stock | 1000+ |
| Lead time | 30 days |
Datasheet
## **PSMN8R3-40YS** **N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET** **Rev. 01 — 25 June 2009** **Product data sheet** ## **1. Product profile** ## **1.1 General description** Standard level N-channel MOSFET in LFPAK package qualified to 175 °C. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. ## **1.2 Features and benefits** - Advanced TrenchMOS provides low RDSon and low gate charge - High efficiency gains in switching power converters - Improved mechanical and thermal characteristics - LFPAK provides maximum power density in a Power SO8 package ## **1.3 Applications** - DC-to-DC convertors - Lithium-ion battery protection - Motor control - Server power supplies - Load switching ## **1.4 Quick reference data** |**Quick reference data**|| |---|---| |**Table 1.**<br>**Quick reference**|| |**Symbol**<br>**Parameter**<br>**Conditions**|**Min**<br>**Typ**<br>**Max**<br>**Unit**| |VDS<br>drain-source voltage<br>Tj≥25 °C; Tj≤175 °C|-<br>-<br>40<br>V| |ID<br>drain current<br>Tmb= 25 °C; VGS= 10 V;<br>seeFigure 1|-<br>-<br>70<br>A| |Ptot<br>total power<br>dissipation<br>Tmb= 25 °C; see Figure 2|-<br>-<br>74<br>W| |Tj<br>junction temperature|-55<br>-<br>175<br>°C| |**Avalanche ruggedness**|| |EDS(AL)S<br>non-repetitive<br>drain-source<br>avalanche energy<br>VGS= 10 V; Tj(init)= 25 °C;<br>ID= 62 A; Vsup≤40 V;<br>unclamped; RGS= 50 Ω|-<br>-<br>33<br>mJ| |**Dynamic characteristics**|| |QGD<br>gate-drain charge<br>VGS= 10 V; ID= 25 A;<br>VDS= 20 V; seeFigure 14<br>;<br>seeFigure 15<br>QG(tot)<br>total gate charge|-<br>4.5<br>-<br>nC| ||-<br>20<br>-<br>nC| **==> picture [81 x 42] intentionally omitted <==** **PSMN8R3-40YS** **NXP Semiconductors** **N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET** **Table 1. Quick reference** _…continued_ |**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---|---| |**Static characteristics**|||||||| |RDSon|drain-source|VGS= 10 V; ID= 15 A;||-|-|11.6|mΩ| ||on-state resistance|Tj= 100 °C; see Figure 12|||||| |||VGS= 10 V; ID= 15 A;||-|6.6|8.6|mΩ| |||Tj= 25 °C; seeFigure 12<br>;|||||| |||seeFigure 13|||||| ## **2. Pinning information** ## **Table 2. Pinning information** |**Pin**|**Symbol**|**Description**|**Simplified outline**|**Simplified outline**|**Simplified outline**|**Graphic symbol**|**Graphic symbol**|**Graphic symbol**|**Graphic symbol**|| |---|---|---|---|---|---|---|---|---|---|---| |1|S|source||||||||| |2|S|source||mb||||D||| |3|S|source||||||||| |||||||G||||| |4|G|gate||||||||| |mb|D|drain||||_mbb076_||S||| ||||1|2<br>3|4|||||| ||||**SOT669**|||||||| ||||**(LFPAK)**|||||||| ## **3. Ordering information** ## **Table 3. Ordering information** |**Type number**|**Package**| |---|---| ||**Name**<br>**Description**<br>**Version**| |PSMN8R3-40YS|LFPAK<br>plastic single-ended surface-mounted package (LFPAK); 4 leads<br>SOT669| © NXP B.V. 2009. All rights reserved. PSMN8R3-40YS_1 **Product data sheet** **Rev. 01 — 25 June 2009** **2 of 13** **PSMN8R3-40YS** **NXP Semiconductors** **N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET** ## **4. Limiting values** **Table 4. Limiting values** _In accordance with the Absolute Maximum Rating System (IEC 60134)._ |**Symbol**|**Parameter**|**Conditions**|**Min**|**Max**|**Unit**| |---|---|---|---|---|---| |VDS|drain-source voltage|Tj≥25 °C; Tj≤175 °C|-|40|V| |VDGR|drain-gate voltage|Tj≥25 °C; Tj≤175 °C; RGS= 20 kΩ|-|40|V| |VGS|gate-source voltage||-20|20|V| |ID|drain current|VGS= 10 V; Tmb= 100 °C; seeFigure 1|-|50|A| |||VGS= 10 V; Tmb= 25 °C; seeFigure 1|-|70|A| |IDM|peak drain current|tp≤10 µs; pulsed; Tmb= 25 °C; seeFigure 3|-|274|A| |Ptot|total power dissipation|Tmb= 25 °C; seeFigure 2|-|74|W| ||||||| |Tstg|storage temperature||-55|175|°C| |Tj|junction temperature||-55|175|°C| |Tsld(M)|peak soldering||-|260|°C| ||temperature||||| |**Source-drain diode**|||||| |IS|source current|Tmb= 25 °C|-|70|A| |ISM|peak source current|tp≤10 µs; pulsed; Tmb= 25 °C|-|274|A| |**Avalanche**|**ruggedness**||||| |EDS(AL)S|non-repetitive|VGS= 10 V; Tj(init)= 25 °C; ID= 62 A; Vsup≤40 V;|-|33|mJ| ||drain-source avalanche|unclamped; RGS= 50 Ω|||| ||energy||||| **==> picture [235 x 237] intentionally omitted <==** **----- Start of picture text -----**<br> 003aad264<br>80<br>ID<br>(A)<br>60<br>40<br>20<br>0<br>0 50 100 150 200<br>Tmb (°C)<br>Fig 1. Continuous drain current as a function of<br>mounting base temperature<br>**----- End of picture text -----**<br> **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 03aa16<br>120<br>Pder<br>(%)<br>80<br>40<br>0<br>0 50 100 150 200<br>Tmb (°C)<br>**----- End of picture text -----**<br> **Fig 2. Normalized total power dissipation as a function of mounting base temperature** © NXP B.V. 2009. All rights reserved. PSMN8R3-40YS_1 **Product data sheet** **Rev. 01 — 25 June 2009** **3 of 13** **PSMN8R3-40YS** **NXP Semiconductors** **N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET** **==> picture [481 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aad320<br> 10 [3]<br>ID<br>10μ s<br>(A) Limit RDSon = VDS / ID<br> 10 [2]<br>100μ s<br> 10<br>1ms<br> 1 DC<br>10ms<br>100ms<br>10 [-1]<br>10 [-1] 1 10 VDS (V) 10 [2]<br>**----- End of picture text -----**<br> **Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage** ## **5. Thermal characteristics** ## **Table 5. Thermal characteristics** **==> picture [498 x 285] intentionally omitted <==** **----- Start of picture text -----**<br> Symbol Parameter Conditions Min Typ Max Unit<br>Rth(j-mb) thermal resistance from see Figure 4 - 1.39 2 K/W<br>junction to mounting<br>base<br>003aac558<br> 10<br>Zth(j-mb)<br> (K/W)<br> 1<br>δ = 0.5<br>0.2<br>0.1<br>P δ = tp<br>10 [-1] 0.05 T<br>0.02<br>single shot tp t<br>T<br>10 [-2]<br>10 [-6] 10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] tp (s) 1<br>Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration<br>**----- End of picture text -----**<br> © NXP B.V. 2009. All rights reserved. PSMN8R3-40YS_1 **Product data sheet** **Rev. 01 — 25 June 2009** **4 of 13** **PSMN8R3-40YS** **NXP Semiconductors** **N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET** ## **6. Characteristics** |**Table 6.**<br>**Characteristics**||| |---|---|---| |**Symbol**<br>**Parameter**|**Conditions**|**Min**<br>**Typ**<br>**Max**<br>**Unit**| |**Static characteristics**||| |V(BR)DSS<br>drain-source<br>breakdown voltage|ID= 250 µA; VGS= 0 V; Tj= -55 °C|36<br>-<br>-<br>V| ||ID= 250 µA; VGS= 0 V; Tj= 25 °C|40<br>-<br>-<br>V| |VGS(th)<br>gate-source threshold<br>voltage|ID= 1 mA; VDS= VGS; Tj= -55 °C;<br>seeFigure 10<br>;see Figure 11|-<br>-<br>4.6<br>V| ||ID= 1 mA; VDS= VGS; Tj= 175 °C;<br>seeFigure 10<br>;see Figure 11|1<br>-<br>-<br>V| ||ID= 1 mA; VDS= VGS; Tj= 25 °C;<br>seeFigure 10<br>;see Figure 11|2<br>3<br>4<br>V| |IDSS<br>drain leakage current|VDS= 40 V; VGS= 0 V; Tj= 25 °C|-<br>-<br>1.5<br>µA| ||VDS= 40 V; VGS= 0 V; Tj= 125 °C|-<br>-<br>10<br>µA| |IGSS<br>gate leakage current|VGS= 20 V; VDS= 0 V; Tj= 25 °C|-<br>-<br>100<br>nA| ||VGS= -20 V; VDS= 0 V; Tj= 25 °C|-<br>-<br>100<br>nA| |RDSon<br>drain-source on-state<br>resistance|VGS= 10 V; ID= 15 A; Tj= 100 °C;<br>seeFigure 12|-<br>-<br>11.6<br>mΩ| ||VGS= 10 V; ID= 15 A; Tj= 175 °C;<br>seeFigure 12|-<br>-<br>16<br>mΩ| ||VGS= 10 V; ID= 15 A; Tj= 25 °C;<br>seeFigure 12<br>;see Figure 13|-<br>6.6<br>8.6<br>mΩ| |RG<br>internal gate resistance<br>(AC)|f = 1 MHz|-<br>0.63<br>-<br>Ω| |**Dynamic characteristics**||| |QG(tot)<br>total gate charge|ID= 25 A; VDS= 20 V; VGS= 10 V;<br>seeFigure 14<br>;see Figure 15|-<br>20<br>-<br>nC| ||ID= 0 A; VDS= 0 V; VGS= 10 V|-<br>17<br>-<br>nC| |QGS<br>gate-source charge|ID= 25 A; VDS= 20 V; VGS= 10 V;<br>seeFigure 14<br>;see Figure 15|-<br>8<br>-<br>nC| |QGS(th)<br>pre-threshold<br>gate-source charge||-<br>4<br>-<br>nC| |QGS(th-pl)<br>post-threshold<br>gate-source charge||-<br>4<br>-<br>nC| |QGD<br>gate-drain charge||-<br>4.5<br>-<br>nC| |VGS(pl)<br>gate-source plateau<br>voltage|ID= 25 A; VDS= 20 V; seeFigure 14<br>;<br>seeFigure 15|-<br>5.5<br>-<br>V| |Ciss<br>input capacitance|VDS= 20 V; VGS= 0 V; f = 1 MHz;<br>Tj= 25 °C; seeFigure 16|-<br>1215<br>-<br>pF| |Coss<br>output capacitance||-<br>270<br>-<br>pF| |Crss<br>reverse transfer<br>capacitance||-<br>146<br>-<br>pF| |td(on)<br>turn-on delay time|VDS= 30 V; RL= 1.5 Ω; VGS= 10 V;<br>RG(ext)= 4.7 Ω|-<br>13<br>-<br>ns| |tr<br>rise time||-<br>11<br>-<br>ns| |td(off)<br>turn-off delay time||-<br>21<br>-<br>ns| |tf<br>fall time||-<br>6<br>-<br>ns| © NXP B.V. 2009. All rights reserved. PSMN8R3-40YS_1 **Product data sheet** **Rev. 01 — 25 June 2009** **5 of 13** **PSMN8R3-40YS** **NXP Semiconductors** **N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET** **Table 6. Characteristics** _…continued_ |**Symbol**<br>**Parameter**<br>**Conditions**|**Min**<br>**Typ**<br>**Max**<br>**Unit**| |---|---| |**Source-drain diode**|| |VSD<br>source-drain voltage<br>IS= 25 A; VGS= 0 V; Tj= 25 °C;<br>seeFigure 17|-<br>0.84<br>1.2<br>V| |trr<br>reverse recovery time<br>IS= 50 A; dIS/dt = -100 A/µs; VGS= 0 V;<br>VDS= 20 V<br>Qr<br>recovered charge|-<br>29<br>-<br>ns<br>-<br>26<br>-<br>nC| [1] Tested to JEDEC standards where applicable. **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aad163<br>80<br>ID<br>(A) 20 10<br>8<br>7 6.5<br>60<br>6<br>40<br>5.5<br>20 5<br>VGS (V) = 4.5<br>0<br>0 1 2 3 4<br>VDS (V)<br>**----- End of picture text -----**<br> **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aad165<br>70<br>ID<br>(A)<br>60<br>50<br>40<br>30<br>20 Tj = 175 °C Tj = 25 °C<br>10<br>0<br>0 3 6 9<br>VGS (V)<br>**----- End of picture text -----**<br> **Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values** **Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aad171<br>40<br>RDSon<br>(mΩ)<br>30<br>20<br>10<br>0<br>0 5 10 15 20<br>VGS (V)<br>**----- End of picture text -----**<br> **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aad170<br>40<br>gfs<br>(S)<br>30<br>20<br>10<br>0<br>0 20 40 60<br>ID (A)<br>**----- End of picture text -----**<br> **Fig 7. Drain-source on-state resistance as a function of gate-source voltage; typical values** **Fig 8. Forward transconductance as a function of drain current; typical values** © NXP B.V. 2009. All rights reserved. PSMN8R3-40YS_1 **Product data sheet** **Rev. 01 — 25 June 2009** **6 of 13** **PSMN8R3-40YS** **NXP Semiconductors** **N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET** **==> picture [498 x 442] intentionally omitted <==** **----- Start of picture text -----**<br> 003aad169 03aa35<br>1800 10 [−][1]<br>C Ciss ID<br>(A)<br>(pF) min typ max<br>10 [−][2]<br>1500<br>10 [−][3]<br>1200<br>10 [−][4]<br>Crss<br>900<br>10 [−][5]<br>600 10 [−][6]<br>0 3 6 9 12 0 2 4 6<br>VGS (V) VGS (V)<br>Fig 9. Input and reverse transfer capacitances as a Fig 10. Sub-threshold drain current as a function of<br>function of gate-source voltage; typical values gate-source voltage<br>003aad280 03aa27<br>5 2<br>VGS(th)<br>(V) a<br>4<br>max<br>1.5<br>3<br>typ<br>1<br>2 min<br>0.5<br>1<br>0 0<br>−60 0 60 120 Tj (°C) 180 −60 0 60 120 Tj (°C) 180<br>**----- End of picture text -----**<br> **Fig 11. Gate-source threshold voltage as a function of junction temperature** **Fig 12. Normalized drain-source on-state resistance factor as a function of junction temperature** © NXP B.V. 2009. All rights reserved. PSMN8R3-40YS_1 **Product data sheet** **Rev. 01 — 25 June 2009** **7 of 13** **PSMN8R3-40YS** **NXP Semiconductors** **N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aad164<br>20<br>VGS (V) = 6 6.5<br>RDSon<br>(mΩ)<br>15<br>7<br>7.5<br>10<br>8<br>10<br>20<br>5<br>0 20 40 60<br>ID (A)<br>**----- End of picture text -----**<br> **==> picture [161 x 160] intentionally omitted <==** **----- Start of picture text -----**<br> VDS<br>ID<br>VGS(pl)<br>VGS(th)<br>VGS<br>QGS1 QGS2<br>QGS QGD<br>QG(tot)<br>003aaa508<br>**----- End of picture text -----**<br> **Fig 14. Gate charge waveform definitions** **Fig 13. Drain-source on-state resistance as a function of drain current; typical values** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aad167<br>10<br>VGS<br>(V)<br>8<br>32V<br>VDS = 20V<br>8V<br>6<br>4<br>2<br>0<br>0 5 10 15 20 25<br>QG (nC)<br>**----- End of picture text -----**<br> **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aad168<br> 10 [4]<br>C<br>(pF)<br>Ciss<br> 10 [3]<br>Coss<br>Crss<br> 10 [2]<br>10 [-1] 1 10 10 [2]<br>VDS (V)<br>**----- End of picture text -----**<br> **Fig 15. Gate-source voltage as a function of gate charge; typical values** **Fig 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values** © NXP B.V. 2009. All rights reserved. PSMN8R3-40YS_1 **Product data sheet** **Rev. 01 — 25 June 2009** **8 of 13** **PSMN8R3-40YS** **NXP Semiconductors** **N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aad166<br>100<br>IS<br>(A)<br>80<br>60<br>40<br>Tj = 175 °C<br>20 Tj = 25 °C<br>0<br>0 0.3 0.6 0.9 1.2<br>VSD (V)<br>**----- End of picture text -----**<br> **Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values** © NXP B.V. 2009. All rights reserved. PSMN8R3-40YS_1 **Product data sheet** **Rev. 01 — 25 June 2009** **9 of 13** **PSMN8R3-40YS** **NXP Semiconductors** **N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET** ## **7. Package outline** ## **Plastic single-ended surface-mounted package (LFPAK); 4 leads** **==> picture [35 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> SOT669<br>**----- End of picture text -----**<br> **==> picture [478 x 570] intentionally omitted <==** **----- Start of picture text -----**<br> A2<br>E A C<br>b2 c2 E1<br>L1 b3<br>mounting<br>base b4<br>D1<br>H D<br>L2<br>1 2 3 4<br>X<br>e b w M A c<br>1/2 e<br>A (A )3<br>A1 C<br>θ<br>L<br>detail X<br>y C<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT A A1 A2 A3 b b2 b3 b4 c c2 D [(1)] D1max [(1)] E [(1)] E1(1) e H L L1 L2 w y θ<br>1.20 0.15 1.10 0.50 4.41 2.2 0.9 0.25 0.30 4.10 5.0 3.3 6.2 0.85 1.3 1.3 8°<br>mm 1.01 0.00 0.95 0.25 0.35 3.62 2.0 0.7 0.19 0.24 3.80 4.20 4.8 3.1 1.27 5.8 0.40 0.8 0.8 0.25 0.1 0°<br>Note<br>1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>04-10-13<br>SOT669 MO-235<br>06-03-16<br>**----- End of picture text -----**<br> ## **Fig 18. Package outline SOT669 (LFPAK)** © NXP B.V. 2009. All rights reserved. PSMN8R3-40YS_1 **Product data sheet** **Rev. 01 — 25 June 2009** **10 of 13** **PSMN8R3-40YS** **NXP Semiconductors** **N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET** ## **8. Revision history** |**Table 7.**|**Revision**|**history**|||| |---|---|---|---|---|---| |**Document**|**ID**|**Release date**|**Data sheet status**|**Change notice**|**Supersedes**| |PSMN8R3-40YS_1||20090625|Product data sheet|-|-| © NXP B.V. 2009. All rights reserved. PSMN8R3-40YS_1 **Product data sheet** **Rev. 01 — 25 June 2009** **11 of 13** **PSMN8R3-40YS** **NXP Semiconductors** **N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET** ## **9. Legal information** ## **9.1 Data sheet status** |**Document status** **[1]**<br>**[2]**|**Product status[3]**|**Definition**| |---|---|---| |Objective [short] data sheet|Development|This document contains data from the objective specification for product development.| |Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.| |Product [short] data sheet|Production|This document contains the product specification.| - [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. ## **9.2 Definitions** **Draft** — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet** — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. ## **9.3 Disclaimers** **General** — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. **Right to make changes** — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **Suitability for use** — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. **Applications** — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. **Quick reference data** — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. **Limiting values** — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. **Terms and conditions of sale** — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. **No offer to sell or license** — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. **Export control** — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. ## **9.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. **TrenchMOS** — is a trademark of NXP B.V. ## **10. Contact information** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com © NXP B.V. 2009. All rights reserved. PSMN8R3-40YS_1 **Product data sheet** **Rev. 01 — 25 June 2009** **12 of 13** **PSMN8R3-40YS** **NXP Semiconductors** **N-channel LFPAK 40 V 8.6 mΩ standard level MOSFET** ## **11. Contents** |**1**|**Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1**| |---|---| |1.1|General description . . . . . . . . . . . . . . . . . . . . . .1| |1.2|Features and benefits. . . . . . . . . . . . . . . . . . . . .1| |1.3|Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1| |1.4|Quick reference data . . . . . . . . . . . . . . . . . . . . .1| |**2**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . .2**| |**3**|**Ordering information. . . . . . . . . . . . . . . . . . . . . .2**| |**4**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3**| |**5**|**Thermal characteristics . . . . . . . . . . . . . . . . . . .4**| |**6**|**Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5**| |**7**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10**| |**8**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11**| |**9**|**Legal information. . . . . . . . . . . . . . . . . . . . . . . .12**| |9.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12| |9.2|Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12| |9.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12| |9.4|Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12| |**10**|**Contact information. . . . . . . . . . . . . . . . . . . . . .12**| Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. **==> picture [84 x 52] intentionally omitted <==** **© NXP B.V. 2009.** **All rights reserved.** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 25 June 2009 Document identifier: PSMN8R3-40YS_1**
Updated at April 29, 2026
Nexperia is a dedicated global leader in discretes, logic, and MOSFET devices. Built on over half a century of semiconductor expertise and operating independently since 2017, the company produces consistently reliable components at an exceptional volume of 85 billion units annually. With its own manufacturing facilities, Nexperia delivers industry-leading small packages that combine power and thermal efficiency with best-in-class quality, meeting the rigorous standards of the automotive sector. Our extensive Nexperia portfolio is heavily focused on discrete semiconductors, providing engineers with a robust selection of core building blocks. This includes a comprehensive range of diodes and rectifiers, featuring a vast selection of Zener single diodes and Schottky diodes designed for precise voltage regulation and efficient power routing. Additionally, we offer an expansive array of bipolar transistors and single MOSFETs tailored for reliable switching and amplification in demanding applications. Beyond these primary offerings, the lineup extends into specialized circuit protection and passive components. This includes transient voltage suppressor (TVS) diodes, Zener array diodes, and small signal diodes, alongside dual MOSFETs and fast recovery rectifiers. For comprehensive design needs, the selection also encompasses integrated passive filters, common mode chokes, and precision timers and oscillators, ensuring a complete solution for high-performance electronic systems.
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