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PSMN2R8-25MLC,115
Power MOSFET, N Channel, 25 V, 70 A, 2450 µohm, SC-100, Surface Mount
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- Manufacturer: NEXPERIA
- Product type: Single MOSFETs
- Transistor Polarity:N Channel; Continuous Drain Current Id:70A; Drain Source Voltage Vds:25V; On Resistance Rds(on):0.00245ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:1.74V;
- MSL: MSL 1 - Unlimited
- SVHC: Lead (25-Jun-2025)
- No. of Pins: 4Pins
- Channel Type: N Channel
- Product Range: -
- Qualification: -
- Power Dissipation: 88W
- Transistor Mounting: Surface Mount
- Rds(on) Test Voltage: 10V
- Transistor Case Style: SC-100
- Drain Source Voltage Vds: 25V
- Operating Temperature Max: 175°C
- Continuous Drain Current Id: 70A
- Drain Source On State Resistance: 2450µohm
- Gate Source Threshold Voltage Max: 1.74V
| Delivery and price | |
|---|---|
| Units per pack | 5000 |
| Price | 0.36 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
**==> picture [56 x 40] intentionally omitted <==** **----- Start of picture text -----**<br> - wu<br>LFPAK33<br>**----- End of picture text -----**<br> ## **PSMN2R8-25MLC** **N-channel 25 V 2.8 mΩ logic level MOSFET in LFPAK33 using NextPower Technology** **Rev. 3 — 15 June 2012** **Product data sheet** ## **1. Product profile** ## **1.1 General description** Logic level enhancement mode N-channel MOSFET in LFPAK33 package. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. ## **1.2 Features and benefits** - Low parasitic inductance and resistance - Optimised for 4.5V Gate drive utilising NextPower Superjunction technology - Ultra low QG, QGD, & QOSS for high system efficiencies at low and high loads ## **1.3 Applications** - DC-to-DC converters - Synchronous buck regulator - Load switching ## **1.4 Quick reference data** ## **Table 1. Quick reference data** |**Symbol**|**Parameter**|**Conditions**|||**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---|---|---| |VDS|drain-source voltage|Tj= 25°C|||-|-|25|V| |ID|drain current|Tmb= 25 °C; VGS= 10 V; seeFigure 1||[1]|-|-|70|A| |Ptot|total power dissipation|Tmb= 25 °C; seeFigure 2|||-|-|88|W| |Tj|junction temperature||||-55|-|175|°C| |**Static characteristics**||||||||| |RDSon|drain-source on-state|VGS= 4.5 V; ID= 25 A; Tj= 25 °C;|||-|3.25|3.75|mΩ| ||resistance|seeFigure 10||||||| |||||||||| |||VGS= 10 V; ID= 25 A; Tj= 25 °C;|||-|2.45|2.8|mΩ| |||seeFigure 10||||||| |||||||||| |**Dynamic characteristics**|**Dynamic characteristics**|||||||| |QGD|gate-drain charge|VGS= 4.5 V; ID= 25 A; VDS= 12.5 V;|||-|3.9|-|nC| |||seeFigure 12<br>;see Figure 13||||||| |||||||||| |QG(tot)|total gate charge|VGS= 4.5 V; ID= 25 A; VDS= 12.5 V;|||-|16.3|-|nC| |||seeFigure 12<br>;see Figure 13||||||| [1] Continuous current is limited by package. **PSMN2R8-25MLC** **NXP Semiconductors** **N-channel 25 V 2.8 mΩ logic level MOSFET in LFPAK33 using NextPower Technology** ## **2. Pinning information** ## **Table 2. Pinning information** |**Pin**|**Symbol**|**Description**|**Simplified outline**|**Simplified outline**|**Simplified outline**|**Simplified outline**|**Simplified outline**|**Simplified outline**|**Simplified outline**|**Simplified outline**|**Simplified outline**||||**Graphic symbol**||||| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |1|S|source|||||||||||||||||| |2|S|source|||||||||||||||D||| |3|S|source|||||||||||||||||| ||||||||||||||||G||||| |4|G|gate|||||||||||||||||| |mb|D|mounting base; connected to|||||||||||||_mbb076_||S||| |||drain|||||||||||||||||| ||||||1||2||3|||4|||||||| ||||**SOT1210**|||||**(LFPAK33)**|||||||||||| ## **3. Ordering information** ## **Table 3. Ordering information** |**Type number**|**Package**| |---|---| ||**Name**<br>**Description**<br>**Version**| |PSMN2R8-25MLC|LFPAK33<br>Plastic single ended surface mounted package (LFPAK33);<br>4 leads<br>SOT1210| ## **4. Limiting values** **Table 4. Limiting values** _In accordance with the Absolute Maximum Rating System (IEC 60134)._ |**Symbol**|**Parameter**|**Conditions**||**Min**|**Max**|**Unit**| |---|---|---|---|---|---|---| |VDS|drain-source voltage|Tj= 25°C||-|25|V| |VGS|gate-source voltage|||-20|20|V| |ID|drain current|VGS= 10 V; Tmb= 25 °C; seeFigure 1|[1]|-|70|A| |||VGS= 10 V; Tmb= 100 °C; seeFigure 1|[1]|-|70|A| |IDM|peak drain current|pulsed; tp≤10 µs; Tmb= 25 °C;||-|536|A| |||seeFigure 4||||| |Ptot|total power dissipation|Tmb= 25 °C; seeFigure 2||-|88|W| |||||||| |Tstg|storage temperature|||-55|175|°C| |Tj|junction temperature|||-55|175|°C| |Tsld(M)|peak soldering temperature|||-|260|°C| |VESD|electrostatic discharge voltage|MM (JEDEC JESD22-A115)||350|-|V| |**Source-drain**|**diode**|||||| |IS|source current|Tmb= 25 °C|[1]|-|70|A| |ISM|peak source current|pulsed; tp≤10 µs; Tmb= 25 °C||-|536|A| |**Avalanche ruggedness**||||||| |EDS(AL)S|non-repetitive drain-source|VGS= 10 V; Tj(init)= 25 °C; ID= 70 A;||-|77|mJ| ||avalanche energy|Vsup≤25 V; RGS= 50 Ω; unclamped;||||| |||seeFigure 3||||| All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. [1] Continuous current is limited by package. PSMN2R8-25MLC **Product data sheet** **Rev. 3 — 15 June 2012** **2 of 14** **PSMN2R8-25MLC** ## **NXP Semiconductors** **N-channel 25 V 2.8 mΩ logic level MOSFET in LFPAK33 using NextPower Technology** **==> picture [431 x 456] intentionally omitted <==** **----- Start of picture text -----**<br> 003aaj762 03na19<br>150 120<br>ID<br>(A) Pee) Pder oe<br>120 PIN (%)<br>2 | PE tT<br>80<br>90 HEEeaee| EXGEEEaE\<br>Pt} [PIN] NCOE LING EET<br>(1)<br>60<br>40<br>ANSPt | te | KT EERE.<br>30<br>PPP rar BEREAN<br>0 ptt} | | ty 0 \<br>0 CEEEECHE 50 100 150 200 0 Ty 50 ELEN 100 150 200<br>Tmb ( ° C) Tmb ( ° C)<br>Vay>10V P<br>(1) Capped #70 A due to package. Paer= Pare acces<br>Continuous drain current as a function of Fig 2. Normalized total power dissipation as a<br>mounting base temperature function of mounting base temperature<br>003aaj763<br> 10 [2]<br>SOCi<br>IAL<br>SS<br>(A) LOTTI TNNUITENS ETT<br>NN<br>(1)<br> 10 PLUMEAUIE ATUTTI EHIME NUNN PST TNE THT NAT<br>ert<br>EEE=r CII“St (2) NS<br>| |<br> 1 BIN<br>10 [-3] 10 [-2] 10 [-1] A 1 10<br>tAL (ms)<br>**----- End of picture text -----**<br> **Fig 1. Continuous drain current as a function of Fig 2. Normalized total power dissipation as a mounting base temperature function of mounting base temperature** **Fig 3. Single pulse avalanche rating; avalanche current as a function of avalanche time** © NXP B.V. 2012. All rights reserved. PSMN2R8-25MLC All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 3 — 15 June 2012** **3 of 14** **PSMN2R8-25MLC** ## **NXP Semiconductors** **N-channel 25 V 2.8 mΩ logic level MOSFET in LFPAK33 using NextPower Technology** **==> picture [480 x 565] intentionally omitted <==** **----- Start of picture text -----**<br> 003aaj764<br> 10 [3]<br>(A)ID oS SS<br>Limit R DSon = V DS / I D<br>tp =10 μ s<br> 10 [2] erei <5 ss<br>100 μ s<br>[SOE a<br>ee ee ee ee eee<br> 10 Ss!<br>DC 1 ms<br>—— a ee ee ee<br>po eS 10 ms [ | ttt<br> 1 a a 100 ms<br>poee TTseee<br>10 [-1] PoE ET TE [EET]<br>10 [-1] 1 10 10 [2]<br>VDS (V)<br>Typ =25°C. Ipy is asingle pulse<br>Fig 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage<br>5. Thermal characteristics<br>Table 5. Thermal characteristics<br>Symbol Parameter Conditions Min Typ Max Unit<br>Rth(j-mb) thermal resistance from see Figure 5 - 1.49 1.7 K/W<br>junction to mounting base<br>003aaj765<br> 10<br>Z<br>th(j-mb) pot UT ETTTTPTT<br> (K/W) Mt Ht HH<br> 1 δ = 0.5<br>aSe ee<br>0.2 SSS<br>0.1 ea ann ee ee ee<br>10 [-1] 0.05 er<br>SSS<br>0.02 [oy ee | Py ye P δ = t p |<br>PE —H T<br>10 [-2]<br>petas single shot TT |:<br>EH<br>t p t<br>10 [-3] pteeTt PTT TTee eee“Led T ll<br>10 [-6] 10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] tp (s) 1<br>Fig 5. Transient thermal impedance from junction to mounting base as a function of pulse duration<br>**----- End of picture text -----**<br> ## **5. Thermal characteristics** **Table 5. Thermal characteristics** © NXP B.V. 2012. All rights reserved. PSMN2R8-25MLC All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 3 — 15 June 2012** **4 of 14** **PSMN2R8-25MLC** **NXP Semiconductors** **N-channel 25 V 2.8 mΩ logic level MOSFET in LFPAK33 using NextPower Technology** ## **6. Characteristics** |**Table 6.**<br>**Characteristics**||| |---|---|---| |**Symbol**<br>**Parameter**|**Conditions**|**Min**<br>**Typ**<br>**Max**<br>**Unit**| |**Static characteristics**||| |V(BR)DSS<br>drain-source<br>breakdown voltage|ID= 250 µA; VGS= 0 V; Tj= 25 °C|25<br>-<br>-<br>V| ||ID= 250 µA; VGS= 0 V; Tj= -55 °C|22.5<br>-<br>-<br>V| |VGS(th)<br>gate-source threshold<br>voltage|ID= 1 mA; VDS= VGS; Tj= 25 °C|1.45<br>1.74<br>2.15<br>V| |∆VGS(th)/∆T<br>gate-source threshold<br>voltage variation with<br>temperature||-<br>-4.2<br>-<br>mV/K| |IDSS<br>drain leakage current|VDS= 25 V; VGS= 0 V; Tj= 25 °C|-<br>-<br>1<br>µA| ||VDS= 25 V; VGS= 0 V; Tj= 150 °C|-<br>-<br>100<br>µA| |IGSS<br>gate leakage current|VGS= 16 V; VDS= 0 V; Tj= 25 °C|-<br>-<br>100<br>nA| ||VGS= -16 V; VDS= 0 V; Tj= 25 °C|-<br>-<br>100<br>nA| |RDSon<br>drain-source on-state<br>resistance|VGS= 4.5 V; ID= 25 A; Tj= 25 °C;<br>seeFigure 10|-<br>3.25<br>3.75<br>mΩ| ||VGS= 4.5 V; ID= 25 A; Tj= 150 °C;<br>seeFigure 10<br>;see Figure 11|-<br>-<br>6<br>mΩ| ||VGS= 10 V; ID= 25 A; Tj= 25 °C;<br>seeFigure 10|-<br>2.45<br>2.8<br>mΩ| ||VGS= 10 V; ID= 25 A; Tj= 150 °C;<br>seeFigure 10<br>;see Figure 11|-<br>-<br>4.5<br>mΩ| |RG<br>gate resistance|f = 1 MHz|0.37<br>0.74<br>1.48<br>Ω| |**Dynamic characteristics**||| |QG(tot)<br>total gate charge|ID= 25 A; VDS= 12.5 V; VGS= 10 V;<br>seeFigure 12<br>;see Figure 13|-<br>37.7<br>-<br>nC| ||<br>|| ||ID= 25 A; VDS= 12.5 V; VGS= 4.5 V;<br>seeFigure 12<br>;see Figure 13|-<br>16.3<br>-<br>nC| ||ID= 0 A; VDS= 0 V; VGS= 10 V|-<br>36.7<br>-<br>nC| |QGS<br>gate-source charge|ID= 25 A; VDS= 12.5 V; VGS= 4.5 V;<br>seeFigure 12<br>;see Figure 13|-<br>6.5<br>-<br>nC| |QGS(th)<br>pre-threshold<br>gate-source charge||-<br>3.9<br>-<br>nC| |QGS(th-pl)<br>post-threshold<br>gate-source charge||-<br>2.6<br>-<br>nC| |QGD<br>gate-drain charge||-<br>3.9<br>-<br>nC| |VGS(pl)<br>gate-source plateau<br>voltage|ID= 25 A; VDS= 12.5 V; seeFigure 12<br>;<br>seeFigure 13|-<br>2.9<br>-<br>V| |Ciss<br>input capacitance|VDS= 12.5 V; VGS= 0 V; f = 1 MHz;<br>Tj= 25 °C; seeFigure 14|-<br>2432<br>-<br>pF| |Coss<br>output capacitance||-<br>533<br>-<br>pF| |Crss<br>reverse transfer<br>capacitance||-<br>198<br>-<br>pF| © NXP B.V. 2012. All rights reserved. PSMN2R8-25MLC All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 3 — 15 June 2012** **5 of 14** **PSMN2R8-25MLC** ## **NXP Semiconductors** **N-channel 25 V 2.8 mΩ logic level MOSFET in LFPAK33 using NextPower Technology** **Table 6. Characteristics** _…continued_ |**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---| |td(on)|turn-on delay time|VDS= 12.5 V; RL= 0.5 Ω; VGS= 4.5 V;|-|16.4|-|ns| |tr|rise time|RG(ext)= 5 Ω|-|24.6|-|ns| |td(off)|turn-off delay time||-|19.9|-|ns| |tf|fall time||-|13.1|-|ns| |Qoss|output charge|VGS= 0 V; VDS= 12.5 V; f = 1 MHz;|-|14.3|-|nC| |||Tj= 25 °C||||| |**Source-drain diode**|**Source-drain diode**|||||| |VSD|source-drain voltage|IS= 25 A; VGS= 0 V; Tj= 25 °C;|-|0.82|1.1|V| |||seeFigure 15||||| |trr|reverse recovery time|IS= 25 A; dIS/dt = -100 A/µs; VGS= 0 V;|-|21.3|-|ns| |Qr|recovered charge|VDS= 12.5 V|-|14.1|-|nC| |ta|reverse recovery rise|VGS= 0 V; IS= 25 A; dIS/dt = -100 A/µs;|-|12.1|-|ns| ||time|VDS= 12.5 V; seeFigure 16||||| |||||||| |tb|reverse recovery fall||-|9.2|-|ns| ||time|||||| **==> picture [484 x 241] intentionally omitted <==** **----- Start of picture text -----**<br> 003aaj766 003aaj767<br>75 20<br>(A)ID 10 4.5 3.5 RDSon<br>3 (m Ω )<br>60<br>15<br>[- TTLLa PTT, EEL<br>| SCE<br>45<br>WemV7 10 |ce<br>2.8<br>30 (=Anna 5 PTEPT TELLTTT<br>2.6<br>15<br>|/—-— aM<br>V GS (V) = 2.4<br>0 pa 0 CCPC<br>0 0.5 1 1.5 2 0 4 8 12 16<br>VDS (V) VGS (V)<br>Fig 6. Output characteristics; drain current as a Fig 7. Drain-source on-state resistance as a function<br>function of drain-source voltage; typical values of gate-source voltage; typical values<br>**----- End of picture text -----**<br> © NXP B.V. 2012. All rights reserved. PSMN2R8-25MLC All information provided in this document is subject to legal disclaimers. **Rev. 3 — 15 June 2012** **Product data sheet** **6 of 14** **PSMN2R8-25MLC** **NXP Semiconductors** **N-channel 25 V 2.8 mΩ logic level MOSFET in LFPAK33 using NextPower Technology** **==> picture [186 x 186] intentionally omitted <==** **----- Start of picture text -----**<br> 003aaj768<br>150<br>gfs<br>(S) P| | | ptt |<br>120 Pitti yee tT<br>Plizc || |<br>90 Pi 7] | Tt<br>PIA TT Tet<br>60 Py; | | Ty |<br>PAT | yt | Ty<br>30<br>fit | | yt tt<br>0 JiPiet}i ttty etey yy}ty<br>0 15 30 45 60 75<br>ID (A)<br>**----- End of picture text -----**<br> **==> picture [180 x 186] intentionally omitted <==** **----- Start of picture text -----**<br> 003aaj769<br>75<br>ID<br>(A) |] | | Tt yy |<br>60 Pt | | | ey<br>Pt | tT te |<br>45 P| Tt |ey<br>Pt | | |<br>30 P| | | |PT<br>Pt | | Ty |<br>15 Tj = 150 ° C<br>+) fA<br>Tj = 25 ° C<br>0 |YY | fo<br>0 1 2 3 4<br>VGS (V)<br>**----- End of picture text -----**<br> **Fig 8. Forward transconductance as a function of drain current; typical values** **Fig 9. Transfer characteristics; drain current as a function of gate-source voltage; typical values** **==> picture [435 x 187] intentionally omitted <==** **----- Start of picture text -----**<br> 003aaj772 003aaj773<br>20 2<br>2.8 3<br>RDSon a<br>(m Ω ) TOO Te CT 10V<br>15 COOP 1.5 CCE<br>V GS =4.5V<br>10 COOOL 1 Sanne 70p<br>aoAnne 408 eT<br>VT Cer ECC<br>5 CEPT 3.5 0.5 Seccco<br>4.5<br>—====—=== Cee eee<br>VGS (V) = 10<br>0 CEE 0 CEPT<br>0 15 30 45 60 75 -60 0 60 120 180<br>ID (A) Tj ( ° C)<br>**----- End of picture text -----**<br> **Fig 10. Drain-source on-state resistance as a function of drain current; typical values** **Fig 11. Normalized drain-source on-state resistance factor as a function of junction temperature** © NXP B.V. 2012. All rights reserved. PSMN2R8-25MLC All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 3 — 15 June 2012** **7 of 14** **PSMN2R8-25MLC** **NXP Semiconductors** **N-channel 25 V 2.8 mΩ logic level MOSFET in LFPAK33 using NextPower Technology** **==> picture [433 x 444] intentionally omitted <==** **----- Start of picture text -----**<br> 003aaj774<br>10<br>~-=--- VGS “TLLLIL ey<br>VDS (V)<br>— 8 Oe<br>ID<br>i\ Of<br>6 5 V<br>VGS(pl) 20 V<br>YE Of<br>ee NZ<br>VGS(th) 4<br>VDS = 12.5 V<br>VGS r an\ O NY<br>7 QGS1 QGS2 2 YT ELLL ee<br>QGS QGD ALLEL ELL<br>QG(tot)<br>0 ZELLELELEL,<br>003aaa508 0 10 20 30 40<br>QG (nC)<br>Gate charge waveform definitions Fig 13. Gate-source voltage as a function of gate<br>charge; typical values<br>003aaj775 003aaj776j776776<br> 10 [4] 80<br>ISS<br>C (A)<br>(pF)<br>60<br>Ciss<br>SST PTT<br> 10 [3] UNITS EEC 40 AAoToT L A T<br>Coss<br>20<br>Tj = 150j = 150 = 150 ° C Tj = 25 j = 25 = 25 ° C<br>HAE Crss SF<br> 10 [2] UL TUIML EINE 0 TLE DT DT<br>10 [-1] 1 10 10 [2] 0 0.3 0.6 0.9 1.2<br>VDS (V) VSD (V)SD (V) (V)<br>**----- End of picture text -----**<br> **Fig 12. Gate charge waveform definitions** **Fig 13. Gate-source voltage as a function of gate charge; typical values** **==> picture [181 x 186] intentionally omitted <==** **----- Start of picture text -----**<br> 003aaj776j776776<br>80<br>ISS<br>(A)<br>60 PTT<br>40 AAoToT L A T<br>20<br>Tj = 150j = 150 = 150 ° C Tj = 25 j = 25 = 25 ° C<br>SF<br>0 TLE DT DT<br>0 0.3 0.6 0.9 1.2<br>VSD (V)SD (V) (V)<br>**----- End of picture text -----**<br> **Fig 14. Input, output and reverse transfer capacitances Fig 15. Source current as a function of source-drain as a function of drain-source voltage; typical voltage; typical values values** © NXP B.V. 2012. All rights reserved. PSMN2R8-25MLC All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 3 — 15 June 2012** **8 of 14** **PSMN2R8-25MLC** ## **NXP Semiconductors** **N-channel 25 V 2.8 mΩ logic level MOSFET in LFPAK33 using NextPower Technology** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aaf 444<br>ID<br>(A)<br>trr<br>ta tb<br>0<br>0.25 IRM<br>IRM<br>t (s)<br>**----- End of picture text -----**<br> **Fig 16. Reverse recovery timing definition** © NXP B.V. 2012. All rights reserved. PSMN2R8-25MLC All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 3 — 15 June 2012** **9 of 14** **PSMN2R8-25MLC** **NXP Semiconductors** **N-channel 25 V 2.8 mΩ logic level MOSFET in LFPAK33 using NextPower Technology** ## **7. Package outline** **Plastic single ended surface mounted package (LFPAK33); 8 leads** **SOT1210** **==> picture [481 x 565] intentionally omitted <==** **----- Start of picture text -----**<br> E A A<br>e1<br>L b1 c1 E1<br>mounting<br>base<br>D1<br>D<br>H<br>1 4<br>e X<br>b w A<br>A1 C c<br>θ<br>Lp<br>y C<br>detail X<br>0 2.5 5 mm<br>scale<br>Dimensions<br>Unit [(1)] A A1 b b1 c c1 D [(1)] D1 E [(1)] E1 e e1 H L Lp w y θ<br>max 0.90 0.10 0.35 0.35 0.20 0.30 2.70 2.35 3.40 2.45 3.40 0.25 0.50 8 [°]<br>mm nom 0.65 0.65 0.20 0.10<br>min 0.80 0.00 0.25 0.25 0.10 0.20 2.50 1.90 3.20 2.00 3.20 0.13 0.30 0 [°]<br>Note<br>1. Plastic or metal protrusions of 0.15 mm per side are not included. sot1210_po<br>Outline References European Issue date<br>version IEC JEDEC JEITA projection<br>11-12-19<br>SOT1210<br>12-03-12<br>**----- End of picture text -----**<br> ## **Fig 17. Package outline SOT1210 (LFPAK33)** All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. PSMN2R8-25MLC **Product data sheet** **Rev. 3 — 15 June 2012** **10 of 14** **PSMN2R8-25MLC** **NXP Semiconductors** **N-channel 25 V 2.8 mΩ logic level MOSFET in LFPAK33 using NextPower Technology** ## **8. Revision history** |**Table 7.**<br>**Revision history**|**Table 7.**<br>**Revision history**|||| |---|---|---|---|---| |**Document ID**|**Release date**|**Data sheet status**|**Change notice**|**Supersedes**| |PSMN2R8-25MLC v.3|20120615|Product data sheet|-|PSMN2R8-25MLC v.2| |Modifications:|**•** Various changes to content.|||| |PSMN2R8-25MLC v.2|20120607|Product data sheet|-|PSMN2R8-25MLC v.1| © NXP B.V. 2012. All rights reserved. PSMN2R8-25MLC All information provided in this document is subject to legal disclaimers. **Rev. 3 — 15 June 2012** **Product data sheet** **11 of 14** **PSMN2R8-25MLC** **NXP Semiconductors** **N-channel 25 V 2.8 mΩ logic level MOSFET in LFPAK33 using NextPower Technology** ## **9. Legal information** ## **9.1 Data sheet status** |**Document statu**~~**s**~~**[1]**<br> **[2]**|**Product status[3]**|**Definition**| |---|---|---| |Objective [short] data sheet|Development|This document contains data from the objective specification for product development.| |Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.| |Product [short] data sheet|Production|This document contains the product specification.| [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URLhttp://www.nxp.com. ## **9.2 Definitions** **Right to make changes** — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **Preview** — The document is a preview version only. The document is still subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Suitability for use** — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. **Draft** — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet** — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. **Quick reference data** — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. **Applications** — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. **Product specification** — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. ## **9.3 Disclaimers** **Limited warranty and liability** — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. **Limiting values** — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors. © NXP B.V. 2012. All rights reserved. PSMN2R8-25MLC All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 3 — 15 June 2012** **12 of 14** **PSMN2R8-25MLC** ## **NXP Semiconductors** **N-channel 25 V 2.8 mΩ logic level MOSFET in LFPAK33 using NextPower Technology** **Terms and conditions of commercial sale** — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published athttp://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. **No offer to sell or license** — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. **Export control** — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. **Non-automotive qualified products** — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. **Translations** — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. ## **9.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. **Adelante** , **Bitport** , **Bitsound** , **CoolFlux** , **CoReUse** , **DESFire** , **EZ-HV** , **FabKey** , **G reenChip** , **HiPerSmart** , **HITAG** , **I²C-bus** logo, **ICODE** , **I-CODE** , **ITEC** , **Labelution** , **MIFARE** , **MIFARE Plus** , **MIFARE Ultralight** , **MoReUse** , **QLPAK** , **Silicon Tuner** , **SiliconMAX** , **SmartXA** , **STARplug** , **TOPFET** , **TrenchMOS** , **TriMedia** and **UCODE** — are trademarks of NXP B.V. **HD Radio** and **HD Radio** logo — are trademarks of iBiquity Digital Corporation. ## **10. Contact information** For more information, please visit:http://www.nxp.com For sales office addresses, please send an email to:salesaddresses@nxp.com © NXP B.V. 2012. All rights reserved. PSMN2R8-25MLC All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 3 — 15 June 2012** **13 of 14** **PSMN2R8-25MLC** **NXP Semiconductors** **N-channel 25 V 2.8 mΩ logic level MOSFET in LFPAK33 using NextPower Technology** ## **11. Contents** |**11. **|**Contents**| |---|---| |**1**|**Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1**| |1.1|General description . . . . . . . . . . . . . . . . . . . . . .1| |1.2|Features and benefits. . . . . . . . . . . . . . . . . . . . .1| |1.3|Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1| |1.4|Quick reference data . . . . . . . . . . . . . . . . . . . . .1| |**2**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . .2**| |**3**|**Ordering information. . . . . . . . . . . . . . . . . . . . . .2**| |**4**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2**| |**5**|**Thermal characteristics . . . . . . . . . . . . . . . . . . .4**| |**6**|**Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5**| |**7**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10**| |**8**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11**| |**9**|**Legal information. . . . . . . . . . . . . . . . . . . . . . . .12**| |9.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12| |9.2|Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12| |9.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12| |9.4|Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13| |**10**|**Contact information. . . . . . . . . . . . . . . . . . . . . .13**| Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. **© NXP B.V. 2012.** **All rights reserved.** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 15 June 2012 Document identifier: PSMN2R8-25MLC**
Updated at April 24, 2026
Nexperia is a dedicated global leader in discretes, logic, and MOSFET devices. Built on over half a century of semiconductor expertise and operating independently since 2017, the company produces consistently reliable components at an exceptional volume of 85 billion units annually. With its own manufacturing facilities, Nexperia delivers industry-leading small packages that combine power and thermal efficiency with best-in-class quality, meeting the rigorous standards of the automotive sector. Our extensive Nexperia portfolio is heavily focused on discrete semiconductors, providing engineers with a robust selection of core building blocks. This includes a comprehensive range of diodes and rectifiers, featuring a vast selection of Zener single diodes and Schottky diodes designed for precise voltage regulation and efficient power routing. Additionally, we offer an expansive array of bipolar transistors and single MOSFETs tailored for reliable switching and amplification in demanding applications. Beyond these primary offerings, the lineup extends into specialized circuit protection and passive components. This includes transient voltage suppressor (TVS) diodes, Zener array diodes, and small signal diodes, alongside dual MOSFETs and fast recovery rectifiers. For comprehensive design needs, the selection also encompasses integrated passive filters, common mode chokes, and precision timers and oscillators, ensuring a complete solution for high-performance electronic systems.
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