PSMN2R0-30YLE,115

## **PSMN2R0-30YLE** 

**N-channel 30 V 2 mΩ logic level MOSFET in LFPAK 12 October 2012** 

## **Product data sheet** 

## **1. Product profile** 

## **1.1 General description** 

Logic level N-channel MOSFET in LFPAK package qualified to 175 °C. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. 

## **1.2 Features and benefits** 

- Enhanced forward biased safe operating area for superior linear mode operation 

- Very low Rdson for low conduction losses 

## **1.3 Applications** 

- Electronic fuse 

- Hot swap 

- Load switch 

- Soft start 

## **1.4 Quick reference data** 

## **Table 1. Quick reference data** 

|**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|VDS|drain-source voltage|Tj≥ 25 °C; Tj≤ 175 °C||-|-|30|V|
|ID|drain current|Tmb= 25 °C; VGS= 10 V;Fig. 1|[1]|-|-|100|A|
|Ptot|total power dissipation|Tmb= 25 °C;Fig. 2||-|-|272|W|
|**Static characteristics**||||||||
|RDSon|drain-source on-state<br>resistance|VGS= 10 V; ID= 25 A; Tj= 25 °C;<br>Fig. 12||-|1.7|2|mΩ|
|||VGS= 4.5 V; ID= 25 A; Tj= 25 °C;<br>Fig. 12||-|3|3.5|mΩ|
|**Dynamic characteristics**||||||||
|QGD<br>~~|~~|gate-drain charge|VGS= 4.5 V; ID= 25 A; VDS= 15 V;<br>Fig. 14<br>; Fig. 15||-|13.8|-|nC|
|QG(tot)<br>~~a~~|total gate charge<br>~~ee~~|VGS= 10 V; ID= 25 A; VDS= 15 V;<br>Fig. 14<br>; Fig. 15<br>~~ee~~|~~ee~~|-<br>~~ee~~|87<br>~~ee~~|-<br>~~ee~~|nC<br>~~ee~~|



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**NXP Semiconductors** 

**PSMN2R0-30YLE** 

**N-channel 30 V 2 mΩ logic level MOSFET in LFPAK** 

|**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|**Avalanche ruggedness**||||||||
|EDS(AL)S|non-repetitive drain-<br>source avalanche<br>energy|VGS= 10 V; Tj(init)= 25 °C; ID= 100 A;<br>Vsup≤ 30 V; unclamped; RGS= 50 Ω;<br>Fig. 3||-|-|370|mJ|



[1] Capped at 100A due to package 

## **2. Pinning information** 

## **Table 2. Pinning information** 

|**Pin**|**Symbol**|**Description**|**Simplified outline**|**Graphic symbol**|
|---|---|---|---|---|
|1|S|source|mb<br>1<br>2<br>3<br>4<br>**LFPAK; Power-**<br>**SO8 (SOT669)**|S<br>D<br>G<br>_mbb076_|
|2|S|source|||
|3|S|source|||
|4|G|gate|||
|mb|D|mounting base; connected to<br>drain|||



## **3. Ordering information** 

## **Table 3. Ordering information** 

|**Type number**|**Package**|||
|---|---|---|---|
||**Name**|**Description**|**Version**|
|PSMN2R0-30YLE|LFPAK;<br>Power-SO8|plastic single-ended surface-mounted package; 4 leads|SOT669|



## **4. Marking** 

**Table 4. Marking codes** 

|**Type number**|**Marking code**|
|---|---|
|PSMN2R0-30YLE|2R030|



## **5. Limiting values** 

## **Table 5. Limiting values** 

_In accordance with the Absolute Maximum Rating System (IEC 60134)._ 

|**Symbol**|**Parameter**|**Conditions**||**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VDS|drain-source voltage|Tj≥ 25 °C; Tj≤ 175 °C||-|30|V|
|VDGR|drain-gate voltage|Tj≤ 175 °C; Tj≥ 25 °C; RGS= 20 kΩ||-|30|V|
|VGS|gate-source voltage|||-20|20|V|
|PSMN2R0-30YLE|All informatio|nprovided in this document is subject to legal disclaimers.||© NXP|B.V. 2012. All|rights reserved|
|**Product data sheet**||**12 October 2012**||||**2 / 13**|



**NXP Semiconductors** 

**PSMN2R0-30YLE** 

**N-channel 30 V 2 mΩ logic level MOSFET in LFPAK** 

|**Symbol**<br>~~Rs~~|**Parameter**<br>~~se~~|**Conditions**<br>~~se~~|~~se~~<br>~~ee~~|**Min**<br>~~se~~<br>~~ee~~|**Max**<br>~~se~~<br>~~ee~~|**Unit**<br>~~se~~<br>~~eee~~|
|---|---|---|---|---|---|---|
|ID<br>~~Rs~~<br>~~es~~|drain current<br>~~se~~<br>|VGS= 10 V; Tmb= 100 °C;Fig. 1<br>~~se~~<br>~~ee~~<br>|[1]<br>~~se~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|-<br>~~se~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|100<br>~~se~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|A<br>~~se~~<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>|
|||VGS= 10 V; Tmb= 25 °C; Fig. 1<br>~~ee~~<br>~~ee~~<br>|[1]<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|-<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|100<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>|A<br>~~ee~~<br> ~~eee~~<br>~~ee~~<br>~~ee~~<br>|
|IDM<br>~~es~~|peak drain current<br>~~ne~~|pulsed; tp≤ 10 µs; Tmb= 25 °C; Fig. 4<br>~~ee~~<br>~~ne~~|~~ee~~<br>~~ee~~<br>~~ne~~|-<br>~~ee~~<br>~~ee~~<br>~~ne~~|1084<br>~~ee~~<br>~~ee~~<br>~~ne~~|A<br>~~ee~~<br>~~ee~~<br>~~ne~~|
|Ptot<br>~~es~~<br>~~a~~|total power dissipation<br>~~ne~~|Tmb= 25 °C; Fig. 2<br>~~ne~~|~~ee~~<br>~~ne~~|-<br>~~ee ~~<br>~~ne~~|272<br> ~~ee ~~<br>~~ne~~|W<br> ~~ee~~<br>~~ne~~|
|Tstg<br>~~a~~<br>~~a~~<br>~~es~~|storage temperature<br>~~Ge~~<br>|~~Ge~~<br>|~~Ge~~<br>|-55<br>~~Ge~~<br>|175<br>~~Ge~~<br>|°C<br>~~Ge~~<br>|
|Tj<br>~~a~~<br>~~es~~<br>~~es~~|junction temperature<br>~~Ge~~<br>~~ee~~<br>|~~Ge~~<br>~~ee~~|~~Ge~~<br>~~ee~~|-55<br>~~Ge~~<br>~~ee~~|175<br>~~Ge~~<br>~~ee~~|°C<br>~~Ge~~<br>~~ee~~|
|Tsld(M)<br><br>~~es~~<br>~~es~~<br>~~CR~~|peak soldering temperature<br>~~Ge~~<br>~~ee~~<br>~~i~~<br>~~CR~~|~~Ge~~<br>~~ee~~<br>~~es~~|~~Ge~~<br>~~ee~~<br>~~es~~|-<br>~~Ge~~<br>~~ee~~<br>~~es~~|260<br>~~Ge~~<br>~~ee~~<br>~~es~~|°C<br>~~Ge~~<br>~~ee~~<br>~~es~~|
|**Source-drain diode**<br>~~ee~~<br>~~esi~~<br>~~es~~<br>~~CR~~<br>~~esee~~|||||||
|IS<br>~~CR~~<br>~~es~~|source current<br>~~CR~~<br>~~ee~~|Tmb= 25 °C<br>~~ee~~|[1]<br>~~ee~~|-<br>~~ee~~|100<br>~~ee~~|A<br>~~ee~~|
|ISM<br>~~es~~<br>~~a~~|peak source current<br>~~ee~~<br>|pulsed; tp≤ 10 µs; Tmb= 25 °C<br>~~ee~~<br>|~~ee~~<br>|-<br>~~ee~~<br>|1084<br>~~ee~~<br>|A<br>~~ee~~<br>|
|**Avalanche ruggedness**<br>~~aCe~~|||||||
|EDS(AL)S|non-repetitive drain-source<br>avalanche energy|VGS= 10 V; Tj(init)= 25 °C; ID= 100 A;<br>Vsup≤ 30 V; unclamped; RGS= 50 Ω;<br>Fig. 3||-|370|mJ|



[1] Capped at 100A due to package 

**==> picture [455 x 253] intentionally omitted <==**

**----- Start of picture text -----**<br>
003aah010 03aa16<br>300 120<br>ID Pder<br>(A) (%)<br>PNT ET S ERRE<br>200 BESNEEEe 80 P N<br>UE EEE<br>100 satestea imsfaxcett 40<br>(1)<br>TELE \ \<br>0 0<br>0 TLE 50 100 EL 150 TLA 200 0 EERERNEEPLT 50  LLELN- 100 150 200<br>Tmb(°C) Tmb (°C)<br>(1) Capped at 100A due to package<br>Fig. 2. Normalized total power dissipation as a<br>Fig. 1. Continuous drain current as a function of function of mounting base temperature<br>mounting base temperature<br>Vos? 107 Peer = BS x 100%<br>**----- End of picture text -----**<br>


© NXP B.V. 2012. All rights reserved 

PSMN2R0-30YLE 

All information provided in this document is subject to legal disclaimers. 

**12 October 2012** 

**Product data sheet** 

**3 / 13** 

**NXP Semiconductors** 

**PSMN2R0-30YLE** 

**N-channel 30 V 2 mΩ logic level MOSFET in LFPAK** 

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**Fig. 3. Single pulse avalanche rating; avalanche current as a function of avalanche time** 

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**----- Start of picture text -----**<br>
003aah012<br>10 [4]<br>ID ———————<br>Po—CSd<br>(A)<br>es<br>10 [3]<br>Limit RDSon = VDS/ ID<br>SS SSE SS Saas<br>t p =10 µs<br>——ee ee<br>10 [2] 100 µs<br>1 ms<br>10 ON DC<br>10 ms<br>GO GO ON OO NO OC CO CS GS GO NO | 100 ms a<br>aee ee= Se<br>1 A<br>10 [-1] 1 10 10 [2]<br>VDS(V)<br>**----- End of picture text -----**<br>


**Fig. 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage** 

## **6. Thermal characteristics** 

## **Table 6. Thermal characteristics** 

|**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|Rth(j-mb)|thermal resistance<br>from junction to<br>mounting base|Fig. 5||-|0.45|0.55|K/W|



© NXP B.V. 2012. All rights reserved 

PSMN2R0-30YLE **Product data sheet** 

All information provided in this document is subject to legal disclaimers. 

**12 October 2012** 

**4 / 13** 

**NXP Semiconductors** 

**PSMN2R0-30YLE** 

**N-channel 30 V 2 mΩ logic level MOSFET in LFPAK** 

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**----- Start of picture text -----**<br>
003aag993<br>1<br>Z<br>th(j-mb)<br>(K/W)<br>δ  [= 0.5]<br>10 [-1]<br>0.2<br>0.1<br>0.05<br>0.02 P δ = tp<br>10 [-2] T<br>single shot<br>tp t<br>T<br>10 [-3]<br>10 [-6] 10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 1<br>tp (s)<br>**----- End of picture text -----**<br>


**Fig. 5. Transient thermal impedance from junction to mounting base as a function of pulse duration** 

## **7. Characteristics** 

**Table 7. Characteristics** 

|**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|**Static characteristics**||||||||
|V(BR)DSS|drain-source<br>breakdown voltage|ID= 250 µA; VGS= 0 V; Tj= -55 °C||27|-|-|V|
|||ID= 250 µA; VGS= 0 V; Tj= 25 °C||30|-|-|V|
|VGS(th)|gate-source threshold<br>voltage|ID= 1 mA; VDS= VGS; Tj= 175 °C;<br>Fig. 10||0.5|-|-|V|
|||ID= 1 mA; VDS= VGS; Tj= 25 °C;<br>Fig. 11<br>; Fig. 10||1.3|1.7|2.15|V|
|||ID= 1 mA; VDS= VGS; Tj= -55 °C;<br>Fig. 10||-|-|2.45|V|
|IDSS|drain leakage current|VDS= 30 V; VGS= 0 V; Tj= 25 °C||-|0.05|10|µA|
|||VDS= 30 V; VGS= 0 V; Tj= 100 °C||-|-|200|µA|
|IGSS|gate leakage current|VGS= 16 V; VDS= 0 V; Tj= 25 °C||-|10|100|nA|
|||VGS= -16 V; VDS= 0 V; Tj= 25 °C||-|10|100|nA|
|RDSon|drain-source on-state<br>resistance|VGS= 10 V; ID= 25 A; Tj= 25 °C;<br>Fig. 12||-|1.7|2|mΩ|
|||VGS= 10 V; ID= 25 A; Tj= 100 °C;<br>Fig. 13<br>; Fig. 12||-|-|2.8|mΩ|
|||VGS= 4.5 V; ID= 25 A; Tj= 25 °C;<br>Fig. 12||-|3|3.5|mΩ|
|||VGS= 10 V; ID= 25 A; Tj= 175 °C;<br>Fig. 13<br>; Fig. 12||-|-|3.8|mΩ|



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© NXP B.V. 2012. All rights reserved 

PSMN2R0-30YLE 

**12 October 2012** 

**Product data sheet** 

**5 / 13** 

**NXP Semiconductors** 

**PSMN2R0-30YLE** 

**N-channel 30 V 2 mΩ logic level MOSFET in LFPAK** 

|**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|RG|internal gate<br>resistance (AC)|f = 1 MHz||0.3|0.6|1.2|Ω|
|**Dynamic characteristics**||||||||
|QG(tot)|total gate charge|ID= 25 A; VDS= 15 V; VGS= 10 V;<br>Fig. 14<br>; Fig. 15||-|87|-|nC|
|||ID= 25 A; VDS= 15 V; VGS= 4.5 V;<br>Fig. 14<br>; Fig. 15||-|41|-|nC|
|||ID= 0 A; VDS= 0 V; VGS= 10 V||-|79|-|nC|
|QGS|gate-source charge|ID= 25 A; VDS= 15 V; VGS= 4.5 V;<br>Fig. 14<br>; Fig. 15||-|13.3|-|nC|
|QGS(th)|pre-threshold gate-<br>source charge|||-|8.1|-|nC|
|QGS(th-pl)|post-threshold gate-<br>source charge|||-|5.2|-|nC|
|QGD|gate-drain charge|||-|13.8|-|nC|
|VGS(pl)|gate-source plateau<br>voltage|ID= 25 A; VDS= 15 V;Fig. 14<br>; Fig. 15||-|2.8|-|V|
|Ciss|input capacitance|VDS= 15 V; VGS= 0 V; f = 1 MHz;<br>Tj= 25 °C; Fig. 16||-|5217|-|pF|
|Coss|output capacitance|||-|1015|-|pF|
|Crss|reverse transfer<br>capacitance|||-|474|-|pF|
|td(on)|turn-on delay time|VDS= 15 V; RL= 0.6 Ω; VGS= 4.5 V;<br>RG(ext)= 4.7 Ω; Tj= 25 °C||-|32.7|-|ns|
|tr|rise time|||-|55.7|-|ns|
|td(off)|turn-off delay time|||-|41.5|-|ns|
|tf|fall time|||-|29.5|-|ns|
|**Source-drain diode**||||||||
|VSD|source-drain voltage|IS= 25 A; VGS= 0 V; Tj= 25 °C; Fig. 17||-|0.8|1.2|V|
|trr|reverse recovery time|IS= 25 A; dIS/dt = 100 A/µs; VGS= 0 V;<br>VDS= 15 V||-|42.6|-|ns|
|Qr|recovered charge|||-|49.8|-|nC|



© NXP B.V. 2012. All rights reserved 

PSMN2R0-30YLE 

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**12 October 2012** 

**Product data sheet** 

**6 / 13** 

**NXP Semiconductors** 

**PSMN2R0-30YLE** 

**N-channel 30 V 2 mΩ logic level MOSFET in LFPAK** 

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**----- Start of picture text -----**<br>
003aah014 003aah015<br>100 8<br>ID Tinea 10 4.5 VGS(V) = 3.5 RDSon<br>(A) (mΩ)<br>80<br>WY 6 PACE<br>[foo CA<br>60 THA)| | jd<br>4<br>3<br>40 me ee<br>2.8 2<br>20 a TONCELES<br>2.6<br>Woo PP) Pars<br>2.4<br>0 bE 0 Pt Et LL<br>0 0.5 1 1.5 2 0 4 8 12 16<br>VDS(V) VGS(V)<br>**----- End of picture text -----**<br>


**Fig. 6. Output characteristics; drain current as a function of drain-source voltage; typical values** 

**Fig. 7. Drain-source on-state resistance as a function of gate-source voltage; typical values** 

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003aah016 003aah017<br>150 200<br>(S)gfs Tz ID TT<br>(A)<br>120<br>150<br>SeeeeeeyCECE ae OEELELLLULL<br>90 || | iE eerEEEtt COCOA<br>100<br>60 ser 4ennnne FL-HHH AH<br>A 50 CECA<br>30 Tj = 175 °C<br>T = 25 °C<br>j<br>0 TCEELPFE CEEL E LELLLLL 0 (|| LY_ | |<br>0 20 40 60 80 100 0 1 2 3 4 5<br>ID (A) VGS(V)<br>**----- End of picture text -----**<br>


**Fig. 8. Forward transconductance as a function of drain current; typical values** 

**Fig. 9. Transfer characteristics; drain current as a function of gate-source voltage; typical values** 

© NXP B.V. 2012. All rights reserved 

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**12 October 2012** 

**Product data sheet** 

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**NXP Semiconductors** 

**PSMN2R0-30YLE** 

**N-channel 30 V 2 mΩ logic level MOSFET in LFPAK** 

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**----- Start of picture text -----**<br>
003aaj515 003aaj514<br>3 10 [-1]<br>ID<br>VGS(th) (A)<br>(V) — 10 [-2] ee ee ee) ee<br>2 JW~ max LL SSS[| [|5—_=f<br>min typ max<br>10 [-3]<br>typ<br>min 10 [-4]<br>1<br>10 [-5]<br>0-60 FLT 0 60 Ty 120 ~yl 180 10 [-6] 0 [|—ff|[/fiyf 1 foA [| 2 | | 3<br>Tj (°C) VGS(V)<br>**----- End of picture text -----**<br>


**Fig. 10. Gate-source threshold voltage as a function of junction temperature** 

**Fig. 11. Sub-threshold drain current as a function of gate-source voltage** 

**==> picture [440 x 186] intentionally omitted <==**

**----- Start of picture text -----**<br>
003aah020 003aag820<br>30 2<br>2.8 VGS(V) = 3<br>RDSon a<br>(mΩ)<br>Py 1.5 Pi; Tt<br>20<br>LA / 1 PiSennPaneLZ ee<br>10<br>3.5 0.5<br>Set Cee ZC<br>ae 4.5 Pere<br>a err<br>0 a _ 10 0 PittT yy<br>10 30 50 70 90 -60 0 60 120 180<br>ID(A) Tj (°C)<br>**----- End of picture text -----**<br>


**Fig. 12. Drain-source on-state resistance as a function of drain current; typical values** 

**Fig. 13. Normalized drain-source on-state resistance factor as a function of junction temperature** 

© NXP B.V. 2012. All rights reserved 

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**NXP Semiconductors** 

**PSMN2R0-30YLE** 

**N-channel 30 V 2 mΩ logic level MOSFET in LFPAK** 

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**----- Start of picture text -----**<br>
003aah022<br>10<br>VDS VGS<br>—-—-- (V) See<br>ID 8<br>i Ze<br>ae vane<br>VGS(pl) YA Sanne 7en<br>24 V<br>6<br>VGS(th) 5 SeEED/ aan<br>VGS 4 VDS= 15V<br>7 QGS1 QGS2 ofA) cH<br>2ay/ZNe 6 V a<br>QGS QG D 2 PVT Tt. | i ty<br>QG(tot)<br>003aaa508 AT |tty<br>0 Vi [litt] tt tt<br>Gate charge waveform definitions 0 20 40 60 80 100<br>QG (nC)<br>Fig. 15. Gate-source voltage as a function of gate<br>charge; typical values<br>003aah023 003aah024<br>10 [4] 100<br>IS<br>C iss (A)<br>C 80<br>(pF)<br>en TIT<br>SSS 60 si<br>10 [3] ee Coss CCC<br>40<br>Crss Tj = 150°C<br>20<br>Tj = 25 °C<br>10 [2] EI EAI LE 0 eeeSAT eeTT<br>10 [-1] 1 10 10 [2] 0 0.3 0.6 0.9 1.2<br>VDS(V) VSD(V)<br>**----- End of picture text -----**<br>


**Fig. 14. Gate charge waveform definitions** 

**Fig. 15. Gate-source voltage as a function of gate charge; typical values** 

**Fig. 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values** 

**Fig. 17. Source current as a function of source-drain voltage; typical values** 

© NXP B.V. 2012. All rights reserved 

PSMN2R0-30YLE 

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**12 October 2012** 

**Product data sheet** 

**9 / 13** 

**NXP Semiconductors** 

**PSMN2R0-30YLE** 

**N-channel 30 V 2 mΩ logic level MOSFET in LFPAK** 

## **8. Package outline** 

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**----- Start of picture text -----**<br>
Plastic single-ended surface-mounted package (LFPAK; Power-SO8); 4 leads SOT669<br>A2<br>E A C<br>b2 c2 E1<br>L1 b3<br>mounting<br>base b4<br>D1<br>H D<br>L2<br>1 2 3 4<br>X<br>e b w M A c<br>1/2 e<br>A (A  )3<br>A1 C<br>θ<br>L<br>detail X<br>y C<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT A A1 A2 A3 b b2 b3 b4 c c2 D [(1)] D1max(1) E [(1)] E1 [(1)] e H L L1 L2 w y θ<br>1.20 0.15 1.10 0.50 4.41 2.2 0.9 0.25 0.30 4.10 5.0 3.3 6.2 0.85 1.3 1.3 8°<br>mm 0.25 4.20 1.27 0.25 0.1<br>1.01 0.00 0.95 0.35 3.62 2.0 0.7 0.19 0.24 3.80 4.8 3.1 5.8 0.40 0.8 0.8 0°<br>Note<br>1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.<br>OUTLINE  REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION  IEC JEDEC  JEITA PROJECTION<br>06-03-16<br>SOT669 MO-235<br>11-03-25<br>Fig. 18. Package outline LFPAK; Power-SO8 (SOT669)<br>PSMN2R0-30YLE All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved<br>**----- End of picture text -----**<br>


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10 / 13<br>**----- End of picture text -----**<br>


**12 October 2012** 

**Product data sheet** 

**NXP Semiconductors** 

**PSMN2R0-30YLE** 

**N-channel 30 V 2 mΩ logic level MOSFET in LFPAK** 

## **9. Legal information** 

## **9.1 Data sheet status** 

|**Document**<br>**status [1]**<br>**[2]**|**Product**<br>**status [3]**|**Definition**|
|---|---|---|
|Objective<br>[short] data<br>sheet|Development|This document contains data from<br>the objective specification for product<br>development.|
|Preliminary<br>[short] data<br>sheet|Qualification|This document contains data from the<br>preliminary specification.|
|Product<br>[short] data<br>sheet|Production|This document contains the product<br>specification.|



[1] Please consult the most recently issued document before initiating or completing a design. 

[2] The term 'short data sheet' is explained in section "Definitions". 

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 

## **9.2 Definitions** 

**Preview** — The document is a preview version only. The document is still subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 

**Draft** — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 

**Short data sheet** — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 

**Product specification** — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 

## **9.3 Disclaimers** 

**Limited warranty and liability** — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. 

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors. 

**Right to make changes** — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 

**Suitability for use** — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 

**Quick reference data** — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 

**Applications** — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. 

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. 

**Limiting values** — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 

**Terms and conditions of commercial sale** — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 

**No offer to sell or license** — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the 

© NXP B.V. 2012. All rights reserved 

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grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 

**Export control** — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 

**Non-automotive qualified products** — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. 

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 

**Translations** — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 

## **9.4 Trademarks** 

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 

**Adelante** , **Bitport** , **Bitsound** , **CoolFlux** , **CoReUse** , **DESFire** , **EZ-HV** , **FabKey** , **GreenChip** , **HiPerSmart** , **HITAG** , **I²C-bus** logo, **ICODE** , **I-CODE** , **ITEC** , **Labelution** , **MIFARE** , **MIFARE Plus** , **MIFARE Ultralight** , **MoReUse** , **QLPAK** , **Silicon Tuner** , **SiliconMAX** , **SmartXA** , **STARplug** , **TOPFET** , **TrenchMOS** , **TriMedia** and **UCODE** — are trademarks of NXP B.V. 

**HD Radio** and **HD Radio** logo — are trademarks of iBiquity Digital Corporation. 

© NXP B.V. 2012. All rights reserved 

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All information provided in this document is subject to legal disclaimers. 

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**Product data sheet** 

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**N-channel 30 V 2 mΩ logic level MOSFET in LFPAK** 

## **10. Contents** 

|**10. **|**Contents**|
|---|---|
|**1**|**Product profile ....................................................... 1**|
|1.1|General description .............................................. 1|
|1.2|Features and benefits ...........................................1|
|1.3|Applications .......................................................... 1|
|1.4|Quick reference data ............................................ 1|
|**2**|**Pinning information ...............................................2**|
|**3**|**Ordering information .............................................2**|
|**4**|**Marking ...................................................................2**|
|**5**|**Limiting values .......................................................2**|
|**6**|**Thermal characteristics .........................................4**|
|**7**|**Characteristics .......................................................5**|
|**8**|**Package outline ................................................... 10**|
|**9**|**Legal information .................................................11**|
|9.1|Data sheet status ............................................... 11|
|9.2|Definitions ...........................................................11|
|9.3|Disclaimers .........................................................11|
|9.4|Trademarks ........................................................ 12|



## **© NXP B.V. 2012. All rights reserved** 

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 12 October 2012** 

© NXP B.V. 2012. All rights reserved 

PSMN2R0-30YLE 

All information provided in this document is subject to legal disclaimers. 

**12 October 2012** 

**Product data sheet** 

**13 / 13**