Image not available
Illustrative purposes only
PSMN1R6-30PL
Power MOSFET, N Channel, 30 V, 100 A, 0.0014 ohm, TO-220AB, Through Hole
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: NEXPERIA
- Product type: Single MOSFETs
- No. of Pins: 3Pins
- Channel Type: N Channel
- Power Dissipation: 306W
- Transistor Mounting: Through Hole
- Transistor Polarity: N Channel
- Power Dissipation Pd: 306W
- Rds(on) Test Voltage: 10V
- On Resistance Rds(on): 0.0014ohm
- Transistor Case Style: TO-220AB
- Drain Source Voltage Vds: 30V
- Operating Temperature Max: 175°C
- Continuous Drain Current Id: 100A
- Drain Source On State Resistance: 0.0014ohm
- Gate Source Threshold Voltage Max: 1.7V
| Delivery and price | |
|---|---|
| Units per pack | 1 |
| Price | 0.69 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
## **PSMN1R6-30PL** **N-channel 30 V 1.7 mΩ logic level MOSFET** **Rev. 02 — 25 June 2009** ## **Product data sheet** ## **1. Product profile** ## **1.1 General description** Logic level N-channel MOSFET in TO220 package qualified to 175 °C. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. ## **1.2 Features and benefits** - High efficiency due to low switching and conduction losses - Suitable for logic level gate drive sources ## **1.3 Applications** - DC-to-DC converters - Load switiching - Motor control - Server power supplies ## **1.4 Quick reference data** **Table 1. Quick reference** |**Symbol**|**Parameter**|**Conditions**|||**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---|---|---| |VDS|drain-source voltage|Tj≥25 °C; Tj≤175 °C|||-|-|30|V| |ID|drain current|Tmb= 25 °C; VGS= 10 V;||[1]|-|-|100|A| |||seeFigure 1<br>;||||||| |||||||||| |Ptot|total power|Tmb= 25 °C; see Figure 2|||-|-|306|W| ||dissipation|||||||| |**Dynamic**|**characteristics**|||||||| |QGD|gate-drain charge|VGS= 4.5 V; ID= 25 A;|||-|27|-|nC| |||VDS= 15 V; seeFigure 14<br>;||||||| |||seeFigure 15||||||| |||||||||| |QG(tot)|total gate charge|VGS= 4.5 V; ID= 25 A;|||-|101|-|nC| |||VDS= 15 V; seeFigure 14||||||| |||||||||| |**Static characteristics**||||||||| |RDSon|drain-source|VGS= 10 V; ID= 25 A;||[2]|-|1.4|1.7|mΩ| ||on-state resistance|Tj= 25 °C;||||||| - [1] Continuous current is limited by package. - [2] Measured 3 mm from package. **==> picture [81 x 42] intentionally omitted <==** **PSMN1R6-30PL** **NXP Semiconductors** **N-channel 30 V 1.7 mΩ logic level MOSFET** ## **2. Pinning information** ## **Table 2. Pinning information** |**Pin**<br>**Symbol**<br>**Description**<br>**Simplified**|**outline**<br>**Graphic symbol**| |---|---| |1<br>G<br>gate<br>**SOT78**<br>**(TO-220AB; SC-46)**<br>2<br>D<br>drain<br>3<br>S<br>source<br>mb<br>D<br>mounting base; connected to<br>drain<br>1<br>2<br>mb<br>3<br>S<br>D<br>G<br>mbb076|| ## **3. Ordering information** ## **Table 3. Ordering information** |**Type number**|**Package**| |---|---| ||**Name**<br>**Description**<br>**Version**| |PSMN1R6-30PL|TO-220AB;<br>SC-46<br>plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead<br>TO-220AB<br>SOT78| © NXP B.V. 2009. All rights reserved. PSMN1R6-30PL_2 **Product data sheet** **Rev. 02 — 25 June 2009** **2 of 13** **PSMN1R6-30PL** **NXP Semiconductors** **N-channel 30 V 1.7 mΩ logic level MOSFET** ## **4. Limiting values** **Table 4. Limiting values** _In accordance with the Absolute Maximum Rating System (IEC 60134)._ |**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Max**<br>**Unit**| |---|---| |VDS<br>drain-source voltage|Tj≥25 °C; Tj≤175 °C<br>-<br>30<br>V| |VDGR<br>drain-gate voltage|Tj≥25 °C; Tj≤175 °C; RGS= 20 kΩ<br>-<br>30<br>V| |VGS<br>gate-source voltage|-20<br>20<br>V| |ID<br>drain current|VGS= 10 V; Tmb= 100 °C; seeFigure 1<br>;<br>[1]<br>-<br>100<br>A| ||VGS= 10 V; Tmb= 25 °C; seeFigure 1<br>;<br>[1]<br>-<br>100<br>A| |IDM<br>peak drain current|tp≤10 µs; pulsed; Tmb= 25 °C; seeFigure 3<br>-<br>1268<br>A| |Ptot<br>total power dissipation|Tmb= 25 °C; seeFigure 2<br>-<br>306<br>W| |Tstg<br>storage temperature|-55<br>175<br>°C| |Tj<br>junction temperature|-55<br>175<br>°C| |**Source-drain diode**|| |IS<br>source current|Tmb= 25 °C;<br>[1]<br>-<br>100<br>A| ||| |ISM<br>peak source current|tp≤10 µs; pulsed; Tmb= 25 °C<br>-<br>1268<br>A| |**Avalanche ruggedness**|| |EDS(AL)S<br>non-repetitive<br>drain-source avalanche<br>energy|VGS= 10 V; Tj(init)= 25 °C; ID= 100 A; Vsup≤30 V;<br>RGS= 50 Ω; unclamped<br>-<br>1.7<br>J| [1] Continuous current is limited by package. **==> picture [235 x 249] intentionally omitted <==** **----- Start of picture text -----**<br> 003aad003<br>400<br>ID<br>(A)<br>300<br>200<br>100<br>(1)<br>0<br>0 50 100 150 200<br>Tmb (°C)<br>Fig 1. Continuous drain current as a function of<br>mounting base temperature<br>**----- End of picture text -----**<br> **==> picture [235 x 251] intentionally omitted <==** **----- Start of picture text -----**<br> 03aa16<br>120<br>Pder<br>(%)<br>80<br>40<br>0<br>0 50 100 150 200<br>Tmb (°C)<br>Fig 2. Normalized total power dissipation as a<br>function of mounting base temperature<br>**----- End of picture text -----**<br> © NXP B.V. 2009. All rights reserved. PSMN1R6-30PL_2 **Product data sheet** **Rev. 02 — 25 June 2009** **3 of 13** **PSMN1R6-30PL** **NXP Semiconductors** **N-channel 30 V 1.7 mΩ logic level MOSFET** **==> picture [481 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aad115<br> 10 [4]<br>ID<br>(A)<br>Limit RDSon = VDS / ID 10 μs<br> 10 [3]<br>100 μs<br> 10 [2]<br>(1)<br>1 ms<br> 10 10 ms<br>DC<br>100 ms<br> 1<br>10 [-1] 1 10 VDS (V) 10 [2]<br>**----- End of picture text -----**<br> **Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage** ## **5. Thermal characteristics** ## **Table 5. Thermal characteristics** **==> picture [498 x 297] intentionally omitted <==** **----- Start of picture text -----**<br> Symbol Parameter Conditions Min Typ Max Unit<br>Rth(j-mb) thermal resistance from see Figure 4 - 0.22 0.49 K/W<br>junction to mounting<br>base<br>003aad005<br> 1<br>Zth(j-mb)<br>(K/W) δ = 0.5<br>10 [-1]<br>0.2<br>0.1<br>0.05<br>10 [-2]<br>0.02<br>P δ = tp<br>T<br>10 [-3]<br>single shot tp t<br>T<br>10 [-4]<br>10 [-6] 10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] tp (s) 1<br>Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration; typical<br>values<br>**----- End of picture text -----**<br> © NXP B.V. 2009. All rights reserved. PSMN1R6-30PL_2 **Product data sheet** **Rev. 02 — 25 June 2009** **4 of 13** **PSMN1R6-30PL** **NXP Semiconductors** **N-channel 30 V 1.7 mΩ logic level MOSFET** ## **6. Characteristics** |**Table 6.**|**Characteristics**| |---|---| |_Tested to_|_JEDEC standards where applicable._| |**Table 6.**<br>**Characteristics**<br>_Tested to JEDEC standards where applicable._|**Table 6.**<br>**Characteristics**<br>_Tested to JEDEC standards where applicable._|**Table 6.**<br>**Characteristics**<br>_Tested to JEDEC standards where applicable._| |---|---|---| |**Symbol**<br>**Parameter**|**Conditions**|**Min**<br>**Typ**<br>**Max**<br>**Unit**| |**Static characteristics**||| |V(BR)DSS<br>drain-source<br>breakdown voltage|ID= 250 µA; VGS= 0 V; Tj= 25 °C|30<br>-<br>-<br>V| ||ID= 250 µA; VGS= 0 V; Tj= -55 °C|27<br>-<br>-<br>V| |VGS(th)<br>gate-source threshold<br>voltage|ID= 1 mA; VDS= VGS; Tj= 25 °C; see<br>Figure 11<br>;seeFigure 12|1.3<br>1.7<br>2.15<br>V| ||ID= 1 mA; VDS= VGS; Tj= 175 °C; see<br>Figure 12|0.5<br>-<br>-<br>V| ||ID= 1 mA; VDS= VGS; Tj= -55 °C; see<br>Figure 12|-<br>-<br>2.45<br>V| |||| |IDSS<br>drain leakage current|VDS= 30 V; VGS= 0 V; Tj= 25 °C|-<br>-<br>5<br>µA| ||VDS= 30 V; VGS= 0 V; Tj= 125 °C|-<br>-<br>150<br>µA| |IGSS<br>gate leakage current|VGS= 16 V; VDS= 0 V; Tj= 25 °C|-<br>-<br>100<br>nA| ||VGS= -16 V; VDS= 0 V; Tj= 25 °C|-<br>-<br>100<br>nA| |RDSon<br>drain-source on-state<br>resistance|VGS= 4.5 V; ID= 25 A; Tj= 25 °C|-<br>1.6<br>2.1<br>mΩ| ||VGS= 10 V; ID= 25 A; Tj= 100 °C; see<br>Figure 13|-<br>-<br>2.3<br>mΩ| ||VGS= 10 V; ID= 25 A; Tj= 25 °C;|[1]<br>-<br>1.4<br>1.7<br>mΩ| |RG<br>gate resistance|f = 1 MHz|-<br>0.98<br>-<br>Ω| |**Dynamic characteristics**||| |QG(tot)<br>total gate charge|ID= 25 A; VDS= 15 V; VGS= 10 V; see<br>Figure 14<br>;see Figure 15|-<br>212<br>-<br>nC| ||ID= 0 A; VDS= 0 V; VGS= 10 V|-<br>193<br>-<br>nC| ||ID= 25 A; VDS= 15 V; VGS= 4.5 V; see<br>Figure 14|-<br>101<br>-<br>nC| |QGS<br>gate-source charge|ID= 25 A; VDS= 15 V; VGS= 4.5 V; see<br>Figure 14<br>;see Figure 15|-<br>33<br>-<br>nC| ||<br>|| |QGS(th)<br>pre-threshold<br>gate-source charge|ID= 25 A; VDS= 15 V; VGS= 4.5 V; see<br>Figure 14|-<br>20<br>-<br>nC| |QGS(th-pl)<br>post-threshold<br>gate-source charge||-<br>13<br>-<br>nC| |QGD<br>gate-drain charge|ID= 25 A; VDS= 15 V; VGS= 4.5 V; see<br>Figure 14<br>;see Figure 15|-<br>27<br>-<br>nC| |VGS(pl)<br>gate-source plateau<br>voltage|VDS= 15 V; seeFigure 14|-<br>2.5<br>-<br>V| |Ciss<br>input capacitance|VDS= 12 V; VGS= 0 V; f = 1 MHz;<br>Tj= 25 °C; seeFigure 16|-<br>12493<br>-<br>pF| |Coss<br>output capacitance||-<br>2486<br>-<br>pF| |Crss<br>reverse transfer<br>capacitance||-<br>1034<br>-<br>pF| © NXP B.V. 2009. All rights reserved. PSMN1R6-30PL_2 **Product data sheet** **Rev. 02 — 25 June 2009** **5 of 13** **PSMN1R6-30PL** **NXP Semiconductors** **N-channel 30 V 1.7 mΩ logic level MOSFET** **Table 6. Characteristics** _…continued Tested to JEDEC standards where applicable._ |**Symbol**<br>**Parameter**<br>**Conditions**|**Min**<br>**Typ**<br>**Max**<br>**Unit**| |---|---| |td(on)<br>turn-on delay time<br>VDS= 12 V; RL= 0.5 Ω; VGS= 4.5 V;<br>RG(ext)= 4.7 Ω<br>tr<br>rise time<br>td(off)<br>turn-off delay time<br>tf<br>fall time|-<br>104<br>-<br>ns<br>-<br>163<br>-<br>ns<br>-<br>174<br>-<br>ns<br>-<br>87<br>-<br>ns| |**Source-drain diode**|| |VSD<br>source-drain voltage<br>IS= 25 A; VGS= 0 V; Tj= 25 °C; see<br>Figure 17|-<br>0.77<br>1.2<br>V| |trr<br>reverse recovery time<br>IS= 50 A; dIS/dt = -100 A/µs; VGS= 0 V;<br>VDS= 15 V<br>Qr<br>recovered charge|-<br>64<br>-<br>ns<br>-<br>79<br>-<br>nC| [1] Measured 3 mm from package. **==> picture [498 x 254] intentionally omitted <==** **----- Start of picture text -----**<br> 003aad011 003aad012<br>300 10<br> (A)I250D 3.54.510 3 (mRDSonΩ) 2.6 2.8<br>8 VGS (V) = 3<br>200<br>2.8 6<br>150<br>4<br>100<br>2.6 4.5<br>3.5<br>2<br>50<br>VGS (V) = 2.4<br>10<br>0 0<br>0 2 4 6 8 10 0 100 200 ID (A) 300<br>VDS (V)<br>Fig 5. Output characteristics: drain current as a Fig 6. Drain-source on-state resistance as a function<br>function of drain-source voltage; typical values of drain current; typical values<br>**----- End of picture text -----**<br> © NXP B.V. 2009. All rights reserved. PSMN1R6-30PL_2 **Product data sheet** **Rev. 02 — 25 June 2009** **6 of 13** **PSMN1R6-30PL** **NXP Semiconductors** **N-channel 30 V 1.7 mΩ logic level MOSFET** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aad013<br>100<br>ID<br>(A)<br>80<br>Tj = 175 °C<br>60<br>25 °C<br>40<br>20<br>0<br>0 1 2 3 VGS (V) 4<br>**----- End of picture text -----**<br> **Fig 7. Transfer characteristics: drain current as a function of gate-source voltage; typical values** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aad019<br>10<br>RDSon<br>(mΩ)<br>8<br>6<br>4<br>2<br>0<br>0 5 10 15 20<br>VGS (V)<br>**----- End of picture text -----**<br> **Fig 9. Drain-source on-state resistance as a function of gate-source voltage; typical values** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aad018<br>400<br>gfs<br>(S)<br>300<br>200<br>100<br>0<br>0 20 40 60 80 100<br>ID (A)<br>**----- End of picture text -----**<br> **Fig 8. Forward transconductance as a function of drain current; typical values** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aad017<br>10 [5]<br>C<br>(pF)<br>Ciss<br> 10 [4]<br>Crss<br> 10 [3]<br>10 [-1] 1 10 VGS (V) 10 [2]<br>**----- End of picture text -----**<br> **Fig 10. Input and reverse transfer capacitances as a function of gate-source voltage; typical values** © NXP B.V. 2009. All rights reserved. PSMN1R6-30PL_2 **Product data sheet** **Rev. 02 — 25 June 2009** **7 of 13** **PSMN1R6-30PL** **NXP Semiconductors** **N-channel 30 V 1.7 mΩ logic level MOSFET** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aab271<br>10 [[-1]]<br>ID D<br>(A)<br>10 [[-2]]<br>min typ max<br>10 [[-3]]<br>10 [[-4]]<br>10 [[-5]]<br>10 [[-6]]<br>0 1 2 VGS (V)GS (V) (V) 3<br>**----- End of picture text -----**<br> **==> picture [498 x 412] intentionally omitted <==** **----- Start of picture text -----**<br> 003aab271 003aac982<br>10 [[-1]] 3<br>ID D<br>(A) VGS(th)<br>10 [[-2]]<br>(V) max<br>min typ max 2<br>10 [[-3]] typ<br>min<br>10 [[-4]]<br>1<br>10 [[-5]]<br>10 [[-6]] 0<br>0 1 2 VGS (V)GS (V) (V) 3 -60 0 60 120 Tj (°C) 180<br>Fig 11. Sub-threshold drain current as a function of Fig 12. Gate-source threshold voltage as a function of<br>gate-source voltage junction temperature<br>03aa27<br>2<br>VDS<br>a<br>ID<br>1.5<br>VGS(pl)<br>1 VGS(th)<br>VGS<br>QGS1 QGS2<br>0.5<br>QGS QGD<br>QG(tot)<br>003aaa508<br>**----- End of picture text -----**<br> **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 03aa27<br>2<br>a<br>1.5<br>1<br>0.5<br>0<br>−60 0 60 120 Tj (°C) 180<br>**----- End of picture text -----**<br> **Fig 14. Gate charge waveform definitions** **Fig 13. Normalized drain-source on-state resistance factor as a function of junction temperature** © NXP B.V. 2009. All rights reserved. PSMN1R6-30PL_2 **Product data sheet** **Rev. 02 — 25 June 2009** **8 of 13** **PSMN1R6-30PL** **NXP Semiconductors** **N-channel 30 V 1.7 mΩ logic level MOSFET** **==> picture [498 x 465] intentionally omitted <==** **----- Start of picture text -----**<br> 003aad015 003aad016<br>10 10 [5]<br>VGS<br> (V) C<br>8 (pF)<br>VDS = 15 V<br>Ciss<br> 10 [4]<br>6<br>Coss<br>4<br> 10 [3] Crss<br>2<br>0 10 [2]<br>0 40 80 120 160 200 240 10 [-1] 1 10 10 [2]<br>QG (nC) VDS (V)<br>Fig 15. Gate-source voltage as a function of gate Fig 16. Input, output and reverse transfer capacitances<br>charge; typical values as a function of drain-source voltage; typical<br>values<br>003aad014<br>100<br>IS<br>(A)<br>80<br>60<br>175 °C<br>40<br>20<br>Tj = 25 °C<br>0<br>0 0.2 0.4 0.6 0.8 1<br>VSD (V)<br>**----- End of picture text -----**<br> **Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values** © NXP B.V. 2009. All rights reserved. PSMN1R6-30PL_2 **Product data sheet** **Rev. 02 — 25 June 2009** **9 of 13** **PSMN1R6-30PL** **NXP Semiconductors** **N-channel 30 V 1.7 mΩ logic level MOSFET** ## **7. Package outline** ## **Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220AB** **==> picture [26 x 7] intentionally omitted <==** **----- Start of picture text -----**<br> SOT78<br>**----- End of picture text -----**<br> **==> picture [482 x 565] intentionally omitted <==** **----- Start of picture text -----**<br> E A<br>p A1<br>q mounting<br>D1 base<br>D<br>L1 [(1)] L2 [(1)]<br>Q<br>b1 [(2)]<br>L (3×)<br>b2 [(2)]<br>(2×)<br>1 2 3<br>b(3×) c<br>e e<br>0 5 10 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT A A1 b b1 [(2)] b2 [(2)] c D D1 E e L L1 [(1)] L2 [(1)] p q Q<br>max.<br>4.7 1.40 0.9 1.6 1.3 0.7 16.0 6.6 10.3 15.0 3.30 3.8 3.0 2.6<br>mm 2.54 3.0<br>4.1 1.25 0.6 1.0 1.0 0.4 15.2 5.9 9.7 12.8 2.79 3.5 2.7 2.2<br>Notes<br>1. Lead shoulder designs may vary.<br>2. Dimension includes excess dambar.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>08-04-23<br>SOT78 3-lead TO-220AB SC-46<br>08-06-13<br>**----- End of picture text -----**<br> **Fig 18. Package outline SOT78 (TO-220AB)** © NXP B.V. 2009. All rights reserved. PSMN1R6-30PL_2 **Product data sheet** **Rev. 02 — 25 June 2009** **10 of 13** **PSMN1R6-30PL** **NXP Semiconductors** **N-channel 30 V 1.7 mΩ logic level MOSFET** ## **8. Revision history** |**Table 7.**<br>**Revision**|**history**|||| |---|---|---|---|---| |**Document ID**|**Release date**|**Data sheet status**|**Change notice**|**Supersedes**| |PSMN1R6-30PL_2|20090625|Product data sheet|-|PSMN1R6-30PL_1| |Modifications:|**•** Data sheet|status changed from objective to product.||| ||**•** Various content changes.|||| |PSMN1R6-30PL_1|20090518|Objective data sheet|-|-| © NXP B.V. 2009. All rights reserved. PSMN1R6-30PL_2 **Product data sheet** **Rev. 02 — 25 June 2009** **11 of 13** **PSMN1R6-30PL** **NXP Semiconductors** **N-channel 30 V 1.7 mΩ logic level MOSFET** ## **9. Legal information** ## **9.1 Data sheet status** |**Document status** **[1]**<br>**[2]**|**Product status[3]**|**Definition**| |---|---|---| |Objective [short] data sheet|Development|This document contains data from the objective specification for product development.| |Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.| |Product [short] data sheet|Production|This document contains the product specification.| - [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. ## **9.2 Definitions** **Draft** — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet** — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. ## **9.3 Disclaimers** **General** — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. **Right to make changes** — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **Suitability for use** — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. **Applications** — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. **Quick reference data** — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. **Limiting values** — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. **Terms and conditions of sale** — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. **No offer to sell or license** — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. **Export control** — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. ## **9.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. **TrenchMOS** — is a trademark of NXP B.V. ## **10. Contact information** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com © NXP B.V. 2009. All rights reserved. PSMN1R6-30PL_2 **Product data sheet** **Rev. 02 — 25 June 2009** **12 of 13** **PSMN1R6-30PL** **NXP Semiconductors** **N-channel 30 V 1.7 mΩ logic level MOSFET** ## **11. Contents** |**1**|**Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1**| |---|---| |1.1|General description . . . . . . . . . . . . . . . . . . . . . .1| |1.2|Features and benefits. . . . . . . . . . . . . . . . . . . . .1| |1.3|Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1| |1.4|Quick reference data . . . . . . . . . . . . . . . . . . . . .1| |**2**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . .2**| |**3**|**Ordering information. . . . . . . . . . . . . . . . . . . . . .2**| |**4**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3**| |**5**|**Thermal characteristics . . . . . . . . . . . . . . . . . . .4**| |**6**|**Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5**| |**7**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10**| |**8**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11**| |**9**|**Legal information. . . . . . . . . . . . . . . . . . . . . . . .12**| |9.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12| |9.2|Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12| |9.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12| |9.4|Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12| |**10**|**Contact information. . . . . . . . . . . . . . . . . . . . . .12**| Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. **==> picture [84 x 52] intentionally omitted <==** **© NXP B.V. 2009.** **All rights reserved.** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 25 June 2009 Document identifier: PSMN1R6-30PL_2**
Updated at February 9, 2023
Nexperia is a dedicated global leader in discretes, logic, and MOSFET devices. Built on over half a century of semiconductor expertise and operating independently since 2017, the company produces consistently reliable components at an exceptional volume of 85 billion units annually. With its own manufacturing facilities, Nexperia delivers industry-leading small packages that combine power and thermal efficiency with best-in-class quality, meeting the rigorous standards of the automotive sector. Our extensive Nexperia portfolio is heavily focused on discrete semiconductors, providing engineers with a robust selection of core building blocks. This includes a comprehensive range of diodes and rectifiers, featuring a vast selection of Zener single diodes and Schottky diodes designed for precise voltage regulation and efficient power routing. Additionally, we offer an expansive array of bipolar transistors and single MOSFETs tailored for reliable switching and amplification in demanding applications. Beyond these primary offerings, the lineup extends into specialized circuit protection and passive components. This includes transient voltage suppressor (TVS) diodes, Zener array diodes, and small signal diodes, alongside dual MOSFETs and fast recovery rectifiers. For comprehensive design needs, the selection also encompasses integrated passive filters, common mode chokes, and precision timers and oscillators, ensuring a complete solution for high-performance electronic systems.
About Novapart
Novapart is a B2B electronic component broker specialising in stock shortages and cost reduction. We source hard-to-find parts and identify compliant alternatives across a catalogue of 410,000+ components from 500+ manufacturers.
Learn more →Stock Shortage Specialist
When a component is unavailable, discontinued or has an unacceptable lead time, we tap into our network of vetted European and Asian distributors to source what you need — without compromising on quality or traceability.
Request a quote →Compliant Alternatives
We identify pin-to-pin, electrically equivalent substitutes that meet the same certifications (RoHS, AEC-Q100, REACH) as your original specification — validated against datasheets, not just part numbers. Often at a lower cost.
BOM Analysis service →