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PSMN1R5-30YL,115
Power MOSFET, N Channel, 30 V, 100 A, 1500 µohm, SOT-669, Surface Mount
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- Manufacturer: NEXPERIA
- Product type: Single MOSFETs
- Transistor Polarity:N Channel; Continuous Drain Current Id:100A; Drain Source Voltage Vds:30V; On Resistance Rds(on):0.0013ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:1.7V; Power
- MSL: MSL 1 - Unlimited
- SVHC: Lead (25-Jun-2025)
- No. of Pins: 4Pins
- Channel Type: N Channel
- Product Range: -
- Qualification: -
- Power Dissipation: 109W
- Transistor Mounting: Surface Mount
- Rds(on) Test Voltage: 10V
- Transistor Case Style: SOT-669
- Drain Source Voltage Vds: 30V
- Operating Temperature Max: 175°C
- Continuous Drain Current Id: 100A
- Drain Source On State Resistance: 1500µohm
- Gate Source Threshold Voltage Max: 1.7V
| Delivery and price | |
|---|---|
| Units per pack | 5000 |
| Price | 0.692 € |
| Current stock | 200+ |
| Lead time | 30 days |
Datasheet
## **PSMN1R5-30YL** ## **N-channel 30 V 1.5 mΩ logic level MOSFET in LFPAK** **Rev. 01 — 9 April 2010 Product data sheet** ## **1. Product profile** ## **1.1 General description** Logic level N-channel MOSFET in LFPAK package qualified to 175 °C. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. ## **1.2 Features and benefits** - Advanced TrenchMOS provides low RDSon and low gate charge - High efficiency gains in switching power convertors - Improved mechanical and thermal characteristics - LFPAK provides maximum power density in a Power SO8 package ## **1.3 Applications** - DC-to-DC converters - Lithium-ion battery protection - Motor control - Server power supplies - Load switching ## **1.4 Quick reference data** **Table 1. Quick reference data** |**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---|---| |VDS|drain-source|Tj≥25 °C; Tj≤175 °C||-|-|30|V| ||voltage||||||| |ID|drain current|Tmb= 25 °C; VGS= 10 V; see|[1]|-|-|100|A| |||Figure 1|||||| |Ptot|total power|Tmb= 25 °C; seeFigure 2||-|-|109|W| ||dissipation||||||| |Tj|junction|||-55|-|175|°C| ||temperature||||||| |**Static characteristics**|||||||| |RDSon|drain-source|VGS= 10 V; ID= 15 A;||-|-|2.4|mΩ| ||on-state|Tj= 100 °C; seeFigure 14|||||| ||resistance|VGS= 10 V; ID= 15 A;||-|1.3|1.5|mΩ| |||Tj= 25 °C|||||| |**Dynamic**|**characteristics**||||||| |QGD|gate-drain charge|VGS= 4.5 V; ID= 10 A;||-|8.7|-|nC| |||VDS= 12 V; see Figure 15<br>;see|||||| |||Figure 16|||||| **==> picture [172 x 101] intentionally omitted <==** **PSMN1R5-30YL** **NXP Semiconductors** **N-channel 30 V 1.5 mΩ logic level MOSFET in LFPAK** ## **Table 1. Quick reference data** _…continued_ |**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---| |QG(tot)|total gate charge|VGS= 4.5 V; ID= 10 A;|-|36.2|-|nC| |||VDS= 12 V; see Figure 15||||| |**Avalanche**|**ruggedness**|||||| |EDS(AL)S|non-repetitive|VGS= 10 V; Tj(init)= 25 °C;|-|-|241|mJ| ||drain-source|ID= 100 A; Vsup≤30 V;||||| ||avalanche energy|RGS= 50 Ω; unclamped||||| [1] Continuous current is limited by package. ## **2. Pinning information** **Table 2. Pinning information** |**Pin**|**Symbol**|**Description**|**Simplified outline**|**Simplified outline**|**Simplified outline**|**Simplified outline**|**Graphic symbol**||||| |---|---|---|---|---|---|---|---|---|---|---|---| |1|S|source|||||||||| |2|S|source||mb|||||D||| |3|S|source|||||||||| ||||||||G||||| |4|G|gate|||||||||| |mb|D|mounting base; connected to|||||_mbb076_||S||| |||drain|1|2|3|4|||||| ||||**SOT669**||**(LFPAK)**||||||| ## **3. Ordering information** **Table 3. Ordering information** |**Type number**|**Package**| |---|---| ||**Name**<br>**Description**<br>**Version**| |PSMN1R5-30YL|LFPAK<br>plastic single-ended surface-mounted package (LFPAK); 4 leads<br>SOT669| © NXP B.V. 2010. All rights reserved. PSMN1R5-30YL All information provided in this document is subject to legal disclaimers. **Rev. 01 — 9 April 2010** **Product data sheet** **2 of 15** **PSMN1R5-30YL** **NXP Semiconductors** **N-channel 30 V 1.5 mΩ logic level MOSFET in LFPAK** ## **4. Limiting values** ## **Table 4. Limiting values** _In accordance with the Absolute Maximum Rating System (IEC 60134)._ |**Symbol**|**Parameter**|**Conditions**||||**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---|---|---|---| |VDS|drain-source voltage|Tj≥25 °C; Tj≤175 °C||||-|-|30|V| |VDGR|drain-gate voltage|Tj≥25 °C; Tj≤175 °C; RGS= 20 kΩ||||-|-|30|V| |VGS|gate-source voltage|||||-20|-|20|V| |ID|drain current|VGS= 10 V; Tmb= 100 °C; seeFigure 1|[1]|||-|-|100|A| |||VGS= 10 V; Tmb= 25 °C; see Figure 1|[1]|||-|-|100|A| |IDM|peak drain current|tp≤10 µs; pulsed; Tmb= 25 °C;||||-|-|790|A| |||seeFigure 4|||||||| |Ptot|total power dissipation|Tmb= 25 °C; see Figure 2||||-|-|109|W| ||||||||||| |Tstg|storage temperature|||||-55|-|175|°C| |Tj|junction temperature|||||-55|-|175|°C| |**Source-drain**|**diode**||||||||| |IS|source current|Tmb= 25 °C|[1]|||-|-|100|A| |ISM|peak source current|tp≤10 µs; pulsed; Tmb= 25 °C||||-|-|790|A| |**Avalanche ruggedness**|||||||||| |EDS(AL)R|repetitive drain-source|seeFigure 3|[2]<br>[3]<br>[4]|||-|-|-|J| ||avalanche energy||||||||| |EDS(AL)S|non-repetitive|VGS= 10 V; Tj(init)= 25 °C; ID= 100 A;||||-|-|241|mJ| ||drain-source|Vsup≤30 V; RGS= 50 Ω; unclamped|||||||| ||avalanche energy||||||||| [1] Continuous current is limited by package. [2] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C. [3] Repetitive avalanche rating limited by average junction temperature of 170 °C. [4] Refer to application note AN10273 for further information. © NXP B.V. 2010. All rights reserved. PSMN1R5-30YL All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 01 — 9 April 2010** **3 of 15** **PSMN1R5-30YL** **NXP Semiconductors** **N-channel 30 V 1.5 mΩ logic level MOSFET in LFPAK** **==> picture [438 x 450] intentionally omitted <==** **----- Start of picture text -----**<br> 120 003aac446 120 03aa16<br>ID<br>(A)100 PF | tT (1) | | dt | | Pder<br>(%)<br>80 P| tf | | ft hI 80 .<br>FEPEPREH «| EN<br>60 P| | | ft NY \<br>40 EEA 40 CEN<br>20 P| tf | ft ft \ |<br>0 | | | | tT ty 0<br>0 |FEEEEEFE) 50 100 150 Tmb ( ° C)200 =| 0 COT 50 100 150 N- Tmb ( ° C)200<br>Ves = 10 V; (1) Capped at 100 A due to package Pp. - Prot ~ 100%<br>der Prot25°c)<br>Continuous drain current as a function of Fig 2. Normalized total power dissipation as a<br>mounting base temperature function of mounting base temperature<br>003aac266<br> 10 [3]<br>IAL<br>(A) a<br> 10 [2] Le (1)<br>(2)<br> 10 HSS<br>ao (3)<br> 1 BA A<br>|<br>10 [-1] PETIT TE TTIIE E LEVITT ETT<br>10 [-3] 10 [-2] 10 [-1] 1 tAL (ms) 10<br>**----- End of picture text -----**<br> **Fig 1. Continuous drain current as a function of Fig 2. Normalized total power dissipation as a mounting base temperature function of mounting base temperature** **Fig 3. Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time** © NXP B.V. 2010. All rights reserved. PSMN1R5-30YL All information provided in this document is subject to legal disclaimers. **Rev. 01 — 9 April 2010** **Product data sheet** **4 of 15** **PSMN1R5-30YL** **NXP Semiconductors** **N-channel 30 V 1.5 mΩ logic level MOSFET in LFPAK** **==> picture [480 x 563] intentionally omitted <==** **----- Start of picture text -----**<br> 003aad111<br> 10 [4]<br>ID<br>(A) po<br> 10 [3] i Limit RDSon = VDS / ID ee 10 μ s<br>ee<br> 10 [2] ed<br>(1) ed 100 μ s<br>aaa<br>1 ms<br> 10 a<br>aeea ee ea eeESee DC 10 ms<br> 1 Poe ELSE 100 ms<br>rr eee ee eee TT<br>10 [-1] 1 10 VDS (V) 10 [2]<br>Trp = 25 °CiIpyis single pulse<br>(1) Capped at 100 A due to package.<br>Fig 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage<br>5. Thermal characteristics<br>Table 5. Thermal characteristics<br>Symbol Parameter Conditions Min Typ Max Unit<br>Rth(j-mb) thermal resistance see Figure 5 - 0.5 1.1 K/W<br>from junction to<br>mounting base<br>003aac456<br> 10<br>Zth(j-mb)<br> (K/W) aa<br> 1 A<br>δ = 0.5<br>SSS 0.2 ee<br>10 [-1] 0.1<br>Smee remem mm seoeet<br>0.05 P δ = tp<br>10 [-2] Feeeel 0.02 IIHT| lil T Ul<br>single shot<br>tp t<br>10 [-3] aaa DDeel| T J 1<br>10 [-6] 10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] tp (s) 1<br>**----- End of picture text -----**<br> ## **5. Thermal characteristics** ## **Table 5. Thermal characteristics** **Fig 5. Transient thermal impedance from junction to mounting base as a function of pulse duration** © NXP B.V. 2010. All rights reserved. PSMN1R5-30YL All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 01 — 9 April 2010** **5 of 15** **PSMN1R5-30YL** **NXP Semiconductors** **N-channel 30 V 1.5 mΩ logic level MOSFET in LFPAK** ## **6. Characteristics** ## **Table 6. Characteristics** _Tested to JEDEC standards where applicable._ |**Symbol**<br>**Parameter**|**Conditions**|**Min**<br>**Typ**<br>**Max**<br>**Unit**| |---|---|---| |**Static characteristics**||| |V(BR)DSS<br>drain-source<br>breakdown voltage|ID= 20 A; VGS= 0 V; Tj= 25 °C; tav=<br>100 ns|35<br>-<br>-<br>V| ||ID= 250 µA; VGS= 0 V; Tj= 25 °C|30<br>-<br>-<br>V| ||ID= 250 µA; VGS= 0 V; Tj= -55 °C|27<br>-<br>-<br>V| |VGS(th)<br>gate-source threshold<br>voltage|ID= 1 mA; VDS= VGS; Tj= 25 °C;<br>seeFigure 12<br>;seeFigure 13|1.3<br>1.7<br>2.15<br>V| ||ID= 1 mA; VDS= VGS; Tj= 150 °C;<br>seeFigure 13|0.65<br>-<br>-<br>V| ||ID= 1 mA; VDS= VGS; Tj= -55 °C;<br>seeFigure 13|-<br>-<br>2.45<br>V| |||| |IDSS<br>drain leakage current|VDS= 30 V; VGS= 0 V; Tj= 25 °C|-<br>-<br>1<br>µA| ||VDS= 30 V; VGS= 0 V; Tj= 150 °C|-<br>-<br>100<br>µA| |IGSS<br>gate leakage current|VGS= 16 V; VDS= 0 V; Tj= 25 °C|-<br>-<br>100<br>nA| ||VGS= -16 V; VDS= 0 V; Tj= 25 °C|-<br>-<br>100<br>nA| |RDSon<br>drain-source on-state<br>resistance|VGS= 4.5 V; ID= 15 A; Tj= 25 °C|-<br>1.8<br>1.9<br>mΩ| ||VGS= 10 V; ID= 15 A; Tj= 150 °C;<br>seeFigure 14|-<br>-<br>2.8<br>mΩ| |||| ||VGS= 10 V; ID= 15 A; Tj= 100 °C;<br>seeFigure 14|-<br>-<br>2.4<br>mΩ| |||| ||VGS= 10 V; ID= 15 A; Tj= 25 °C|-<br>1.3<br>1.5<br>mΩ| |RG<br>gate resistance|f = 1 MHz|-<br>0.77<br>1.5<br>Ω| |**Dynamic characteristics**||| |QG(tot)<br>total gate charge|ID= 10 A; VDS= 12 V; VGS= 10 V;<br>seeFigure 15<br>;seeFigure 16|-<br>77.9<br>-<br>nC| ||ID= 0 A; VDS= 0 V; VGS= 10 V|-<br>70<br>-<br>nC| ||ID= 10 A; VDS= 12 V; VGS= 4.5 V;<br>seeFigure 15|-<br>36.2<br>-<br>nC| |QGS<br>gate-source charge|ID= 10 A; VDS= 12 V; VGS= 4.5 V;<br>seeFigure 15<br>;seeFigure 16|-<br>11.6<br>-<br>nC| |QGS(th)<br>pre-threshold<br>gate-source charge||-<br>8<br>-<br>nC| |QGS(th-pl)<br>post-threshold<br>gate-source charge||-<br>3.6<br>-<br>nC| |QGD<br>gate-drain charge||-<br>8.7<br>-<br>nC| |VGS(pl)<br>gate-source plateau<br>voltage|VDS= 12 V; see Figure 15<br>;<br>seeFigure 16|-<br>2.34<br>-<br>V| |Ciss<br>input capacitance|VDS= 12 V; VGS= 0 V; f = 1 MHz;<br>Tj= 25 °C; seeFigure 17|-<br>5057<br>-<br>pF| |Coss<br>output capacitance||-<br>1082<br>-<br>pF| |Crss<br>reverse transfer<br>capacitance||-<br>398<br>-<br>pF| © NXP B.V. 2010. All rights reserved. PSMN1R5-30YL **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 01 — 9 April 2010** **6 of 15** **PSMN1R5-30YL** **NXP Semiconductors** **N-channel 30 V 1.5 mΩ logic level MOSFET in LFPAK** **Table 6. Characteristics** _…continued_ ## _Tested to JEDEC standards where applicable._ |**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---| |td(on)|turn-on delay time|VDS= 12 V; RL= 0.5 Ω; VGS= 4.5 V;|-|46|-|ns| |tr|rise time|RG(ext)= 4.7 Ω|-|72|-|ns| |td(off)|turn-off delay time||-|76|-|ns| |tf|fall time||-|34|-|ns| |**Source-drain diode**|**Source-drain diode**|||||| |VSD|source-drain voltage|IS= 25 A; VGS= 0 V; Tj= 25 °C;|-|0.78|1.2|V| |||seeFigure 18||||| |trr|reverse recovery time|IS= 20 A; dIS/dt = -100 A/µs; VGS= 0 V;|-|45|-|ns| |Qr|recovered charge|VDS= 20 V|-|56|-|nC| **==> picture [464 x 242] intentionally omitted <==** **----- Start of picture text -----**<br> 003aac449 003aac450<br>300 5<br>ID<br>(A)250 = 1043.6 ee R(mDSon Ω ) PPTL EL<br>3.4 VGS (V) = 3.2 4<br>200 | Jee PELE EEE VGS (V) = 3.4<br>js 3<br>150 3 3.6<br>2.8 4<br>100 |[=ee<br>2<br>2.6 7<br>50<br>sRERREEEoe SERERREEE<br>a a ee 2.4 P| a<br>10<br>2.2<br>0 gonzeneees 1 ott<br>0 2 4 6 8 10 0 50 100 150 200 250<br>VDS (V) ID (A)<br>T, = 25°C; ty = 300ps T; = 25°C; ty = 300ps<br>Output characteristics: drain current as a Fig 7. Drain-source on-state resistance as a function<br>function of drain-source voltage; typical values of drain current; typical values<br>**----- End of picture text -----**<br> **Fig 6. Output characteristics: drain current as a function of drain-source voltage; typical values** © NXP B.V. 2010. All rights reserved. PSMN1R5-30YL All information provided in this document is subject to legal disclaimers. **Rev. 01 — 9 April 2010** **Product data sheet** **7 of 15** **PSMN1R5-30YL** **NXP Semiconductors** **N-channel 30 V 1.5 mΩ logic level MOSFET in LFPAK** **==> picture [467 x 500] intentionally omitted <==** **----- Start of picture text -----**<br> 003aac452 003aac455<br>200 8000<br>C Ciss<br>gfs<br> (pF)<br>(S)<br>150 6000<br>SEPRerEr] | BCE<br>tT yA LO Pt Tt tT yt<br>100 4000<br>TAL TT EL SS<br>C rss<br>50 fi ttt yy 2000 Te<br>AU} | tt ty Pt tt yt<br>See Piet<br>0 0<br>0 ETE 20 40 ETT 60 ID TT (A) 80 2 PE [TTT] 4 te 6 Tt 8 VGS (V) 10<br>Tj =25°C;Vp5 =15V Vps = OV; f = 1MHz<br>Forward transconductance as a function of Fig 9. Input and reverse transfer capacitances as a<br>drain current; typical values function of gate-source voltage; typical values<br>003aac451 003aad113<br>3.0 80<br>RDSon ID<br> (m Ω ) PAT TT Ty (A) Pt TTeT<br>2.5 60<br>PT TT Tt See<br>PA | Tt et Pt TT<br>2.0 40<br>NE Tj = 175 Ty ° C<br>pi Pt tt PT EAE<br>Tj = 25 ° C<br>1.5 20<br>PP MT TT eo<br>Pt IN| |RLYE oePt tT Pa<br>1.0 0<br>PEL ELE] Pt |LAA| T T<br>2 4 6 8 VGS (V) 10 0 1 2 3 VGS (V) 4<br>T;=25°CjIp =15A Vps= 15V<br>Drain-source on-state resistance as a function Fig 11. Transfer characteristics: drain current as a<br>of gate-source voltage; typical values function of gate-source voltage; typical values<br>**----- End of picture text -----**<br> **Fig 8. Forward transconductance as a function of drain current; typical values** **Fig 9. Input and reverse transfer capacitances as a function of gate-source voltage; typical values** **Fig 10. Drain-source on-state resistance as a function of gate-source voltage; typical values** All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. **Rev. 01 — 9 April 2010 8 of 15** PSMN1R5-30YL **Product data sheet** **8 of 15** **PSMN1R5-30YL** **NXP Semiconductors** **N-channel 30 V 1.5 mΩ logic level MOSFET in LFPAK** **==> picture [181 x 178] intentionally omitted <==** **----- Start of picture text -----**<br> 003aab271<br>10 [-1]<br>ID<br>(A)<br>10 [-2]<br>min typ max<br>10 [-3]<br>—— Ss<br>10 [-4]<br>fF<br>———<br>10 [-5]<br>ee<br>10 [-6] i<br>0 1 2 VGS (V) 3<br>**----- End of picture text -----**<br> **Fig 12. Sub-threshold drain current as a function of gate-source voltage** _03aa27_ **==> picture [184 x 180] intentionally omitted <==** **----- Start of picture text -----**<br> 2<br>a<br>1.51 a ftTierrt| aa| |aeTtdTT|<br>0.5<br>0<br>− 60 0 60 120 Tj ( ° C) 180<br>**----- End of picture text -----**<br> **Fig 14. Normalized drain-source on-state resistance factor as a function of junction temperature** **==> picture [189 x 417] intentionally omitted <==** **----- Start of picture text -----**<br> 003aac982<br>3<br>VGS(th)<br>(V) max<br>2<br>typ<br>SOKA<br>min<br>in ene<br>1 oN<br>oN<br>0<br>-60 0 60 120 Tj ( ° C) 180<br>ios tneMos= Ns tneMos= Ns= Ns Ns<br>Gate-source threshold voltage as a function of<br>junction temperature<br>VDS<br>ID<br>|'|\<br>VGS(pl) —____f_,<br>LA<br>VGS(th) Sf<br>VGS<br>QGS1 QGS2<br>QGS QGD<br>QG(tot)<br>003aaa508<br>**----- End of picture text -----**<br> ios tneMos= Ns tneMos= Ns= Ns Ns **Fig 13. Gate-source threshold voltage as a function of junction temperature** **Fig 15. Gate charge waveform definitions** All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. **Rev. 01 — 9 April 2010 9 of 15** PSMN1R5-30YL **Product data sheet** **9 of 15** **PSMN1R5-30YL** **NXP Semiconductors** **N-channel 30 V 1.5 mΩ logic level MOSFET in LFPAK** **==> picture [484 x 251] intentionally omitted <==** **----- Start of picture text -----**<br> 003aac448 003aac454<br>10 6000<br>VGS Ciss<br>(V) TEE C CTT TT TT<br>8 | | | | | [fA | (pF) Lee LM _|<br>Coss<br>4000<br>6 Senne an gt<br>V DS = 12 (V)<br>VDS = 19 (V)<br>4 at PILE<br>2000<br>fe SN<br>2 Crss<br>> 2055 a ea<br>0 POO 0 PCMecemtt<br>0 20 40 60 QG (nC) 80 10 [-1] 1 10 VDS (V) 10 [2]<br>T, 225°C, 2100 Ves = OV;f = 1MHz<br>Fig 16. Gate-source voltage as a function of gate Fig 17. Input, output and reverse transfer capacitances<br>charge; typical values as a function of drain-source voltage; typical<br>values<br>**----- End of picture text -----**<br> **==> picture [180 x 186] intentionally omitted <==** **----- Start of picture text -----**<br> 003aac447<br>100<br>IS Seen<br>(A)80 FEEFEEECO<br>60 FECESCEECECCRo<br>40 FECES<br>Tj = 150 ° C<br>Soaeeeeen<br>20 FEESCEC 25 ° C<br>0 FERRE ETO<br>0.0 0.2 0.4 0.6 0.8 1.0<br>VSD (V)<br>**----- End of picture text -----**<br> **Fig 18. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values** © NXP B.V. 2010. All rights reserved. PSMN1R5-30YL **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 01 — 9 April 2010** **10 of 15** **PSMN1R5-30YL** **NXP Semiconductors** **N-channel 30 V 1.5 mΩ logic level MOSFET in LFPAK** ## **7. Package outline** ## **Plastic single-ended surface-mounted package (LFPAK); 4 leads** ## **SOT669** **==> picture [478 x 570] intentionally omitted <==** **----- Start of picture text -----**<br> A2<br>E A C<br>b2 c2 E1<br>L1 b3<br>mounting<br>base b4<br>D1<br>H D<br>L2<br>1 2 3 4<br>X<br>e b w M A c<br>1/2 e<br>A<br>(A )3<br>A1 C<br>θ<br>L<br>detail X<br>y C<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT A A1 A2 A3 b b2 b3 b4 c c2 D [(1)] D1max [(1)] E [(1)] E1 [(1)] e H L L1 L2 w y θ<br>1.20 0.15 1.10 0.50 4.41 2.2 0.9 0.25 0.30 4.10 5.0 3.3 6.2 0.85 1.3 1.3 8 °<br>mm 1.01 0.00 0.95 0.25 0.35 3.62 2.0 0.7 0.19 0.24 3.80 4.20 4.8 3.1 1.27 5.8 0.40 0.8 0.8 0.25 0.1 0 °<br>Note<br>1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>04-10-13<br>SOT669 MO-235<br>06-03-16<br>**----- End of picture text -----**<br> ## **Fig 19. Package outline SOT669 (LFPAK)** All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. PSMN1R5-30YL **Product data sheet** **Rev. 01 — 9 April 2010** **11 of 15** **PSMN1R5-30YL** **NXP Semiconductors** **N-channel 30 V 1.5 mΩ logic level MOSFET in LFPAK** ## **8. Revision history** |**Table 7.**|**Revision**|**history**|||| |---|---|---|---|---|---| |**Document**|**ID**|**Release date**|**Data sheet status**|**Change notice**|**Supersedes**| |PSMN1R5-30YL_1||20100409|Product data sheet|-|-| © NXP B.V. 2010. All rights reserved. PSMN1R5-30YL All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 01 — 9 April 2010** **12 of 15** **PSMN1R5-30YL** **NXP Semiconductors** **N-channel 30 V 1.5 mΩ logic level MOSFET in LFPAK** ## **9. Legal information** ## **9.1 Data sheet status** |**Document status[1]**<br>**[2]**|**Product status[3]**|**Definition**| |---|---|---| |Objective [short] data sheet|Development|This document contains data from the objective specification for product development.| |Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.| |Product [short] data sheet|Production|This document contains the product specification.| [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. ## **9.2 Definitions** **Draft** — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet** — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. **Product specification** — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. ## **9.3 Disclaimers** **Limited warranty and liability** — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors. **Right to make changes** — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **Suitability for use** — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. **Applications** — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. **Quick reference data** — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. **Terms and conditions of commercial sale** — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. **No offer to sell or license** — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. **Export control** — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. PSMN1R5-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. **Product data sheet Rev. 01 — 9 April 2010 13 of 15** **PSMN1R5-30YL** **NXP Semiconductors** **N-channel 30 V 1.5 mΩ logic level MOSFET in LFPAK** **Non-automotive qualified products** — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. ## **9.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. **Adelante** , **Bitport** , **Bitsound** , **CoolFlux** , **CoReUse** , **DESFire** , **EZ-HV** , **FabKey** , **GreenChip** , **HiPerSmart** , **HITAG** , **I²C-bus** logo, **ICODE** , **I-CODE** , **ITEC** , **Labelution** , **MIFARE** , **MIFARE Plus** , **MIFARE Ultralight** , **MoReUse** , **QLPAK** , **Silicon Tuner** , **SiliconMAX** , **SmartXA** , **STARplug** , **TOPFET** , **TrenchMOS** , **TriMedia** and **UCODE** — are trademarks of NXP B.V. **HD Radio** and **HD Radio** logo — are trademarks of iBiquity Digital Corporation. ## **10. Contact information** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com © NXP B.V. 2010. All rights reserved. PSMN1R5-30YL All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 01 — 9 April 2010** **14 of 15** **PSMN1R5-30YL** **NXP Semiconductors** **N-channel 30 V 1.5 mΩ logic level MOSFET in LFPAK** ## **11. Contents** |**11. **|**Contents**| |---|---| |**1**|**Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1**| |1.1|General description . . . . . . . . . . . . . . . . . . . . . .1| |1.2|Features and benefits. . . . . . . . . . . . . . . . . . . . .1| |1.3|Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1| |1.4|Quick reference data . . . . . . . . . . . . . . . . . . . . .1| |**2**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . .2**| |**3**|**Ordering information. . . . . . . . . . . . . . . . . . . . . .2**| |**4**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3**| |**5**|**Thermal characteristics . . . . . . . . . . . . . . . . . . .5**| |**6**|**Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .6**| |**7**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . .11**| |**8**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . . .12**| |**9**|**Legal information. . . . . . . . . . . . . . . . . . . . . . . .13**| |9.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . .13| |9.2|Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .13| |9.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .13| |9.4|Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .14| |**10**|**Contact information. . . . . . . . . . . . . . . . . . . . . .14**| Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. **© NXP B.V. 2010.** **All rights reserved.** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 9 April 2010 Document identifier: PSMN1R5-30YL**
Updated at April 29, 2026
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