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PSMN102-200Y,115
Power MOSFET, N Channel, 200 V, 21.5 A, 0.086 ohm, LFPAK56, Surface Mount
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- Manufacturer: NEXPERIA
- Product type: Single MOSFETs
- MSL: MSL 1 - Unlimited
- SVHC: Lead (25-Jun-2025)
- No. of Pins: 4Pins
- Channel Type: N Channel
- Product Range: TrenchMOS
- Qualification: -
- Power Dissipation: 113W
- Transistor Mounting: Surface Mount
- Rds(on) Test Voltage: 10V
- Transistor Case Style: LFPAK56
- Drain Source Voltage Vds: 200V
- Operating Temperature Max: 150°C
- Continuous Drain Current Id: 21.5A
- Drain Source On State Resistance: 0.086ohm
- Gate Source Threshold Voltage Max: 3V
| Delivery and price | |
|---|---|
| Units per pack | 5000 |
| Price | 0.49 € |
| Current stock | 1000+ |
| Lead time | 30 days |
Datasheet
**==> picture [24 x 23] intentionally omitted <==** **----- Start of picture text -----**<br> LFPAK<br>**----- End of picture text -----**<br> ## **PSMN102-200Y** ## **N-channel TrenchMOS SiliconMAX standard level FET** **Rev. 03 — 16 March 2011** **Product data sheet** ## **1. Product profile** ## **1.1 General description** SiliconMAX standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. ## **1.2 Features and benefits** - Higher operating power due to low thermal resistance - Suitable for high frequency applications due to fast switching characteristics ## **1.3 Applications** - Class D amplifier - DC-to-DC converters - Motion control - Switched-mode power supplies ## **1.4 Quick reference data** ## **Table 1. Quick reference data** |**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---|---| |VDS|drain-source|Tj≥25 °C; Tj≤150 °C||-|-|200|V| ||voltage||||||| |ID|drain current|Tmb= 25 °C; VGS= 10 V;||-|-|21.5|A| |||seeFigure 1<br>;see Figure 3|||||| ||||||||| |Ptot|total power|Tmb= 25 °C; seeFigure 2||-|-|113|W| ||dissipation||||||| |**Static characteristics**|||||||| |RDSon|drain-source|VGS= 10 V; ID= 12 A;||-|86|102|mΩ| ||on-state|Tj= 25 °C; see Figure 9<br>;|||||| ||resistance|seeFigure 10|||||| ||||||||| |**Dynamic characteristics**|**Dynamic characteristics**||||||| |QGD|gate-drain charge|VGS= 10 V; ID= 12 A;||-|10.1|-|nC| |||VDS= 100 V; seeFigure 11<br>;|||||| |||seeFigure 12|||||| **PSMN102-200Y** **NXP Semiconductors** **N-channel TrenchMOS SiliconMAX standard level FET** ## **2. Pinning information** **Table 2. Pinning information** |**Pin**|**Symbol**|**Description**|**Simplified outline**|**Simplified outline**|**Simplified outline**|**Simplified outline**|**Graphic symbol**||||| |---|---|---|---|---|---|---|---|---|---|---|---| |1|S|source|||||||||| |2|S|source||mb|||||D||| |3|S|source|||||||||| ||||||||G||||| |4|G|gate|||||||||| |mb|D|mounting base; connected to|||||_mbb076_||S||| |||drain|1|2|3|4|||||| ||||**SOT669**||**(LFPAK)**||||||| ## **3. Ordering information** ## **Table 3. Ordering information** |**Type number**|**Package**| |---|---| ||**Name**<br>**Description**<br>**Version**| |PSMN102-200Y|LFPAK<br>plastic single-ended surface-mounted package (LFPAK); 4 leads<br>SOT669| ## **4. Limiting values** ## **Table 4. Limiting values** _In accordance with the Absolute Maximum Rating System (IEC 60134)._ |**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Max**<br>**Unit**| |---|---| |VDS<br>drain-source voltage|Tj≥25 °C; Tj≤150 °C<br>-<br>200<br>V| |VDGR<br>drain-gate voltage|Tj≥25 °C; Tj≤150 °C; RGS= 20 kΩ<br>-<br>200<br>V| |VGS<br>gate-source voltage|-20<br>20<br>V| |ID<br>drain current|VGS= 10 V; Tmb= 25 °C; see Figure 1<br>;<br>seeFigure 3<br>-<br>21.5<br>A| ||VGS= 10 V; Tmb= 100 °C; seeFigure 1<br>-<br>13.6<br>A| |IDM<br>peak drain current|pulsed; tp≤10 µs; Tmb= 25 °C;<br>seeFigure 3<br>-<br>65<br>A| ||| |Ptot<br>total power dissipation|Tmb= 25 °C; see Figure 2<br>-<br>113<br>W| |Tstg<br>storage temperature|-55<br>150<br>°C| |Tj<br>junction temperature|-55<br>150<br>°C| |**Source-drain diode**|| |IS<br>source current|Tmb= 25 °C<br>-<br>52<br>A| |ISM<br>peak source current|pulsed; tp≤10 µs; Tmb= 25 °C<br>-<br>208<br>A| |**Avalanche ruggedness**|| |EDS(AL)S<br>non-repetitive drain-source<br>avalanche energy|VGS= 10 V; Tj(init)= 25 °C; ID= 10.8 A;<br>Vsup≤200 V; unclamped; tp= 0.14 ms;<br>RGS= 50 Ω<br>-<br>202<br>mJ| © NXP B.V. 2011. All rights reserved. PSMN102-200Y **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 03 — 16 March 2011** **2 of 13** **PSMN102-200Y** **NXP Semiconductors** ## **N-channel TrenchMOS SiliconMAX standard level FET** **==> picture [436 x 186] intentionally omitted <==** **----- Start of picture text -----**<br> 003aac023 003aab937<br>120 120<br>Ider Pder<br>(%) (%)<br>80 80<br>40 40<br>0 0<br>0 50 100 150 200 0 50 100 150 200<br>Tmb ( ° C) Tmb ( ° C)<br>**----- End of picture text -----**<br> **==> picture [454 x 20] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 1. Normalized continuous drain current as a Fig 2. Normalized total power dissipation as a<br>function of mounting base temperature function of solder point temperature<br>**----- End of picture text -----**<br> **==> picture [436 x 187] intentionally omitted <==** **----- Start of picture text -----**<br> 003aab740<br>10 [3]<br>ID<br>(A) pS rti“<“‘iTSt:i“‘iTESSC TT<br>10 [2] Limit RDSon = VDS / ID<br>a a<br>ee<br>t p = 10 μ s<br>10 AeNaec cce SSN8 MEO ERD TESS eeee ee<br>100 μ s<br>SE<br>es ee er DC eee 1 ms eee ee<br>1<br>ee eee ee<br>10 ms<br>10 [−] [1] Ppeerti“—~sTti“‘“‘Y CTOeTT PTne eG SYeaeaiii 100 ms yt| dT LT<br>1 10 10 [2] 10 [3]<br>VDS (V)<br>**----- End of picture text -----**<br> **Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage** © NXP B.V. 2011. All rights reserved. PSMN102-200Y **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 03 — 16 March 2011** **3 of 13** **PSMN102-200Y** **NXP Semiconductors** **N-channel TrenchMOS SiliconMAX standard level FET** ## **5. Thermal characteristics** ## **Table 5. Thermal characteristics** **==> picture [497 x 279] intentionally omitted <==** **----- Start of picture text -----**<br> Symbol Parameter Conditions Min Typ Max Unit<br>Rth(j-mb) thermal resistance from Mounted on a printed-circuit board; - - 1.1 K/W<br>junction to mounting base vertical in still air; see Figure 4<br>003aac268<br>10<br>Zth(j-mb)<br>(K/W)<br>1<br>d = 0.5<br>0.2<br>10 [−] [1] 0.1<br>0.05<br>0.02 P δ = t p<br>T<br>10 [−] [2]<br>single shot<br>tp t<br>T<br>10 [−] [3]<br>10 [−] [6] 10 [−] [5] 10 [−] [4] 10 [−] [3] 10 [−] [2] 10 [−] [1] 1<br>tp (s)<br>Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration<br>**----- End of picture text -----**<br> © NXP B.V. 2011. All rights reserved. PSMN102-200Y **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 03 — 16 March 2011** **4 of 13** **PSMN102-200Y** **NXP Semiconductors** **N-channel TrenchMOS SiliconMAX standard level FET** ## **6. Characteristics** |**Table 6.**<br>**Characteristics**||| |---|---|---| |**Symbol**<br>**Parameter**|**Conditions**|**Min**<br>**Typ**<br>**Max**<br>**Unit**| |**Static characteristics**||| |V(BR)DSS<br>drain-source<br>breakdown voltage|ID= 250 µA; VGS= 0 V; Tj= 25 °C|200<br>-<br>-<br>V| ||ID= 250 µA; VGS= 0 V; Tj= -55 °C|178<br>-<br>-<br>V| |VGS(th)<br>gate-source threshold<br>voltage|ID= 1 mA; VDS= VGS; Tj= 25 °C;<br>seeFigure 7<br>;see Figure 8|2<br>3<br>4<br>V| ||ID= 1 mA; VDS= VGS; Tj= 150 °C;<br>seeFigure 7<br>;see Figure 8|1<br>-<br>-<br>V| ||ID= 1 mA; VDS= VGS; Tj= -55 °C;<br>seeFigure 7<br>;see Figure 8|-<br>-<br>4.4<br>V| |IDSS<br>drain leakage current|VDS= 160 V; VGS= 0 V; Tj= 25 °C|-<br>-<br>1<br>µA| ||VDS= 160 V; VGS= 0 V; Tj= 150 °C|-<br>-<br>100<br>µA| |IGSS<br>gate leakage current|VGS= 20 V; VDS= 0 V; Tj= 20 °C|-<br>-<br>100<br>nA| ||VGS= -20 V; VDS= 0 V; Tj= 20 °C|-<br>-<br>100<br>nA| |RDSon<br>drain-source on-state<br>resistance|VGS= 10 V; ID= 12 A; Tj= 25 °C;<br>seeFigure 9<br>;see Figure 10|-<br>86<br>102<br>mΩ| ||VGS= 10 V; ID= 12 A; Tj= 150 °C;<br>seeFigure 9<br>;see Figure 10|-<br>206<br>245<br>mΩ| |RG<br>gate resistance|f = 1 MHz|-<br>1.1<br>-<br>Ω| |**Dynamic characteristics**||| |QG(tot)<br>total gate charge|ID= 12 A; VDS= 100 V; VGS= 10 V;<br>seeFigure 11<br>;see Figure 12|-<br>30.7<br>-<br>nC| |QGS<br>gate-source charge||-<br>6.3<br>-<br>nC| |QGD<br>gate-drain charge||-<br>10.1<br>-<br>nC| |VGS(pl)<br>gate-source plateau<br>voltage|ID= 12 A; VDS= 100 V; see Figure 11<br>;<br>seeFigure 12|-<br>4.6<br>-<br>V| |Ciss<br>input capacitance|VDS= 30 V; VGS= 0 V; f = 1 MHz;<br>Tj= 25 °C; seeFigure 13|-<br>1568<br>-<br>pF| |Coss<br>output capacitance||-<br>170<br>-<br>pF| |Crss<br>reverse transfer<br>capacitance||-<br>55<br>-<br>pF| |td(on)<br>turn-on delay time|VDS= 100 V; RL= 5.8 Ω; VGS= 10 V;<br>RG(ext)= 5.6 Ω|-<br>14.2<br>-<br>ns| |tr<br>rise time||-<br>29.5<br>-<br>ns| |td(off)<br>turn-off delay time||-<br>33<br>-<br>ns| |tf<br>fall time||-<br>28<br>-<br>ns| |**Source-drain diode**||| |VSD<br>source-drain voltage|IS= 12 A; VGS= 0 V; Tj= 25 °C;<br>seeFigure 14|-<br>0.9<br>1.2<br>V| |trr<br>reverse recovery time|IS= 20 A; dIS/dt = -100 A/µs; VGS= 0 V;<br>VDS= 30 V|-<br>143<br>-<br>ns| |Qr<br>recovered charge|IS= 20 A; dIS/dt = -100 A/µs; VGS= 0 V|-<br>268<br>-<br>nC| © NXP B.V. 2011. All rights reserved. PSMN102-200Y **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 03 — 16 March 2011** **5 of 13** **PSMN102-200Y** **NXP Semiconductors** ## **N-channel TrenchMOS SiliconMAX standard level FET** **==> picture [435 x 434] intentionally omitted <==** **----- Start of picture text -----**<br> 003aab742 003aab744<br>40 50<br>ID VGS (V) = 10 ID VDS > ID × RDSon<br>ef ft | pp (A) ee<br>(A) 6<br>40<br>30<br>SEREED7a ee<br>Sane 268 30 TEE Tee<br>20<br>Tj = 150 ° C 25 ° C<br>5<br>20<br>10 _ Yj or 4.8 1<br> fo 10 Cee<br>4.6<br>Lf | e/a<br>4.4<br>4.2<br>0 == 0 PTCA TLE<br>0 1.25 2.5 3.75 5 0 2 4 6 8<br>VDS (V) VGS (V)<br>Tj = 25 °C Tj = 25 °C and 150 °C; VDS > ID x RDSon<br>Output characteristics: drain current as a Fig 6. Transfer characteristics: drain current as a<br>function of drain-source voltage; typical values function of gate-source voltage; typical values<br>003aac062 003aab852<br>10 [−] [1] 5<br>ID VGS(th)<br>(A) === (V) Soe<br>10 [−] [2] 4<br>ees oe ee max<br>— — | —--—- | | [nf tt<br>min typ max<br>10 [−] [3] 3<br>ee pgo-b]| typ PAA<br>10 [−] [4] 2<br>rr= SS >| |Pepe min<br>SS [=] |<br>10 [−] [5] a 1 Pe<br>SS SSeS p f}f te|p| tt|PAI<br>10 [−] [6] ee se 0 P| | | fttt t<br>0 2 4 6 − 60 0 60 120 160<br>VGS (V) Tj ( ° C)<br>**----- End of picture text -----**<br> **Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values** **Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values** **Fig 7. Sub-threshold drain current as a function of gate-source voltage** **Fig 8. Gate-source threshold voltage as a function of junction temperature** © NXP B.V. 2011. All rights reserved. PSMN102-200Y All information provided in this document is subject to legal disclaimers. **Rev. 03 — 16 March 2011** **Product data sheet** **6 of 13** **PSMN102-200Y** **NXP Semiconductors** ## **N-channel TrenchMOS SiliconMAX standard level FET** **==> picture [464 x 456] intentionally omitted <==** **----- Start of picture text -----**<br> 03al52 003aab743<br>3 200<br>4.5 5<br>a RDSon<br>(m Ω )<br>SA ee<br>2 160<br>V GS (V) = 6<br>10<br>HA Ge<br>1 120<br>et Bee<br>O TE<br>0 80<br>− 60 PTOCCcr 0 60 120 180 = 0 REESE 10 20 30 40<br>Tj ( ° C) ID (A)<br>ee Rosen Ty = 25°C<br>~ Rps oryv25°C)<br>Normalized drain-source on-state resistance Fig 10. Drain-source on-state resistance as a function<br>factor as a function of junction temperature of drain current; typical values<br> / 003aab746<br>10<br>VDS ___i VGS T ID j = 25 = 12 A ° C<br>ID (V) 8 n/n<br>i Seeee//2e<br>40<br>VGS(pl) SN e/a 100<br>6<br>—5H . e/a<br>VGS(th) V DS = 160 V<br>VGS 4<br>[ QGS1 | QGS2 | Pftet| | tT tt ft<br>QGS QGD 2 P/L | | tT tt<br>QG(tot)<br>fi | | tt ft |<br>003aaa508<br>0 Vi | i tt tf<br>0 10 20 30 40<br>QG (nC)<br>**----- End of picture text -----**<br> **Fig 9. Normalized drain-source on-state resistance factor as a function of junction temperature** **Fig 11. Gate charge waveform definitions** **Fig 12. Gate-source voltage as a function of gate charge; typical values** © NXP B.V. 2011. All rights reserved. PSMN102-200Y All information provided in this document is subject to legal disclaimers. **Rev. 03 — 16 March 2011** **Product data sheet** **7 of 13** **PSMN102-200Y** **NXP Semiconductors** ## **N-channel TrenchMOS SiliconMAX standard level FET** **==> picture [436 x 186] intentionally omitted <==** **----- Start of picture text -----**<br> 003aab747 003aab745<br>10 [4] 50<br>IS<br>C (A)<br>(pF) 40<br>EEE pp it |et<br>Ciss<br>10 [3]<br>Stl 30 eee<br>Tj = 150 ° C 25 ° C<br>Coss 20<br>10 [2] |St eeLTAee<br>Crss<br>Feet TL 10 elit] yyy |<br>10 Cee nn 0 TELAT<br>10 [−] [1] 1 10 10 [2] 0 0.3 0.6 0.9 1.2<br>VDS (V) VSD (V)<br>**----- End of picture text -----**<br> **Fig 13. Input, output and reverse transfer capacitances Fig 14. Source current as a function of source-drain as a function of drain-source voltage; typical voltage; typical values values** © NXP B.V. 2011. All rights reserved. PSMN102-200Y **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 03 — 16 March 2011** **8 of 13** **PSMN102-200Y** **NXP Semiconductors** **N-channel TrenchMOS SiliconMAX standard level FET** ## **7. Package outline** ## **Plastic single-ended surface-mounted package (LFPAK); 4 leads** ## **SOT669** **==> picture [478 x 570] intentionally omitted <==** **----- Start of picture text -----**<br> A2<br>E A C<br>b2 c2 E1<br>L1 b3<br>mounting<br>base b4<br>D1<br>H D<br>L2<br>1 2 3 4<br>X<br>e b w M A c<br>1/2 e<br>A<br>(A )3<br>A1 C<br>θ<br>L<br>detail X<br>y C<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT A A1 A2 A3 b b2 b3 b4 c c2 D [(1)] D1max [(1)] E [(1)] E1 [(1)] e H L L1 L2 w y θ<br>1.20 0.15 1.10 0.50 4.41 2.2 0.9 0.25 0.30 4.10 5.0 3.3 6.2 0.85 1.3 1.3 8 °<br>mm 1.01 0.00 0.95 0.25 0.35 3.62 2.0 0.7 0.19 0.24 3.80 4.20 4.8 3.1 1.27 5.8 0.40 0.8 0.8 0.25 0.1 0 °<br>Note<br>1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>04-10-13<br>SOT669 MO-235<br>06-03-16<br>**----- End of picture text -----**<br> **Fig 15. Package outline SOT669 (LFPAK)** PSMN102-200Y All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. **Product data sheet** **Rev. 03 — 16 March 2011** **9 of 13** **PSMN102-200Y** **NXP Semiconductors** **N-channel TrenchMOS SiliconMAX standard level FET** ## **8. Revision history** |**Table 7.**<br>**Revision**|**history**|||| |---|---|---|---|---| |**Document ID**|**Release date**|**Data sheet status**|**Change notice**|**Supersedes**| |PSMN102-200Y v.3|20110316|Product data sheet|-|PSMN102-200Y v.2| |Modifications:|**•** Various changes to content.|||| |PSMN102-200Y v.2|20101220|Product data sheet|-|PSMN102-200Y v.1| © NXP B.V. 2011. All rights reserved. PSMN102-200Y All information provided in this document is subject to legal disclaimers. **Rev. 03 — 16 March 2011** **Product data sheet** **10 of 13** **PSMN102-200Y** **NXP Semiconductors** **N-channel TrenchMOS SiliconMAX standard level FET** ## **9. Legal information** ## **9.1 Data sheet status** |**Document status** **[1]**<br> **[2]**|**Product status[3]**|**Definition**| |---|---|---| |Objective [short] data sheet|Development|This document contains data from the objective specification for product development.| |Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.| |Product [short] data sheet|Production|This document contains the product specification.| [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. ## **9.2 Definitions** **Draft** — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet** — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. **Product specification** — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. ## **9.3 Disclaimers** **Limited warranty and liability** — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors. **Right to make changes** — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **Suitability for use** — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. **Quick reference data** — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. **Applications** — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. **Limiting values** — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. **Terms and conditions of commercial sale** — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective © NXP B.V. 2011. All rights reserved. PSMN102-200Y **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 03 — 16 March 2011** **11 of 13** **PSMN102-200Y** ## **NXP Semiconductors** ## **N-channel TrenchMOS SiliconMAX standard level FET** agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. **No offer to sell or license** — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. **Export control** — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. **Non-automotive qualified products** — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. ## **9.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. **Adelante** , **Bitport** , **Bitsound** , **CoolFlux** , **CoReUse** , **DESFire** , **EZ-HV** , **FabKey** , **GreenChip** , **HiPerSmart** , **HITAG** , **I²C-bus** logo, **ICODE** , **I-CODE** , **ITEC** , **Labelution** , **MIFARE** , **MIFARE Plus** , **MIFARE Ultralight** , **MoReUse** , **QLPAK** , **Silicon Tuner** , **SiliconMAX** , **SmartXA** , **STARplug** , **TOPFET** , **TrenchMOS** , **TriMedia** and **UCODE** — are trademarks of NXP B.V. **HD Radio** and **HD Radio** logo — are trademarks of iBiquity Digital Corporation. ## **10. Contact information** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com © NXP B.V. 2011. All rights reserved. PSMN102-200Y **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 03 — 16 March 2011** **12 of 13** **PSMN102-200Y** **NXP Semiconductors** **N-channel TrenchMOS SiliconMAX standard level FET** ## **11. Contents** |**11. **|**Contents**| |---|---| |**1**|**Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1**| |1.1|General description . . . . . . . . . . . . . . . . . . . . . .1| |1.2|Features and benefits. . . . . . . . . . . . . . . . . . . . .1| |1.3|Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1| |1.4|Quick reference data . . . . . . . . . . . . . . . . . . . . .1| |**2**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . .2**| |**3**|**Ordering information. . . . . . . . . . . . . . . . . . . . . .2**| |**4**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2**| |**5**|**Thermal characteristics . . . . . . . . . . . . . . . . . . .4**| |**6**|**Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5**| |**7**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9**| |**8**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10**| |**9**|**Legal information. . . . . . . . . . . . . . . . . . . . . . . .11**| |9.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11| |9.2|Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11| |9.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .11| |9.4|Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12| |**10**|**Contact information. . . . . . . . . . . . . . . . . . . . . .12**| Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. **© NXP B.V. 2011.** **All rights reserved.** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 16 March 2011 Document identifier: PSMN102-200Y**
Updated at April 24, 2026
Nexperia is a dedicated global leader in discretes, logic, and MOSFET devices. Built on over half a century of semiconductor expertise and operating independently since 2017, the company produces consistently reliable components at an exceptional volume of 85 billion units annually. With its own manufacturing facilities, Nexperia delivers industry-leading small packages that combine power and thermal efficiency with best-in-class quality, meeting the rigorous standards of the automotive sector. Our extensive Nexperia portfolio is heavily focused on discrete semiconductors, providing engineers with a robust selection of core building blocks. This includes a comprehensive range of diodes and rectifiers, featuring a vast selection of Zener single diodes and Schottky diodes designed for precise voltage regulation and efficient power routing. Additionally, we offer an expansive array of bipolar transistors and single MOSFETs tailored for reliable switching and amplification in demanding applications. Beyond these primary offerings, the lineup extends into specialized circuit protection and passive components. This includes transient voltage suppressor (TVS) diodes, Zener array diodes, and small signal diodes, alongside dual MOSFETs and fast recovery rectifiers. For comprehensive design needs, the selection also encompasses integrated passive filters, common mode chokes, and precision timers and oscillators, ensuring a complete solution for high-performance electronic systems.
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