PSMN059-150Y,115

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LFPAK56<br>**----- End of picture text -----**<br>


## **PSMN059-150Y** 

## **N-channel TrenchMOS SiliconMAX standard level FET** 

**3 October 2013** 

## **Product data sheet** 

## **1. General description** 

SiliconMAX standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 

## **2. Features and benefits** 

- Higher operating power due to low thermal resistance 

- Suitable for high frequency applications due to fast switching characteristics 

## **3. Applications** 

- Class D amplifier 

- DC-to-DC converters 

- Motion control 

- Switched-mode power supplies 

## **4. Quick reference data** 

## **Table 1. Quick reference data** 

|**Symbol**<br>**Parameter**<br>~~I~~<br>~~es~~|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|VDS<br>drain-source voltage<br>~~es~~<br>~~ee~~<br>~~a~~|drain-source voltage<br>~~es~~<br>|Tj≥ 25 °C; Tj≤ 150 °C<br>~~en~~<br>|~~en~~<br>|-<br>~~en~~<br>~~ee~~<br>|-<br>~~en~~<br>~~ee~~<br>|150<br>~~en~~<br>~~ee~~<br>|V<br>~~en~~<br>~~ee~~<br>|
|ID<br>drain current<br>~~es~~<br>~~ee~~<br>~~a~~|drain current<br>~~es~~<br>|Tmb= 25 °C; VGS= 10 V;Fig. 1<br>; Fig. 3<br>~~en~~<br>|~~en~~<br>|-<br>~~en~~<br>~~ee~~<br>|-<br>~~en~~<br>~~ee~~<br>|43<br>~~en~~<br>~~ee~~<br>|A<br>~~en~~<br>~~ee~~<br>|
|Ptot<br>total power dissipation<br>~~ee~~<br>~~a ee~~|total power dissipation<br>~~es~~<br>~~ee~~|Tmb= 25 °C;Fig. 2<br>~~en~~<br>~~ee~~|~~en~~<br>~~ee~~|-<br>~~en~~<br>~~ee~~<br>~~ee~~|-<br>~~en~~<br>~~ee~~<br>~~ee~~|113<br>~~en~~<br>~~ee~~<br>~~ee~~|W<br>~~en~~<br>~~ee~~<br>~~ee~~|
|**Static characteristics**<br>~~ee ee~~<br>~~a ee~~<br>~~eee~~<br>~~ee~~||||||||
|RDSon<br>drain-source on-state<br>resistance<br>~~ee~~|drain-source on-state<br>resistance<br>~~ee~~|VGS= 10 V; ID= 12 A; Tj= 25 °C;<br>Fig. 9<br>; Fig. 10<br>~~ee~~<br>~~eee~~|~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|46<br>~~ee~~<br>~~ee~~|59<br>~~ee~~<br>~~ee~~|mΩ<br>~~ee~~<br>~~ee~~|
|**Dynamic characteristics**<br>~~ee~~<br>~~eee~~<br>~~ee~~<br>~~eeeee~~||||||||
|QGD<br>gate-drain charge<br>~~eee~~|gate-drain charge<br>~~eee~~|VGS= 10 V; ID= 12 A; VDS= 75 V;<br>Fig. 11<br>; Fig. 12<br>~~eee~~|~~ee~~|-<br>~~ee~~|9.1<br>~~ee~~|-<br>~~ee~~|nC<br>~~ee~~|



Scan or click this QR code to view the latest information for this product 

**NXP Semiconductors** 

**PSMN059-150Y** 

**N-channel TrenchMOS SiliconMAX standard level FET** 

## **5. Pinning information** 

## **Table 2. Pinning information** 

|**Pin**|**Symbol**|**Description**|**Simplified outline**|**Graphic symbol**|
|---|---|---|---|---|
|1|S|source|mb<br>1<br>2<br>3<br>4<br>**LFPAK56; Power-**<br>**SO8 (SOT669)**|S<br>D<br>G<br>_mbb076_|
|2|S|source|||
|3|S|source|||
|4|G|gate|||
|mb|D|mounting base; connected to<br>drain|||



## **6. Ordering information** 

## **Table 3. Ordering information** 

|**Type number**|**Package**|||
|---|---|---|---|
||**Name**|**Description**|**Version**|
|PSMN059-150Y|LFPAK56;<br>Power-SO8|Plastic single-ended surface-mounted package (LFPAK56;<br>Power-SO8); 4 leads|SOT669|



## **7. Marking** 

## **Table 4. Marking codes** 

|**Type number**|**Marking code**|
|---|---|
|PSMN059-150Y|059150|



## **8. Limiting values** 

## **Table 5. Limiting values** 

_In accordance with the Absolute Maximum Rating System (IEC 60134)._ 

|**Symbol**|**Parameter**|**Conditions**||**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|VDS|drain-source voltage|Tj≥ 25 °C; Tj≤ 150 °C||-|150|V|
|VDGR|drain-gate voltage|Tj≥ 25 °C; Tj≤ 150 °C; RGS= 20 Ω||-|150|V|
|VGS|gate-source voltage|||-20|20|V|
|ID|drain current|VGS= 10 V; Tmb= 25 °C; Fig. 1<br>; Fig. 3||-|43|A|
|||VGS= 10 V; Tmb= 100 °C;Fig. 1||-|27.7|A|
|IDM|peak drain current|pulsed; tp≤ 10 µs; Tmb= 25 °C; Fig. 3||-|129|A|
|Ptot|total power dissipation|Tmb= 25 °C; Fig. 2||-|113|W|
|Tstg|storage temperature|||-55|150|°C|



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**N-channel TrenchMOS SiliconMAX standard level FET** 

|**Symbol**|**Parameter**|**Conditions**||**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Tj|junction temperature|||-55|150|°C|
|**Source-drain diode**|||||||
|IS|source current|Tmb= 25 °C||-|52|A|
|ISM|peak source current|pulsed; tp≤ 10 µs; Tmb= 25 °C||-|208|A|
|**Avalanche ruggedness**|||||||
|EDS(AL)S|non-repetitive drain-source<br>avalanche energy|VGS= 10 V; Tj(init)= 25 °C; ID= 12.1 A;<br>Vsup≤ 150 V; unclamped; tp= 0.21 ms;<br>RGS= 50 Ω||-|255|mJ|



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003aac023 003aab937<br>120 120<br>Ider EERE EEE Pder EERREEEe<br>(%) (%)<br>80 ERNGEEEE 80 ENEREEEE<br>BERNER BENSEEEE<br>40 40<br>BEREKUEE PL] NT<br>ety PLT TNT<br>0 0<br>0 BERRA 50 100 150 200 0 Li 50 EITN 100 150 | 200<br>Tmb (°C) Tmb (°C)<br>Fig. 1. Normalized continuous drain current as a Fig. 2. Normalized total power dissipation as a<br>function of mounting base temperature function of solder point temperature<br>**----- End of picture text -----**<br>


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## **N-channel TrenchMOS SiliconMAX standard level FET** 

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**----- Start of picture text -----**<br>
003aab749<br>10 [3]<br>ID SSS Limit RDSon = VDS SSS / ID SSSSSSSSSE<br>(A) —a ee —Po ee eee<br>10 [2]<br>a Ne ee ee<br>——— >...ssRe tp = 10 µs EH<br>FEES eeee<br>10<br>SS SS SSSS 100 µs ==<br>1 ms<br>tsSSSee [SSS] ee eee ee ee eee | eme e e<br>DC<br>1 eg ee 10 ms<br>100 ms<br>TT  E<br>SS eeee<br>po tCis<br>10 [- 1] PETT<br>1 10 10 [2] 10 [3]<br>VDS (V)<br>**----- End of picture text -----**<br>


**Fig. 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage** 

## **9. Thermal characteristics** 

## **Table 6. Thermal characteristics** 

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**----- Start of picture text -----**<br>
Symbol Parameter Conditions Min Typ Max Unit<br>Rth(j-mb) thermal resistance mounted on a printed-circuit board; - - 1.1 K/W<br>from junction to vertical in still air; Fig. 4<br>mounting base<br>003aac268<br>10<br>Zth(j-mb)<br>(K/W) fT CE TE Ty<br>1 ra<br>d = 0.5<br>a a<br>0.2 |<br>10 [- 1] 0.1<br>0.05<br>0.02 P δ = tp<br>peer _| T<br>10 [- 2] Ee |<br>single shot<br>Po TT ~~ t p _ t l]<br>10 [- 3] fTaaahE ETT TT ee en | -| — T | | |<br>10 [- 6] 10 [- 5] 10 [- 4] 10 [- 3] 10 [- 2] 10 [- 1] 1<br>tp (s)<br>**----- End of picture text -----**<br>


**Fig. 4. Transient thermal impedance from junction to mounting base as a function of pulse duration** 

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**N-channel TrenchMOS SiliconMAX standard level FET** 

## **10. Characteristics** 

|**10. Characteristics**|**10. Characteristics**|||||||
|---|---|---|---|---|---|---|---|
|**Table 7.**<br>**Characteristics**||||||||
|**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**|
|**Static characteristics**||||||||
|V(BR)DSS|drain-source<br>breakdown voltage|ID= 250 µA; VGS= 0 V; Tj= 25 °C||150|-|-|V|
|||ID= 250 µA; VGS= 0 V; Tj= -55 °C||133|-|-|V|
|VGS(th)|gate-source threshold<br>voltage|ID= 1 mA; VDS= VGS; Tj= 25 °C;<br>Fig. 7<br>; Fig. 8||2|3|4|V|
|||ID= 1 mA; VDS= VGS; Tj= 150 °C;<br>Fig. 7<br>; Fig. 8||1|-|-|V|
|||ID= 1 mA; VDS= VGS; Tj= -55 °C;<br>Fig. 7<br>; Fig. 8||-|-|4.4|V|
|IDSS|drain leakage current|VDS= 120 V; VGS= 0 V; Tj= 25 °C||-|-|1|µA|
|||VDS= 120 V; VGS= 0 V; Tj= 150 °C||-|-|100|µA|
|IGSS|gate leakage current|VGS= 20 V; VDS= 0 V; Tj= 25 °C||-|-|100|nA|
|||VGS= -20 V; VDS= 0 V; Tj= 25 °C||-|-|100|nA|
|RDSon|drain-source on-state<br>resistance|VGS= 10 V; ID= 12 A; Tj= 25 °C;<br>Fig. 9<br>; Fig. 10||-|46|59|mΩ|
|||VGS= 10 V; ID= 12 A; Tj= 150 °C;<br>Fig. 9<br>; Fig. 10||-|101|135|mΩ|
|RG|gate resistance|f = 1 MHz||-|1.1|-|Ω|
|**Dynamic characteristics**||||||||
|QG(tot)|total gate charge|ID= 12 A; VDS= 75 V; VGS= 10 V;<br>Fig. 11<br>; Fig. 12||-|27.9|-|nC|
|QGS|gate-source charge|||-|6.3|-|nC|
|QGD|gate-drain charge|||-|9.1|-|nC|
|VGS(pl)|gate-source plateau<br>voltage|ID= 12 A; VDS= 75 V;Fig. 11<br>; Fig. 12||-|4.8|-|V|
|Ciss|input capacitance|VDS= 30 V; VGS= 0 V; f = 1 MHz;<br>Tj= 25 °C; Fig. 13||-|1529|-|pF|
|Coss|output capacitance|||-|208|-|pF|
|Crss|reverse transfer<br>capacitance|||-|66|-|pF|
|td(on)|turn-on delay time|VDS= 75 V; RL= 3 Ω; VGS= 10 V;<br>RG(ext)= 5.6 Ω||-|14.2|-|ns|
|tr|rise time|||-|42|-|ns|
|td(off)|turn-off delay time|||-|54.2|-|ns|
|tf|fall time|||-|11.1|-|ns|
|**Source-drain diode**||||||||
|VSD|source-drain voltage|IS= 12 A; VGS= 0 V; Tj= 25 °C; Fig. 14||-|0.9|1.2|V|
|PSMN059-150Y||All informationprovided in this document is subject to legal disclaimers.|||© NXP|N.V. 2013. All|rights reserved|



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**PSMN059-150Y** 

**N-channel TrenchMOS SiliconMAX standard level FET** 

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Symbol Parameter Conditions Min Typ Max Unit<br>trr reverse recovery time IS = 12 A; dIS/dt = -100 A/µs; VGS = 0 V; - 67 - ns<br>VDS = 30 V<br>Qr recovered charge IS = 12 A; dIS/dt = -100 A/µs; VGS = 0 V - 226 - nC<br>003aab751 003aab753<br>50 60<br>(A)ID BERRA 10 7 6 ID VDS > ID × RDSon<br>(A)<br>40<br>Co 45 fe<br>Pi | | war Scene<br>30 ft VGS (V) = 5.5 |<br>30<br>20 Z|<br>Tj = 150 °C 25 °C<br>5<br>fit 15 Ee pe<br>10 Zane<br>4 .5<br>0 F oT 0 pttLLY! iia TLtt<br>0 1 2 3 4 5 0 2 4 6 8<br>VDS (V) VGS (V)<br>Tj = 25 °C Tj = 25 °C and 150 °C; VDS > ID x RDSon<br>Fig. 5. Output characteristics: drain current as a Fig. 6. Transfer characteristics: drain current as a<br>function of drain-source voltage; typical values function of gate-source voltage; typical values<br>003aab852 003aab853<br>5 10 [- 1]<br>VGS(th) ID<br>(V) {i} } tt (A) == == min typ max<br>4 10 [- 2]<br>po] | max | ed<br>| {| [xy tt ===<br>3 10 [- 3]<br>yesh | typ PN eeSSa<br>2 10 [- 4]<br>ee ee min ee<br>{| {| fot Po ==<br>1 10 [- 5]<br>pf | | | | ve ee<br>ptt ttt tt SSSe<br>0 Pt | | | ty ft 10 [- 6] ns es<br>- 60 0 60 120 160 0 2 4 6<br>Tj (°C) VGS (V)<br>Fig. 7. Gate-source threshold voltage as a function of Fig. 8. Sub-threshold drain current as a function of<br>junction temperature gate-source voltage<br>**----- End of picture text -----**<br>


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**N-channel TrenchMOS SiliconMAX standard level FET** 

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03al51 003aab752<br>3 150<br>[CELL ELLLE RDSon TT 4.5 5 TP 5.5 pp<br>a (mΩ)<br>Htiti ttt tly, 120 PTE dE | | ee<br>ott tt TCO EE<br>2 CelePe ely VGS (V) = 6<br>FCLELEI AL 90 Tie<br>7<br>10<br>EERE PP<br>1 POELZ| 60 Ee| j ae<br>RSE LL -=————_ aan<br>EEE EE 30 Saeeeeeeee<br>eT<br>ee CEEee EEL Pf tee eee yd<br>0 PrEPELEEree ey 0 Pi Ett ttt et<br>- 75 - 25 25 75 125 175 0 10 20 30 40 50<br>Tj (°C) ID (A)<br>**----- End of picture text -----**<br>


**Fig. 9. Normalized drain-source on-state resistance factor as a function of junction temperature** 

**Fig. 10. Drain-source on-state resistance as a function of drain current; typical values** 

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**----- Start of picture text -----**<br>
003aab754<br>10<br>VDS VGS ID = 12 A<br>(V) Tj = 25 °C<br>— ID 8 TT 30 Y<br>75<br>VGS(pl)<br>6<br>oY ei 7/an<br>VVGS(th)GS : 4 vaneeee V DS  = 120 V<br>|| QGS1 QGS2 Py]| | ft ff<br>QGS QG D 2 PAT<br>QG(tot)<br>i | | tt<br>003aaa508 0 Yitt| | | tt f t e<br>Gate charge waveform definitions 0 7.5 15 22.5 30<br>QG (nC)<br>**----- End of picture text -----**<br>


**Fig. 11. Gate charge waveform definitions** 

**Fig. 12. Gate-source voltage as a function of gate charge; typical values** 

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## **N-channel TrenchMOS SiliconMAX standard level FET** 

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**----- Start of picture text -----**<br>
003aab755 003aab756<br>10 [4] 80<br>IS<br>C<br>A (X)<br>(pF)<br>ee ae ee ee Ciss 60<br>10 [3]<br>eT lll eff |] LP<br>a eee enn ]<br>SSSa 40 ef fo | | Upp<br>Coss 150 °C Tj = 25 °C<br>10 [2] TTUE SREPePT ill ee ee |<br>Crss 20<br>LT ETTTT<br>EE at ] [of U7 TI<br>a ee 7 7<br>10 A a 0 | | LAF LL<br>10 [- 1] 1 10 10 [2] 0 0.3 0.6 0.9 1.2<br>VDS (V) VSD (V)<br>**----- End of picture text -----**<br>


**Fig. 13. Input, output and reverse transfer capacitances Fig. 14. Source current as a function of source-drain as a function of drain-source voltage; typical voltage; typical values values** 

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**N-channel TrenchMOS SiliconMAX standard level FET** 

## **11. Package outline** 

**Plastic single-ended surface-mounted package (LFPAK56; Power-SO8); 4 leads** 

**SOT669** 

**==> picture [481 x 565] intentionally omitted <==**

**----- Start of picture text -----**<br>
E A A2 C<br>b2 c2 E1<br>L1 b3<br>mountingbase b4<br>D1<br>H D<br>L2<br>1 2 3 4<br>X<br>e b w A c<br>1/2 e<br>A (A3)<br>A1 C<br>q<br>L<br>detail X<br>y C<br>0 5 mm θ<br>scale 8 [°]<br>0 [°]<br>Dimensions (mm are the original dimensions)<br>Unit [(1)] A A1 A2 A3 b b2 b3 b4 c c2 D [(1)] D1 [(1)] E [(1)] E1 [(1)] e H L L1 L2 w y<br>max 1.20 0.15 1.10 0.50 4.41 2.2 0.9 0.25 0.30 4.10 4.20 5.0 3.3 6.2 0.85 1.3 1.3<br>mm nom 0.25 1.27 0.25 0.1<br>min 1.01 0.00 0.95 0.35 3.62 2.0 0.7 0.19 0.24 3.80 4.8 3.1 5.8 0.40 0.8 0.8<br>Note<br>1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. sot669_po<br>Outline References European Issue date<br>version IEC JEDEC JEITA projection<br>11-03-25<br>SOT669 MO-235<br>13-02-27<br>**----- End of picture text -----**<br>


## **Fig. 15. Package outline LFPAK56; Power-SO8 (SOT669)** 

PSMN059-150Y 

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© NXP N.V. 2013. All rights reserved 

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**Product data sheet** 

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**PSMN059-150Y** 

## **N-channel TrenchMOS SiliconMAX standard level FET** 

## **12. Legal information** 

## **12.1 Data sheet status** 

|**Document**<br>**status [1]**<br>**[2]**|**Product**<br>**status [3]**|**Definition**|
|---|---|---|
|Objective<br>[short] data<br>sheet|Development|This document contains data from<br>the objective specification for product<br>development.|
|Preliminary<br>[short] data<br>sheet|Qualification|This document contains data from the<br>preliminary specification.|
|Product<br>[short] data<br>sheet|Production|This document contains the product<br>specification.|



[1] Please consult the most recently issued document before initiating or completing a design. 

[2] The term 'short data sheet' is explained in section "Definitions". 

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 

## **12.2 Definitions** 

**Preview** — The document is a preview version only. The document is still subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 

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**Short data sheet** — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 

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## **12.3 Disclaimers** 

**Limited warranty and liability** — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. 

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**Quick reference data** — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 

**Applications** — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. 

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. 

**Limiting values** — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 

**Terms and conditions of commercial sale** — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 

**No offer to sell or license** — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the 

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**NXP Semiconductors** 

**PSMN059-150Y** 

**N-channel TrenchMOS SiliconMAX standard level FET** 

grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 

**Export control** — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 

**Non-automotive qualified products** — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. 

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 

**Translations** — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 

## **12.4 Trademarks** 

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 

**Adelante** , **Bitport** , **Bitsound** , **CoolFlux** , **CoReUse** , **DESFire** , **EZ-HV** , **FabKey** , **GreenChip** , **HiPerSmart** , **HITAG** , **I²C-bus** logo, **ICODE** , **I-CODE** , **ITEC** , **Labelution** , **MIFARE** , **MIFARE Plus** , **MIFARE Ultralight** , **MoReUse** , **QLPAK** , **Silicon Tuner** , **SiliconMAX** , **SmartXA** , **STARplug** , **TOPFET** , **TrenchMOS** , **TriMedia** and **UCODE** — are trademarks of NXP B.V. 

**HD Radio** and **HD Radio** logo — are trademarks of iBiquity Digital Corporation. 

© NXP N.V. 2013. All rights reserved 

PSMN059-150Y 

All information provided in this document is subject to legal disclaimers. 

**3 October 2013** 

**Product data sheet** 

**11 / 12** 

**NXP Semiconductors** 

**PSMN059-150Y** 

**N-channel TrenchMOS SiliconMAX standard level FET** 

## **13. Contents** 

|**13. **|**Contents**|
|---|---|
|**1**|**General description ............................................... 1**|
|**2**|**Features and benefits ............................................1**|
|**3**|**Applications ........................................................... 1**|
|**4**|**Quick reference data ............................................. 1**|
|**5**|**Pinning information ...............................................2**|
|**6**|**Ordering information .............................................2**|
|**7**|**Marking ...................................................................2**|
|**8**|**Limiting values .......................................................2**|
|**9**|**Thermal characteristics .........................................4**|
|**10**|**Characteristics .......................................................5**|
|**11**|**Package outline ..................................................... 9**|
|**12**|**Legal information .................................................10**|
|12.1|Data sheet status ............................................... 10|
|12.2|Definitions ...........................................................10|
|12.3|Disclaimers .........................................................10|
|12.4|Trademarks ........................................................ 11|



## **© NXP N.V. 2013. All rights reserved** 

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 3 October 2013** 

© NXP N.V. 2013. All rights reserved 

PSMN059-150Y 

All information provided in this document is subject to legal disclaimers. 

**3 October 2013** 

**Product data sheet** 

**12 / 12**