PSM03S93E5-A

## **< Dual-In-Line Package Intelligent Power Module > PSM03S93E5-A TRANSFER MOLDING TYPE INSULATED TYPE** 

- **OUTLINE MAIN FUNCTION AND RATINGS**  3 phase DC/AC inverter  500V / 3A (MOSFET) 

   -  N-side MOSFET open source 

   -  Built-in bootstrap diodes with current limiting resistor **APPLICATION**  AC 100~240Vrms(DC voltage:400V or below) class low power motor control 

   - **TYPE NAME** PSM03S93E5-A With over temperature protection 

## **INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS** 

- For P-side : Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection ● For N-side : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC), Over temperature protection (OT) 

- Fault signaling  : Corresponding to SC fault (N-side MOSFET), UV fault (N-side supply) and OT fault 

- Input interface  : 3, 5V line, Schmitt trigger receiver circuit (High Active) 

- ●UL Recognized : UL1557  File E323585 

## **INTERNAL CIRCUIT** 

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MOSFET1  P(24)<br>VUFB(2)<br>VVFB(3)<br>U(23)<br>MOSFET2<br>VWFB(4) re ey<br>HVIC<br>UP(5) V(22)<br>VP(6) ei L MOSFET3  e| | |<br>WP(7)<br>VP1(8)<br>W(21)<br>VNC(9)<br>MOSFET4<br>UN(10)<br>VN(11)<br>NU(20)<br>WN(12) MOSFET5<br>VN1(13)<br>LVIC<br>FO(14)<br>NV(19)<br>CIN(15)VNC(16) Tf MOSFET6<br>NW(18)<br>**----- End of picture text -----**<br>


Publication Date : October 2013 

1 

**< Dual-In-Line Package Intelligent Power Module > PSM03S93E5-A TRANSFER MOLDING TYPE INSULATED TYPE** 

**MAXIMUM RATINGS** (Tch = 25°C, unless otherwise noted) 

## **INVERTER PART** 

|Symbol|Parameter|Condition|Ratings|Unit|
|---|---|---|---|---|
|VDD|Supplyvoltage|Applied between P-NU,NV,NW|400|V|
|VDD(surge)|Supplyvoltage(surge)|Applied between P-NU,NV,NW|450|V|
|VDSS|Drain-source voltage||500|V|
|±ID|Each MOSFET drain current|TC= 25°C|3|A|
|±IDP|Each MOSFET drain current(peak)|TC= 25°C,less than 1ms|6|A|
|PD|Drain dissipation|TC= 25°C,per 1 chip|29.4|W|
|Tch|Channel temperature|(Note 1)|-20~+150|°C|



Note1: The maximum junction temperature rating of built-in power chips is 150°C(@Tc≤100°C).However, to ensure safe operation of DIPIPM, the average channel temperature should be limited to Tch(Ave)≤125°C (@Tc≤100°C). 

## **CONTROL (PROTECTION) PART** 

|Symbol|Parameter|Condition|Ratings|Unit|
|---|---|---|---|---|
|VD|Control supplyvoltage|Applied between VP1-VNC, VN1-VNC|20|V|
|VDB|Control supplyvoltage|Applied between VUFB-U, VVFB-V, VWFB-W|20|V|
|VIN|Input voltage|Applied between UP, VP, WP-VPC, UN, VN, WN-VNC|-0.5~VD+0.5|V|
|VFO|Fault output supplyvoltage|Applied between FO-VNC|-0.5~VD+0.5|V|
|IFO|Fault output current|Sink current at FOterminal|1|mA|
|VSC|Current sensinginput voltage|Applied between CIN-VNC|-0.5~VD+0.5|V|



## **TOTAL SYSTEM** 

|Symbol|Parameter|Condition|Ratings|Unit|
|---|---|---|---|---|
|VDD(PROT)|Self protection supply voltage limit<br>(Short circuit protectioncapability)|VD= 13.5~16.5V, Inverter Part<br>Tch = 125°C,non-repetitive,less than 2μs|400|V|
|TC|Module case operation temperature|Measurementpoint of Tc isprovided in Fig.1|-20~+100|°C|
|Tstg|Storage temperature||-40~+125|°C|
|Viso|Isolation voltage|60Hz, Sinusoidal, AC 1min, between connected all pins<br>and heat sinkplate|1500|Vrms|



Fig. 1: TC MEASUREMENT POINT 

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Control terminals<br>DIPIPM<br>11.6mm<br>3mm<br>IGBT chip position  Tc point<br>Heat sink side<br>Power terminals<br>**----- End of picture text -----**<br>


## **THERMAL RESISTANCE** 

|Symbol|Parameter|Condition|Limits|Limits|Limits|Unit|
|---|---|---|---|---|---|---|
||||Min.|Typ.|Max.||
|Rth(ch-c)Q|Junction to case thermal resistance(Note2)<br>|1/6 module|-|-|3.4|K/W|



Note 2: Grease with good thermal conductivity and long-term endurance should be applied evenly with about +100μm~+200μm on the contacting surface of DIPIPM and heat sink. The contacting thermal resistance between DIPIPM case and heat sink Rth(c-f) is determined by the thickness and the thermal conductivity of the applied grease. For reference, Rth(c-f) is about 0.3K/W (per 1/6 module, grease thickness: 20μm, thermal conductivity: 1.0W/m•k). 

Publication Date : October 2013 

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**< Dual-In-Line Package Intelligent Power Module > PSM03S93E5-A TRANSFER MOLDING TYPE INSULATED TYPE** 

## **ELECTRICAL CHARACTERISTICS** (Tch = 25°C, unless otherwise noted) **INVERTER PART** 

|Symbol|Parameter|Condition|Condition||Limits|Limits|Limits|Unit|
|---|---|---|---|---|---|---|---|---|
||||||Min.|Typ.|Max.||
|VDS(on)|Drain-source on-state<br>resistance|VD=VDB= 15V, VIN= 5V, ID= 3A||Tch= 25°C|-|1.50|2.00|Ω|
|||||Tch= 125°C|-|3.40|4.50||
|VSD|Source-drain voltage drop|VIN= 0V, -ID= 3A|||-|0.90|1.30|V|
|ton|Switching times|VDD= 300V, VD= VDB= 15V<br>ID= 3A, Tch= 125°C, VIN= 0↔5V<br>Inductive Load (upper-lower arm)|||0.65|1.15|1.65|μs|
|tC(on)|||||-|0.35|0.55|μs|
|toff|||||-|1.00|1.50|μs|
|tC(off)|||||-|0.10|0.20|μs|
|trr|||||-|0.25|-|μs|
|IDSS|Drain-source cut-off<br>current|VDS=VDSS||Tch= 25°C|-|-|1|mA|
|||||Tch= 125°C|-|-|10||
|**CONTROL(PROTECTION) PART**|||||||||
|Symbol|Parameter|Condition|||Limits|||Unit|
||||||Min.|Typ.|Max.||
|ID|Circuit current|Total of VP1-VNC, VN1-VNC|VD=15V, VIN=0V||-|-|2.80|mA|
||||VD=15V,VIN=5V||-|-|2.80||
|IDB||Each part of VUFB-U,<br>VVFB-V, VWFB-W|VD=VDB=15V,VIN=0V||-|-|0.10||
||||VD=VDB=15V, VIN=5V||-|-|0.10||
|VSC(ref)|Short circuit triplevel|VD= 15V|(Note 3)||0.43|0.48|0.53|V|
|UVDBt|P-side Control supply<br>under-voltage protection(UV)|Tch ≤125°C|Triplevel||7.0|10.0|12.0|V|
|UVDBr|||Reset level||7.0|10.0|12.0|V|
|UVDt|N-side Control supply<br>under-voltage protection(UV)||Triplevel||10.3|-|12.5|V|
|UVDr|||Reset level||10.8|-|13.0|V|
|OTt|Over temperature protection<br>(OT)                 (Note4)|VD= 15V<br>Detect LVIC temperature|Triplevel||100|120|140|°C|
|OTrh|||Hysteresis of trip-reset||-|10|-|°C|
|VFOH|Fault output voltage|VSC= 0V, FOterminalpulled upto 5V by10kΩ|||4.9|-|-|V|
|VFOL||VSC= 1V, IFO= 1mA|||-|-|0.95|V|
|tFO|Fault outputpulse width|(Note 5)|||20|-|-|μs|
|IIN|Input current|VIN= 5V|||0.70|1.00|1.50|mA|
|Vth(on)|ON threshold voltage|Applied between UP, VP, WP, UN, VN, WN-VNC|||-|2.10|2.60|V|
|Vth(off)|OFFthresholdvoltage||||0.80|1.30|-||
|Vth(hys)|ON/OFF threshold<br>hysteresis voltage||||0.35|0.65|-||
|VF|BootstrapDi forward voltage|IF=10mA includingvoltage dropbylimitingresistor<br>(Note 6)|||1.1|1.7|2.3|V|
|R|Built-in limitingresistance|Included in bootstrapDi|||80|100|120|Ω|



Note 3 : SC protection works for N-side only. Please select the external shunt resistance such that the SC trip-level is less than 1.7 times of the current rating. 4 : When the LVIC temperature exceeds OT trip temperature level(OTt), OT protection works and Fo outputs. In that case if the heat sink dropped off or fixed loosely, don't reuse that DIPIPM. (There is a possibility that channel temperature of power chips exceeded maximum Tch(150°C). 

5 : Fault signal Fo outputs when SC, UV or OT protection works. Fo pulse width is different for each protection modes. At SC failure, Fo pulse width is a fixed width (=minimum 20μs), but at UV or OT failure, Fo outputs continuously until recovering from UV or OT state. (But minimum Fo pulse width is 20μs.) 6 : The characteristics of bootstrap Di is described in Fig.2. 

Fig. 2 Characteristics of bootstrap Di VF-IF curve (@Ta=25°C) including voltage drop by limiting resistor (Right chart is enlarged chart.) 

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160 30<br>140<br>25<br>120<br>100 20<br>80 15<br>60<br>10<br>40<br>20 5<br>0 0<br>0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5<br>VF [V] VF [V]<br> [mA]IF I [mA]F<br>**----- End of picture text -----**<br>


Publication Date : October 2013 

3 

**< Dual-In-Line Package Intelligent Power Module > PSM03S93E5-A TRANSFER MOLDING TYPE INSULATED TYPE** 

## **MECHANICAL CHARACTERISTICS AND RATINGS** 

|Parameter|Condition|Condition|Limits|Limits|Limits|Unit|
|---|---|---|---|---|---|---|
||||Min.|Typ.|Max.||
|Mountingtorque|Mountingscrew : M3(Note 8)|Recommended  0.69N·m|0.59|0.69|0.78|N·m|
|Terminal pulling strength|Control terminal: Load 4.9N<br>Powerterminal: Load 9.8N|EIAJ-ED-4701|10|-|-|s|
|Terminal bending strength|Control terminal: Load 2.45N<br>Power terminal: Load 4.9N<br>90deg. bend|EIAJ-ED-4701|2|-|-|times|
|Weight|||-|8.5|-|g|
|Heat-sink flatness|(Note 9)||-50|-|100|μm|



Note 8: Plain washers (ISO 7089~7094) are recommended. 

Note 9: Measurement point of heat sink flatness 

|**RECOMMENDED OPERATION CONDITIONS**<br>Heat sink side<br>+-|**RECOMMENDED OPERATION CONDITIONS**<br>Heat sink side<br>+-|sink side<br>+-|sink side<br>+-||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||||||||||||||||
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||||||Measurem||||ent position||||||||||
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||||||||||17.5mm||||||||||
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||||||-<br>+||||||||||||||
||||||||||H||||||||||
|Symbol|Parameter||||||||Condition||||||Limits|||Unit|
||||||||||||||||Min.|Typ.|Max.||
|VCC|Supplyvoltage||Applied between P-NU, NV, NW||||||||||||0|300|400|V|
|VD|Control supplyvoltage||Applied between VP1-VNC,VN1-VNC||||||||||||13.5|15.0|16.5|V|
|VDB|Control supplyvoltage||Applied between VUFB-U, VVFB-V, VWFB-W||||||||||||13.0|15.0|18.5|V|
|ΔVD, ΔVDB|Control supplyvariation||||||||||||||-1|-|+1|V/μs|
|tdead|Arm shoot-through blockingtime||For each input signal||||||||||||1.0|-|-|μs|
|fPWM|PWM input frequency||TC≤ 100°C,Tch ≤ 125°C||||||||||||-|-|20|kHz|
|IO|Allowable r.m.s. current||VDD= 300V, VD= 15V, P.F = 0.8,<br>Sinusoidal PWM<br>TC≤ 100°C, Tch ≤ 125°C(Note10)||||||||||fPWM= 5kHz||-|-|1.5|Arms|
||||||||||||||fPWM= 15kHz||-|-|1.2||
|PWIN(on)|Minimum input pulse width||||||||||||(Note 11)||0.7|-|-|μs|
|PWIN(off)|||||||||||||||0.7|-|-||
|VNC|VNCvariation||Between VNC-NU,NV,NW(includingsurge)||||||||||||-5.0|-|+5.0|V|
|Tch|Channel temperature||||||||||||||-20|-|+125|°C|



Note 10: Allowable r.m.s. current depends on the actual application conditions. 

11: DIPIPM might not make response if the input signal pulse width is less than PWIN(on), PWIN(off). 

Publication Date : October 2013 

4 

**< Dual-In-Line Package Intelligent Power Module > PSM03S93E5-A TRANSFER MOLDING TYPE INSULATED TYPE** 

## Fig. 3 Timing Charts of The DIPIPM Protective Functions 

## [A] Short-Circuit Protection (N-side only with the external shunt resistor and RC filter) 

a1. Normal operation: MOSFET ON and outputs current. 

a2. Short circuit current detection (SC trigger) 

(It is recommended to set RC time constant 1.5~2.0μs so that MOSFET shut down within 2.0μs when SC.) 

a3. All N-side MOSFET's gates are hard interrupted. 

a4. All N-side MOSFETs turn OFF. 

a5. FO outputs for tFo=minimum 20μs. 

a6. Input = “L”: MOSFET OFF 

- a7. Fo finishes output, but MOSFETs don't turn on until inputting next ON signal (LH). 

(MOSFET of each phase can return to normal state by inputting ON signal to each phase.) 

a8. Normal operation: MOSFET ON and outputs current. 

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Lower-side control<br>input  a6<br>SET  RESET<br>Protection circuit state<br>a3<br>Internal gate<br>a4<br>SC trip current level<br>a8<br>Output current ID a1  a7<br>a2<br>SC reference voltage<br>Sense voltage of<br>the shunt resistor<br>Delay by RC filtering<br>Error output Fo  a5<br>**----- End of picture text -----**<br>


## [B] Under-Voltage Protection (N-side, UVD) 

b1. Control supply voltage V D exceeds under voltage reset level (UVDr), but MOSFET turns ON by next ON signal (LH). (MOSFET of each phase can return to normal state by inputting ON signal to each phase.) 

b2. Normal operation: MOSFET ON and outputs current. 

b3. VD level drops to under voltage trip level. (UVDt). 

b4. All N-side MOSFETs turn OFF in spite of control input condition. 

b5. Fo outputs for tFo=minimum 20μs, but output is extended during VD keeps below UVDr. 

b6. VD level reaches UVDr. 

b7. Normal operation: MOSFET ON and outputs current. 

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Control input<br>Protection circuit state  RESET  SET RESET<br>Control supply voltage VD UVDr b1  UVDt b3  b6<br>b2  b4  b7<br>Output current ID<br>Error output Fo  b5<br>**----- End of picture text -----**<br>


Publication Date : October 2013 

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**< Dual-In-Line Package Intelligent Power Module > PSM03S93E5-A TRANSFER MOLDING TYPE INSULATED TYPE** 

## [C] Under-Voltage Protection (P-side, UVDB) 

- c1. Control supply voltage VDB rises. After the voltage reaches under voltage reset level UVDBr, MOSFET turns on by next ON signal (LH). c2. Normal operation: MOSFET ON and outputs current. 

- c3. VDB level drops to under voltage trip level (UVDBt). 

- c4. MOSFET of the correspond phase only turns OFF in spite of control input signal level, but there is no FO signal output. c5. VDB level reaches UVDBr. 

c6. Normal operation: MOSFET ON and outputs current. 

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Control input<br>R ESET  SET<br>RESET<br>Protection circuit state<br>UVDBr c3<br>Control supply voltage VDB c1  UVDBt c5<br>c2  c4  c6<br>Output current ID<br>Error output Fo  Keep High-level (no fault output)<br>**----- End of picture text -----**<br>


## [D] Over Temperature Protection (N-side, Detecting LVIC temperature) 

- d1. Normal operation: MOSFET ON and outputs current. 

- d2. LVIC temperature exceeds over temperature trip level(OTt). 

- d3. All N-side MOSFETs turn OFF in spite of control input condition. 

- d4. Fo outputs for tFo=minimum 20μs, but output is extended during LVIC temperature keeps over OTt. 

- d5. LVIC temperature drops to over temperature reset level. 

- d6. Normal operation: MOSFET turns on by next ON signal (LH). 

(MOSFET of each phase can return to normal state by inputting ON signal to each phase.) 

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Control input<br>Protection circuit state  SET RESET<br>d2<br>OTt<br>d5<br>Temperature of LVIC<br>OTt - OTrh<br>d1  d3  d6<br>Output current ID<br>d4<br>Error output Fo<br>**----- End of picture text -----**<br>


Publication Date : October 2013 

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**< Dual-In-Line Package Intelligent Power Module > PSM03S93E5-A TRANSFER MOLDING TYPE INSULATED TYPE** 

Fig. 4 Example of Application Circuit 

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Bootstrap negative electrodes<br>should be connected to U,V,W<br>terminals directly and separated<br>from the main output wires<br>P(24)<br>C1 D1 C2  VUFB(2)  MOSFET1<br>+<br>VVFB(3)<br>+ U(23)<br>MOSFET2<br>VWFB(4)<br>+<br>HVIC<br>UP(5)  V(22)<br>M<br>VP(6)<br>MOSFET3<br>WP(7)<br>VP1(8)<br>C2 W(21)<br>+<br>VNC(9)<br>MOSFET4 C3<br>UN(10)<br>VN(11)<br>NU(20)<br>WN(12)<br>5V  MOSFET5<br>Fo(14)<br>LVIC<br>NV(19)<br>MOSFET6<br>15V VD VN1(13)  NW(18)  Long wiring might cause<br>C1 +D1  C2 VNC(16)  short circuit failure<br>Long wiring might cause SC level  C<br>fluctuation and malfunction.<br>CIN(15)<br>B  D<br>Long GND wiring might generate  R1  Shunt<br>C4<br>noise to input signal and cause  resistor<br>MOSFET malfunction. A  N1<br>Control GND wiring  Power GND wiring<br>MCU<br>**----- End of picture text -----**<br>


- (1) If control GND is connected with power GND by common broad pattern, it may cause malfunction by power GND fluctuation. It is recommended to connect control GND and power GND at only a point N1 (near the terminal of shunt resistor). 

- (2) It is recommended to insert a Zener diode D1(24V/1W) between each pair of control supply terminals to prevent surge destruction. (3) To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible. Generally a 0.1-0.22μF snubber capacitor C3 between the P-N1 terminals is recommended. 

- (4) R1, C4 of RC filter for preventing protection circuit malfunction is recommended to select tight tolerance, temp-compensated type. The time constant R1C4 should be set so that SC current is shut down within 2μs. (1.5μs~2μs is general value.) SC interrupting time might vary with the wiring pattern, so the enough evaluation on the real system is necessary. 

- (5) To prevent malfunction, the wiring of A, B, C should be as short as possible. 

- (6) The point D at which the wiring to CIN filter is divided should be near the terminal of shunt resistor. NU, NV, NW terminals should be connected at near NU, NV, NW terminals. 

- (7) All capacitors should be mounted as close to the terminals as possible. (C1: good temperature, frequency characteristic electrolytic type and C2:0.22μ-2μF, good temperature, frequency and DC bias characteristic ceramic type are recommended.) 

- (8) Input drive is High-active type. There is a minimum 3.3kΩ pull-down resistor in the input circuit of IC. To prevent malfunction, the wiring of each input should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on and turn-off threshold voltage. 

- (9) Fo output is open drain type. It should be pulled up to MCU or control power supply (e.g. 5V,15V) by a resistor that makes IFo up to 1mA. (IFO is estimated roughly by the formula of control power supply voltage divided by pull-up resistance. In the case of pulled up to 5V, 10kΩ (5kΩ or more) is recommended.) 

- (10) Thanks to built-in HVIC, direct coupling to MCU without any opto-coupler or transformer isolation is possible. 

- (11) Two VNC terminals (9 & 16 pin) are connected inside DIPIPM, please connect either one to the 15V power supply GND outside and leave another one open. 

- (12) If high frequency noise superimposed to the control supply line, IC malfunction might happen and cause DIPIPM erroneous operation. To avoid such problem, line ripple voltage should meet dV/dt ≤+/-1V/μs, Vripple≤2Vp-p. 

- (13) For DIPIPM, it isn't recommended to drive same load by parallel connection with other phase MOSFET or other DIPIPM. 

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**< Dual-In-Line Package Intelligent Power Module > PSM03S93E5-A TRANSFER MOLDING TYPE INSULATED TYPE** 

Fig. 5 MCU I/O Interface Circuit 

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5V line<br>10kΩ DIPIPM<br>UP,VP,WP,UN,VN,WN<br>MCU<br>Fo  3.3kΩ(min)<br>VNC(Logic)<br>**----- End of picture text -----**<br>


Note) 

Design for input RC filter depends on PWM control scheme used in the application and wiring impedance of the printed circuit board. DIPIPM input signal interface integrates a minimum 3.3kΩ pull-down resistor. Therefore, when inserting RC filter, it is necessary to satisfy turn-on threshold voltage requirement. Fo output is open drain type. It should be pulled up to control power supply (e.g. 5V, 15V) with a resistor that makes Fo sink current IFo 1mA or less. In the case of pulled up to 5V supply, 10kΩ （5kΩ or more） is recommended. 

## Fig. 6 Pattern Wiring Around the Shunt Resistor 

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NU, NV, NW should be connected<br>each other at near terminals.<br>DIPIPM  DIPIPM<br>Wiring Inductance should be less than 10nH.  Each wiring Inductance should be less than 10nH.<br>Inductance of a copper pattern with  Inductance of a copper pattern with<br>length=17mm, width=3mm is about 10nH.  length=17mm, width=3mm is about 10nH.<br>NU NV  N1  NU  N1<br>NV<br>NW<br>VNC Shunt  VNC NW<br>resistor  GND wiring from VNC should  Shunt  GND wiring from VNC should<br>be connected close to the  resistors  be connected close to the<br>terminal of shunt resistor. terminal of shunt resistor.<br>**----- End of picture text -----**<br>


Low inductance shunt resistor like surface mounted (SMD) type is recommended. 

## Fig. 7 Pattern Wiring Around the Shunt Resistor (for the case of open source) 

When DIPIPM is operated with three shunt resistors, voltage of each shunt resistor cannot be input to CIN terminal directly. In that case, it is necessary to use the external protection circuit as below. 

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DIPIPM<br>Drive circuit<br>P<br>P-side MOSFETs<br>U<br>V External protection circuit<br>W<br>N-side MOSFETs Comparators<br>(Open collector output type)<br>C Rf B<br>NW -  5V<br>NV Cf Vref  +<br>NU<br>Drive circuit  -<br>Protection circuit  D  Vref  +  OR output<br>VNC CIN<br>Shunt  -<br>A  resistors  Vref  +<br>N1<br>**----- End of picture text -----**<br>


- (1) It is necessary to set the time constant RfCf of external comparator input so that MOSFET stops within 2μs when short circuit occurs. SC interrupting time might vary with the wiring pattern, comparator speed and so on. 

- (2) It is recommended for the threshold voltage Vref to set to the same rating of short circuit trip level (Vsc(ref): typ. 0.48V). 

- (3) Select the external shunt resistance so that SC trip-level is less than specified value (=1.7 times of rating current). 

- (4) To avoid malfunction, the wiring A, B, C should be as short as possible. 

- (5) The point D at which the wiring to comparator is divided should be close to the terminal of shunt resistor. 

- (6) OR output high level when protection works should be over 0.53V (=maximum Vsc(ref) rating). 

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**< Dual-In-Line Package Intelligent Power Module > PSM03S93E5-A TRANSFER MOLDING TYPE INSULATED TYPE** 

## Fig. 8 Package Outlines 

**==> picture [471 x 250] intentionally omitted <==**

**----- Start of picture text -----**<br>
Long terminal type (PSM03S93E5-A)                                                              Dimensions in mm<br>TERMINAL CODE<br>aon A Cc B a 1-A  NC(VNC)<br>20X1.778(=35.56) a 1-B  NC(VP1)<br>2  VUFB<br>0.28 35 a 3  VVFB ee<br>177802| | |,:  hss aa 4  VWFB<br>I. 3 CT a 5  UP<br>6  VP<br>SUTRA po | a 7  WP<br>eH 7 a 8  VP1<br>9  VNC  *1<br>10  UN<br>2 ! “ : eR rH o -——_ 11  LS VN<br>12  WN<br>al oT [| iti name | oll a 13  VN1<br>3 Code} jot No. | a a 14  Fo<br>15  CIN<br>PISS LLGHALGRLIGELIBI IRL HEAT SINK. SIDE a<br>16  VNC  *1<br>17  NC<br>028 $08 . as ee 18  NW<br>2séua| | a 19  NV<br>44X2.54(=35 56) a 20  NU<br>2.5 ~ 21  LC W<br>MIN a DETAIL C Po 22  V<br>0s540.05 gJ {TERMINAL No) bt 23  LC U<br>| 15 24  P<br>25  NC<br>**----- End of picture text -----**<br>


1) 9 & 16 pins (VNC) are connected inside DIPIPM, please connect either one to the control power supply GND outside and leave another one open. 

QR Code is registered trademark of DENSO WAVE INCORPORATED in JAPAN and other countries. 

Publication Date : October 2013 

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**< Dual-In-Line Package Intelligent Power Module > PSM03S93E5-A TRANSFER MOLDING TYPE INSULATED TYPE** 

## Revision Record 

|Revision Record||||
|---|---|---|---|
|Rev.|Date|Page|Revised contents|
|1|10/15/2013|-|New|



Publication Date : October 2013 

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**< Dual-In-Line Package Intelligent Power Module > PSM03S93E5-A TRANSFER MOLDING TYPE INSULATED TYPE** 

## **Keep safety first in your circuit designs!** 

Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. 

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© 2013 MITSUBISHI ELECTRIC CORPORATION. ALL RIGHTS RESERVED. DIPIPM and CSTBT are registered trademarks of MITSUBISHI ELECTRIC CORPORATION. 

Publication Date : October 2013 

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