PRMD3Z

## **PRMD3** 

## **50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET) 15 June 2017** 

**Product data sheet** 

## **1.  General description** 

NPN/PNP Resistor-Equipped double Transistors (RET) in a leadless ultra small DFN1412-6 (SOT1268) leadless Surface-Mounted Device (SMD) plastic package. 

NPN/NPN complement: PRMH11; PNP/PNP complement: PRMB11. 

## **2.  Features and benefits** 

- 100 mA output current capability 

- Built-in bias resistors 

- Simplifies circuit design 

- Reduces component count 

- Reduces pick and place costs 

- Low package height of 0.5 mm 

- AEC-Q101 qualified 

## **3.  Applications** 

- Digital applications 

- Cost-saving alternative to BC847/BC857 series in digital applications 

- Control of IC inputs 

- Switching loads 

## **4.  Quick reference data** 

|**Symbol**<br>~~Rs~~|**Parameter**<br>|**Conditions**<br>||**Min**<br>|**Typ**<br>|**Max**<br>|**Unit**<br>|
|---|---|---|---|---|---|---|---|
|**Per transistor, for the PNP transistor with negative polarity**<br>~~RspT~~<br>~~a~~<br>~~ee~~<br>~~eeee~~||||||||
|VCEO<br>~~a~~|collector-emitter<br>voltage<br>~~ee~~|open base<br>~~eeee~~|~~ee~~|-<br>~~ee~~|-<br>~~ee~~|50<br>~~ee~~|V<br>~~ee~~|
|IO<br>~~a~~<br>~~sD~~|output current<br>~~ee~~<br>~~sD~~|~~eeee~~<br>~~sD~~|~~ee~~<br>~~sD~~|-<br>~~ee~~<br>~~sD~~|-<br>~~ee~~<br>~~sD~~|100<br>~~ee~~<br>~~sD~~|mA<br>~~ee~~<br>~~sD~~|
|hFE<br>~~a~~|DC current gain<br>|VCE= 5 V; IC= 5 mA; Tamb= 25 °C<br>||30|-|-||
|R1<br>~~aSf~~<br>~~a~~|bias resistor 1<br>~~Sf~~<br>~~ee~~|Tamb= 25 °C<br>~~Sf~~<br>~~ee~~<br>~~I~~|[1]<br>~~I~~<br>~~|~~|7<br>~~|~~|10<br>~~|~~|13<br>~~ft~~|kΩ<br>~~ft~~|
|R2/R1<br>~~Sf~~<br>~~a~~|bias resistor ratio<br>~~Sf~~<br>~~ee~~||[1]<br>~~I~~<br>~~|~~|0.8<br>~~|~~|1<br>~~|~~|1.2<br>~~ft~~|~~ft~~|



[1] See section "Test information" for resistor calculation and test conditions. 

**Nexperia** 

**PRMD3** 

**50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)** 

## **5.  Pinning information** 

**Table 2. Pinning information** 

|**Pin**|**Symbol**|**Description**|**Simplified outline**|**Graphic symbol**|
|---|---|---|---|---|
|1|GND1|GND (emitter) TR1|Transparent top view<br>1<br>6<br>7<br>8<br>2<br>3<br>5<br>4<br>**DFN1412-6 (SOT1268)**|O1<br>I2<br>GND2<br>GND1<br>I1<br>O2<br>R2<br>TR1<br>TR2<br>R1<br>R2<br>R1<br>_aaa-007379_|
|2|I1|input ( base) TR1|||
|3|O2|output (collector) TR2|||
|4|GND2|GND (emitter) TR2|||
|5|I2|input ( base) TR2|||
|6|O1|output (collector) TR1|||
|7|O1|output (collector) TR1|||
|8|O2|output (collector) TR2|||



## **6.  Ordering information** 

**Table 3. Ordering information** 

|**Type number**|**Package**|||
|---|---|---|---|
||**Name**|**Description**|**Version**|
|PRMD3|DFN1412-6|plastic thermal enhanced ultra thin small outline package; no<br>leads; 6 terminals; body: 1.4 mm x 1.2 mm x 0.47 mm|SOT1268|



## **7.  Marking** 

**Table 4. Marking codes** 

|**Type number**|**Marking code**|
|---|---|
|PRMD3|B3|



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All information provided in this document is subject to legal disclaimers. 

PRMD3 

**2 / 15** 

**15 June 2017** 

**Product data sheet** 

**Nexperia** 

**PRMD3** 

**50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)** 

## **8.  Limiting values** 

## **Table 5. Limiting values** 

_In accordance with the Absolute Maximum Rating System (IEC 60134)._ 

|**Symbol**|**Parameter**|**Conditions**||**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**Per transistor, for the PNP transistor with negative polarity**|||||||
|VCBO|collector-base voltage|open emitter||-|50|V|
|VCEO|collector-emitter voltage|open base||-|50|V|
|VEBO|emitter-base voltage|open collector||-|10|V|
|VI|input voltage|positive||-|40|V|
|||negative||-|-10|V|
|IO|output current|||-|100|mA|
|Ptot|total power dissipation|Tamb≤  25 °C|[1]|-|325|mW|
|**Per device**|||||||
|Ptot|total power dissipation|Tamb≤  25 °C|[1]|-|480|mW|
|Tj|junction temperature|||-|150|°C|
|Tamb|ambient temperature|||-55|150|°C|
|Tstg|storage temperature|||-65|150|°C|



[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. 

**==> picture [361 x 217] intentionally omitted <==**

**----- Start of picture text -----**<br>
aaa-024487<br>500<br>Ptot<br>(mW)<br>400<br>300<br>200<br>100<br>0<br>-75 -25 25 75 125 175<br>Tamb (°C)<br>FR4 PCB, standard footprint<br>Fig. 1. Per device: Power derating curve<br>**----- End of picture text -----**<br>


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PRMD3 

**3 / 15** 

**15 June 2017** 

**Product data sheet** 

**Nexperia** 

**PRMD3** 

**50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)** 

## **9.  Thermal characteristics** 

**Table 6. Thermal characteristics** 

|**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|**Per transistor**||||||||
|Rth(j-a)|thermal resistance<br>from junction to<br>ambient|in free air|[1]|-|-|385|K/W|
|**Per device**||||||||
|Rth(j-a)|thermal resistance<br>from junction to<br>ambient|in free air|[1]|-|-|261|K/W|



- [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. 

**==> picture [485 x 229] intentionally omitted <==**

**----- Start of picture text -----**<br>
aaa-024488<br>10 [3]<br>Zth(j-a) duty cycle = 1<br>(K/W) 0.75<br>0.5<br>10 [2] 0.33<br>0.2<br>0.1<br>0.05<br>0.02 0.01<br>10<br>0<br>1<br>10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 1 10 10 [2] 10 [3]<br>tp (s)<br>FR4 PCB, standard footprint<br>Fig. 2. Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration;<br>typical values<br>**----- End of picture text -----**<br>


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PRMD3 

**4 / 15** 

**15 June 2017** 

**Product data sheet** 

**Nexperia** 

**PRMD3** 

**50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)** 

## **10.  Characteristics** 

## **Table 7. Characteristics** 

|**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|**Per transistor, for the PNP transistor with negative polarity**||||||||
|ICBO|collector-base cut-off<br>current (emitter open)|VCB= 50 V; IE= 0 A; Tamb= 25 °C||-|-|100|nA|
|ICEO|collector-emitter cut-off<br>current (base open)|VCE= 30 V; IB= 0 A; Tamb= 25 °C||-|-|1|µA|
|||VCE= 30 V; IB= 0 A; Tamb= 150 °C||-|-|5|µA|
|IEBO|emitter-base cut-off<br>current (collector open)|VEB= 5 V; IC= 0 A; Tamb= 25 °C||-|-|400|µA|
|hFE|DC current gain|VCE= 5 V; IC= 5 mA; Tamb= 25 °C||30|-|-||
|VCEsat|collector-emitter<br>saturation voltage|IC= 10 mA; IB= 0.5 mA; Tamb= 25 °C||-|-|150|mV|
|VI(off)|off-state input voltage|VCE= 5 V; IC= 100 µA; Tamb= 25 °C||-|1.1|0.8|V|
|VI(on)|on-state input voltage|VCE= 0.3 V; IC= 10 mA; Tamb= 25 °C||2.5|1.8|-|V|
|R1|bias resistor 1|Tamb= 25 °C|[1]|7|10|13|kΩ|
|R2/R1|bias resistor ratio||[1]|0.8|1|1.2||
|CC|collector capacitance|VCB= 10 V; IE= 0 A; ie= 0 A;<br>f = 1 MHz; Tamb= 25 °C||-|-|2.5|pF|
|||VCB= -10 V; IE= 0 A; ie= 0 A;<br>f = 1 MHz; Tamb= 25 °C||-|-|3|pF|
|fT|transition frequency|VCE= 5 V; IC= 10 mA; f = 100 MHz;<br>Tamb= 25 °C|[2]|-|230|-|MHz|
|||VCE= -5 V; IC= -10 mA; f = 100 MHz;<br>Tamb= 25 °C|[2]|-|180|-|MHz|



[1] See section "Test information" for resistor calculation and test conditions. 

[2] Characteristics of built-in transistor. 

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PRMD3 

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**Product data sheet** 

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**PRMD3** 

**50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)** 

**==> picture [497 x 547] intentionally omitted <==**

**----- Start of picture text -----**<br>
006aac768 aaa-018663<br>10 [3] 0.1<br>0.60 mA<br>IC 0.54 mA<br>hFE (A) 0.48 mA<br>(1)<br>0.08 0.42 mA<br>0.36 mA<br>10 [2] (2)<br>(3) 0.06 0.30 mA<br>0.24 mA<br>0.04<br>10 0.18 mA<br>0.02 0.12 mA<br>IB = 0.06 mA<br>1 0<br>10 [-1] 1 10 10 [2] 0 1 2 3 4 5<br>IC (mA) VCE (V)<br>VCE = 5 V Tamb = 25 °C<br>(1) Tamb = 100 °C<br>Fig. 4. NPN transistor: Collector current as a function<br>(2) Tamb = 25 °C<br>of collector-emitter voltage; typical values<br>(3) Tamb = -40 °C<br>Fig. 3. NPN transistor: DC current gain as a function<br>of collector current; typical values<br>006aac769 006aac770<br>1 10<br>VCEsat VI(on)<br>(V) (V)<br>(1)<br>(2)<br>10 [-1] 1<br>(1) (3)<br>(2)<br>(3)<br>10 [-2] 10 [-1]<br>1 10 10 [2] 10 [-1] 1 10 10 [2]<br>IC (mA) IC (mA)<br>IC/IB = 20 VCE = 0.3 V<br>(1) Tamb = 100 °C (1) Tamb = -40 °C<br>(2) Tamb = 25 °C (2) Tamb = 25 °C<br>(3) Tamb = -40 °C (3) Tamb = 100 °C<br>Fig. 5. NPN transistor: Collector-emitter saturation Fig. 6. NPN transistor: On-state input voltage as a<br>voltage as a function of collector current; function of collector current; typical values<br>typical values<br>**----- End of picture text -----**<br>


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PRMD3 

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**Product data sheet** 

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**PRMD3** 

**50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)** 

**==> picture [497 x 536] intentionally omitted <==**

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006aac771 006aac772<br>10 3<br>Cc<br>VI(off) (pF)<br>(V)<br>2<br>(1)<br>(2)<br>1<br>(3)<br>1<br>10 [-1] 0<br>10 [-1] 1 10 0 10 20 30 40 50<br>IC (mA) VCB (V)<br>VCE = 5 V f = 1 MHz; Tamb = 25 °C<br>(1) Tamb = -40 °C<br>Fig. 8. NPN transistor: Collector capacitance as a<br>(2) Tamb = 25 °C<br>function of collector-base voltage; typical<br>(3) Tamb = 100 °C<br>values<br>Fig. 7. NPN transistor: Off-state input voltage as a<br>function of collector current; typical values<br>006aac757 006aac773<br>10 [3] 10 [3]<br>hFE<br>(1)<br>fT<br>(MHz)<br>10 [2] (2)<br>(3)<br>10 [2]<br>10<br>10 1<br>10 [-1] 1 10 10 [2] -10 [-1] -1 -10 -10 [2]<br>IC (mA) IC (mA)<br>VCE = 5 V; Tamb = 25 °C VCE = -5 V<br>(1) Tamb = 100 °C<br>Fig. 9. NPN transistor: Transition frequency as a<br>(2) Tamb = 25 °C<br>function of collector current; typical values of<br>(3) Tamb = -40 °C<br>built-in transistor<br>Fig. 10. PNP transistor: DC current gain as a function<br>of collector current; typical values<br>**----- End of picture text -----**<br>


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PRMD3 

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**Product data sheet** 

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**PRMD3** 

**50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)** 

**==> picture [497 x 547] intentionally omitted <==**

**----- Start of picture text -----**<br>
aaa-017927 aaa-017926<br>-0.1 -1<br>-0.80 mA<br>IC<br>(A) -0.72 mA<br>-0.08 -0.64 mA VCEsat<br>-0.56 mA (V)<br>-0.48 mA<br>-0.06<br>-0.40 mA<br>-10 [-1]<br>-0.32 mA (1)<br>-0.04 (2)<br>-0.24 mA<br>(3)<br>-0.02 -0.16 mA<br>IB = -0.08 mA<br>0 -10 [-2]<br>0 -1 -2 -3 -4 -5 -1 -10 -10 [2]<br>VCE (V) IC (mA)<br>Tamb = 25 °C IC/IB = 20<br>(1) Tamb = 100 °C<br>Fig. 11. PNP transistor: Collector current as a function<br>(2) Tamb = 25 °C<br>of collector-emitter voltage; typical values<br>(3) Tamb = -40 °C<br>Fig. 12. PNP transistor: Collector-emitter saturation<br>voltage as a function of collector current;<br>typical values<br>006aac775 006aac776<br>-10 -10<br>VI(on) VI(off)<br>(V) (V)<br>(1) (1)<br>(2) (2)<br>-1 -1<br>(3) (3)<br>-10 [-1] -10 [-1]<br>-10 [-1] -1 -10 -10 [2] -10 [-1] -1 -10<br>IC (mA) IC (mA)<br>VCE = -0.3 V VCE = -5 V<br>(1) Tamb = -40 °C (1) Tamb = -40 °C<br>(2) Tamb = 25 °C (2) Tamb = 25 °C<br>(3) Tamb = 100 °C (3) Tamb = 100 °C<br>Fig. 13. PNP transistor: On-state input voltage as a Fig. 14. PNP transistor: Off-state input voltage as a<br>function of collector current; typical values function of collector current; typical values<br>**----- End of picture text -----**<br>


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PRMD3 

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**Product data sheet** 

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**PRMD3** 

**50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)** 

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**----- Start of picture text -----**<br>
006aac777 006aac763<br>6 10 [3]<br>Cc<br>(pF) fT<br>(MHz)<br>4<br>10 [2]<br>2<br>0 10<br>0 -10 -20 -30 -40 -50 -10 [-1] -1 -10 -10 [2]<br>VCB (V) IC (mA)<br>f = 1 MHz; Tamb = 25 °C VCE = -5 V; Tamb = 25 °C<br>Fig. 15. PNP transistor: Collector capacitance as a Fig. 16. PNP transistor: Transition frequency as a<br>function of collector-base voltage; typical function of collector current; typical values of<br>values built-in transistor<br>**----- End of picture text -----**<br>


## **11.  Test information** 

## **Quality information** 

This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in automotive applications. 

## **Resistor calculation** 

- Calculation of bias resistor 1 (R1) 

- Calculation of bias resistor ratio (R2/R1) 

**==> picture [302 x 148] intentionally omitted <==**

**----- Start of picture text -----**<br>
n.c.<br>II1; II2 R1<br>II3; II4<br>R2<br>GND<br>aaa-020082<br>Fig. 17. NPN transistor: Resistor test circuit<br>**----- End of picture text -----**<br>


All information provided in this document is subject to legal disclaimers. 

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PRMD3 

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**Product data sheet** 

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**PRMD3** 

**50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)** 

**==> picture [302 x 149] intentionally omitted <==**

**----- Start of picture text -----**<br>
n.c.<br>II1; II2 R1<br>II3; II4<br>R2<br>GND<br>aaa-020083<br>Fig. 18. PNP transistor: Resistor test circuit<br>**----- End of picture text -----**<br>


## **Resistor test conditions** 

**Table 8. Resistor test conditions** 

_Per transistor; for the PNP transistor with negative polarity_ 

|**R1 (kΩ)**|**R2 (kΩ)**|**Test conditions**||||
|---|---|---|---|---|---|
|||**II1**|**II2**|**II3**|**II4**|
|10|10|350 μA|450 μA|-350 μA|-450 μA|



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PRMD3 

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**Product data sheet** 

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**PRMD3** 

**50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)** 

## **12.  Package outline** 

**==> picture [481 x 574] intentionally omitted <==**

**----- Start of picture text -----**<br>
DFN1412-6: plastic thermal enhanced ultra thin small outline package; no leads;<br>6 terminals; body: 1.4 x 1.2 x 0.47 mm SOT1268<br>(2×)<br>E B A<br>pin 1<br>index area<br>A<br>D<br>A1<br>detail X<br>C<br>E1 L v A B y1 C y<br>(2×) (6×)<br>4<br>3<br>e<br>e1<br>2 5<br>e1 b<br>(6×) e<br>D1<br>(2×)<br>1<br>6<br>pin 1<br>index area 0 1 mm X<br>scale<br>Dimensions (mm are the original dimensions)<br>Unit [(1)] A A1 b D D1 E E1 e e1 L V Y Y1<br>min 0.44 0.00 0.15 1.35 0.43 1.15 0.32 0.145<br>mm nom 0.47 0.20 1.40 0.48 1.20 0.37 0.5 0.35 0.195 0.1 0.05 0.05<br>max 0.50 0.04 0.25 1.45 0.53 1.25 0.42 0.245<br>Note<br>1. Dimension A is including plating thickness. sot1268_po<br>Outline References European Issue date<br>version IEC JEDEC JEITA projection<br>16-02-25<br>SOT1268 - - - 16-09-02<br>**----- End of picture text -----**<br>


**Fig. 19. Package outline DFN1412-6 (SOT1268)** 

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PRMD3 

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**Product data sheet** 

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**PRMD3** 

**50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)** 

## **13.  Soldering** 

**==> picture [481 x 573] intentionally omitted <==**

**----- Start of picture text -----**<br>
Footprint information for reflow soldering of DFN1412-6 package  SOT1268<br>1.6<br>1.4<br>1.3<br>0.3 0.2<br>0.25 0.5<br>0.3 0.35<br>1.71 1.51 1.41 0.71 0.27 0.37<br>0.17<br>0.43<br>0.17<br>1.23<br>occupied area solder resist<br>solder lands solder paste<br>Dimensions in mm<br>16-04-18<br>Issue date sot1268_fr<br>16-09-02<br>**----- End of picture text -----**<br>


**==> picture [260 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Fig. 20. Reflow soldering footprint for DFN1412-6 (SOT1268)<br>**----- End of picture text -----**<br>


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PRMD3 

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**Product data sheet** 

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**PRMD3** 

**50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)** 

## **14.  Revision history** 

|**14.  Revision history**|**14.  Revision history**||||
|---|---|---|---|---|
|**Table 9. Revision history**|||||
|**Data sheet ID**|**Release date**|**Data sheet status**|**Change notice**|**Supersedes**|
|PRMD3 v.1|20170615|Product data sheet|-|-|



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**Product data sheet** 

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**PRMD3** 

**50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)** 

## **15.  Legal information** 

## **Data sheet status** 

|**Document**<br>**status [1]**<br>**[2]**|**Product**<br>**status [3]**|**Definition**|
|---|---|---|
|Objective<br>[short] data<br>sheet|Development|This document contains data from<br>the objective specification for product<br>development.|
|Preliminary<br>[short] data<br>sheet|Qualification|This document contains data from the<br>preliminary specification.|
|Product<br>[short] data<br>sheet|Production|This document contains the product<br>specification.|



[1] Please consult the most recently issued document before initiating or completing a design. 

[2] The term 'short data sheet' is explained in section "Definitions". 

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 

## **Definitions** 

**Preview** — The document is a preview version only. The document is still subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 

**Draft** — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 

**Short data sheet** — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 

**Product specification** — The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. 

## **Disclaimers** 

**Limited warranty and liability** — Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. 

In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 

Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’ aggregate and cumulative liability towards customer 

for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of Nexperia. 

**Right to make changes** — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 

**Suitability for use in automotive applications** — This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 

**Quick reference data** — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 

**Applications** — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 

Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. 

Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. 

**Limiting values** — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 

**Terms and conditions of commercial sale** — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. 

**No offer to sell or license** — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 

**Export control** — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 

**Translations** — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 

## **Trademarks** 

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 

© Nexperia B.V. 2017. All rights reserved 

All information provided in this document is subject to legal disclaimers. 

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**Nexperia** 

**PRMD3** 

**50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)** 

## **16. Contents** 

**1.  General description......................................................1 2.  Features and benefits.................................................. 1 3.  Applications.................................................................. 1 4.  Quick reference data....................................................1 5.  Pinning information......................................................2 6.  Ordering information....................................................2 7.  Marking..........................................................................2 8.  Limiting values............................................................. 3 9.  Thermal characteristics............................................... 4 10.  Characteristics............................................................5 11.  Test information......................................................... 9 12.  Package outline........................................................ 11 13.  Soldering................................................................... 12 14.  Revision history........................................................13 15.  Legal information..................................................... 14** 

## © **Nexperia B.V. 2017. All rights reserved** 

For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com **Date of release: 15 June 2017** 

© Nexperia B.V. 2017. All rights reserved 

All information provided in this document is subject to legal disclaimers. 

PRMD3 

**15 / 15** 

**15 June 2017** 

**Product data sheet**