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PMP5501Y,135
Bipolar Transistor Array, Dual PNP, 45 V, 100 mA
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- Manufacturer: NEXPERIA
- Product type: Bipolar Junction Transistor Arrays - BJT
- MSL: MSL 1 - Unlimited
- SVHC: No SVHC (25-Jun-2025)
- No. of Pins: 6Pins
- Product Range: -
- Qualification: AEC-Q101
- Transistor Mounting: Surface Mount
- Transistor Polarity: Dual PNP
- Power Dissipation NPN: -
- Power Dissipation PNP: 300mW
- Transistor Case Style: TSSOP
- Transition Frequency NPN: -
- Transition Frequency PNP: 175MHz
- Operating Temperature Max: 150°C
- DC Current Gain hFE Min NPN: -
- DC Current Gain hFE Min PNP: 200hFE
- Continuous Collector Current NPN: -
- Continuous Collector Current PNP: 100mA
- Collector Emitter Voltage Max NPN: -
- Collector Emitter Voltage Max PNP: 45V
| Delivery and price | |
|---|---|
| Units per pack | 30000 |
| Price | 0.131 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
## **Important notice** Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename **Nexperia** . Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use **http://www.nexperia.com** Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use **salesaddresses@nexperia.com** (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - **© Nexperia B.V. (year). All rights reserved** . If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via **salesaddresses@nexperia.com** ). Thank you for your cooperation and understanding, Kind regards, Team Nexperia ## **PMP5501V; PMP5501G; PMP5501Y** ## **PNP/PNP matched double transistors** **Rev. 03 — 28 August 2009** **Product data sheet** ## **1.** ## **1.1 General description** PNP/PNP matched double transistors in small Surface-Mounted Device (SMD) plastic packages. The transistors in the SOT666 and SOT363 (SC-88) packages are fully isolated internally. ## **Table 1. Product overview** |**Type number**|**Package**|**Package**|**PNP/PNP hFE1/hFE2**<br>**0.98 complement**|**NPN/NPN**<br>**complement**| |---|---|---|---|---| ||**NXP**|**JEITA**||| |PMP5501V|SOT666<br>-<br>PMP5201V<br>PMP4501V|||| |PMP5501G|SOT353<br>SC-88A<br>PMP5201G<br>PMP4501G|||| |PMP5501Y|SOT363<br>SC-88<br>PMP5201Y<br>PMP4501Y|||| ## **1.2 Features** I Current gain matching - I Base-emitter voltage matching - I - I Application-optimized pinout ## **1.3 Applications** - I Current mirror - I ## **1.4 Quick reference data** ## **Table 2. Quick reference data** |**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---| |**Per transistor**||||||| |VCEO|collector-emitter voltage|open base|-|-|−45|V| |IC|collector current||-|-|−100|mA| |hFE|DC current gain|VCE=−5 V;|200|290|450|| |||IC=−2 mA||||| **==> picture [211 x 101] intentionally omitted <==** **PMP5501V; PMP5501G; PMP5501Y** **NXP Semiconductors** **PNP/PNP matched double transistors** **Table 2. Quick reference data** …continued |**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---|---| |**Per device**|||||||| |hFE1/hFE2|hFEmatching|VCE=−5 V;|[1]|0.95|1|-|| |||IC=−2 mA|||||| |VBE1−VBE2|VBEmatching|VCE=−5 V;|[2]|-|-|2|mV| |||IC=−2 mA|||||| - [1] The smaller of the two values is taken as the numerator. - [2] The smaller of the two values is subtracted from the larger value. ## **2. Pinning information** **==> picture [397 x 235] intentionally omitted <==** **----- Start of picture text -----**<br> Table 3. Pinning<br>Pin Description Simplified outline Symbol<br>SOT666; SOT363<br>1 base TR1<br>6 5 4 6 5 4<br>2 base TR2<br>TR1<br>3 collector TR2<br>TR2<br>4 emitter TR2<br>5 emitter TR1 1 2 3<br>1 2 3 006aaa550<br>6 collector TR1 001aab555<br>SOT353<br>1 base TR1<br>5 4 5 4<br>2 emitter TR1, TR2<br>3 base TR2<br>TR1 TR2<br>4 collector TR2<br>5 collector TR1 1 2 3 1 2 3<br>006aaa551<br>**----- End of picture text -----**<br> ## **3. Ordering information** **Table 4. Ordering information** |**Type number**|**Package**|**Package**|**Package**| |---|---|---|---| ||**Name**|**Description**|**Version**| |PMP5501V|-<br>plastic surface-mounted package; 6 leads<br>SOT666||| |PMP5501G|SC-88A<br>plastic surface-mounted package; 5 leads<br>SOT353||| |PMP5501Y|SC-88<br>plastic surface-mounted package; 6 leads<br>SOT363||| © NXP B.V. 2009. All rights reserved. PMP5501V_G_Y_3 **Product data sheet** **Rev. 03 — 28 August 2009** **2 of 14** **PMP5501V; PMP5501G; PMP5501Y** **NXP Semiconductors** **PNP/PNP matched double transistors** ## **4. Marking** **Table 5. Marking codes** |**Type number**|**Marking**|**cod**~~**e**~~<br>**[1]**| |---|---|---| |PMP5501V|ED|| |PMP5501G|R4*|| |PMP5501Y|S6*|| - [1] * = -: made in Hong Kong - = p: made in Hong Kong - = t: made in Malaysia - = W: made in China ## **5. Limiting values** ## **Table 6. Limiting values** In accordance with the Absolute Maximum Rating System (IEC 60134). |**Symbol**|**Parameter**|**Conditions**||**Min**|**Max**|**Unit**| |---|---|---|---|---|---|---| |**Per transistor**||||||| |VCBO|collector-base voltage|open emitter||-|−50|V| |VCEO|collector-emitter voltage|open base||-|−45|V| |VEBO|emitter-base voltage|open collector||-|−5|V| |IC|collector current|||-|−100|mA| |ICM|peak collector current|single pulse;||-|−200|mA| |||tp≤1 ms||||| |Ptot|total power dissipation|Tamb≤25°C||||| ||SOT666||[1]<br>[2]|-|200|mW| ||SOT353||[1]|-|200|mW| ||SOT363||[1]|-|200|mW| |**Per device**||||||| |Ptot|total power dissipation|Tamb≤25°C||||| ||SOT666||[1]<br>[2]|-|300|mW| ||SOT353||[1]|-|300|mW| ||SOT363||[1]|-|300|mW| |Tj|junction temperature|||-|150|°C| |Tamb|ambient temperature|||−65|+150|°C| |Tstg|storage temperature|||−65|+150|°C| - [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. - [2] © NXP B.V. 2009. All rights reserved. PMP5501V_G_Y_3 **Product data sheet** **Rev. 03 — 28 August 2009** **3 of 14** **NXP Semiconductors** **PNP/PNP matched double transistors** ## **PMP5501V; PMP5501G; PMP5501Y** ## **6. Thermal characteristics** ## **Table 7. Thermal characteristics** |**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---|---| |**Per transistor**|||||||| |Rth(j-a)|thermal resistance from|in free air|||||| ||junction to ambient||||||| ||SOT666||[1]<br>[2] -||-|625|K/W| ||SOT353|||[1] -|-|625|K/W| ||SOT363|||[1] -|-|625|K/W| |**Per device**|||||||| |Rth(j-a)|thermal resistance from|in free air|||||| ||junction to ambient||||||| ||SOT666||[1]<br>[2] -||-|416|K/W| ||SOT353|||[1] -|-|416|K/W| ||SOT363|||[1] -|-|416|K/W| - [1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint. - [2] ## **7. Characteristics** ## **Table 8. Characteristics** Tamb = 25 ° |**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**| |---|---| |**Per transistor**|| |ICBO<br>collector-base cut-off<br>current|VCB=−30 V;<br>IE= 0 A<br>-<br>-<br>−15<br>nA| ||VCB=−30 V;<br>IE= 0 A;<br>Tj= 150°C<br>-<br>-<br>−5<br>µA| |IEBO<br>emitter-base cut-off<br>current|VEB=−5 V;<br>IC= 0 A<br>-<br>-<br>−100<br>nA| |hFE<br>DC current gain|VCE=−5 V;<br>IC=−10µA<br>-<br>250<br>-| ||VCE=−5 V;<br>IC=−2 mA<br>200<br>290<br>450| |VCEsat<br>collector-emitter<br>saturation voltage|IC=−10 mA;<br>IB=−0.5 mA<br>-<br>−50<br>−200<br>mV| ||IC=−100 mA;<br>IB=−5 mA<br>-<br>−200<br>−400<br>mV| |VBEsat<br>base-emitter saturation<br>voltage|IC=−10 mA;<br>IB=−0.5 mA<br>[1] -<br>−760<br>-<br>mV| ||IC=−100 mA;<br>IB=−5 mA<br>[1] -<br>−920<br>-<br>mV| © NXP B.V. 2009. All rights reserved. PMP5501V_G_Y_3 **Product data sheet** **Rev. 03 — 28 August 2009** **4 of 14** **NXP Semiconductors** **PNP/PNP matched double transistors** ## **PMP5501V; PMP5501G; PMP5501Y** **Table 8. Characteristics** …continued Tamb = 25 °C unless otherwise specified. |**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**| |---|---| |VBE<br>base-emitter voltage|VCE=−5 V;<br>IC=−2 mA<br>[2] −600<br>−650<br>−700<br>mV| ||VCE=−5 V;<br>IC=−10 mA<br>[2] -<br>-<br>−760<br>mV| |Cc<br>collector capacitance|VCB=−10 V;<br>IE= ie= 0 A;<br>f = 1 MHz<br>-<br>-<br>2.2<br>pF| |Ce<br>emitter capacitance|VEB=−0.5 V;<br>IC= ic= 0 A;<br>f = 1 MHz<br>-<br>10<br>-<br>pF| |fT<br>transition frequency|VCE=−5 V;<br>IC=−10 mA;<br>f = 100 MHz<br>100<br>175<br>-<br>MHz| |NF<br>noise fgure|VCE=−5 V;<br>IC=−0.2 mA;<br>RS= 2 kΩ;<br>f = 10 Hz to<br>15.7 kHz<br>-<br>1.6<br>-<br>dB| ||VCE=−5 V;<br>IC=−0.2 mA;<br>RS= 2 kΩ;<br>f = 1 kHz;<br>B = 200 Hz<br>-<br>3.1<br>-<br>dB| |**Per device**|| |hFE1/hFE2<br>hFEmatching|VCE=−5 V;<br>IC=−2 mA<br>[3] 0.95<br>1<br>-| |VBE1−VBE2<br>VBEmatching|VCE=−5 V;<br>IC=−2 mA<br>[4] -<br>-<br>2<br>mV| - [1] VBEsat decreases by about 1.7 mV/K with increasing temperature. - [2] VBE decreases by about 2 mV/K with increasing temperature. - [3] The smaller of the two values is taken as the numerator. - [4] The smaller of the two values is subtracted from the larger value. © NXP B.V. 2009. All rights reserved. PMP5501V_G_Y_3 **Product data sheet** **Rev. 03 — 28 August 2009** **5 of 14** **PMP5501V; PMP5501G; PMP5501Y** **NXP Semiconductors** **PNP/PNP matched double transistors** **==> picture [233 x 209] intentionally omitted <==** **----- Start of picture text -----**<br> −0.20 006aaa540<br>IB (mA) = −2.5<br>IC −2.25<br>(A) −2.0<br>−0.16 −1.75<br>−1.5<br>−1.25<br>−0.12 −1.0<br>−0.75<br>−0.08 −0.5<br>−0.25<br>−0.04<br>0<br>0 −2 −4 −6 −8 −10<br>VCE (V)<br>Tamb = 25 °C<br>**----- End of picture text -----**<br> **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 006aaa541<br>600<br>hFE<br>(1)<br>400<br>(2)<br>200<br>(3)<br>0<br>−10 [−][2] −10 [−][1] −1 −10 −10 [2] −10 [3]<br>IC (mA)<br>**----- End of picture text -----**<br> ## VCE = −5 V - (1) Tamb = 100 °C - (2) Tamb = 25 °C - (3) Tamb = −55 °C **Fig 1. Collector current as a function of collector-emitter voltage; typical values** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> −1.3 006aaa542<br>VBEsat<br>(V)<br>−1.1<br>−0.9<br>(1)<br>−0.7 (2)<br>(3)<br>−0.5<br>−0.3<br>−0.1<br>−10 [−][1] −1 −10 −10 [2] −10 [3]<br>IC (mA)<br>**----- End of picture text -----**<br> ## IC/IB = 20 - (1) Tamb = −55 °C - (2) Tamb = 25 °C (3) Tamb = 100 °C **Fig 3. Base-emitter saturation voltage as a function of collector current; typical values** **Fig 2. DC current gain as a function of collector current; typical values** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> −10 006aaa543<br>VCEsat<br>(V)<br>−1<br>−10 [−][1] (1)<br>(2)<br>(3)<br>−10 [−][2]<br>−10 [−][1] −1 −10 −10 [2] −10 [3]<br>IC (mA)<br>**----- End of picture text -----**<br> IC/IB = 20 - (1) Tamb = 100 °C - (2) Tamb = 25 °C (3) Tamb = −55 °C **Fig 4. Collector-emitter saturation voltage as a function of collector current; typical values** © NXP B.V. 2009. All rights reserved. PMP5501V_G_Y_3 **Product data sheet** **Rev. 03 — 28 August 2009** **6 of 14** **PMP5501V; PMP5501G; PMP5501Y** **NXP Semiconductors** ## **PNP/PNP matched double transistors** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> −1 006aaa544<br>VBE<br>(V)<br>−0.8<br>−0.6<br>−0.4<br>−10 [−][1] −1 −10 −10 [2] −10 [3]<br>IC (mA)<br>**----- End of picture text -----**<br> ## VCE = −5 V; Tamb = 25 °C **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 006aaa545<br>10 [3]<br>fT<br>(MHz)<br>10 [2]<br>10<br>−1 −10 −10 [2]<br>IC (mA)<br>**----- End of picture text -----**<br> ## VCE = −5 V; Tamb = 25 °C **Fig 5. Base-emitter voltage as a function of collector Fig 6. Transition frequency as a function of collector current; typical values current; typical values** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 006aaa546<br>8<br>Cc<br>(pF)<br>6<br>4<br>2<br>0<br>0 −2 −4 −6 −8 −10<br>VCB (V)<br>**----- End of picture text -----**<br> f = 1 MHz; Tamb = 25 °C **Fig 7. Collector capacitance as a function of collector-base voltage; typical values** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 006aaa547<br>15<br>Ce<br>(pF)<br>13<br>11<br>9<br>7<br>5<br>0 −2 −4 −6<br>VEB (V)<br>**----- End of picture text -----**<br> f = 1 MHz; Tamb = 25 °C **Fig 8. Emitter capacitance as a function of emitter-base voltage; typical values** © NXP B.V. 2009. All rights reserved. PMP5501V_G_Y_3 **Product data sheet** **Rev. 03 — 28 August 2009** **7 of 14** **NXP Semiconductors** **PNP/PNP matched double transistors** ## **PMP5501V; PMP5501G; PMP5501Y** ## **8. Application information** **==> picture [497 x 155] intentionally omitted <==** **----- Start of picture text -----**<br> V−<br>VCC<br>OUT1 OUT2<br>R1 IN1 TR1 TR2 IN2<br>lout<br>TR1 TR2<br>V+<br>006aaa524 006aaa526<br>Fig 9. Current mirror Fig 10. Differential amplifier<br>**----- End of picture text -----**<br> ## **9. Package outline** **==> picture [497 x 398] intentionally omitted <==** **----- Start of picture text -----**<br> 1.7 0.6 2.2 1.1<br>1.5 0.5 1.8 0.8<br>6 5 4 5 4 0.45<br>0.15<br>0.3<br>0.1<br>1.7 1.3 2.2 1.35<br>1.5 1.1 2.0 1.15<br>pin 1 index<br>1 2 3 1 2 3<br>0.5 0.270.17 0.180.08 0.65 0.30.2 0.250.10<br>1 1.3<br>Dimensions in mm 04-11-08 Dimensions in mm 04-11-16<br>Fig 11. Package outline SOT666 Fig 12. Package outline SOT353 (SC-88A)<br>2.2 1.1<br>1.8 0.8<br>6 5 4 0.45<br>0.15<br>2.2 1.35<br>2.0 1.15 pin 1<br>index<br>1 2 3<br>0.3 0.25<br>0.65<br>0.2 0.10<br>1.3<br>Dimensions in mm 06-03-16<br>Fig 13. Package outline SOT363 (SC-88)<br>**----- End of picture text -----**<br> © NXP B.V. 2009. All rights reserved. PMP5501V_G_Y_3 **Product data sheet** **Rev. 03 — 28 August 2009** **8 of 14** **PMP5501V; PMP5501G; PMP5501Y** **NXP Semiconductors** **PNP/PNP matched double transistors** ## **10. Packing information** ## **Table 9. Packing methods** The indicated -xxx are the last three digits of the 12NC ordering code ~~.~~ [1] |**Type number**<br>**Package**|**Description**|**Packing quantity**|**Packing quantity**|**Packing quantity**|**Packing quantity**| |---|---|---|---|---|---| |||**3000**|**4000**|**8000**|**10000**| |PMP5501V<br>SOT666|2 mm pitch, 8 mm tape and reel<br>4 mm pitch, 8 mm tape and reel|-<br>-<br>-315<br>-|||| |||-<br>-115<br>-<br>-|||| |PMP5501G<br>SOT353|4 mm pitch, 8 mm tape and reel|-115<br>-<br>-<br>-135|||| |PMP5501Y<br>SOT363|4 mm pitch, 8 mm tape and reel; T1<br>[2] <br>4 mm pitch, 8 mm tape and reel; T2<br>[3]|-115<br>-<br>-<br>-135|||| |||-125<br>-<br>-<br>-165|||| - [1] For further information and the availability of packing methods, see Section 14. - [2] T1: normal taping - [3] T2: reverse taping ## **11. Soldering** **==> picture [380 x 216] intentionally omitted <==** **----- Start of picture text -----**<br> 2.75<br>2.45<br>2.1<br>1.6<br>solder lands<br>0.4<br>(6×) 0.25 0.3<br>0.538 (2×) (2×) placement area<br>0.55<br>2 1.7 1.075<br>(2×) solder paste<br>occupied area<br>0.325 0.375<br>(4×) (4×) Dimensions in mm<br>1.7<br>0.45 0.6<br>(4×) (2×)<br>0.5 0.65<br>(4×) (2×) sot666_fr<br>**----- End of picture text -----**<br> **==> picture [27 x 6] intentionally omitted <==** **----- Start of picture text -----**<br> sot666_fr<br>**----- End of picture text -----**<br> **Fig 14.** © NXP B.V. 2009. All rights reserved. PMP5501V_G_Y_3 **Product data sheet** **Rev. 03 — 28 August 2009** **9 of 14** **NXP Semiconductors** **PNP/PNP matched double transistors** ## **PMP5501V; PMP5501G; PMP5501Y** **==> picture [274 x 163] intentionally omitted <==** **----- Start of picture text -----**<br> 2.65<br>0.60<br>(1×)<br>2.35 0.40 0.90 2.10<br>solder lands<br>0.50<br>solder paste (4×)<br>solder resist<br>0.50<br>occupied area (4×) 1.20<br>2.40 msa366<br>**----- End of picture text -----**<br> **==> picture [66 x 7] intentionally omitted <==** **----- Start of picture text -----**<br> Dimensions in mm<br>**----- End of picture text -----**<br> **==> picture [224 x 14] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 15. Reflow soldering footprint SOT353 (SC-88A)<br>**----- End of picture text -----**<br> **==> picture [372 x 217] intentionally omitted <==** **----- Start of picture text -----**<br> 4.9<br>2.25<br>1.5 solder lands<br>1<br>0.85 solder resist<br>4.5 2.5<br>occupied area<br>0.85<br>1 Dimensions in mm<br>1.5<br>preferred transport<br>direction during soldering<br>1.3 1.3<br>1.225 1.225 sot353_fw<br>**----- End of picture text -----**<br> **==> picture [66 x 7] intentionally omitted <==** **----- Start of picture text -----**<br> Dimensions in mm<br>**----- End of picture text -----**<br> **Fig 16. Wave soldering footprint SOT353 (SC-88A)** © NXP B.V. 2009. All rights reserved. PMP5501V_G_Y_3 **Product data sheet** **Rev. 03 — 28 August 2009** **10 of 14** **NXP Semiconductors** **PNP/PNP matched double transistors** ## **PMP5501V; PMP5501G; PMP5501Y** **==> picture [324 x 150] intentionally omitted <==** **----- Start of picture text -----**<br> 2.65<br>solder lands<br>2.35 1.5 0.6 0.5 0.4 (2×)<br>(4×) (4×) solder resist<br>solder paste<br>0.5 0.6<br>occupied area<br>(4×) (2×)<br>0.6<br>Dimensions in mm<br>(4×)<br>1.8 sot363_fr<br>**----- End of picture text -----**<br> **Fig 17.** **==> picture [372 x 187] intentionally omitted <==** **----- Start of picture text -----**<br> 1.5<br>solder lands<br>4.5 0.3 2.5<br>solder resist<br>occupied area<br>1.5<br>Dimensions in mm<br>preferred transport<br>1.3 1.3 direction during soldering<br>2.45<br>5.3 sot363_fw<br>**----- End of picture text -----**<br> **Fig 18. Wave soldering footprint SOT363 (SC-88)** © NXP B.V. 2009. All rights reserved. PMP5501V_G_Y_3 **Product data sheet** **Rev. 03 — 28 August 2009** **11 of 14** **NXP Semiconductors** **PNP/PNP matched double transistors** ## **PMP5501V; PMP5501G; PMP5501Y** ## **12. Revision history** **Table 10. Revision history** |**Document ID**|**Release date**|**Data sheet status**<br>**Change notice**||**Supersedes**| |---|---|---|---|---| |PMP5501V_G_Y_3|20090828|Product data sheet<br>-||PMP5501V_G_Y_2| |Modifcations:|**•** This data<br>including|sheet was changed to refect the new company name NXP Semiconductors,<br>new legal defnitions and disclaimers. No changes were made to the technical||| ||content.|||| ||**•**<br>Figure14|“Ref<br>o<br>wsolder<br>ingf<br>ootpr<br>int SO<br>T666”: updated||| ||**•**<br>Figure16|“W<br>a<br>v<br>e solder<br>ingf<br>ootpr<br>int SO<br>T353 (SC-88A)”: updated||| ||**•**<br>Figure17|“Ref<br>o<br>wsolder<br>ingf<br>ootpr<br>int SO<br>T363 (SC-88)”: updated||| ||**•**<br>Figure18|“W<br>a<br>v<br>e solder<br>ingf<br>ootpr<br>int SO<br>T363 (SC-88)”: updated||| |PMP5501V_G_Y_2|20060919|Product data sheet<br>-||PMP5501G_Y_1| |PMP5501G_Y_1|20060221|Product data sheet<br>-||-| © NXP B.V. 2009. All rights reserved. PMP5501V_G_Y_3 **Product data sheet** **Rev. 03 — 28 August 2009** **12 of 14** **PMP5501V; PMP5501G; PMP5501Y** **NXP Semiconductors** **PNP/PNP matched double transistors** ## **13. Legal information** ## **13.1 Data sheet status** |**Document statu**|**s**<br>**[1]**<br>**[2]**<br>**Product status**<br>**[3]**<br>**Defnition**| |---|---| |Objective [short] data sheet<br>Development<br>This document contains data from the objective specifcation for product development.|| |Preliminary [short] data sheet<br>Qualifcation<br>This document contains data from the preliminary specifcation.|| |Product [short] data sheet<br>Production<br>This document contains the product specifcation.|| [1] Please consult the most recently issued document before initiating or completing a design. [2] [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. ## **13.2** **Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. ## **13.3 Disclaimers** **General —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. **Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. **Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. **Limiting values —** the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. **Terms and conditions of sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. **No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. **Export control —** This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. **Quick reference data —** The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. ## **13.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. ## **14. Contact information** For more information, please visit: **http://www.nxp.com** **salesaddresses@nxp.com** © NXP B.V. 2009. All rights reserved. PMP5501V_G_Y_3 **Product data sheet** **Rev. 03 — 28 August 2009** **13 of 14** **PMP5501V; PMP5501G; PMP5501Y** **NXP Semiconductors** **PNP/PNP matched double transistors** ## **15. Contents** |**1**|**Product profle . . . . . . . . . . . . . . . . . . . . . . . . . . 1**| |---|---| |1.1|General description. . . . . . . . . . . . . . . . . . . . . . 1| |1.2|Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1| |1.3|Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1| |1.4|Quick reference data. . . . . . . . . . . . . . . . . . . . . 1| |**2**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . 2**| |**3**|**Ordering information . . . . . . . . . . . . . . . . . . . . . 2**| |**4**|**Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3**| |**5**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3**| |**6**|**Thermal characteristics. . . . . . . . . . . . . . . . . . . 4**| |**7**|**Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 4**| |**8**|**Application information. . . . . . . . . . . . . . . . . . . 8**| |**9**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8**| |**10**|**Packing information. . . . . . . . . . . . . . . . . . . . . . 9**| |**11**|**Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9**| |**12**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12**| |**13**|**Legal information. . . . . . . . . . . . . . . . . . . . . . . 13**| |13.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13| |13.2|Defnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13| |13.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13| |13.4|Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13| |**14**|**Contact information. . . . . . . . . . . . . . . . . . . . . 13**| |**15**|**Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14**| **==> picture [151 x 121] intentionally omitted <==** Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. **© NXP B.V. 2009.** **All rights reserved.** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 28 August 2009 Document identifier: PMP5501V_G_Y_3**
Updated at June 10, 2026
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