Image not available
Illustrative purposes only
PHB21N06LT,118
Power MOSFET, N Channel, 55 V, 19 A, 0.055 ohm, TO-263 (D2PAK), Surface Mount
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: NEXPERIA
- Product type: Single MOSFETs
- MSL: MSL 1 - Unlimited
- SVHC: Lead (25-Jun-2025)
- No. of Pins: 3Pins
- Channel Type: N Channel
- Product Range: TrenchMOS
- Qualification: -
- Power Dissipation: 56W
- Transistor Mounting: Surface Mount
- Rds(on) Test Voltage: 10V
- Transistor Case Style: TO-263 (D2PAK)
- Drain Source Voltage Vds: 55V
- Operating Temperature Max: 175°C
- Continuous Drain Current Id: 19A
- Drain Source On State Resistance: 0.055ohm
- Gate Source Threshold Voltage Max: 1.5V
| Delivery and price | |
|---|---|
| Units per pack | 800 |
| Price | 0.398 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
## **Important notice** Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename **Nexperia** . Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use **http://www.nexperia.com** Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use **salesaddresses@nexperia.com** (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - **© Nexperia B.V. (year). All rights reserved** . If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via **salesaddresses@nexperia.com** ). Thank you for your cooperation and understanding, Kind regards, Team Nexperia **Philips Semiconductors** **Product specification** ## **N-channel TrenchMOS** **transistor Logic level FET** ## **PHP21N06LT, PHB21N06LT PHD21N06LT** **==> picture [559 x 111] intentionally omitted <==** **----- Start of picture text -----**<br> FEATURES SYMBOL QUICK REFERENCE DATA<br>• ’Trench’ technology d VDSS = 55 V<br>• Low on-state resistance<br>• Fast switching ID = 19 A<br>• Logic level compatible<br>g RDS(ON) ≤ 75 mΩ (VGS = 5 V)<br>RDS(ON) ≤ 70 mΩ (VGS = 10 V)<br>s<br>**----- End of picture text -----**<br> ## **GENERAL DESCRIPTION** N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’ **trench** ’ technology. ## **Applications:-** - d.c. to d.c. converters - switched mode power supplies The PHP21N06LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB21N06LT is supplied in the SOT404 (D[2] PAK) surface mounting package. The PHD21N06LT is supplied in the SOT428 (DPAK) surface mounting package. **==> picture [616 x 124] intentionally omitted <==** **----- Start of picture text -----**<br> PINNING SOT78 (TO220AB) SOT404 (D [2] PAK) SOT428 (DPAK)<br>PIN DESCRIPTION tab tab<br>tab<br>1 gate<br>2 drain [1]<br>2 2<br>3 source<br>1 2 3 1 3 1 3<br>tab drain<br>**----- End of picture text -----**<br> ## **LIMITING VALUES** Limiting values in accordance with the Absolute Maximum System (IEC 134) |||**SYMBOL PARAMETER**|**SYMBOL PARAMETER**|**SYMBOL PARAMETER**|**SYMBOL PARAMETER**|**SYMBOL PARAMETER**||**CONDITIONS**|**CONDITIONS**|**CONDITIONS**||||**MIN.**|**MIN.**||**MAX.**|**MAX.**|**MAX.**||**UNIT**|**UNIT**||||| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |||VDSS|Drain-source voltage|||||Tj= 25 ˚C to||175˚C||||-||||55||||V||||| |||VDGR|Drain-gate voltage|||||Tj= 25 ˚C to||175˚C; RGS= 20 kΩ||||-||||55||||V||||| |||VGS|Gate-source|||voltage||||||||-|||±15|||||V||||| |||VGSM|Pulsed gate-source voltage|||||Tj ≤150˚C||||||-|||±20|||||V||||| |||ID|Continuous drain current|||||Tmb= 25 ˚C||||||-||||19||||A||||| |||||||||Tmb= 100 ˚C||||||-||||13||||A||||| |||IDM|Pulsed drain current|||||Tmb= 25 ˚C||||||-||||76||||A||||| |||PD|Total power dissipation|||||Tmb= 25 ˚C||||||-||||56||||W||||| |||Tj, Tstg|Operating junction and|||||||||||- 55|||175|||||˚C||||| ||||storage temperature|||||||||||||||||||||||| > **1** It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages. August 1999 Rev 1.500 1 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET ## PHP21N06LT, PHB21N06LT PHD21N06LT ## **AVALANCHE ENERGY LIMITING VALUES** Limiting values in accordance with the Absolute Maximum System (IEC 134) |**SYMBOL PARAMETER**|**SYMBOL PARAMETER**|**SYMBOL PARAMETER**|**SYMBOL PARAMETER**|**SYMBOL PARAMETER**|**SYMBOL PARAMETER**||**CONDITIONS**|**CONDITIONS**|**CONDITIONS**|||**MIN.**||**MAX.**||**UNIT**|||| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |EAS|||Non-repetitive avalanche||||Unclamped inductive load, IAS= 9.7 A;|||||-||34||mJ|||| ||||energy||||tp= 100µs; Tjprior to avalanche = 25˚C;||||||||||||| ||||||||VDD ≤25 V; RGS= 50Ω; VGS= 5 V; refer to||||||||||||| ||||||||fig:15||||||||||||| |IAS|||Peak non-repetitive|||||||||-||19||A|||| ||||avalanche current||||||||||||||||| ## **THERMAL RESISTANCES** ||**SYMBOL PARAMETER**<br>**CONDITIONS**<br>**TYP.**<br>**MAX.**<br>**UNIT**<br>Rth j-mb<br>Thermal resistance junction<br>-<br>2.7<br>K/W<br>to mounting base<br>Rth j-a<br>Thermal resistance junction<br>SOT78 package, in free air<br>60<br>-<br>K/W<br>to ambient<br>SOT428 and SOT404 package, pcb<br>50<br>-<br>K/W<br>mounted, minimum footprint| |---|---| ## **ELECTRICAL CHARACTERISTICS** Tj= 25˚C unless otherwise specified ||**SYMBOL PARAMETER**|**SYMBOL PARAMETER**|**SYMBOL PARAMETER**|**SYMBOL PARAMETER**|**SYMBOL PARAMETER**|**SYMBOL PARAMETER**|**SYMBOL PARAMETER**|**SYMBOL PARAMETER**|**SYMBOL PARAMETER**|||||||**CONDITIONS**|**CONDITIONS**|**CONDITIONS**|**CONDITIONS**|**CONDITIONS**|||||||||**MIN.**|**MIN.**|**MIN.**|**MIN.**|**MIN.**|||**TYP.**|**TYP.**|**TYP.**|**TYP.**|**TYP.**||**MAX.**|**MAX.**|**MAX.**|**MAX.**|**MAX.**|**MAX.**||**UNIT**|**UNIT**|**UNIT**|**UNIT**|**UNIT**|||||||| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| ||V(BR)DSS||||Drain-source breakdown|||||||||||VGS||= 0 V; ID= 0.25 mA;||||||||||||55||||||||-|||||||-|||||V||||||||||| ||||||voltage|||||||||||||||||Tj= -55˚C||||||||50||||||||-|||||||-|||||V||||||||||| ||VGS(TO)||||Gate|||threshold|||voltage|||||VDS||= VGS; ID= 1 mA||||||||||||1.0|||||||1.5|||||||2.0||||||V||||||||||| |||||||||||||||||||||||Tj=|175˚C|||||||0.5||||||||-|||||||-|||||V||||||||||| |||||||||||||||||||||||Tj= -55˚C|||||||||-|||||||-||||||2.3||||||V||||||||||| ||RDS(ON)||||Drain-source on-state|||||||||||VGS||= 10 V; ID= 10 A|||||||||||||-||||||55|||||||70|||||mΩ|||||||||||| ||||||resistance|||||||||||VGS||= 5 V; ID= 10 A|||||||||||||-||||||60|||||||75|||||mΩ|||||||||||| |||||||||||||||||||||||Tj=|175˚C||||||||-|||||||-|||||158||||||mΩ|||||||||||| ||gfs||||Forward transconductance|||||||||||VDS||= 25 V; ID= 10 A|||||||||||||5||||||13||||||||-|||||S||||||||||| ||IGSS||||Gate|||source leakage current<br>VGS||||||||||=±5 V; VDS= 0 V|||||||||||||-||||||10|||||||100||||||nA||||||||||| ||IDSS||||Zero|||gate voltage drain||||||||VDS||= 55 V; VGS= 0 V;|||||||||||||-|||||0.05||||||||10||||||µA||||||||||| ||||||current|||||||||||||||||Tj=|175˚C||||||||-|||||||-|||||500|||||||µA||||||||||| ||Qg(tot)||||Total gate charge|||||||||||ID=||20 A; VDD= 44 V; VGS= 5 V|||||||||||||-||||||9.4||||||||-|||||nC||||||||||| ||Qgs||||Gate-source charge||||||||||||||||||||||||||-||||||2.2||||||||-|||||nC||||||||||| ||Qgd||||Gate-drain(Miller)charge||||||||||||||||||||||||||-||||||5.4||||||||-|||||nC||||||||||| ||td on||||Turn-on delay|||||time||||||VDD||= 30 V; RD|||= 1.2Ω;||||||||||-|||||||7||||||15||||||ns||||||||||| ||tr||||Turn-on rise time|||||||||||RG=|||10Ω; VGS||= 5 V||||||||||-||||||88||||||120|||||||ns||||||||||| ||td off||||Turn-off delay|||||time||||||Resistive load|||||||||||||||-||||||25|||||||40||||||ns||||||||||| ||tf||||Turn-off fall time||||||||||||||||||||||||||-||||||25|||||||45||||||ns||||||||||| ||Ld||||Internal drain inductance|||||||||||Measured from tab to centre of die|||||||||||||||-||||||3.5||||||||-|||||nH||||||||||| ||Ld||||Internal drain inductance|||||||||||Measured from drain lead to centre of die|||||||||||||||-||||||4.5||||||||-|||||nH||||||||||| |||||||||||||||||(SOT78 package only)||||||||||||||||||||||||||||||||||||||||||||| ||Ls||||Internal source||||||inductance|||||Measured from source lead||||||to source|||||||||-||||||7.5||||||||-|||||nH||||||||||| |||||||||||||||||bond pad||||||||||||||||||||||||||||||||||||||||||||| ||Ciss||||Input capacitance|||||||||||VGS||= 0 V; VDS= 25 V; f = 1 MHz|||||||||||||-||||||466||||||650|||||||pF||||||||||| ||Coss||||Output capacitance||||||||||||||||||||||||||-||||||95||||||135|||||||pF||||||||||| ||Crss||||Feedback capacitance||||||||||||||||||||||||||-||||||71|||||||85||||||pF||||||||||| August 1999 Rev 1.500 2 Philips Semiconductors Product specification ## N-channel TrenchMOS transistor Logic level FET ## PHP21N06LT, PHB21N06LT PHD21N06LT ## **REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS** ## Tj = 25˚C unless otherwise specified |**SYMBOL PARAMETER**|**SYMBOL PARAMETER**|**SYMBOL PARAMETER**|**SYMBOL PARAMETER**|**SYMBOL PARAMETER**|||**CONDITIONS**|**CONDITIONS**|**CONDITIONS**|**CONDITIONS**||||**MIN.**|**MIN.**|**MIN.**|**MIN.**|**MIN.**||**TYP.**|**TYP.**|**TYP.**|**TYP.**|**TYP.**||**MAX.**|**MAX.**|**MAX.**|**MAX.**|**MAX.**||**UNIT**|**UNIT**|**UNIT**|**UNIT**|**UNIT**|||| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |IS|||Continuous source current|||||||||||||-||||||-|||||19||||||A||||||| ||||(body|diode)|||||||||||||||||||||||||||||||||||| |ISM|||Pulsed source current (body|||||||||||||-||||||-|||||76||||||A||||||| ||||diode)||||||||||||||||||||||||||||||||||||| |VSD|||Diode|forward voltage|||IF= 20 A; VGS= 0 V|||||||||-|||||1.2||||||1.5||||||V||||||| |trr|||Reverse recovery time||||IF= 20 A; -dIF/dt = 100 A/µs;|||||||||-|||||43|||||||-|||||ns||||||| |Qrr|||Reverse recoverycharge||||VGS= 0 V; VR= 30 V|||||||||-|||||94|||||||-|||||nC||||||| **==> picture [327 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> Normalised Power Derating, PD (%)<br>100<br>90<br>80<br>70<br>60<br>50<br>40<br>30<br>20<br>10<br>0<br>0 25 50 75 100 125 150 175<br>Mounting Base temperature, Tmb (C)<br>Fig.1. Normalised power dissipation.<br>PD% = 100⋅PD/PD 25 ˚C = f(Tmb)<br>**----- End of picture text -----**<br> **==> picture [214 x 151] intentionally omitted <==** **----- Start of picture text -----**<br> 100 Peak Pulsed Drain Current, IDM (A)<br>RDS(on) = VDS/ ID<br>tp = 10 us<br>10<br>100 us<br>1 ms<br>D.C.<br>10 ms<br>1<br>100 ms<br>0.1<br>1 10 100<br>Drain-Source Voltage, VDS (V)<br>**----- End of picture text -----**<br> Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp **==> picture [480 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> Normalised Current Derating, ID (%) 10 Transient thermal impedance, Zth j-mb (K/W)<br>100<br>90 D = 0.5<br>80<br>70 1 0.2<br>60 0.1<br>50 0.05<br>40 0.1 0.02 PD tp D = tp/T<br>30<br>single pulse<br>20<br>10 T<br>0 0.01<br>0 25 50 75 100 125 150 175 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00<br>Mounting Base temperature, Tmb (C) Pulse width, tp (s)<br>**----- End of picture text -----**<br> Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 5 V Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T August 1999 Rev 1.500 3 Philips Semiconductors Product specification ## N-channel TrenchMOS transistor Logic level FET ## PHP21N06LT, PHB21N06LT PHD21N06LT **==> picture [479 x 151] intentionally omitted <==** **----- Start of picture text -----**<br> 35 Drain Current, ID (A) 15 Transconductance, gfs (S)<br>Tj = 25 C 14 VDS > ID X RDS(ON) Tj = 25 C<br>30 VGS = 10V 5 V 13<br>12<br>25 11 175 C<br>10<br>9<br>20<br>3.4 V 8<br>7<br>15 3.2 V 6<br>3 V 5<br>10 4<br>2.8 V 3<br>5 2.6 V 2<br>2.4 V 1<br>0 0<br>0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 2 4 6 8 10 12 14 16 18 20<br>Drain-Source Voltage, VDS (V) Drain current, ID (A)<br>**----- End of picture text -----**<br> Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS) Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID) **==> picture [207 x 146] intentionally omitted <==** **----- Start of picture text -----**<br> Drain-Source On Resistance, RDS(on) (Ohms)<br>0.3<br>2.6 V 2.8V Tj = 25 C<br>0.25<br>2.4 V<br>0.2 3 V<br>3.2 V<br>0.15<br>3.4 V<br>0.1<br>5 V<br>0.05<br>VGS = 10V<br>0<br>0 5 10 15 20 25 30 35<br>Drain Current, ID (A)<br>**----- End of picture text -----**<br> Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID) **==> picture [220 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> Normalised On-state Resistance<br>2.4<br>2.2<br>2<br>1.8<br>1.6<br>1.4<br>1.2<br>1<br>0.8<br>0.6<br>0.4<br>0.2<br>0<br>-60 -40 -20 0 20 40 60 80 100 120 140 160 180<br>Junction temperature, Tj (C)<br>**----- End of picture text -----**<br> Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 ˚C = f(Tj) **==> picture [700 x 190] intentionally omitted <==** **----- Start of picture text -----**<br> Drain current, ID (A) 2.25 Threshold Voltage, VGS(TO) (V)<br>20<br>18 VDS > ID X RDS(ON) 2 maximum<br>16 1.75<br>14 1.5 typical<br>12 1.25<br>10 minimum<br>1<br>8<br>0.75<br>6<br>4 0.5<br>175 C<br>2 Tj = 25 C 0.25<br>0 0<br>0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180<br>Gate-source voltage, VGS (V) Junction Temperature, Tj (C)<br>Fig.7. Typical transfer characteristics. Fig.10. Gate threshold voltage.<br>ID = f(VGS) VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS<br>**----- End of picture text -----**<br> August 1999 Rev 1.500 4 Philips Semiconductors Product specification ## N-channel TrenchMOS transistor Logic level FET ## PHP21N06LT, PHB21N06LT PHD21N06LT **==> picture [700 x 190] intentionally omitted <==** **----- Start of picture text -----**<br> 1.0E-01 Drain current, ID (A) Source-Drain Diode Current, IF (A)<br>30<br>VGS = 0 V<br>1.0E-02 25<br>20<br>1.0E-03 minimum<br>typical 15<br>175 C<br>1.0E-04 maximum Tj = 25 C<br>10<br>1.0E-05 5<br>1.0E-06 0<br>0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5<br>0 0.5 1 1.5 2 2.5 3<br>Gate-source voltage, VGS (V) Source-Drain Voltage, VSDS (V)<br>Fig.11. Sub-threshold drain current. Fig.14. Typical reverse diode current.<br>ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS IF = f(VSDS); conditions: VGS = 0 V; parameter Tj<br>**----- End of picture text -----**<br> **==> picture [341 x 357] intentionally omitted <==** **----- Start of picture text -----**<br> Capacitances, Ciss, Coss, Crss (pF)<br>10000<br>1000<br>Ciss<br>Coss<br>100<br>Crss<br>10<br>0.1 1 10 100<br>Drain-Source Voltage, VDS (V)<br>Fig.12. Typical capacitances, Ciss, Coss, Crss.<br>C = f(VDS); conditions: VGS = 0 V; f = 1 MHz<br>Gate-source voltage, VGS (V)<br>15<br>14 ID = 20A<br>13 Tj = 25 C<br>12<br>11<br>10 VDD = 11 V<br>9<br>8<br>VDD = 44 V<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>0<br>0 2 4 6 8 10 12 14 16 18 20<br>Gate charge, QG (nC)<br>**----- End of picture text -----**<br> **==> picture [209 x 145] intentionally omitted <==** **----- Start of picture text -----**<br> Maximum Avalanche Current, IAS (A)<br>100<br>10 25 C<br>1 Tj prior to avalanche = 150 C<br>0.1<br>0.001 0.01 0.1 1 10<br>Avalanche time, tAV (ms)<br>**----- End of picture text -----**<br> Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tAV); unclamped inductive load Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG) August 1999 Rev 1.500 5 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET ## PHP21N06LT, PHB21N06LT PHD21N06LT ## **MECHANICAL DATA** **==> picture [1032 x 522] intentionally omitted <==** **----- Start of picture text -----**<br> Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220 SOT78<br>E A<br>P A1<br>q<br>D1<br>D<br>L2 [(1)] L1<br>Q<br>b1<br>L<br>1 2 3<br>b c<br>e e<br>0 5 10 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>(1)<br>UNIT A A1 b b1 c D D1 E e L L1 L2 P q Q<br>max.<br>mm 4.5 1.39 0.9 1.3 0.7 15.8 6.4 10.3 2.54 15.0 3.30 3.0 3.8 3.0 2.6<br>4.1 1.27 0.7 1.0 0.4 15.2 5.9 9.7 13.5 2.79 3.6 2.7 2.2<br>Note<br>1. Terminals in this zone are not tinned.<br>OUTLINE REFERENCES EUROPEAN ISSUE DATE<br>VERSION IEC JEDEC EIAJ PROJECTION<br> SOT78 TO-220 97-06-11<br>Fig.16. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)<br>**----- End of picture text -----**<br> ## **Notes** 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to mounting instructions for SOT78 (TO220AB) package. 3. Epoxy meets UL94 V0 at 1/8". August 1999 Rev 1.500 6 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET ## PHP21N06LT, PHB21N06LT PHD21N06LT ## **MECHANICAL DATA** **==> picture [975 x 465] intentionally omitted <==** **----- Start of picture text -----**<br> Plastic single-ended surface mounted package (Philips version of D [2] -PAK); 3 leads<br>(one lead cropped) SOT404<br>A<br>E A1<br>D1 mounting<br>base<br>D<br>HD<br>2<br>Lp<br>1 3<br>b c<br>e e Q<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT A A1 b c max.D D1 E e Lp HD Q<br>mm 4.50 1.40 0.85 0.64 11 1.60 10.30 2.54 2.90 15.40 2.60<br>4.10 1.27 0.60 0.46 1.20 9.70 2.10 14.80 2.20<br>VERSIONOUTLINE IEC JEDEC REFERENCES EIAJ PROJECTIONEUROPEAN ISSUE DATE<br> SOT404 98-12-14 99-06-25<br>Fig.17. SOT404 surface mounting package. Centre pin connected to mounting base.<br>**----- End of picture text -----**<br> ## **Notes** 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". August 1999 Rev 1.500 7 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET PHP21N06LT, PHB21N06LT PHD21N06LT ## **MOUNTING INSTRUCTIONS** **==> picture [737 x 227] intentionally omitted <==** **----- Start of picture text -----**<br> Dimensions in mm<br>11.5<br>9.0<br>17.5<br>2.0<br>3.8<br>5.08<br>Fig.18. SOT404 : soldering pattern for surface mounting.<br>**----- End of picture text -----**<br> August 1999 Rev 1.500 8 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET ## PHP21N06LT, PHB21N06LT PHD21N06LT ## **MECHANICAL DATA** **==> picture [975 x 465] intentionally omitted <==** **----- Start of picture text -----**<br> Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads<br>(one lead cropped) SOT428<br>seating plane<br>y<br>A<br>E A A2<br>b2 A1 D1<br>mounting<br>base<br>E1<br>D<br>HE<br>L2<br>2<br>L L1<br>1 3<br>b1 b w M A c<br>e<br>e1<br>0 10 20 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT max.A A1 [(1)] A2 b max.b1 b2 c max.D max.D1 max.E min.E1 e e1 max.HE L min.L1 L2 w max.y<br>mm 2.38 0.65 0.89 0.89 1.1 5.36 0.4 6.22 4.81 6.73 4.0 2.285 4.57 10.4 2.95 0.5 0.7 0.2 0.2<br>2.22 0.45 0.71 0.71 0.9 5.26 0.2 5.98 4.45 6.47 9.6 2.55 0.5<br>Note<br>1. Measured from heatsink back to lead.<br>VERSIONOUTLINE IEC JEDEC REFERENCES EIAJ PROJECTIONEUROPEAN ISSUE DATE<br> SOT428 98-04-07<br>Fig.19. SOT428 surface mounting package. Centre pin connected to mounting base.<br>**----- End of picture text -----**<br> ## **Notes** 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8". ## **MOUNTING INSTRUCTIONS** August 1999 Rev 1.500 9 Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FET ## PHP21N06LT, PHB21N06LT PHD21N06LT **==> picture [737 x 227] intentionally omitted <==** **----- Start of picture text -----**<br> Dimensions in mm<br>7.0<br>7.0<br>2.15 1.5<br>2.5<br>4.57<br>Fig.20. SOT428 : soldering pattern for surface mounting.<br>**----- End of picture text -----**<br> August 1999 Rev 1.500 10 |Philips Semiconductors|Product specification| |---|---| |N-channel TrenchMOStransistor|PHP21N06LT, PHB21N06LT| |Logic level FET|PHD21N06LT| ## **DEFINITIONS** |**DEFINITIONS**||||| |---|---|---|---|---| |**Data sheet status**||||| |Objective specification|This data sheet contains target orgoal specifications forproduct development.|||| |Preliminaryspecification This data sheet containspreliminarydata; supplementarydata maybepublished later.||||| |Product specification|This data sheet contains final product specifications.|||| ## **Limiting values** Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. ## **Application information** Where application information is given, it is advisory and does not form part of the specification. ## **Philips Electronics N.V. 1999** All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. ## **LIFE SUPPORT APPLICATIONS** These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August 1999 Rev 1.500 11
Updated at April 29, 2026
Nexperia is a dedicated global leader in discretes, logic, and MOSFET devices. Built on over half a century of semiconductor expertise and operating independently since 2017, the company produces consistently reliable components at an exceptional volume of 85 billion units annually. With its own manufacturing facilities, Nexperia delivers industry-leading small packages that combine power and thermal efficiency with best-in-class quality, meeting the rigorous standards of the automotive sector. Our extensive Nexperia portfolio is heavily focused on discrete semiconductors, providing engineers with a robust selection of core building blocks. This includes a comprehensive range of diodes and rectifiers, featuring a vast selection of Zener single diodes and Schottky diodes designed for precise voltage regulation and efficient power routing. Additionally, we offer an expansive array of bipolar transistors and single MOSFETs tailored for reliable switching and amplification in demanding applications. Beyond these primary offerings, the lineup extends into specialized circuit protection and passive components. This includes transient voltage suppressor (TVS) diodes, Zener array diodes, and small signal diodes, alongside dual MOSFETs and fast recovery rectifiers. For comprehensive design needs, the selection also encompasses integrated passive filters, common mode chokes, and precision timers and oscillators, ensuring a complete solution for high-performance electronic systems.
About Novapart
Novapart is a B2B electronic component broker specialising in stock shortages and cost reduction. We source hard-to-find parts and identify compliant alternatives across a catalogue of 410,000+ components from 500+ manufacturers.
Learn more →Stock Shortage Specialist
When a component is unavailable, discontinued or has an unacceptable lead time, we tap into our network of vetted European and Asian distributors to source what you need — without compromising on quality or traceability.
Request a quote →Compliant Alternatives
We identify pin-to-pin, electrically equivalent substitutes that meet the same certifications (RoHS, AEC-Q100, REACH) as your original specification — validated against datasheets, not just part numbers. Often at a lower cost.
BOM Analysis service →