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PDTB143EQAZ
Bipolar Pre-Biased / Digital Transistor, Single PNP, 50 V, 500 mA, 4.7 kohm, 4.7 kohm
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- Manufacturer: NEXPERIA
- Product type: Pre-Biased / Digital Bipolar Transistors
- Digital Transistor Polarity:Single PNP; Collector Emitter Voltage V(br)ceo:-50V; Continuous Collector Current Ic:-500mA; Base Input Resistor R1:4.7kohm; Base-Emitter Resistor R2:4.7
- MSL: MSL 1 - Unlimited
- SVHC: No SVHC (25-Jun-2025)
- No. of Pins: 3 Pin
- Product Range: -
- Qualification: AEC-Q101
- Power Dissipation: 325mW
- Transistor Mounting: Surface Mount
- Transistor Polarity: Single PNP
- Transistor Case Style: SOT-1215
- Base Input Resistor R1: 4.7kohm
- DC Current Gain hFE Min: 60hFE
- Base Emitter Resistor R2: 4.7kohm
- Operating Temperature Max: 150°C
- Continuous Collector Current: 500mA
- Collector Emitter Voltage Max NPN: -
- Collector Emitter Voltage Max PNP: 50V
| Delivery and price | |
|---|---|
| Units per pack | 5000 |
| Price | 0.08 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
## **Important notice** Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename **Nexperia** . Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use **http://www.nexperia.com** Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use **salesaddresses@nexperia.com** (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - **© Nexperia B.V. (year). All rights reserved** . If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via **salesaddresses@nexperia.com** ). Thank you for your cooperation and understanding, Kind regards, Team Nexperia **==> picture [32 x 39] intentionally omitted <==** **----- Start of picture text -----**<br> =r<br>DFN1010D-3<br>**----- End of picture text -----**<br> ## **PDTB113/123/143/114EQA series** ## **50 V, 500 mA PNP resistor-equipped transistors** **Rev. 1 — 30 March 2016 Product data sheet** ## **1. Product profile** ## **1.1 General description** PNP Resistor-Equipped Transistor (RET) family in a leadless ultra small DFN1010D-3 (SOT1215) Surface-Mounted Device (SMD) plastic package with visible and solderable side pads. ## **Table 1. Product overview** |**Type number**|**R1**|**R2**|**Package NXP**|**NPN complement**| |---|---|---|---|---| |PDTB113EQA|1 k|1 k|DFN1010D-3<br>(SOT1215)|PDTD113EQA| |PDTB123EQA|2.2 k|2.2 k||PDTD123EQA| |PDTB143EQA|4.7 k|4.7 k||PDTD143EQA| |PDTB114EQA|10 k|10 k||PDTD114EQA| ## **1.2 Features and benefits** - 500 mA output current capability - Built-in bias resistors - 10% resistor ratio tolerance - Simplifies circuit design - Reduced pick and place costs - Low package height of 0.37 mm - Suitable for Automatic Optical Inspection (AOI) of solder joint - AEC-Q101 qualified - Reduces component count ## **1.3 Applications** - Digital applications - Cost saving alternative for BC807/BC817 series in digital applications - Controlling IC inputs - Switching loads ## **1.4 Quick reference data** **Table 2. Quick reference data** |**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---| |VCEO|collector-emitter voltage|open base|-|-|50|V| |IO|output current||-|-|500|mA| **PDTB113/123/143/114EQA** **NXP Semiconductors** **50 V, 500 mA PNP resistor-equipped transistors** ## **2. Pinning information** **Table 3. Pinning** **==> picture [396 x 130] intentionally omitted <==** **----- Start of picture text -----**<br> Pin Symbol Description Simplified outline Graphic symbol<br>1 I input (base)<br>2 GND GND (emitter) 1 O<br>R1<br>3 O output (collector) I<br>4 O output (collector) 4 3 R2<br>GND<br>2<br>aaa-019606<br>Transparent top view<br>**----- End of picture text -----**<br> ## **3. Ordering information** **Table 4. Ordering information** |**Type number**|**Package**|**Package**|**Package**| |---|---|---|---| ||**Name**|**Description**|**Version**| |PDTB113EQA|DFN1010D-3|plastic thermal enhanced ultra thin small outline<br>package; no leads; 3 terminals;<br>body: 1.11.00.37 mm|SOT1215| |PDTB123EQA|||| |PDTB143EQA|||| |PDTB114EQA|||| © NXP Semiconductors N.V. 2016. All rights reserved. PDTB113_123_143_114EQA_SER **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 1 — 30 March 2016** **2 of 23** **PDTB113/123/143/114EQA** **NXP Semiconductors** **50 V, 500 mA PNP resistor-equipped transistors** ## **4. Marking** ## **Table 5. Marking codes** |**Type number**|**Marking code**| |---|---| |PDTB113EQA|00 00 01| |PDTB123EQA|01 01 01| |PDTB143EQA|01 01 11| |PDTB114EQA|01 10 11| ## **4.1 Binary marking code description** **==> picture [358 x 187] intentionally omitted <==** **----- Start of picture text -----**<br> READING<br>DIRECTION<br>MARKING CODE<br>(EXAMPLE)<br>YEAR DATE<br>CODE<br>VENDOR CODE<br>PIN 1<br>MARK-FREE AREA<br>INDICATION MARK<br>READING EXAMPLE:<br>11<br>01<br>10<br>aaa-008041<br>**----- End of picture text -----**<br> **Fig 1. SOT1215 binary marking code description** ## **5. Limiting values** ## **Table 6. Limiting values** _In accordance with the Absolute Maximum Rating System (IEC 60134)._ |**Symbol**|**Parameter**|**Conditions**|**Min**|**Max**|**Unit**| |---|---|---|---|---|---| |VCBO|collector-base voltage|open emitter|-|50|V| |VCEO|collector-emitter voltage|open base|-|50|V| |VEBO|emitter-base voltage|open collector|-|10|V| © NXP Semiconductors N.V. 2016. All rights reserved. PDTB113_123_143_114EQA_SER **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 1 — 30 March 2016** **3 of 23** **PDTB113/123/143/114EQA** **NXP Semiconductors** **50 V, 500 mA PNP resistor-equipped transistors** **Table 6. Limiting values** _…continued_ _In accordance with the Absolute Maximum Rating System (IEC 60134)._ |**Symbol**|**Parameter**|**Conditions**||**Min**|**Max**|**Unit**| |---|---|---|---|---|---|---| |VI|input voltage|||||| ||PDTB113EQA|||10|+10|V| ||PDTB123EQA|||12|+10|V| ||PDTB143EQA|||30|+10|V| ||PDTB114EQA|||50|+10|V| |IO|output current|||-|500|mA| |Ptot|total power dissipation|Tamb25C|[1]|-|325|mW| ||||[2]|-|575|mW| ||||[3]|-|525|mW| ||||[4]|-|940|mW| |Tj|junction temperature|||-|150|C| |Tamb|ambient temperature|||55|+150|C| |Tstg|storage temperature|||65|+150|C| - [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. - [2] Device mounted on an FR4 PCB, single-sided copper, tin-plated; mounting pad for collector 1 cm[2] . - [3] Device mounted on an FR4 PCB, 4-layer copper, tin-plated and standard footprint. - [4] Device mounted on an FR4 PCB, 4-layer copper, tin-plated; mounting pad for collector 1 cm[2] . **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020277<br>1<br>Ptot (1)<br>(W)<br>0.8<br>0.6<br>(2)<br>(3)<br>0.4<br>(4)<br>0.2<br>0<br>-75 -25 25 75 125 175<br>Tamb (ºC)<br>**----- End of picture text -----**<br> - (1) FR4 PCB, 4-layer copper, 1 cm[2] - (2) FR4 PCB, single-sided copper, 1 cm[2] - (3) FR4 PCB, 4-layer copper, standard footprint - (4) FR4 PCB, single sided copper, standard footprint **Fig 2. Power derating curves** © NXP Semiconductors N.V. 2016. All rights reserved. PDTB113_123_143_114EQA_SER **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 1 — 30 March 2016** **4 of 23** **PDTB113/123/143/114EQA** **NXP Semiconductors** **50 V, 500 mA PNP resistor-equipped transistors** ## **6. Thermal characteristics** ## **Table 7. Thermal characteristics** |**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---|---| |Rth(j-a)|thermal resistance from junction<br>to ambient|in free air|[1]|-|-|385|K/W| ||||[2]|-|-|218|K/W| ||||[3]|-|-|239|K/W| ||||[4]|-|-|133|K/W| |Rth(j-sp)|thermal resistance from junction<br>to solder point|||-|-|40|K/W| - [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint. - [2] Device mounted on an FR4 PCB, single-sided copper, tin-plated; mounting pad for collector 1 cm[2] . - [3] Device mounted on an FR4 PCB, 4-layer copper, tin-plated and standard footprint. - [4] Device mounted on an FR4 PCB, 4-layer copper, tin-plated; mounting pad for collector 1 cm[2] . **==> picture [481 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020278<br>10 [3]<br>Zth(j-a) duty cycle = 1<br>(K/W) 0.75<br>0.5<br>0.33<br>10 [2]<br>0.2<br>0.1<br>0.05<br>10 0.02<br>0.01<br>0<br>1<br>10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 1 10 10 [2] 10 [3]<br>tp (s)<br>**----- End of picture text -----**<br> FR4 PCB, single-sided copper, tin-plated and standard footprint. **Fig 3. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values** © NXP Semiconductors N.V. 2016. All rights reserved. PDTB113_123_143_114EQA_SER **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 1 — 30 March 2016** **5 of 23** **PDTB113/123/143/114EQA** **NXP Semiconductors** ## **50 V, 500 mA PNP resistor-equipped transistors** **==> picture [481 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020279<br>10 [3]<br>Zth(j-a)<br>(K/W)<br>duty cycle = 1<br>0.75<br>10 [2] 0.5<br>0.33<br>0.2<br>0.1<br>0.05<br>10<br>0.02 0.01<br>0<br>1<br>10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 1 10 10 [2] 10 [3]<br>tp (s)<br>**----- End of picture text -----**<br> FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm[2] . **Fig 4. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values** **==> picture [481 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020281<br>10 [3]<br>Zth(j-a)<br>(K/W)<br>duty cycle = 1<br>0.75<br>10 [2] 0.5<br>0.33<br>0.2<br>0.1<br>0.05<br>10<br>0.02 0.01<br>0<br>1<br>10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 1 10 10 [2] 10 [3]<br>tp (s)<br>**----- End of picture text -----**<br> FR4 PCB, 4-layer copper, tin-plated and standard footprint. **Fig 5. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values** © NXP Semiconductors N.V. 2016. All rights reserved. PDTB113_123_143_114EQA_SER **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 1 — 30 March 2016** **6 of 23** **PDTB113/123/143/114EQA** **NXP Semiconductors** **50 V, 500 mA PNP resistor-equipped transistors** **==> picture [481 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020280<br>10 [3]<br>Zth(j-a)<br>(K/W)<br>duty cycle = 1<br>10 [2] 0.75<br>0.5<br>0.33<br>0.2<br>0.1<br>10<br>0.05<br>0.02 0.01<br>0<br>1<br>10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 1 10 10 [2] 10 [3]<br>tp (s)<br>**----- End of picture text -----**<br> FR4 PCB, 4-layer copper, tin-plated; mounting pad for collector 1 cm[2] **Fig 6. Transient thermal impedance from junction to ambient as a function of pulse duration; typical values** © NXP Semiconductors N.V. 2016. All rights reserved. PDTB113_123_143_114EQA_SER **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 1 — 30 March 2016** **7 of 23** **PDTB113/123/143/114EQA** **NXP Semiconductors** **50 V, 500 mA PNP resistor-equipped transistors** ## **7. Characteristics** **Table 8. Characteristics** _Tamb = 25_ _C unless otherwise specified._ |**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---| |ICBO|collector-base cut-off<br>current|VCB=50 V; IE= 0 A|-|-|100|nA| |ICEO|collector-emitter cut-off<br>current|VCE=50 V; IB= 0 A|-|-|0.5|A| |IEBO|emitter-base cut-off current|||||| ||PDTB113EQA|VEB=5 V; IC= 0 A|-|-|4|mA| ||PDTB123EQA||-|-|2|mA| ||PDTB143EQA||-|-|0.9|mA| ||PDTB114EQA||-|-|0.4|mA| |hFE|DC current gain|||||| ||PDTB113EQA|VCE=5 V; IC=50 mA|33|-|-|| ||PDTB123EQA||40|-|-|| ||PDTB143EQA||60|-|-|| ||PDTB114EQA||70|-|-|| |VCEsat|collector-emitter<br>saturation voltage|IC=50 mA; IB=2.5 mA|-|-|100|mV| |VI(off)|off-state input voltage|||||| ||PDTB113EQA|VCE=5 V; IC=100A|0.6|1.05|1.5|V| ||PDTB123EQA||0.6|1.05|1.8|V| ||PDTB143EQA||0.6|1.05|1.5|V| ||PDTB114EQA||0.6|1.05|1.5|V| |VI(on)|on-state input voltage|||||| ||PDTB113EQA|VCE=0.3 V; IC=20 mA|1|1.45|1.8|V| ||PDTB123EQA||1|1.5|2|V| ||PDTB143EQA||1|1.7|2.2|V| ||PDTB114EQA||1|2.2|3|V| |R1|bias resistor 1 (input)|[1]||||| ||PDTB113EQA||0.7|1|1.3|k| ||PDTB123EQA||1.54|2.2|2.86|k| ||PDTB143EQA||3.3|4.7|6.1|k| ||PDTB114EQA||7|10|13|k| |R2/R1|bias resistor ratio|[1]|0.9|1|1.1|| |Cc|collector capacitance|VCB=10 V; IE= ie= 0 A; f = 1 MHz|-|7|-|pF| |fT|transition frequency|VCE=5 V; IC=50 mA; f = 100 MHz<br>[2]|-|150|-|MHz| [1] See section test information for resistor calculation and test conditions. [2] Characteristics of built-in transistor. © NXP Semiconductors N.V. 2016. All rights reserved. PDTB113_123_143_114EQA_SER **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 1 — 30 March 2016** **8 of 23** **PDTB113/123/143/114EQA** **NXP Semiconductors** ## **50 V, 500 mA PNP resistor-equipped transistors** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020282<br>10 [3]<br>hFE (1)<br>(2)<br>10 [2] (3)<br>10<br>1<br>10 [-1]<br>-10 [-1] -1 -10 -10 [2] -10 [3]<br>IC (mA)<br>**----- End of picture text -----**<br> VCE = 5 V **==> picture [233 x 209] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020283<br>-0.5<br>IC IB (mA) = -3.6 -3.24<br>(A)<br>-0.4<br>-2.88<br>-2.52<br>-0.3<br>-2.16<br>-1.8<br>-0.2<br>-1.44<br>-0.1 -1.08<br>-0.72<br>0<br>0 -1 -2 -3 -4 -5<br>VCE (V)<br>Tamb = 25 C<br>**----- End of picture text -----**<br> (1) Tamb = 100 C - (2) Tamb = 25 C (3) Tamb = 40 C **Fig 7. PDTB113EQA: DC current gain as a function of Fig 8. PDTB113EQA: Collector current as a function collector current; typical values of collector-emitter voltage; typical values** **==> picture [234 x 276] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020285<br>-10<br>VI(on)<br>(V)<br>-1<br>(1)<br>(2)<br>(3)<br>-10 [-1]<br>-10 [-1] -1 -10 -10 [2] -10 [3]<br>IC (mA)<br>VCE = 0.3 V<br>(1) Tamb = 40 C<br>(2) Tamb = 25 C<br>(3) Tamb = 100 C<br>Fig 9. PDTB113EQA: On-state input voltage as a<br>function of collector current; typical values<br>**----- End of picture text -----**<br> **==> picture [235 x 276] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020286<br>-10<br>VI(off)<br>(V)<br>(1)<br>-1 (2)<br>(3)<br>-10 [-1]<br>-10 [-1] -1 -10<br>IC (mA)<br>VCE = 5 V<br>(1) Tamb = 40 C<br>(2) Tamb = 25 C<br>(3) Tamb = 100 C<br>Fig 10. PDTB113EQA: Off-state input voltage as a<br>function of collector current; typical values<br>**----- End of picture text -----**<br> © NXP Semiconductors N.V. 2016. All rights reserved. PDTB113_123_143_114EQA_SER **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 1 — 30 March 2016** **9 of 23** **PDTB113/123/143/114EQA** **NXP Semiconductors** ## **50 V, 500 mA PNP resistor-equipped transistors** **==> picture [233 x 209] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020284<br>-10 [-1]<br>VCEsat<br>(V)<br>(1)<br>(2)<br>(3)<br>-10 [-2]<br>-10 -10 [2] -10 [3]<br>IC (mA)<br>IC/IB = 20<br>**----- End of picture text -----**<br> **==> picture [233 x 209] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020287<br>35<br>30<br>Cc<br>(pF)<br>25<br>20<br>15<br>10<br>5<br>0<br>-0 -10 -20 -30 -40 -50<br>VCB (V)<br>f = 1 MHz; Tamb = 25 C<br>**----- End of picture text -----**<br> - (1) Tamb = 100 C - (2) Tamb = 25 C - (3) Tamb = 40 C - **Fig 11. PDTB113EQA: Collector-emitter saturation Fig 12. PDTB113EQA: Collector capacitance as a voltage as a function of collector current; function of collector-base voltage; typical typical values values** © NXP Semiconductors N.V. 2016. All rights reserved. PDTB113_123_143_114EQA_SER **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 1 — 30 March 2016** **10 of 23** **PDTB113/123/143/114EQA** **NXP Semiconductors** ## **50 V, 500 mA PNP resistor-equipped transistors** **==> picture [482 x 275] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020288 aaa-020289<br>10 [3] -0.5<br>hFE (1) IC IB (mA) = -3.47 -3.14<br>(2) (A)<br>(3) -0.4 -2.81<br>10 [2] -2.48<br>-2.15<br>-0.3<br>-1.82<br>10<br>-1.49<br>-0.2<br>-1.16<br>1<br>-0.83<br>-0.1<br>-0.5<br>10 [-1] 0<br>-10 [-1] -1 -10 -10 [2] -10 [3] 0 -1 -2 -3 -4 -5<br>IC (mA) VCE (V)<br>VCE = 5 V Tamb = 25 C<br>(1) Tamb = 100 C<br>(2) Tamb = 25 C<br>(3) Tamb = 40 C<br>Fig 13. PDTB123EQA: DC current gain as a function of Fig 14. PDTB123EQA: Collector current as a function<br>collector current; typical values of collector-emitter voltage; typical values<br>**----- End of picture text -----**<br> **==> picture [482 x 276] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020291 aaa-020292<br>-10 -10<br>VI(on) VI(off)<br>(V) (V)<br>(1)<br>-1 -1 (2)<br>(1)<br>(2) (3)<br>(3)<br>-10 [-1] -10 [-1]<br>-10 [-1] -1 -10 -10 [2] -10 [3] -10 [-1] -1 -10<br>IC (mA) IC (mA)<br>VCE = 0.3 V VCE = 5 V<br>(1) Tamb = 40 C (1) Tamb = 40 C<br>(2) Tamb = 25 C (2) Tamb = 25 C<br>(3) Tamb = 100 C (3) Tamb = 100 C<br>Fig 15. PDTB123EQA: On-state input voltage as a Fig 16. PDTB123EQA: Off-state input voltage as a<br>function of collector current; typical values function of collector current; typical values<br>**----- End of picture text -----**<br> © NXP Semiconductors N.V. 2016. All rights reserved. PDTB113_123_143_114EQA_SER **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 1 — 30 March 2016** **11 of 23** **PDTB113/123/143/114EQA** **NXP Semiconductors** ## **50 V, 500 mA PNP resistor-equipped transistors** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020290<br>-10 [-1]<br>VCEsat<br>(V)<br>(1)<br>(2)<br>(3)<br>-10 [-2]<br>-10 -10 [2] -10 [3]<br>IC (mA)<br>**----- End of picture text -----**<br> - IC/IB = 20 **==> picture [233 x 209] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020293<br>30<br>Cc<br>(pF)<br>25<br>20<br>15<br>10<br>5<br>0<br>-0 -10 -20 -30 -40 -50<br>VCB (V)<br>f = 1 MHz; Tamb = 25 C<br>**----- End of picture text -----**<br> - (1) Tamb = 100 C - (2) Tamb = 25 C - (3) Tamb = 40 C - **Fig 17. PDTB123EQA: Collector-emitter saturation Fig 18. PDTB123EQA: Collector capacitance as a voltage as a function of collector current; function of collector-base voltage; typical typical values values** © NXP Semiconductors N.V. 2016. All rights reserved. PDTB113_123_143_114EQA_SER **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 1 — 30 March 2016** **12 of 23** **PDTB113/123/143/114EQA** **NXP Semiconductors** ## **50 V, 500 mA PNP resistor-equipped transistors** **==> picture [497 x 582] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020294 aaa-020295<br>10 [3] -0.5<br>IC IB (mA) = -2.8 -2.52<br>hFE (A)<br>-0.4<br>-2.24<br>-1.96<br>10 [2]<br>(1) -0.3 -1.68<br>(2) -1.4<br>(3)<br>-0.2 -1.12<br>10 -0.84<br>-0.1 -0.56<br>-0.28<br>1 0<br>-10 [-1] -1 -10 -10 [2] -10 [3] 0 -1 -2 -3 -4 -5<br>IC (mA) VCE (V)<br>VCE = 5 V Tamb = 25 C<br>(1) Tamb = 100 C<br>(2) Tamb = 25 C<br>(3) Tamb = 40 C<br>Fig 19. PDTB143EQA: DC current gain as a function of Fig 20. PDTB143EQA: Collector current as a function<br>collector current; typical values of collector-emitter voltage; typical values<br>aaa-020298 aaa-020296<br>-10 [2] -10<br>VI(on)<br>(V)<br>VI(off)<br>(V)<br>-10<br>(1)<br>-1 (2)<br>(3)<br>-1 (1)<br>(2)<br>(3)<br>-10 [-1] -10 [-1]<br>-10 [-1] -1 -10 -10 [2] -10 [3] -10 [4] -10 [-1] -1 -10<br>IC (mA) IC (mA)<br>VCE = 0.3 V VCE = 5 V<br>(1) Tamb = 40 C (1) Tamb = 40 C<br>(2) Tamb = 25 C (2) Tamb = 25 C<br>(3) Tamb = 100 C (3) Tamb = 100 C<br>Fig 21. PDTB143EQA: On-state input voltage as a Fig 22. PDTB143EQA: Off-state input voltage as a<br>function of collector current; typical values function of collector current; typical values<br>**----- End of picture text -----**<br> © NXP Semiconductors N.V. 2016. All rights reserved. PDTB113_123_143_114EQA_SER **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 1 — 30 March 2016** **13 of 23** **PDTB113/123/143/114EQA** **NXP Semiconductors** ## **50 V, 500 mA PNP resistor-equipped transistors** **==> picture [233 x 209] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020297<br>-10 [-1]<br>VCEsat<br>(V)<br>(1)<br>(2)<br>(3)<br>-10 [-2]<br>-1 -10 -10 [2] -10 [3]<br>IC (mA)<br>IC/IB = 20<br>**----- End of picture text -----**<br> **==> picture [233 x 209] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020299<br>20<br>Cc<br>(pF)<br>16<br>12<br>8<br>4<br>0<br>0 -10 -20 -30 -40 -50<br>VCB (V)<br>f = 1 MHz; Tamb = 25 C<br>**----- End of picture text -----**<br> - (1) Tamb = 100 C (2) Tamb = 25 C (3) Tamb = 40 C - **Fig 23. PDTB143EQA: Collector-emitter saturation Fig 24. PDTB143EQA: Collector capacitance as a voltage as a function of collector current; function of collector-base voltage; typical typical values values** © NXP Semiconductors N.V. 2016. All rights reserved. PDTB113_123_143_114EQA_SER **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 1 — 30 March 2016** **14 of 23** **PDTB113/123/143/114EQA** **NXP Semiconductors** ## **50 V, 500 mA PNP resistor-equipped transistors** **==> picture [481 x 209] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020300 aaa-020301<br>10 [3] -0.5<br>IC IB (mA) = -3.4 -3.05<br>hFE (A)<br>-0.4 -2.7<br>-2.35<br>10 [2]<br>-2<br>-0.3<br>(1) -1.65<br>(2)<br>(3) -1.3<br>-0.2<br>-0.95<br>10<br>-0.6<br>-0.1<br>-0.25<br>1 0<br>-10 [-1] -1 -10 -10 [2] -10 [3] 0 -1 -2 -3 -4 -5<br>IC (mA) VCE (V)<br>VCE = 5 V Tamb = 25 C<br>**----- End of picture text -----**<br> (1) Tamb = 100 C - (2) Tamb = 25 C - (3) Tamb = 40 C **Fig 25. PDTB114EQA: DC current gain as a function of Fig 26. PDTB114EQA: Collector current as a function collector current; typical values of collector-emitter voltage; typical values** **==> picture [481 x 276] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020302 aaa-020303<br>-10 [2] -10<br>VI(on)<br>(V)<br>VI(off)<br>(V)<br>-10<br>(1)<br>-1 (2)<br>(3)<br>-1<br>(1)<br>(2)<br>(3)<br>-10 [-1] -10 [-1]<br>-10 [-1] -1 -10 -10 [2] -10 [3] -10 [-1] -1 -10<br>IC (mA) IC (mA)<br>VCE = 0.3 VCE = 0.3 V = 0.3 V 0.3 V0.3 V VCE = 5 V<br>(1) Tamb = 40 Camb = 40 C = 40 C 40 C40 C CC (1) Tamb = 40 C<br>(2) Tamb = 25 Camb = 25 C = 25 C CC (2) Tamb = 25 C<br>(3) Tamb = 100 Camb = 100 C = 100 C CC (3) Tamb = 100 C<br>Fig 27. PDTB114EQA: On-state input voltage as a Fig 28. PDTB114EQA: Off-state input voltage as a<br>function of collector current; typical values function of collector current; typical values<br>**----- End of picture text -----**<br> VCE = 0.3 VCE = 0.3 V = 0.3 V 0.3 V0.3 V (1) Tamb = 40 Camb = 40 C = 40 C 40 C40 C CC (2) Tamb = 25 Camb = 25 C = 25 C CC (3) Tamb = 100 Camb = 100 C = 100 C CC **Fig 27. PDTB114EQA: On-state input voltage as a function of collector current; typical values** © NXP Semiconductors N.V. 2016. All rights reserved. PDTB113_123_143_114EQA_SER **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 1 — 30 March 2016** **15 of 23** **PDTB113/123/143/114EQA** **NXP Semiconductors** ## **50 V, 500 mA PNP resistor-equipped transistors** **==> picture [497 x 557] intentionally omitted <==** **----- Start of picture text -----**<br> aaa-020304 aaa-020305<br>-10 [-1] 10<br>Cc<br>(pF)<br>VCEsat 8<br>(V)<br>6<br>(1)<br>4<br>(2)<br>(3)<br>2<br>-10 [-2] 0<br>-1 -10 -10 [2] -10 [3] -0 -10 -20 -30 -40 -50<br>IC (mA) VCB (V)<br>IC/IB = 20 f = 1 MHz; Tamb = 25 C<br>(1) Tamb = 100 C<br>(2) Tamb = 25 C<br>(3) Tamb = 40 C<br>Fig 29. PDTB114EQA: Collector-emitter saturation Fig 30. PDTB114EQA: Collector capacitance as a<br>voltage as a function of collector current; function of collector-base voltage; typical<br>typical values values<br>aaa-020306<br>10 [3]<br>fT<br>(MHz)<br>10 [2]<br>10<br>-10 [-1] -1 -10 -10 [2] -10 [3]<br>IC (mA)<br>VCE = 5 V; f = 100 MHz; Tamb = 25 °C<br>Fig 31. Transition frequency as a function of collector current; typical values of built-in transistor<br>**----- End of picture text -----**<br> © NXP Semiconductors N.V. 2016. All rights reserved. PDTB113_123_143_114EQA_SER **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 1 — 30 March 2016** **16 of 23** **PDTB113/123/143/114EQA** **NXP Semiconductors** **50 V, 500 mA PNP resistor-equipped transistors** ## **8. Test information** ## **8.1 Quality information** This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard _Q101 - Stress test qualification for discrete semiconductors_ , and is suitable for use in automotive applications. ## **8.2 Resistor calculation** - Calculation of bias resistor 1 (R1): **==> picture [89 x 25] intentionally omitted <==** - Calculation method A of bias resistor ratio (R2/R1): **==> picture [75 x 26] intentionally omitted <==** - Calculation method B of bias resistor ratio (R2/R1): **==> picture [104 x 26] intentionally omitted <==** **==> picture [249 x 153] intentionally omitted <==** **----- Start of picture text -----**<br> n.c.<br>II1; II2 R1<br>II3; II4<br>R2<br>GND<br>aaa-020083<br>Fig 32. Resistor test circuit<br>**----- End of picture text -----**<br> © NXP Semiconductors N.V. 2016. All rights reserved. PDTB113_123_143_114EQA_SER **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 1 — 30 March 2016** **17 of 23** **PDTB113/123/143/114EQA** **NXP Semiconductors** **50 V, 500 mA PNP resistor-equipped transistors** ## **8.3 Resistor test conditions** **Table 9. Resistor test conditions** |**Type number**||**R1**|**R2**|**Test conditions**|**Test conditions**|**Test conditions**|**Test conditions**| |---|---|---|---|---|---|---|---| |||k|k|**II1**|**II2**|**II3**|**II4**| |PDTB113EQA|[1]|1|1|1.5 mA|1.9 mA|2.20 mA|-| |PDTB123EQA|[1]|2.2|2.2|0.7 mA|0.8 mA|0.75 mA|-| |PDTB143EQA<br>~~ot~~|[2]<br>~~ot~~|4.7<br>~~ot~~|4.7<br>~~ot~~|1.3 mA<br>~~ot~~|1.5 mA<br>~~ot~~|1.05 mA<br>~~ot~~|1.25 mA<br>~~ot~~| |PDTB114EQA<br>~~ot~~|[2]<br>~~ot~~|10<br>~~ot~~|10<br>~~ot~~|0.7 mA<br>~~ot~~|0.8 mA<br>~~ot~~|0.45 mA<br>~~ot~~|0.55 mA<br>~~ot~~| [1] Uses calculation method A of bias resistor ratio R2/R1 [2] Uses calculation method B of bias resistor ratio R2/R1 ## **9. Package outline** **==> picture [223 x 156] intentionally omitted <==** **----- Start of picture text -----**<br> 0.87<br>0.95<br>0.75<br>0.22<br>0.30<br>1 2 0.17<br>iF i Ll 0.25<br>0.951.05 | 0.1 0.160.24<br>0.195<br>3<br>0.275<br>0.04 0.245<br>max 0.34 0.325 1.05<br>F] MS<br>0.40 1.15<br>Dimensions in mm 13-03-05<br>**----- End of picture text -----**<br> **Fig 33. Package outline DFN1010D-3 (SOT1215)** © NXP Semiconductors N.V. 2016. All rights reserved. PDTB113_123_143_114EQA_SER **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 1 — 30 March 2016** **18 of 23** **NXP Semiconductors** ## **PDTB113/123/143/114EQA** **50 V, 500 mA PNP resistor-equipped transistors** ## **10. Soldering** **==> picture [482 x 595] intentionally omitted <==** **----- Start of picture text -----**<br> Footprint information for reflow soldering of DFN1010D-3 package SOT1215<br>_ _ 1.2 a |<br>0.45 (2x) 0.3<br>1.1<br>0.35 (2x) 0.25 (2x)<br>0.4<br>0.75<br>---4--- --+--4-/-}--p-- ,<br>| || 7 I-7 1<br>poser s<br>PSS SS \ eee, %<br>0.5 7 eee) | | gBSkee | I 0.3 0.4<br>1;1I| Gay Gey4BSR '| : 1| Gece G osegy)OE|<br>| | ZZ<br>i} 1 | ioral<br>|<br>1.5 1.4 0.4 4i}Poe:| : fe | a 1 i}! 0.5 1.3<br>|<br>: |<br>po von 1<br>i} _| ;<br>} 1<br>i}<br>! | (RE E | |<br>0.5 1Y Xs eseseatanatecetetZ 0.3 0.4<br>Retenennsesg |<br>; | VASES = ]<br>an 4 - : !<br>i} | Gam a 7<br>boa a=a === 4--P=23a nr on —<br>0.3<br>0.4<br>[ 0.5 ——>|<br>1.3<br>PSSesosd<br>solder land solder land plus solder paste<br>YW,Vs ;bead<br>i-———4 occupied area a'1 solder resist<br>i! --JI LJ<br>Dimensions in mm<br>Issue date 12-11-23 sot1215_fr<br>13-03-06<br>Fig 34. Reflow soldering footprint DFN1010D-3 (SOT1215)<br>**----- End of picture text -----**<br> PDTB113_123_143_114EQA_SER All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. **==> picture [31 x 7] intentionally omitted <==** **----- Start of picture text -----**<br> 19 of 23<br>**----- End of picture text -----**<br> **Product data sheet** **Rev. 1 — 30 March 2016** **PDTB113/123/143/114EQA** **NXP Semiconductors** **50 V, 500 mA PNP resistor-equipped transistors** ## **11. Revision history** |**Table 10.**<br>**Revision history**|**Table 10.**<br>**Revision history**|**Table 10.**<br>**Revision history**|**Table 10.**<br>**Revision history**|**Table 10.**<br>**Revision history**| |---|---|---|---|---| |**Document ID**|**Release date**|**Data sheet status**|**Change notice**|**Supersedes**| |PDTB113_123_143_114EQA_SER v.1|20160330|Product data sheet|-|-| © NXP Semiconductors N.V. 2016. All rights reserved. PDTB113_123_143_114EQA_SER **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 1 — 30 March 2016** **20 of 23** **PDTB113/123/143/114EQA** **NXP Semiconductors** **50 V, 500 mA PNP resistor-equipped transistors** ## **12. Legal information** ## **12.1 Data sheet status** |**Document status[1]**<br>**[2]**|**Product statu**~~**s**~~**[3]**|**Definition**| |---|---|---| |Objective [short] data sheet|Development|This document contains data from the objective specification for product development.| |Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.| |Product [short] data sheet|Production|This document contains the product specification.| [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. ## **12.2 Definitions** **Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. **Product specification —** The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. ## **12.3 Disclaimers** **Limited warranty and liability —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors. **Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **Suitability for use in automotive applications —** This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. **Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. **Limiting values —** Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. **Terms and conditions of commercial sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. © NXP Semiconductors N.V. 2016. All rights reserved. PDTB113_123_143_114EQA_SER **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 1 — 30 March 2016** **21 of 23** **PDTB113/123/143/114EQA** ## **NXP Semiconductors** ## **50 V, 500 mA PNP resistor-equipped transistors** **No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. **Export control —** This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. **Quick reference data —** The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. **Translations —** A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. ## **12.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. ## **13. Contact information** For more information, please visit: **http://www.nxp.com** For sales office addresses, please send an email to: **salesaddresses@nxp.com** © NXP Semiconductors N.V. 2016. All rights reserved. PDTB113_123_143_114EQA_SER **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 1 — 30 March 2016** **22 of 23** **PDTB113/123/143/114EQA** **NXP Semiconductors** **50 V, 500 mA PNP resistor-equipped transistors** ## **14. Contents** |**1**|**Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1**| |---|---| |1.1|General description . . . . . . . . . . . . . . . . . . . . . 1| |1.2|Features and benefits. . . . . . . . . . . . . . . . . . . . 1| |1.3|Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1| |1.4|Quick reference data . . . . . . . . . . . . . . . . . . . . 1| |**2**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . 2**| |**3**|**Ordering information. . . . . . . . . . . . . . . . . . . . . 2**| |**4**|**Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3**| |4.1|Binary marking code description. . . . . . . . . . . . 3| |**5**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3**| |**6**|**Thermal characteristics . . . . . . . . . . . . . . . . . . 5**| |**7**|**Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 6**| |**8**|**Test information. . . . . . . . . . . . . . . . . . . . . . . . 16**| |8.1|Quality information . . . . . . . . . . . . . . . . . . . . . 16| |8.2|Resistor calculation . . . . . . . . . . . . . . . . . . . . 16| |8.3|Resistor test conditions . . . . . . . . . . . . . . . . . 16| |**9**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16**| |**10**|**Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17**| |**11**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18**| |**12**|**Legal information. . . . . . . . . . . . . . . . . . . . . . . 19**| |12.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19| |12.2|Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19| |12.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19| |12.4|Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20| |**13**|**Contact information. . . . . . . . . . . . . . . . . . . . . 20**| |**14**|**Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21**| Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. **© NXP Semiconductors N.V. 2016.** **All rights reserved.** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 30 March 2016 Document identifier: PDTB113_123_143_114EQA_SER**
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