PCF8575TS/1,112

## **INTEGRATED CIRCUITS** 

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DATA SHEET<br>PCF8575C<br>Remote 16-bit I/O expander for<br>I [2] C-bus<br>**----- End of picture text -----**<br>


1999 Aug 05 File under Integrated Circuits, IC12 

**Philips Semiconductors** 

**PCF8575C** 

## **Remote 16-bit I/O expander for I[2] C-bus** 

## **CONTENTS** 

|1|FEATURES|
|---|---|
|2|GENERAL DESCRIPTION|
|3|ORDERING INFORMATION|
|4|BLOCK DIAGRAM|
|5|PINNING|
|6|FUNCTIONAL DESCRIPTION|
|6.1|Quasi-bidirectional I/Os|
|6.2|Addressing|
|6.3|Reading from a port (input mode)|
|6.4|Writing to the port (output mode)|
|6.5|Interrupt|
|7|CHARACTERISTICS OF THE I2C-BUS|
|7.1|Bit transfer|
|7.2|START and STOP conditions|
|7.3|System configuration|
|7.4|Acknowledge|
|8|LIMITING VALUES|
|9|HANDLING|
|10|CHARACTERISTICS|
|11|I2C-BUS TIMING CHARACTERISTICS|
|12|DEVICE PROTECTION|
|13|PACKAGE OUTLINE|
|14|SOLDERING|
|14.1|Introduction to soldering surface mount|
||packages|
|14.2|Reflow soldering|
|14.3|Wave soldering|
|14.4|Manual soldering|
|14.5|Suitability of surface mount IC packages for|
||wave and reflow soldering methods|
|15|DEFINITIONS|
|16|LIFE SUPPORT APPLICATIONS|
|17|PURCHASE OF PHILIPS I2C COMPONENTS|



1999 Aug 05 

2 

Philips Semiconductors 

PCF8575C 

## Remote 16-bit I/O expander for I[2] C-bus 

## **1 FEATURES** 

- Operating supply voltage from 4.5 to 5.5 V 

- Low standby current consumption of 10 µA maximum 

- I[2] C-bus to parallel port expander 

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- 400 kbits/s FAST I[2] C-bus 

- Open-drain interrupt output 

- 16-bit remote I/O port for the I[2] C-bus 

- Compatible with most microcontrollers 

- Latched outputs with high current drive capability for directly driving LEDs 

- Address by 3 hardware address pins for use of up to 8 devices 

- SSOP24 package. 

## **2 GENERAL DESCRIPTION** 

The device is a silicon CMOS circuit. It provides general purpose remote I/O expansion for most microcontroller families via the two-line bidirectional bus (I[2] C-bus). 

The device consists of a 16-bit quasi-bidirectional port and an I[2] C-bus interface. The PCF8575C has a low current consumption and includes latched outputs with high current drive capability for directly driving LEDs. It also possesses an interrupt line (INT) which can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I[2] C-bus. This means that the device is an I[2] C-bus slave transmitter/receiver. 

Every data transmission from the PCF8575C must consist of an even number of bytes, the first byte will be referred to as P07 to P00 and the second byte as P17 to P10. The third will be referred to as P07 to P00 and so on. 

## **3 ORDERING INFORMATION** 

|**3**<br>**ORDERING**|**INFORMATION**|**INFORMATION**|**INFORMATION**|
|---|---|---|---|
|**TYPE**<br>**NUMBER**|**PACKAGE**|||
||**NAME**|**DESCRIPTION**|**VERSION**|
|PCF8575CTS|SSOP24|plastic shrink small outline package; 24 leads; body width 5.3 mm|SOT340-1|



1999 Aug 05 

3 

Philips Semiconductors 

PCF8575C 

## Remote 16-bit I/O expander for I[2] C-bus 

## **4 BLOCK DIAGRAM** 

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handbook, full pagewidth<br>1 INTERRUPT<br>INT LP FILTER<br>LOGIC<br>21 PCF8575C<br>A0<br>2<br>A1<br>3<br>A2<br>SCL 22 P00 to P07<br>INPUT I [2] C-BUS 4 to 11<br>SDA 23 FILTER CONTROL SHIFT 16 BITS I/O<br>REGISTER PORT<br>P10 to P17<br>13 to 20<br>WRITE pulse<br>VDD 24 READ pulse<br>POWER-ON<br>12<br>VSS RESET<br>MGS630<br>**----- End of picture text -----**<br>


Fig.1  Block diagram. 

1999 Aug 05 

4 

Philips Semiconductors 

## Remote 16-bit I/O expander for I[2] C-bus 

## PCF8575C 

||||||||||
|---|---|---|---|---|---|---|---|---|
|**5**<br>**PINNING**<br>**SYMBOL**<br>**PIN**<br>**DESCRIPTION**<br>INT<br>1<br>interrupt output (active LOW)<br>A1<br>2<br>address input 1<br>A2<br>3<br>address input 2<br>P00<br>4<br>quasi-bidirectional I/O 00<br>P01<br>5<br>quasi-bidirectional I/O 01<br>P02<br>6<br>quasi-bidirectional I/O 02<br>P03<br>7<br>quasi-bidirectional I/O 03<br>P04<br>8<br>quasi-bidirectional I/O 04<br>P05<br>9<br>quasi-bidirectional I/O 05<br>P06<br>10<br>quasi-bidirectional I/O 06<br>P07<br>11<br>quasi-bidirectional I/O 07<br>VSS<br>12<br>supply ground<br>P10<br>13<br>quasi-bidirectional I/O 10<br>P11<br>14<br>quasi-bidirectional I/O 11<br>P12<br>15<br>quasi-bidirectional I/O 12<br>P13<br>16<br>quasi-bidirectional I/O 13<br>P14<br>17<br>quasi-bidirectional I/O 14<br>P15<br>18<br>quasi-bidirectional I/O 15<br>P16<br>19<br>quasi-bidirectional I/O 16<br>P17<br>20<br>quasi-bidirectional I/O 17<br>A0<br>21<br>address input 0<br>SCL<br>22<br>serial clock line input<br>SDA<br>23<br>serial data line input/output<br>VDD<br>24<br>supply voltage<br>handbook, halfpage<br>**PCF8575C**<br>MGS631<br>1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>9<br>10<br>11<br>12<br>INT<br>A1<br>A2<br>P00<br>P01<br>P02<br>P03<br>P04<br>P05<br>P06<br>P07<br>VSS<br>VDD<br>SDA<br>SCL<br>A0<br>P17<br>P16<br>P15<br>P14<br>P13<br>P12<br>P11<br>P10<br>24<br>23<br>22<br>21<br>20<br>19<br>18<br>17<br>16<br>15<br>14<br>13<br>Fig.2  Pin configuration.|||||||||
|**SYMBOL**|**PIN**|**DESCRIPTION**|||||||
|INT|1|interrupt output (active LOW)|||||||
|A1|2|address input 1|||||||
|A2|3|address input 2|||||||
||||handbook, halfpage|1<br>INT|||VDD<br>24||
|P00|4|quasi-bidirectional I/O 00|||||||
||||||||||
|P01|5|quasi-bidirectional I/O 01|**PCF8575C**<br>MGS631<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>9<br>10<br>11<br>12<br>A1<br>A2<br>P00<br>P01<br>P02<br>P03<br>P04<br>P05<br>P06<br>P07<br>VSS<br>SDA<br>SCL<br>A0<br>P17<br>P16<br>P15<br>P14<br>P13<br>P12<br>P11<br>P10<br>23<br>22<br>21<br>20<br>19<br>18<br>17<br>16<br>15<br>14<br>13<br>Fig.2  Pin configuration.||2|**PCF8575C**|23||
|P02|6|quasi-bidirectional I/O 02|||||||
|P03|7|quasi-bidirectional I/O 03|||||||
|P04|8|quasi-bidirectional I/O 04|||||||
|P05|9|quasi-bidirectional I/O 05|||||||
|P06|10|quasi-bidirectional I/O 06|||||||
|P07|11|quasi-bidirectional I/O 07|||||||
|VSS|12|supply ground|||||||
|P10|13|quasi-bidirectional I/O 10|||||||
|P11|14|quasi-bidirectional I/O 11|||||||
|P12|15|quasi-bidirectional I/O 12|||||||
|P13|16|quasi-bidirectional I/O 13|||||||
|P14|17|quasi-bidirectional I/O 14|||||||
|P15|18|quasi-bidirectional I/O 15|||||||
|P16|19|quasi-bidirectional I/O 16|||||||
|P17|20|quasi-bidirectional I/O 17|||||||
|A0|21|address input 0|||||||
|SCL|22|serial clock line input|||||||
|SDA|23|serial data line input/output|||||||
|VDD|24|supply voltage|||||||



1999 Aug 05 

5 

Philips Semiconductors 

PCF8575C 

## Remote 16-bit I/O expander for I[2] C-bus 

## **6 FUNCTIONAL DESCRIPTION** 

## **6.1 Quasi-bidirectional I/Os** 

The 16 ports (see Fig.3) are entirely independent and can be used either as input or output ports. Input data is transferred from the ports to the microcontroller in the READ mode (see Fig.6). Output data is transmitted to the ports in the WRITE mode (see Fig.5). 

This quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data direction. At power-on all the I/Os are in 3-state mode. The strong pull-up to VDD (IOHt) allows a fast rising edge into a heavily loaded output. This strong pull-up turns on when the output is written HIGH, and is switched off by the negative edge of SCL. After this short period the output is in 3-state mode. The I/O should be written HIGH before being used as an input. After power-on as all the I/Os are set to 3-state all of them can be used as inputs. Any change in setting of the I/Os as either inputs or outputs can be done with the write mode. Warning: If a HIGH is applied to an I/O which has been written earlier to LOW, a large current (IOL) will flow to VSS (see Chapter 10; note 3). 

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**----- Start of picture text -----**<br>
handbook, full pagewidth VDD<br>write pulse<br>IOHt P00 to P07<br>data from<br>D Q<br>shift register IOL P10 to 17<br>FF<br>CI<br>S VSS<br>power-on<br>reset<br>D Q<br>FF<br>CI<br>read pulse S<br>to interrupt<br>data to logic<br>shift register<br>MGS632<br>Fig.3  Simplified schematic diagram of each I/O.<br>**----- End of picture text -----**<br>


## **6.2 Addressing** 

Figures 4, 5 and 6 show the address and timing diagrams. Before any data is transmitted or received the master must send the address of the receiver via the SDA line. The first byte transmitted after the START condition carries the address of the slave device and the read/write bit. The address of the slave device must not be changed between the START and the STOP conditions. The PCF8575C acts as a slave receiver or a slave transmitter. 

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handbook, halfpage slave address<br>S 0 1 0 0 A2 A1 A0 R/W A<br>MGL541<br>**----- End of picture text -----**<br>


Fig.4  Byte containing the slave address and the R/W bits. 

1999 Aug 05 

6 

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**----- Start of picture text -----**<br>
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in<br>_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in<br>white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...<br>Integral multiples of two bytes<br>SCL 1 2 3 4 5 6 7 8<br>slave address (PCF8575C) data to port 0 data to port 1<br>SDA S 0 1 0 0 A2 A1 A0 0 A P07 P06 1 P00 A P17 P10 A<br>start condition R/W acknowledge P05 acknowledge acknowledge<br>from slave from slave from slave<br>WRITE TO<br>PORT<br>DATA OUTPUT Data A0 and<br>FROM PORT B0 valid<br>tpv<br>05 OUTPUT<br>VOLTAGE<br>05 PULL-UP IOHt<br>OUTPUT CURRENT<br>INT<br>tir MGS633<br>Fig.5  WRITE mode (output).<br>ndbook, full pagewidth<br>**----- End of picture text -----**<br>


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book, full pagewidth<br>**----- End of picture text -----**<br>


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SCL<br>SDA<br>S 0 1 0 0 A2 A1 A0 1 A P07 P06 P05 P04 P03 P02 P01 P00 A P17 P10 A P07 P00 A P17 P10 1 P<br>R/W acknowledge acknowledge acknowledge acknowledge non acknowledge<br>from slave from receiver from receiver from receiver from receiver<br>READ FROM PORT<br>DATA INTO PORT<br>P07 to P00 P17 to P10 P07 to P00 P17 to P10 P07 to P00 P17 to P10<br>th tsu<br>INT<br>tiv tir tir MGL543<br>**----- End of picture text -----**<br>


A LOW-to-HIGH transition of SDA, while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). Input data is lost. 

Fig.6  READ mode (input). 

Philips Semiconductors 

## Remote 16-bit I/O expander for I[2] C-bus 

## PCF8575C 

## **6.3 Reading from a port (input mode)** 

All ports programmed as input should be set to logic 1. To read, the master (microcontroller) first addresses the slave device after it receives the interrupt. By setting the last bit of the byte containing the slave address to logic 1 the read mode is entered. The data bytes that follow on the SDA are the values on the ports. 

If the data on the input port changes faster than the master can read, this data may be lost. 

## **6.4 Writing to the port (output mode)** 

To write, the master (microcontroller) first addresses the slave device. By setting the last bit of the byte containing the slave address to logic 0 the write mode is entered. The PCF8575C acknowledges and the master sends the first data byte for P07 to P00. After the first data byte is acknowledged by the PCF8575C, the second data byte P17 to P10 is sent by the master. Once again the PCF8575C acknowledges the receipt of the data after which this 16-bit data is presented on the port lines. 

The number of data bytes that can be sent successively is not limited. After every two bytes the previous data is overwritten. 

## **6.5 Interrupt** 

The PCF8575C provides an open-drain interrupt (INT) which can be fed to a corresponding input of the microcontroller (see Figs 5, 6 and 8). This gives these chips a kind of a master function which can initiate an action elsewhere in the system. 

An interrupt is generated by any rising or falling edge of the port inputs. After time tiv the signal INT is valid. 

The interrupt disappears when data on the port is changed to the original setting or data is read from or written to the device which has generated the interrupt. 

In the write mode the interrupt may become deactivated (HIGH) on the rising edge of the write to port pulse. On the falling edge of the write to port pulse the interrupt is definitely deactivated (HIGH). 

The interrupt is reset in the read mode on the rising edge of the read from port pulse. 

During the resetting of the interrupt itself any changes on the I/Os may not generate an interrupt. After the interrupt is reset any change in I/Os will be detected and transmitted as an INT. 

The first data byte in every pair refers to Port 0 (P07 to P00), whereas the second data byte in every pair refers to Port 1 (P17 to P10), see Fig.7. 

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**----- Start of picture text -----**<br>
handbook, full pagewidth First Byte Second Byte<br>07 06 05 04 03 02 01 00 A 17 16 15 14 13 12 11 10 A<br>P07 P06 P05 P04 P03 P02 P01 P00 P17 P16 P15 P14 P13 P12 P11 P10<br>MGL545<br>**----- End of picture text -----**<br>


Fig.7  Correlation between bits and ports. 

1999 Aug 05 

9 

Philips Semiconductors 

## Remote 16-bit I/O expander for I[2] C-bus 

## PCF8575C 

**==> picture [497 x 306] intentionally omitted <==**

**----- Start of picture text -----**<br>
handbook, full pagewidth PCF8575C PCF8575C PCF8575C<br>VDD (1) (2) (8)<br>INT INT INT<br>MICROCOMPUTER<br>INT<br>MGS634<br>Fig.8  Application of multiple PCF8575Cs with interrupt.<br>**----- End of picture text -----**<br>


1999 Aug 05 

10 

Philips Semiconductors 

PCF8575C 

## Remote 16-bit I/O expander for I[2] C-bus 

## **7 CHARACTERISTICS OF THE I[2] C-BUS** 

The I[2] C-bus is for bidirectional, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 

## **7.1 Bit transfer** 

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Fig.9). 

## **7.2 START and STOP conditions** 

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). 

A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition P (see Fig.10). 

## **7.4 Acknowledge** 

The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The transmitter must release the SDA line before the receiver can send an acknowledge bit. 

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account. 

A master receiver must signal an end of data to the transmitter by **not** generating an acknowledge after the last byte that has been clocked out of the slave. This is done by the master receiver by holding the SDA line HIGH. In this event the transmitter must release the data line to enable the master to generate a STOP condition. 

## **7.3** 

A device generating a message is a ‘transmitter’, a device receiving the message is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Fig.11). 

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**----- Start of picture text -----**<br>
handbook, full pagewidth<br>SDA<br>SCL<br>data line change<br>stable; of data<br>data valid allowed MBC621<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
Fig.9  Bit transfer.<br>**----- End of picture text -----**<br>


1999 Aug 05 

11 

Philips Semiconductors 

## Remote 16-bit I/O expander for I[2] C-bus 

## PCF8575C 

**==> picture [497 x 86] intentionally omitted <==**

**----- Start of picture text -----**<br>
handbook, full pagewidth<br>SDA SDA<br>SCL SCL<br>S P<br>START condition STOP condition<br>MBC622<br>**----- End of picture text -----**<br>


Fig.10  Definition of START and STOP conditions. 

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**----- Start of picture text -----**<br>
SDA<br>SCL<br>MASTER SLAVE MASTER<br>SLAVE MASTER<br>TRANSMITTER / TRANSMITTER / TRANSMITTER /<br>RECEIVER TRANSMITTER<br>RECEIVER RECEIVER RECEIVER<br>MBA605<br>**----- End of picture text -----**<br>


Fig.11  System configuration. 

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**----- Start of picture text -----**<br>
handbook, full pagewidth<br>DATA OUTPUT<br>BY TRANSMITTER<br>not acknowledge<br>DATA OUTPUT<br>BY RECEIVER<br>acknowledge<br>SCL FROM<br>1 2 8 9<br>MASTER<br>S<br>clock pulse for<br>START<br>acknowledgement<br>condition<br>MGL539<br>**----- End of picture text -----**<br>


Fig.12   Acknowledgment on the I[2] C-bus. 

1999 Aug 05 

12 

Philips Semiconductors 

## Remote 16-bit I/O expander for I[2] C-bus 

## PCF8575C 

## **8 LIMITING VALUES** 

In accordance with the Absolute Maximum Rating System (IEC 134); note 1. 

|**SYMBOL**|**PARAMETER**|**MIN.**|**MAX.**|**UNIT**|
|---|---|---|---|---|
|VDD|supply voltage|−0.5|+6.5|V|
|IDD|supply current|−|±100|mA|
|ISS|supply current|−|±100|mA|
|VI|input voltage|VSS−0.5|VDD+ 0.5|V|
|II|DC input current|−|±20|mA|
|IO|DC output current|−|±25|mA|
|Ptot|total power dissipation|−|400|mW|
|PO|power dissipation per output|−|100|mW|
|Tstg|storage temperature|−65|+150|°C|
|Tamb|ambient temperature|−40|+85|°C|



## **Note** 

1. Stress above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. This is a stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 

## **9 HANDLING** 

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC12 under “Handling MOS Devices”. 

## **10 CHARACTERISTICS** 

VDD = 4.5 to 5.5 V; VSS = 0 V; Tamb = −40 to +85 ° 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**MIN.**|**TYP.**|**MAX.**|**UNIT**|
|---|---|---|---|---|---|---|
|**Supplies**|||||||
|VDD|supply voltage||4.5|−|5.5|V|
|IDD|supply current|operating mode; no<br>load; VI= VDDor VSS;<br>fSCL= 400 kHz|−|100|200|µA|
|IDD(stb)|standby current|standby mode; no load;<br>VI= VDDor VSS|−|2.5|10|µA|
|VPOR|Power-on reset voltage|note 1|−|1.2|1.8|V|
|VIL1|LOW-level input voltage<br>pins A0, A1, A2, SDA and SCL||−0.8|−|0.3VDD|V|
|VIL2|LOW-level input voltage<br>pins P00 to P17||−0.8|−|0.6VDD|V|
|VIH1|HIGH-level input voltage<br>pins A0, A1, A2, SDA and SCL||0.7VDD|−|VDD+ 0.8|V|
|VIH2|HIGH-level input voltage<br>pins P00 to P17||0.8VDD|−|VDD+ 0.8|V|



1999 Aug 05 

13 

Philips Semiconductors 

## Remote 16-bit I/O expander for I[2] C-bus 

## PCF8575C 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**MIN.**|**TYP.**|**MAX.**|**UNIT**|
|---|---|---|---|---|---|---|
|IL|leakage current at all pins|VI= VDDor VSS|−2|−|+2|µA|
|IIHL|current through protection diode|VI> VDDor VI< VSS;<br>note 2|−|−|±2|mA|
|**Input SCL; input/output SDA**|||||||
|IOL|LOW-level output current|VOL= 0.4 V; note 3|3|−|−|mA|
|CI|input capacitance|VI= VSS; note 2|−|−|7|pF|
|**I/Os; P00 to P07 and P10 to P17**|||||||
|IOL|LOW-level output current|VOL= 1 V; note 3|10|25|−|mA|
|IOHt|transient pull-up current|VOH= VSS; see Fig.5|−0.5|−1.0|−|mA|
|CI|input capacitance|note 2|−|−|10|pF|
|CO|output capacitance|note 2|−|−|10|pF|
|**Port timing; CL**≤**100 pF**(see Figs 5 and 6)|||||||
|tpv|output data valid||−|−|4|µs|
|tsu|input data set-up time||0|−|−|µs|
|th|input data hold time||4|−|−|µs|
|**Interrupt**<br>**INT**(see Fig.13)|||||||
|IOL|LOW-level output current|VOL= 0.4 V|1.6|−|−|mA|
|TIMING; CL≤100 PF (see Figs 5 and 6)|||||||
|tiv|input data valid time||−|−|4|µs|
|tir|reset delay time||−|−|4|µs|



## **Notes** 

1. The Power-on reset circuit resets the I[2] C-bus logic with VDD < VPOR and sets all I/Os to logic 1 (with current source to VDD). 

2. The value is not tested, but verified on sampling basis. 

3. A single LOW-level output current (IOL) must not exceed 20 mA for an extended time. The sum of all IOLs at any point in time must not exceed 100 mA. 

1999 Aug 05 

14 

Philips Semiconductors 

## Remote 16-bit I/O expander for I[2] C-bus 

## PCF8575C 

## **11 I[2] C-BUS TIMING CHARACTERISTICS** 

See Fig.13 and note 1. 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**MIN.**|**MAX.**|**UNIT**|
|---|---|---|---|---|---|
|fSCL<br>|SCL clock frequency||−|400|kHz|
|tSW<br>|tolerable spike width on bus|note 2|−|50|ns|
|tBUF<br> <br>|BUS free time between a STOP<br>and START condition||1.3|−|µs|
|tSU;STA<br>|START condition set-up time||0.6|−|µs|
|tHD;STA<br>|START condition hold time||0.6|−|µs|
|tLOW<br>|SCL LOW time||1.3|−|µs|
|tHIGH<br>|SCL HIGH time||0.6|−|µs|
|tr<br>|SCL and SDA rise time|note 3|20 + 0.1Cb|300|ns|
|tf<br>|SCL and SDA fall time|note 3|20 + 0.1Cb|300|ns|
|tSU;DAT<br>|data set-up time||100|−|ns|
|tHD;DAT<br>|data hold time||0|−|ns|
|tSU;STO<br>|STOP condition set-up time||0.6|−|µs|
|Cb<br> <br>|capacitive load represented by<br>each bus line||−|400|pF|



## **Notes** 

1. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing of VSS to VDD. 

2. The device inputs SDA and SCL are filtered and will reject spikes on the bus lines of widths less than tSW(max). 

3. The rise and fall times specified here refer to the driver device (PCF8575C) and are part of the general fast I[2] C-bus specification when PCF8575C asserts an acknowledge on SDA, the minimum fall time is 20 ns + 0.1Cb. 

**==> picture [497 x 258] intentionally omitted <==**

**----- Start of picture text -----**<br>
handbook, full pagewidth START BIT 7 BIT 6 BIT 0 ACKNOWLEDGE STOP<br>PROTOCOL CONDITION MSB (A6) LSB (A) CONDITION<br>(S) (A7) (R/W) (P)<br>tSU;STA tLOW tHIGH<br>1/fSCL<br>SCL<br>tBUF tr tf<br>SDA<br>tHD;STA tSU;DAT tHD;DAT tSU;STO<br>MGL546<br>Fig.13  I [2] C-bus timing diagram.<br>**----- End of picture text -----**<br>


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Philips Semiconductors 

## Remote 16-bit I/O expander for I[2] C-bus 

## PCF8575C 

## **12 DEVICE PROTECTION** 

**==> picture [497 x 255] intentionally omitted <==**

**----- Start of picture text -----**<br>
handbook, full pagewidth<br>1<br>INT VDD 24<br>2 VDD<br>A1<br>23<br>3 SDA<br>A2<br>22<br>4 SCL<br>P00<br>21<br>5 A0<br>P01<br>20<br>6 P17<br>P02<br>19<br>7 P16<br>P03<br>18<br>8 P15<br>P04<br>17<br>9 P14<br>P05<br>16<br>10 P13<br>P06<br>15<br>11 P12<br>P07<br>14<br>12 P11<br>VSS 13<br>P10<br>substrate VSS<br>MGS635<br>**----- End of picture text -----**<br>


Fig.14  Device protection diagram. 

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## Remote 16-bit I/O expander for I[2] C-bus 

## PCF8575C 

## **13 PACKAGE OUTLINE** 

**==> picture [339 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm<br>**----- End of picture text -----**<br>


**==> picture [44 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
SOT340-1<br>**----- End of picture text -----**<br>


**==> picture [495 x 590] intentionally omitted <==**

**----- Start of picture text -----**<br>
D E A<br>X<br>c<br>y HE v M A<br>Z<br>24 13<br>Q<br>A2 A<br>A1 (A  )3<br>pin 1 index<br>θ<br>L p<br>L<br>1 12 detail X<br>w M<br>e b p<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(1)] e HE L Lp Q v w y Z (1) θ<br>mm 2.0 0.210.05 1.801.65 0.25 0.380.25 0.200.09 8.48.0 5.45.2 0.65 7.97.6 1.25 1.030.63 0.90.7 0.2 0.13 0.1 0.80.4 80oo<br>Note<br>1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.<br>OUTLINE  REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION PROJECTION<br> IEC  JEDEC  EIAJ<br>93-09-08<br> SOT340-1  MO-150AG<br>95-02-04<br>**----- End of picture text -----**<br>


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## Remote 16-bit I/O expander for I[2] C-bus 

## PCF8575C 

## **14 SOLDERING** 

## **14.1 Introduction to soldering surface mount packages** 

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). 

There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 

## **14.2** 

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 

Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. 

Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. 

## **14.3 Wave soldering** 

Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. 

To overcome these problems the double-wave soldering method was specifically developed. 

- Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. 

- For packages with leads on two sides and a pitch (e): 

- larger than or equal to 1.27 mm, the footprint longitudinal axis is **preferred** to be parallel to the transport direction of the printed-circuit board; 

- smaller than 1.27 mm, the footprint longitudinal axis **must** be parallel to the transport direction of the printed-circuit board. 

The footprint must incorporate solder thieves at the downstream end. 

- For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. 

During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. 

Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 

## **14.4 Manual soldering** 

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. 

When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 

If wave soldering is used the following conditions must be observed for optimal results: 

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PCF8575C 

## Remote 16-bit I/O expander for I[2] C-bus 

## **14.5** 

|**PACKAGE**|**SOLDERING METHOD**|**SOLDERING METHOD**|
|---|---|---|
||**WAVE**|**REFLOW**(1)|
|BGA, SQFP<br>HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS<br>PLCC(3), SO, SOJ<br>LQFP, QFP, TQFP<br>SSOP, TSSOP, VSO|not suitable<br>not suitable(2)<br>suitable<br>not recommended(3)(4)<br>not recommended(5)|suitable<br>suitable<br>suitable<br>suitable<br>suitable|



## **Notes** 

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 

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## PCF8575C 

## **15 DEFINITIONS** 

|**15 DEFINITIONS**||
|---|---|
|**Data sheet status**||
|Objective specifcation|This data sheet contains target or goal specifcations for product development.|
|Preliminary specifcation|This data sheet contains preliminary data; supplementary data may be published later.|
|Product specifcation|This data sheet contains fnal product specifcations.|
|**Limiting values**||



Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. 

## **Application information** 

## **16 LIFE SUPPORT APPLICATIONS** 

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 

## **17 PURCHASE OF PHILIPS I[2] C COMPONENTS** 

**==> picture [54 x 60] intentionally omitted <==**

Purchase of Philips I[2] C components conveys a license under the Philips’ I[2] C patent to use the components in the I[2] C system provided the system conforms to the I[2] C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 

1999 Aug 05 

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Philips Semiconductors 

PCF8575C 

## Remote 16-bit I/O expander for I[2] C-bus 

## **NOTES** 

1999 Aug 05 

21 

Philips Semiconductors 

PCF8575C 

## Remote 16-bit I/O expander for I[2] C-bus 

## **NOTES** 

1999 Aug 05 

22 

Philips Semiconductors 

PCF8575C 

## Remote 16-bit I/O expander for I[2] C-bus 

## **NOTES** 

1999 Aug 05 

23 

## **Philips Semiconductors – a worldwide company** 

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© Philips Electronics N.V. 1999 

SCA 67 

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. 

Printed in The Netherlands 

**==> picture [214 x 95] intentionally omitted <==**

465006/01/pp24 Date of release: 1999 Aug 05 Document order number: 9397 750 06117