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PCF8574ATS/3,118
I/O Expander, 8bit, 100 kHz, I2C, SMBus, 2.5 V, 6 V, SSOP
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- Manufacturer: NXP
- Product type: I/O Expanders
| Delivery and price | |
|---|---|
| Units per pack | 100 |
| Price | 1.28 € |
| Current stock | 25+ |
| Lead time | 7 days |
Datasheet
**PCF8574; PCF8574A Remote 8-bit I/O expander for I[2] C-bus with interrupt**
**Rev. 5 — 27 May 2013 Product data sheet**
## **1. General description**
The PCF8574/74A provides general-purpose remote I/O expansion via the two-wire bidirectional I[2] C-bus (serial clock (SCL), serial data (SDA)).
The devices consist of eight quasi-bidirectional ports, 100 kHz I[2] C-bus interface, three hardware address inputs and interrupt output operating between 2.5 V and 6 V. The quasi-bidirectional port can be independently assigned as an input to monitor interrupt status or keypads, or as an output to activate indicator devices such as LEDs. System master can read from the input port or write to the output port through a single register.
The low current consumption of 2.5 A (typical, static) is great for mobile applications and the latched output ports directly drive LEDs.
The PCF8574 and PCF8574A are identical, except for the different fixed portion of the slave address. The three hardware address pins allow eight of each device to be on the same I[2] C-bus, so there can be up to 16 of these I/O expanders PCF8574/74A together on the same I[2] C-bus, supporting up to 128 I/Os (for example, 128 LEDs).
The active LOW open-drain interrupt output (INT) can be connected to the interrupt logic of the microcontroller and is activated when any input state differs from its corresponding input port register state. It is used to indicate to the microcontroller that an input state has changed and the device needs to be interrogated without the microcontroller continuously polling the input register via the I[2] C-bus.
The internal Power-On Reset (POR) initializes the I/Os as inputs with a weak internal pull-up 100 A current source.
## **2. Features and benefits**
- I[2] C-bus to parallel port expander
- 100 kHz I[2] C-bus interface (Standard-mode I[2] C-bus)
- Operating supply voltage 2.5 V to 6 V with non-overvoltage tolerant I/O held to VDD with 100 A current source
- 8-bit remote I/O pins that default to inputs at power-up
- Latched outputs directly drive LEDs
- Total package sink capability of 80 mA
- Active LOW open-drain interrupt output
- Eight programmable slave addresses using three address pins
- Low standby current (2.5 A typical)
- 40 C to +85 C operation
- ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
**==> picture [172 x 101] intentionally omitted <==**
**PCF8574 PCF8574A ;**
**NXP Semiconductors**
**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
- Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA
- Packages offered: DIP16, SO16, SSOP20
## **3. Applications**
- LED signs and displays
- Servers
- Key pads
- Industrial control
- Medical equipment
- PLC
- Cellular telephones
- Mobile devices
- Gaming machines
- Instrumentation and test measurement
## **4. Ordering information**
**Table 1. Ordering information**
|**Type number**|**Topside mark**|**Package**|**Package**|**Package**|
|---|---|---|---|---|
|||**Name**|**Description**|**Version**|
|PCF8574P<br>PCF8574P||DIP16<br>plastic dual in-line package; 16 leads (300 mil)<br>SOT38-4|||
|PCF8574AP<br>PCF8574AP|||||
|PCF8574T/3<br>PCF8574T||SO16<br>plastic small outline package; 16 leads; body width 7.5 mm<br>SOT162-1|||
|PCF8574AT/3<br>PCF8574AT|||||
|PCF8574TS/3<br>8574TS||SSOP20<br>plastic shrink small outline package; 20 leads;<br>body width 4.4 mm<br>SOT266-1|||
|PCF8574ATS/3<br>8574A|||||
## **4.1 Ordering options**
**Table 2. Ordering options**
|**Type number**|**Orderable**<br>**part number**<br>**Package**<br>**Packing method**<br>**Minimum**<br>**order**<br>**quantity**<br>**Temperature range**|
|---|---|
|PCF8574P|PCF8574P,112<br>DIP16<br>Standard marking<br>* IC’s tube - DSC bulk pack<br>1000<br>Tamb=40C to +85C|
|PCF8574AP|PCF8574AP,112<br>DIP16<br>Standard marking<br>* IC’s tube - DSC bulk pack<br>1000<br>Tamb=40C to +85C|
|PCF8574T/3|PCF8574T/3,512<br>SO16<br>Standard marking<br>* tube dry pack<br>1920<br>Tamb=40C to +85C|
||PCF8574T/3,518<br>SO16<br>Reel 13” Q1/T1<br>*standard mark SMD dry pack<br>1000<br>Tamb=40C to +85C|
|PCF8574AT/3|PCF8574AT/3,512<br>SO16<br>Standard marking<br>* tube dry pack<br>1920<br>Tamb=40C to +85C|
||PCF8574AT/3,518<br>SO16<br>Reel 13” Q1/T1<br>*standard mark SMD dry pack<br>1000<br>Tamb=40C to +85C|
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
PCF8574_PCF8574A **Product data sheet**
**Rev. 5 — 27 May 2013**
**2 of 33**
**PCF8574 PCF8574A ;**
**NXP Semiconductors**
**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
**Table 2. Ordering options** _…continued_
|**Type number**|**Orderable**<br>**part number**<br>**Package**<br>**Packing method**<br>**Minimum**<br>**order**<br>**quantity**<br>**Temperature range**|
|---|---|
|PCF8574TS/3|PCF8574TS/3,112<br>SSOP20<br>Standard marking<br>* IC’s tube - DSC bulk pack<br>1350<br>Tamb=40C to +85C|
||PCF8574TS/3,118<br>SSOP20<br>Reel 13” Q1/T1<br>*standard mark SMD<br>2500<br>Tamb=40C to +85C|
|PCF8574ATS/3|PCF8574ATS/3,118<br>SSOP20<br>Reel 13” Q1/T1<br>*standard mark SMD<br>2500<br>Tamb=40C to +85C|
## **5. Block diagram**
**==> picture [355 x 214] intentionally omitted <==**
**----- Start of picture text -----**<br>
PCF8574<br>PCF8574A<br>INTERRUPT<br>INT LP FILTER<br>LOGIC<br>A0<br>P0<br>A1<br>P1<br>A2<br>P2<br>SCL INPUT I [2] C-BUS SHIFT 8 bits I/O P3<br>FILTER CONTROL REGISTER PORT P4<br>SDA<br>P5<br>P6<br>P7<br>write pulse<br>read pulse<br>POWER-ON<br>VDD RESET<br>VSS<br>002aad624<br>Fig 1. Block diagram<br>**----- End of picture text -----**<br>
**==> picture [350 x 178] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD<br>write pulse IOH<br>100 μ A<br>Itrt(pu)<br>data from Shift Register D Q<br>FF<br>P0 to P7<br>CI IOL<br>S<br>power-on reset VSS<br>D Q<br>FF<br>read pulse CI<br>S<br>to interrupt logic<br>data to Shift Register<br>002aac109<br>**----- End of picture text -----**<br>
**Fig 2. Simplified schematic diagram of P0 to P7**
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
PCF8574_PCF8574A **Product data sheet**
**Rev. 5 — 27 May 2013**
**3 of 33**
**PCF8574 PCF8574A ;**
**NXP Semiconductors**
**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
## **6. Pinning information**
**==> picture [497 x 230] intentionally omitted <==**
**----- Start of picture text -----**<br>
6.1 Pinning<br>A0 1 16 VDD<br>A1 2 15 SDA INT 1 20 P7<br>SCL 2 19 P6<br>A2 3 14 SCL<br>A0 1 16 VDD n.c. 3 18 n.c.<br>P0 4 PCF8574P 13 INT A1 2 15 SDA SDA 4 17 P5<br>PCF8574AP A2 3 14 SCL VDD 5 PCF8574TS/3 16 P4<br>P1 5 12 P7<br>P0 4 PCF8574T/3 13 INT A0 6 PCF8574ATS/3 15 VSS<br>P2 6 11 P6 P1 5 PCF8574AT/3 12 P7 A1 7 14 P3<br>P2 6 11 P6 n.c. 8 13 n.c.<br>P3 7 10 P5<br>P3 7 10 P5 A2 9 12 P2<br>VSS 8 9 P4 VSS 8 9 P4 P0 10 11 P1<br>002aad625 002aad626 002aad627<br>Fig 3. Pin configuration for DIP16 Fig 4. Pin configuration for SO16 Fig 5. Pin configuration for<br>SSOP20<br>**----- End of picture text -----**<br>
## **6.2 Pin description**
**Table 3. Pin description**
|**Symbol**|**Pin**<br>|**Pin**<br>|**Description**|
|---|---|---|---|
||**DIP16, SO16**|**SSOP20**||
|A0|1<br>6<br>address input 0|||
|A1|2<br>7<br>address input 1|||
|A2|3<br>9<br>address input 2|||
|P0|4<br>10<br>quasi-bidirectional I/O 0|||
|P1|5<br>11<br>quasi-bidirectional I/O 1|||
|P2|6<br>12<br>quasi-bidirectional I/O 2|||
|P3|7<br>14<br>quasi-bidirectional I/O 3|||
|VSS|8<br>15<br>supply ground|||
|P4|9<br>16<br>quasi-bidirectional I/O 4|||
|P5|10<br>17<br>quasi-bidirectional I/O 5|||
|P6|11<br>19<br>quasi-bidirectional I/O 6|||
|P7|12<br>20<br>quasi-bidirectional I/O 7|||
|INT|13<br>1<br>interrupt output (active LOW)|||
|SCL|14<br>2<br>serial clock line|||
|SDA|15<br>4<br>serial data line|||
|VDD|16<br>5<br>supply voltage|||
|n.c.|-<br>3, 8, 13, 18<br>not connected|||
© NXP B.V. 2013. All rights reserved.
PCF8574_PCF8574A **Product data sheet**
All information provided in this document is subject to legal disclaimers.
**Rev. 5 — 27 May 2013**
**4 of 33**
**PCF8574 PCF8574A ;**
**NXP Semiconductors**
**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
## **7. Functional description**
“ ” Refer to Figure 1 Block diagram .
## **7.1 Device address**
Following a START condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). The address format of the PCF8574/74A is shown in Figure 6. Slave address pins A2, A1 and A0 are held HIGH or LOW to choose one of eight slave addresses. To conserve power, no internal pull-up resistors are incorporated on A2, A1 or A0, so they must be externally held HIGH or LOW. The address pins (A2, A1, A0) can connect to VDD or VSS directly or through resistors.
**==> picture [359 x 105] intentionally omitted <==**
**----- Start of picture text -----**<br>
R/W R/W<br>slave address slave address<br>0 1 0 0 A2 A1 A0 0 0 1 1 1 A2 A1 A0 0<br>fixed hardware fixed hardware<br>selectable selectable<br>002aad628 002aad629<br>a. PCF8574 b. PCF8574A<br>Fig 6. PCF8574 and PCF8574A slave addresses<br>**----- End of picture text -----**<br>
The last bit of the first byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation (write operation is shown in Figure 6).
## **7.1.1 Address maps**
The PCF8574 and PCF8574A are functionally the same, but have a different fixed portion (A6 to A3) of the slave address. This allows eight of the PCF8574 and eight of the PCF8574A to be on the same I[2] C-bus without address conflict.
**Table 4. PCF8574 address map**
|**Pin connectivity**|**Pin connectivity**|**Pin connectivity**|**Address of PCF8574**|**Address of PCF8574**|**Address of PCF8574**|**Address of PCF8574**|**Address of PCF8574**|**Address of PCF8574**|**Address of PCF8574**|**Address of PCF8574**|**Address byte value**|**Address byte value**|**7-bit**<br>**hexadecimal**<br>**address**<br>**without R/W**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**A2**|**A1**|**A0**|**A6**|**A5**|**A4**|**A3**|**A2**|**A1**|**A0**|**R/W**|**Write**|**Read**||
|VSS<br>VSS<br>VSS|||0<br>1<br>0<br>0<br>0<br>0<br>0<br>-||||||||40h<br>41h||20h|
|VSS<br>VSS<br>VDD|||0<br>1<br>0<br>0<br>0<br>0<br>1<br>-||||||||42h<br>43h||21h|
|VSS<br>VDD<br>VSS|||0<br>1<br>0<br>0<br>0<br>1<br>0<br>-||||||||44h<br>45h||22h|
|VSS<br>VDD<br>VDD|||0<br>1<br>0<br>0<br>0<br>1<br>1<br>-||||||||46h<br>47h||23h|
|VDD<br>VSS<br>VSS|||0<br>1<br>0<br>0<br>1<br>0<br>0<br>-||||||||48h<br>49h||24h|
|VDD<br>VSS<br>VDD|||0<br>1<br>0<br>0<br>1<br>0<br>1<br>-||||||||4Ah<br>4Bh||25h|
|VDD<br>VDD<br>VSS|||0<br>1<br>0<br>0<br>1<br>1<br>0<br>-||||||||4Ch<br>4Dh||26h|
|VDD<br>VDD<br>VDD|||0<br>1<br>0<br>0<br>1<br>1<br>1<br>-||||||||4Eh<br>4Fh||27h|
© NXP B.V. 2013. All rights reserved.
PCF8574_PCF8574A **Product data sheet**
All information provided in this document is subject to legal disclaimers.
**Rev. 5 — 27 May 2013**
**5 of 33**
**PCF8574 PCF8574A ;**
**NXP Semiconductors**
**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
**Table 5. PCF8574A address map**
|**Pin connectivity**|**Pin connectivity**|**Pin connectivity**|**Address of PCF8574A**|**Address of PCF8574A**|**Address of PCF8574A**|**Address of PCF8574A**|**Address of PCF8574A**|**Address of PCF8574A**|**Address of PCF8574A**|**Address of PCF8574A**|**Address byte value**|**Address byte value**|**7-bit**<br>**hexadecimal**<br>**address**<br>**without R/W**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**A2**|**A1**|**A0**|**A6**|**A5**|**A4**|**A3**|**A2**|**A1**|**A0**|**R/W**|**Write**|**Read**||
|VSS<br>VSS<br>VSS|||0<br>1<br>1<br>1<br>0<br>0<br>0<br>-||||||||70h<br>71h||38h|
|VSS<br>VSS<br>VDD|||0<br>1<br>1<br>1<br>0<br>0<br>1<br>-||||||||72h<br>73h||39h|
|VSS<br>VDD<br>VSS|||0<br>1<br>1<br>1<br>0<br>1<br>0<br>-||||||||74h<br>75h||3Ah|
|VSS<br>VDD<br>VDD|||0<br>1<br>1<br>1<br>0<br>1<br>1<br>-||||||||76h<br>77h||3Bh|
|VDD<br>VSS<br>VSS|||0<br>1<br>1<br>1<br>1<br>0<br>0<br>-||||||||78h<br>79h||3Ch|
|VDD<br>VSS<br>VDD|||0<br>1<br>1<br>1<br>1<br>0<br>1<br>-||||||||7Ah<br>7Bh||3Dh|
|VDD<br>VDD<br>VSS|||0<br>1<br>1<br>1<br>1<br>1<br>0<br>-||||||||7Ch<br>7Dh||3Eh|
|VDD<br>VDD<br>VDD|||0<br>1<br>1<br>1<br>1<br>1<br>1<br>-||||||||7Eh<br>7Fh||3Fh|
## **8. I/O programming**
## **8.1 Quasi-bidirectional I/Os**
A quasi-bidirectional I/O is an input or output port without using a direction control register. Whenever the master reads the register, the value returned to master depends on the actual voltage or status of the pin. At power on, all the ports are HIGH with a weak 100 A internal pull-up to VDD, but can be driven LOW by an internal transistor, or an external signal. The I/O ports are entirely independent of each other, but each I/O octal is controlled by the same read or write data byte.
Advantages of the quasi-bidirectional I/O over totem pole I/O include:
- Better for driving LEDs since the p-channel (transistor to VDD) is small, which saves die size and therefore cost. LED drive only requires an internal transistor to ground, while the LED is connected to VDD through a current-limiting resistor. Totem pole I/O have both n-channel and p-channel transistors, which allow solid HIGH and LOW output levels without a pull-up resistor — good for logic levels.
- Simpler architecture — only a single register and the I/O can be both input and output at the same time. Totem pole I/O have a direction register that specifies the port pin direction and it is always in that configuration unless the direction is explicitly changed.
- Does not require a command byte. The simplicity of one register (no need for the pointer register or, technically, the command byte) is an advantage in some embedded systems where every byte counts because of memory or bandwidth limitations.
© NXP B.V. 2013. All rights reserved.
PCF8574_PCF8574A **Product data sheet**
All information provided in this document is subject to legal disclaimers. **Rev. 5 — 27 May 2013**
**6 of 33**
**PCF8574 PCF8574A ;**
**NXP Semiconductors**
**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
There is only one register to control four possibilities of the port pin: Input HIGH, input LOW, output HIGH, or output LOW.
**Input HIGH:** The master needs to write 1 to the register to set the port as an input mode if the device is not in the default power-on condition. The master reads the register to check the input status. If the external source pulls the port pin up to VDD or drives logic 1, then the master will read the value of 1.
**Input LOW:** The master needs to write 1 to the register to set the port to input mode if the device is not in the default power-on condition. The master reads the register to check the input status. If the external source pulls the port pin down to VSS or drives logic 0, which sinks the weak 100 A current source, then the master will read the value of 0.
**Output HIGH:** The master writes 1 to the register. There is an additional ‘accelerator’ or strong pull-up current when the master sets the port HIGH. The additional strong pull-up is only active during the HIGH time of the acknowledge clock cycle. This accelerator current helps the port’s 100 A current source make a faster rising edge into a heavily loaded output, but only at the start of the acknowledge clock cycle to avoid bus contention if an external signal is pulling the port LOW to VSS/driving the port with logic 0 at the same time. After the half clock cycle there is only the 100 A current source to hold the port HIGH.
**Output LOW:** The master writes 0 to the register. There is a strong current sink transistor that holds the port pin LOW. A large current may flow into the port, which could potentially damage the part if the master writes a 0 to the register and an external source is pulling the port HIGH at the same time.
**==> picture [233 x 147] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD<br>input HIGH<br>weak 100 µA<br>pull-up with current source output HIGH<br>resistor to VDD or (inactive when output LOW)<br>external drive HIGH<br>accelerator<br>pull-up<br>P port<br>P7 - P0<br>pull-down with<br>resistor to VSS or output LOW<br>external drive LOW<br>input LOW<br>VSS<br>002aah683<br>**----- End of picture text -----**<br>
**Fig 7. Simple quasi-bidirectional I/O**
© NXP B.V. 2013. All rights reserved.
PCF8574_PCF8574A **Product data sheet**
All information provided in this document is subject to legal disclaimers.
**Rev. 5 — 27 May 2013**
**7 of 33**
**PCF8574 PCF8574A ;**
**NXP Semiconductors**
**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
## **8.2 Writing to the port (Output mode)**
The master (microcontroller) sends the START condition and slave address setting the last bit of the address byte to logic 0 for the write mode. The PCF8574/74A acknowledges and the master then sends the data byte for P7 to P0 to the port register. As the clock line goes HIGH, the 8-bit data is presented on the port lines after it has been acknowledged by the PCF8574/74A. If a LOW is written, the strong pull-down turns on and stays on. If a HIGH is written, the strong pull-up turns on for[1] ⁄2 of the clock cycle, then the line is held HIGH by the weak current source. The master can then send a STOP or ReSTART condition or continue sending data. The number of data bytes that can be sent successively is not limited and the previous data is overwritten every time a data byte has been sent and acknowledged.
Ensure a logic 1 is written for any port that is being used as an input to ensure the strong external pull-down is turned off.
**==> picture [441 x 191] intentionally omitted <==**
**----- Start of picture text -----**<br>
SCL 1 2 3 4 5 6 7 8 9<br>slave address data 1 data 2<br>SDA S A6 A5 A4 A3 A2 A1 A0 0 A P7 P6 1 P4 P3 P2 P1 P0 A P7 P6 0 P4 P3 P2 P1 P0 A<br>START condition R/W P5 P5 acknowledge<br>acknowledge acknowledge from slave<br>from slave from slave<br>write to port<br>tv(Q) tv(Q)<br>data output from port DATA 1 VALID DATA 2 VALID<br>P5 output voltage<br>P5 pull-up output current Itrt(pu)<br>IOH<br>INT<br>td(rst) 002aah349<br>**----- End of picture text -----**<br>
**Fig 8. Write mode (output)**
Simple code WRITE mode:
<S> <slave address + write> < **ACK** > <data out> < **ACK** > <data out> < **ACK** > ... <data out> < **ACK** > <P>
**Remark:** Bold type = generated by slave device.
All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. **Rev. 5 — 27 May 2013 8 of 33**
PCF8574_PCF8574A **Product data sheet**
**8 of 33**
**PCF8574 PCF8574A ;**
**NXP Semiconductors**
**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
## **8.3 Reading from a port (Input mode)**
The port must have been previously written to logic 1, which is the condition after power-on reset. To enter the Read mode the master (microcontroller) addresses the slave device and sets the last bit of the address byte to logic 1 (address byte read). The slave will acknowledge and then send the data byte to the master. The master will NACK and then send the STOP condition or ACK and read the input register again.
The read of any pin being used as an output will indicate HIGH or LOW depending on the actual state of the pin.
If the data on the input port changes faster than the master can read, this data may be lost. The DATA 2 and DATA3 are lost because these data did not meet the setup time and hold time (see Figure 9).
**==> picture [459 x 158] intentionally omitted <==**
**----- Start of picture text -----**<br>
no acknowledge<br>from master<br>slave address data from port data from port<br>SDA S A6 A5 A4 A3 A2 A1 A0 1 A DATA 1 A DATA 4 1 P<br>START condition R/W acknowledge acknowledge STOP<br>from slave from master condition<br>read from<br>port<br>DATA 2<br>data at<br>DATA 1 DATA 3 DATA 4<br>port<br>th(D) tsu(D)<br>INT<br>tv(INT) trst(INT) trst(INT)<br>002aah383<br>**----- End of picture text -----**<br>
A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input data is lost.
**Fig 9. Read mode (input)**
Simple code for Read mode:
<S> <slave address + read> < **ACK** > < **data in** > <ACK> ... < **data in** > <ACK> < **data in** > <NACK> <P>
**Remark:** Bold type = generated by slave device.
## **8.4 Power-on reset**
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCF8574/74A in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCF8574/74A registers and I[2] C-bus/SMBus state machine will initialize to their default states of all I/Os to inputs with weak current source to VDD. Thereafter VDD must be lowered below VPOR and back up to the operation voltage for power-on reset cycle.
All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
PCF8574_PCF8574A **Product data sheet**
**Rev. 5 — 27 May 2013**
**9 of 33**
**PCF8574 PCF8574A ;**
**NXP Semiconductors**
**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
## **8.5 Interrupt output (INT)**
The PCF8574/74A provides an open-drain output (INT) which can be fed to a corresponding input of the microcontroller (see Figure 10). As soon as a port input is changed, the INT will be active (LOW) and notify the microcontroller.
An interrupt is generated at any rising or falling edge of the port inputs. After time tv(Q), the signal INT is valid.
The interrupt will reset to HIGH when data on the port is changed to the original setting or data is read or written by the master.
In the Write mode, the interrupt may be reset (HIGH) on the rising edge of the acknowledge bit of the address byte and also on the rising edge of the write to port pulse. The interrupt will always be reset (HIGH) on the falling edge of the write to port pulse (see Figure 8).
The interrupt is reset (HIGH) in the Read mode on the rising edge of the read from port pulse (see Figure 9).
During the interrupt reset, any I/O change close to the read or write pulse may not generate an interrupt, or the interrupt will have a very short pulse. After the interrupt is reset, any change in I/Os will be detected and transmitted as an INT.
At power-on reset all ports are in Input mode and the initial state of the ports is HIGH, therefore, for any port pin that is pulled LOW or driven LOW by external source, the interrupt output will be active (output LOW).
**==> picture [345 x 77] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD device 1 device 2 device 16<br>PCF8574 PCF8574 PCF8574A<br>MICROCONTROLLER<br>INT INT INT<br>INT<br>002aad634<br>**----- End of picture text -----**<br>
**Fig 10. Application of multiple PCF8574/74As with interrupt**
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**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
## **9. Characteristics of the I[2] C-bus**
The I[2] C-bus is for 2-way, 2-wire communication between different ICs or modules. The two wires are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
## **9.1 Bit transfer**
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 11).
**==> picture [241 x 87] intentionally omitted <==**
**----- Start of picture text -----**<br>
SDA<br>SCL<br>data line change<br>stable; of data<br>data valid allowed mba607<br>**----- End of picture text -----**<br>
**Fig 11. Bit transfer**
## **9.1.1 START and STOP conditions**
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 12).
**==> picture [351 x 97] intentionally omitted <==**
**----- Start of picture text -----**<br>
SDA<br>SCL<br>S P<br>START condition STOP condition<br>mba608<br>Fig 12. Definition of START and STOP conditions<br>**----- End of picture text -----**<br>
## **9.2 System configuration**
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 13).
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PCF8574_PCF8574A **Product data sheet**
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**NXP Semiconductors**
**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
**==> picture [432 x 110] intentionally omitted <==**
**----- Start of picture text -----**<br>
SDA<br>SCL<br>MASTER SLAVE SLAVE MASTER MASTER I [2] C-BUS<br>TRANSMITTER/ RECEIVER TRANSMITTER/ TRANSMITTER TRANSMITTER/ MULTIPLEXER<br>RECEIVER RECEIVER RECEIVER<br>SLAVE<br>002aaa966<br>**----- End of picture text -----**<br>
**Fig 13. System configuration**
## **9.3 Acknowledge**
The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit (see Figure 14). The acknowledge bit is an active LOW level (generated by the receiving device) that indicates to the transmitter that the data transfer was successful.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that wants to issue an acknowledge bit has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge bit related clock pulse; set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by **not** generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
**==> picture [297 x 130] intentionally omitted <==**
**----- Start of picture text -----**<br>
data output<br>by transmitter<br>not acknowledge<br>data output<br>by receiver<br>acknowledge<br>SCL from master<br>1 2 8 9<br>S<br>clock pulse for<br>START acknowledgement<br>condition 002aaa987<br>**----- End of picture text -----**<br>
**Fig 14. Acknowledgement on the I[2] C-bus**
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**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
## **10. Application design-in information**
## **10.1 Bidirectional I/O expander applications**
In the 8-bit I/O expander application shown in Figure 15, P0 and P1 are inputs, and P2 to P7 are outputs. When used in this configuration, during a write, **the input (P0 and P1) must be written as HIGH so the external devices fully control the input ports** . The desired HIGH or LOW logic levels may be written to the ports used as outputs (P2 to P7). If 10 A internal output HIGH is not enough current source, the port needs external pull-up resistor. During a read, the logic levels of the external devices driving the input ports (P0 and P1) and the previous written logic level to the output ports (P2 to P7) will be read.
The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O informs the microprocessor that there has been a change of data on its ports without having to communicate via the I[2] C-bus.
**==> picture [328 x 152] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD<br>VDD<br>VDD<br>SDA P0 temperature sensor<br>CORE SCL P1 battery status<br>PROCESSOR INT P2 control for latch<br>P3 control for switch<br>P4 control for audio<br>A0 P5 control for camera<br>A1 P6 control for MP3<br>A2 P7<br>002aah384<br>Fig 15. Bidirectional I/O expander application<br>**----- End of picture text -----**<br>
## **10.2 How to read and write to I/O expander (example)**
In the application example of PCF8574 shown in Figure 15, the microcontroller wants to control the P3 switch ON and the P7 LED ON when the temperature sensor P0 changes.
1. When the system power on:
Core Processor needs to issue an initial command to set P0 and P1 as inputs and P[7:2] as outputs with value 1010 00 (LED off, MP3 off, camera on, audio off, switch off and latch off).
2. Operation:
When the temperature changes above the threshold, the temperature sensor signal will toggle from HIGH to LOW. The INT will be activated and notifies the ‘core processor’ that there have been changes on the input pins. Read the input register. If P0 = 0 (temperature sensor has changed), then turn on LED and turn on switch.
3. Software code:
```
//System Power on
```
```
// write to PCF8574 with data 1010 0011b to set P[7:2] outputs and P[1:0] inputs
<S> <0100 0000> <ACK> <1010 0011> <ACK> <P>//Initial setting for PCF9574
```
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**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
```
while (INT == 1); //Monitor the interrupt pin. If INT = 1 do nothing
//When INT = 0 then read input ports
```
```
<S> <slave address read> <ACK> <1010 0010> <NACK> <P> //Read PCF8574 data
If (P0 == 0) //Temperature sensor activated
{
```
```
// write to PCF8574 with data 0010 1011b to turn on LED (P7), on Switch (P3)
and keep P[1:0] as input ports.
```
```
<S> <0100 0000> <ACK> <0010 1011> <ACK> <P> // Write to PCF8574
```
```
}
```
## **10.3 High current-drive load applications**
The GPIO has a minimum guaranteed sinking current of 10 mA per bit at 5 V. In applications requiring additional drive, two port pins may be connected together to sink up to 20 mA current. Both bits must then always be turned on or off together. Up to five pins can be connected together to drive 80 mA, which is the device recommended total limit. Each pin needs its own limiting resistor as shown in Figure 16 to prevent damage to the device should all ports not be turned on at the same time.
**==> picture [231 x 123] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD<br>VDD VDD<br>SDA P0<br>CORE SCL P1<br>PROCESSOR INT P2<br>P3 LOAD<br>P4<br>A0 P5<br>A1 P6<br>A2 P7<br>002aah385<br>**----- End of picture text -----**<br>
**Fig 16. High current-drive load application**
## **10.4 Migration path**
NXP offers newer, more capable drop-in replacements for the PCF8574/74A in newer space-saving packages.
**Table 6. Migration path**
|**Type number**|**I2C-bus**|**Voltage range**|**Number of**|**Interrupt**|**Reset**|**Total package**|
|---|---|---|---|---|---|---|
||**frequency**||**addresses**|||**sink current**|
||||**per device**||||
|PCF8574/74A|100 kHz|2.5 V to 6 V|8|yes|no|80 mA|
|PCA8574/74A|400 kHz|2.3 V to 5.5 V|8|yes|no|200 mA|
|PCA9674/74A|1 MHz Fm+|2.3 V to 5.5 V|64|yes|no|200 mA|
|PCA9670|1 MHz Fm+|2.3 V to 5.5 V|64|no|yes|200 mA|
|PCA9672|1 MHz Fm+|2.3 V to 5.5 V|16|yes|yes|200 mA|
PCA9670 replaces the interrupt output of the PCA9674 with hardware reset input to retain the maximum number of addresses and the PCA9672 replaces address A2 of the PCA9674 with hardware reset input to retain the interrupt but limit the number of addresses.
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**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
## **11. Limiting values**
**Table 7. Limiting values**
_In accordance with the Absolute Maximum Rating System (IEC 60134)._
|**Symbol**|**Parameter**|**Conditions**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|VDD|supply voltage||0.5|+7|V|
|IDD|supply current||-|100|mA|
|ISS|ground supply current||-|100|mA|
|VI|input voltage||VSS0.5|VDD+ 0.5|V|
|II|input current||-|20|mA|
|IO|output current||-|25|mA|
|Ptot|total power dissipation||-|400|mW|
|P/out|power dissipation per output||-|100|mW|
|Tj(max)|maximum junction temperature||-|125|C|
|Tstg|storage temperature||65|+150|C|
|Tamb|ambient temperature|operating|40|+85|C|
## **12. Thermal characteristics**
**Table 8. Thermal characteristics**
|**Symbol**<br>**Parameter**|**Conditions**<br>**Typ**<br>**Unit**|
|---|---|
|Rth(j-a)<br>thermal resistance from junction<br>to ambient|SO16 package<br>115<br>C/W|
||SSOP20 package<br>136<br>C/W|
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## **13. Static characteristics**
**Table 9. Static characteristics** _VDD = 2.5 V to 6 V; VSS = 0 V; Tamb =_ _40_ _C to +85_ _C; unless otherwise specified._
|**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|---|
|**Supply**||||||||
|VDD|supply voltage|||2.5|-|6.0|V|
|IDD|supply current|operating mode; VDD= 6 V; no load;||-|40|100|A|
|||VI= VDDor VSS; fSCL= 100 kHz||||||
|Istb|standby current|standby mode; VDD= 6 V; no load;||-|2.5|10|A|
|||VI= VDDor VSS||||||
|VPOR|power-on reset voltage|VDD= 6 V; no load; VI= VDDor VSS|[1]|-|1.3|2.4|V|
|**Input SCL; input/output SDA**||||||||
|VIL|LOW-level input voltage|||0.5|-|+0.3VDD|V|
|VIH|HIGH-level input voltage|||0.7VDD|-|VDD+ 0.5|V|
|IOL|LOW-level output current|VOL= 0.4 V||3|-|-|mA|
|IL|leakage current|VI= VDDor VSS||1|-|+1|A|
|Ci|input capacitance|VI= VSS||-|-|7|pF|
|**I/Os; P0 to P7**||||||||
|VIL|LOW-level input voltage|||0.5|-|+0.3VDD|V|
|VIH|HIGH-level input voltage|||0.7VDD|-|VDD+ 0.5|V|
|IIHL(max)|maximum allowed input current|VIVDDor VIVSS||-|-|400|A|
||through protection diode|||||||
|IOL|LOW-level output current|VOL= 1 V; VDD= 5 V||10|25|-|mA|
|IOH|HIGH-level output current|VOH= VSS||30|-|300|A|
|Itrt(pu)|transient boosted pull-up current|HIGH during acknowledge (see||-|1|-|mA|
|||Figure 8<br>); VOH= VSS; VDD= 2.5 V||||||
|Ci|input capacitance|||-|-|10|pF|
|Co|output capacitance|||-|-|10|pF|
|**Interrupt INT**<br>**(see Figure 8**<br>**)**||||||||
|||||||||
|IOL|LOW-level output current|VOL= 0.4 V||1.6|-|-|mA|
|IL|leakage current|VI= VDDor VSS||1|-|+1|A|
|**Select inputs A0, A1, A2**||||||||
|VIL|LOW-level input voltage|||0.5|-|+0.3VDD|V|
|VIH|HIGH-level input voltage|||0.7VDD|-|VDD+ 0.5|V|
|ILI|input leakage current|pin at VDDor VSS||250|-|+250|nA|
[1] The power-on reset circuit resets the I[2] C-bus logic at VDD < VPOR and sets all I/Os to logic 1 (with current source to VDD).
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PCF8574_PCF8574A
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**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
## **14. Dynamic characteristics**
## **Table 10. Dynamic characteristics** _VDD = 2.5 V to 6 V; VSS = 0 V; Tamb =_ _40_ _C to +85_ _C; unless otherwise specified._
|**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**I2C-bus timing[1]**<br> **(see Figure 17**<br>**)**|||||||
||||||||
|fSCL|SCL clock frequency||-|-|100|kHz|
|tBUF|bus free time between a STOP and||4.7|-|-|s|
||START condition||||||
|tHD;STA|hold time (repeated) START condition||4|-|-|s|
|tSU;STA|set-up time for a repeated START condition||4.7|-|-|s|
|tSU;STO|set-up time for STOP condition||4|-|-|s|
|tHD;DAT|data hold time||0|-|-|ns|
|tVD;DAT|data valid time||-|-|3.4|s|
|tSU;DAT|data set-up time||250|-|-|ns|
|tLOW|LOW period of the SCL clock||4.7|-|-|s|
|tHIGH|HIGH period of the SCL clock||4|-|-|s|
|tr|rise time of both SDA and SCL signals||-|-|1|s|
|tf|fall time of both SDA and SCL signals||-|-|0.3|s|
|**Port timing**|**(see Figure 8**<br> **and Figure 9**<br>**)**||||||
||||||||
|tv(Q)|data output valid time|CL100 pF|-|-|4|s|
|tsu(D)|data input set-up time|CL100 pF|0|-|-|s|
|th(D)|data input hold time|CL100 pF|4|-|-|s|
|**Interrupt INT**<br>**timing (see Figure 9**<br>**)**|||||||
||||||||
|tv(INT)|valid time on pin INT|from port to INT<br>;|-|-|4|s|
|||CL100 pF|||||
|trst(INT)|reset time on pin INT|from SCL to INT<br>;|-|-|4|s|
|||CL100 pF|||||
[1] All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing of VSS to VDD.
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**==> picture [383 x 191] intentionally omitted <==**
**----- Start of picture text -----**<br>
START bit 7 STOP<br>protocol condition MSB bit 6 bit 0 acknowledge condition<br>(A6) (R/W) (A)<br>(S) (A7) (P)<br>tSU;STA tLOW tHIGH<br>1 / fSCL<br>SCL 0.7 × VDD<br>0.3 × VDD<br>tBUF tf<br>tr<br>SDA 0.7 × VDD<br>0.3 × VDD<br>tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO<br>002aab175<br>Rise and fall times refer to VIL and VIH.<br>Fig 17. I [2] C-bus timing diagram<br>**----- End of picture text -----**<br>
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**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
## **15. Package outline**
## **DIP16: plastic dual in-line package; 16 leads (300 mil)**
**==> picture [38 x 8] intentionally omitted <==**
**----- Start of picture text -----**<br>
SOT38-4<br>**----- End of picture text -----**<br>
**==> picture [478 x 570] intentionally omitted <==**
**----- Start of picture text -----**<br>
D ME<br>A2 A<br>L A1<br>c<br>Z e w M<br>b1<br>(e )1<br>b b2<br>16 9 MH<br>pin 1 index<br>E<br>1 8<br>0 5 10 mm<br>scale<br>DIMENSIONS (inch dimensions are derived from the original mm dimensions)<br>UNIT max.A min.A 1 max.A 2 b b1 b2 c D (1) E (1) e e 1 L M E MH w max.Z (1)<br>1.73 0.53 1.25 0.36 19.50 6.48 3.60 8.25 10.0<br>mm 4.2 0.51 3.2 2.54 7.62 0.254 0.76<br>1.30 0.38 0.85 0.23 18.55 6.20 3.05 7.80 8.3<br>inches 0.17 0.02 0.13 0.068 0.021 0.049 0.014 0.77 0.26 0.1 0.3 0.14 0.32 0.39 0.01 0.03<br>0.051 0.015 0.033 0.009 0.73 0.24 0.12 0.31 0.33<br>Note<br>1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>95-01-14<br>SOT38-4<br>03-02-13<br>seating plane<br>**----- End of picture text -----**<br>
**Fig 18. Package outline SOT38-4 (DIP16)** PCF8574_PCF8574A
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**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
## **SO16: plastic small outline package; 16 leads; body width 7.5 mm**
**==> picture [43 x 8] intentionally omitted <==**
**----- Start of picture text -----**<br>
SOT162-1<br>**----- End of picture text -----**<br>
**==> picture [488 x 603] intentionally omitted <==**
**----- Start of picture text -----**<br>
D E A<br>X<br>c<br>y HE v M A<br>Z<br>16 9<br>Q<br>A2 A<br>A1 (A )3<br>pin 1 index<br>θ<br>L p<br>L<br>1 8 detail X<br>e w M<br>b p<br>0 5 10 mm<br>scale<br>DIMENSIONS (inch dimensions are derived from the original mm dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(1)] e HE L Lp Q v w y Z (1) θ<br>0.3 2.45 0.49 0.32 10.5 7.6 10.65 1.1 1.1 0.9<br>mm 2.65 0.1 2.25 0.25 0.36 0.23 10.1 7.4 1.27 10.00 1.4 0.4 1.0 0.25 0.25 0.1 0.4 8o<br>0.012 0.096 0.019 0.013 0.41 0.30 0.419 0.043 0.043 0.035 0o<br>inches 0.1 0.01 0.05 0.055 0.01 0.01 0.004<br>0.004 0.089 0.014 0.009 0.40 0.29 0.394 0.016 0.039 0.016<br>Note<br>1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>99-12-27<br> SOT162-1 075E03 MS-013<br>03-02-19<br>Package outline SOT162-1 (SO16)<br>_PCF8574APCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.<br>**----- End of picture text -----**<br>
**Fig 19. Package outline SOT162-1 (SO16)** PCF8574_PCF8574APCF8574A
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**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
## **SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm**
**==> picture [43 x 8] intentionally omitted <==**
**----- Start of picture text -----**<br>
SOT266-1<br>**----- End of picture text -----**<br>
**==> picture [488 x 603] intentionally omitted <==**
**----- Start of picture text -----**<br>
D E A<br>X<br>c<br>y HE v M A<br>Z<br>20 11<br>Q<br>pin 1 index A2 A1 (A )3 A<br>θ<br>L p<br>L<br>1 10<br>detail X<br>w M<br>e b p<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(1)] e HE L Lp Q v w y Z (1) θ<br>mm 1.5 0.150 1.41.2 0.25 0.320.20 0.200.13 6.66.4 4.54.3 0.65 6.66.2 1 0.750.45 0.650.45 0.2 0.13 0.1 0.480.18 100oo<br>Note<br>1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>99-12-27<br> SOT266-1 MO-152<br>03-02-19<br>Package outline SOT266-1 (SSOP20)<br>_PCF8574APCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.<br>**----- End of picture text -----**<br>
**Fig 20. Package outline SOT266-1 (SSOP20)** PCF8574_PCF8574APCF8574A
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**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
## **16. Handling information**
All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in _JESD625-A_ or equivalent standards.
## **17. Soldering of SMD packages**
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note _AN10365 “Surface mount reflow soldering description”_ .
## **17.1 Introduction to soldering**
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
## **17.2 Wave and reflow soldering**
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
- Through-hole components
- Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
- Board specifications, including the board finish, solder masks and vias
- Package footprints, including solder thieves and orientation
- The moisture sensitivity level of the packages
- Package placement
- Inspection and repair
- Lead-free soldering versus SnPb soldering
## **17.3 Wave soldering**
Key characteristics in wave soldering are:
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**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
- Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave
- Solder bath specifications, including temperature and impurities
## **17.4 Reflow soldering**
Key characteristics in reflow soldering are:
- Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 21) than a SnPb process, thus reducing the process window
- Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board
- Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 11 and 12
## **Table 11. SnPb eutectic process (from J-STD-020D)**
|**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**|
|---|---|---|
||**Volume (mm3)**||
||**< 350**|**350**|
|< 2.5|235<br>220||
|2.5|220<br>220||
## **Table 12. Lead-free process (from J-STD-020D)**
|**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**|
|---|---|---|---|
||**Volume (mm3)**|||
||**< 350**|**350 to 2000**|**> 2000**|
|< 1.6|260<br>260<br>260|||
|1.6 to 2.5|260<br>250<br>245|||
|> 2.5|250<br>245<br>245|||
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times.
Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 21.
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## **Remote 8-bit I/O expander for I[2] C-bus with interrupt**
**==> picture [352 x 223] intentionally omitted <==**
**----- Start of picture text -----**<br>
maximum peak temperature<br>= MSL limit, damage level<br>temperature<br>minimum peak temperature<br>= minimum soldering temperature<br>peak<br> temperature<br>time<br>001aac844<br>MSL: Moisture Sensitivity Level<br>Fig 21. Temperature profiles for large and small components<br>**----- End of picture text -----**<br>
For further information on temperature profiles, refer to Application Note _AN10365 “Surface mount reflow soldering description”_ .
## **18. Soldering of through-hole mount packages**
## **18.1 Introduction to soldering through-hole mount packages**
This text gives a very brief insight into wave, dip and manual soldering.
Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board.
## **18.2 Soldering by dipping or by solder wave**
Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.
## **18.3 Manual soldering**
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 C and 400 C, contact may be up to 5 seconds.
All information provided in this document is subject to legal disclaimers.
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## **18.4 Package related soldering information**
|**Package related soldering information**|**Package related soldering information**|**Package related soldering information**|
|---|---|---|
|**Table 13.**<br>**Suitability of through-hole mount IC packages for dipping and wave soldering**|||
|**Package**|**Soldering method**||
||**Dipping**|**Wave**|
|CPGA, HCPGA|-<br>suitable||
|DBS, DIP, HDIP, RDBS, SDIP, SIL|suitable<br>suitable[1]||
|PMFP[2]|-<br>not suitable||
[1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
- [2] For PMFP packages hot bar soldering or manual soldering is suitable.
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## **19. Soldering: PCB footprints**
**==> picture [481 x 9] intentionally omitted <==**
**----- Start of picture text -----**<br>
Footprint information for reflow soldering of SO16 package SOT162-1<br>**----- End of picture text -----**<br>
**==> picture [481 x 565] intentionally omitted <==**
**----- Start of picture text -----**<br>
Hx<br>Gx<br>P2<br>(0.125) (0.125)<br>Hy Gy By Ay<br>C<br>D2 (4x) P1 D1<br>Generic footprint pattern<br>Refer to the package outline drawing for actual layout<br>solder land<br>occupied area<br>DIMENSIONS in mm<br>P1 P2 Ay By C D1 D2 Gx Gy Hx Hy<br>1.270 1.320 11.200 6.400 2.400 0.700 0.800 10.040 8.600 11.900 11.450<br>sot162-1_fr<br>**----- End of picture text -----**<br>
**Fig 22. PCB footprint for SOT162-1 (SO16); reflow soldering**
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**==> picture [481 x 9] intentionally omitted <==**
**----- Start of picture text -----**<br>
Footprint information for reflow soldering of SSOP20 package SOT266-1<br>**----- End of picture text -----**<br>
**==> picture [481 x 564] intentionally omitted <==**
**----- Start of picture text -----**<br>
Hx<br>Gx<br>P2 (0.125)<br>(0.125)<br>Hy Gy By Ay<br>C<br>D2 (4x) P1 D1<br>solder land<br>occupied area<br>DIMENSIONS in mm<br>P1 P2 Ay By C D1 D2 Gx Gy Hx Hy<br>0.650 0.750 7.200 4.500 1.350 0.400 0.600 6.900 5.300 7.300 7.450<br>sot266-1_fr<br>**----- End of picture text -----**<br>
**Fig 23. PCB footprint for SOT266-1 (SSOP20); reflow soldering**
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## **20. Abbreviations**
## **Table 14. Abbreviations**
|**Acronym**|**Description**|
|---|---|
|CDM|Charged-Device Model|
|CMOS|Complementary Metal Oxide Semiconductor|
|I/O|Input/Output|
|I2C-bus|Inter IC bus|
|ESD|ElectroStatic Discharge|
|FF|Flip-Flop|
|GPIO|General Purpose Input/Output|
|HBM|Human Body Model|
|IC|Integrated Circuit|
|LED|Light Emitting Diode|
|LP|Low-Pass|
|PLC|Programmable Logic Controller|
|POR|Power-On Reset|
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## **21. Revision history**
**Table 15. Revision history**
|**Document ID**|**Release date**<br>**Data sheet status**<br>**Change notice**<br>**Supersedes**||
|---|---|---|
|PCF8574_PCF8574A v.5|20130527<br>Product data sheet<br>-<br>PCF8574 v.4||
|Modifications:|**•** The format of this data sheet has been redesigned to comply with the new identity||
||guidelines of NXP Semiconductors.||
||**•** Legal texts have been adapted to the new company name where appropriate.||
||**•** Electrical parameter letter-symbols and their definitions are updated to conform to NXP||
||presentation standards.||
||**•** Section 1“<br>General description<br>”<br>:updated||
||**•** Section 2“<br>Features and benefits<br>”<br>:||
||**–**<br>third bullet item: appended “with non-overvoltage tolerant I/O held to VDDwith 100A||
||current source”||
||**–**<br>added (new) fourth and seventh bullet items||
||**–**<br>added sixth bullet item: “Total package sink capability of 80 mA”||
||**–**<br>ninth bullet changed from “(10A maximum)” to “(2.5A typical)”||
||**–**<br>deleted (old) 11th, 12th and 13th bullet items||
||**•** Added (new) eighth bullet item “Mobile devices”||
||**•** Table 1“<br>Ordering information<br>”<br>:||
||**–**<br>Type number corrected from “PCF8574T” to “PCF8574/3”||
||**–**<br>Type number corrected from “PCF8574AT” to “PCF8574AT/3”||
||**–**<br>Type number corrected from “PCF8574TS” to “PCF8574TS/3”||
||**–**<br>Type number corrected from “PCF8574ATS” to “PCF8574ATS/3”||
||**•** Added Section 4.1“<br>Ordering options<br>”||
||**•** Figure 4“<br>Pin configuration for SO16<br>”<br>:updated type numbers (appended “/3”)||
||**•** Figure 5“<br>Pin configuration for SSOP20<br>”<br>:updated type numbers (appended “/3”)||
||**•** Section 6.2“<br>Pin description<br>”<br>:combined DIP16, SO16 and SSOP20 pin descriptions into||
||one table(Table 3<br>)||
||**•** Section 7“<br>Functional description<br>”<br> reorganized||
||**•** Section 7.1“<br>Device address<br>”<br>,first paragraph, fourth sentence: appended “so they must be||
||externally held HIGH or LOW”||
||**•** Table 4“<br>PCF8574 address map<br>”<br> updated: added column for 7-bit hexadecimal address||
||without R/W||
||**•** Table 5“<br>PCF8574A address map<br>”<br> updated: added column for 7-bit hexadecimal address||
||without R/W||
||**•** Section 8.1“<br>Quasi-bidirectional I/Os<br>”<br>:re-written and placed before Section 8.4“<br>Power-on||
||reset<br>”||
||**•** addedSection 8.2“<br>Writing to the port (Output mode)<br>”||
||**•** addedSection 8.3“<br>Reading from a port (Input mode)<br>”||
||**•** Figure 9“<br>Read mode (input)<br>”<br>:changed symbol “tps” to “tsu”||
||**•** Section 8.4“<br>Power-on reset<br>”<br> re-written||
||**•** Section 8.5“<br>Interrupt output (<br>INT<br>)<br>”<br> re-written||
||**•** Figure 10“<br>Application of multiple PCF8574/74As with interrupt<br>”<br> updated: changed||
||device 16 from “PCF8574” to “PCF8574A”||
||**•** Section 9.3“<br>Acknowledge<br>”<br>,first paragraph, third sentence re-written.||
||**•** Added Section 10“<br>Application design-in information<br>”||
All information provided in this document is subject to legal disclaimers.
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|**Table 15.**|**Revision history**_…continued_|**Revision history**_…continued_|**Revision history**_…continued_|||
|---|---|---|---|---|---|
|**Document ID**||**Release date**<br>**Data sheet status**||**Change notice**|**Supersedes**|
|Modifications: (continued)||**•** Table 7“<br>Limiting values<br>”<br>:||||
|||**–**|changed parameter description for symbol IIfrom “DC input current” to “input current”|||
|||**–**|changed parameter description for symbol IOfrom “DC output current” to “output|||
||||current”|||
|||**–**|changed parameter description for symbol ISSfrom “supply||current” to “ground supply|
||||current”|||
|||**–**|changed symbol “PO” to “P/out”|||
|||**–**|added Tj(max)limits|||
|||**•** Added Section 12“<br>Thermal characteristics<br>”||||
|||**•** Table 9“<br>Static characteristics<br>”<br>:||||
|||**–**|table title changed from “DC characteristics” to “Static characteristics”|||
|||**–**|sub-section “I/Os; P0 to P7”: changed parameter description for symbol Itrt(pu)|||
||||from “transient pull-up current” to “transient boosted pull-up||current”|
|||**–**|moved sub-section “Port timing” toTable|10“<br>Dynamic characteristics<br>”||
|||||||
|||**–**|sub-section “Interrupt INT<br>”: moved sub-sub-section “Timing” toTable 10“<br>Dynamic|||
||||characteristics<br>”|||
|||**•** Table 10“<br>Dynamic characteristics<br>”<br>:||||
|||**–**|sub-section “I2C-bus timing”: deleted symbol/parameter “tSW, tolerable spike width on|||
||||bus”|||
|||**–**|sub-section “Port timing”: changed symbol/parameter from “tpv, output data valid time”|||
||||to “tv(Q), data output valid time”|||
|||**–**|sub-section “Port timing”: changed symbol/parameter from “tsu, input data set-up time”|||
||||to “tsu(D), data input set-up time”|||
|||**–**|sub-section “Port timing”: changed symbol/parameter from “th, input data hold time”|||
||||to “th(D), data input hold time”|||
|||**–**|sub-section “Interrupt INT<br>”: changed parameter description||for symbol tv(INT)|
||||from “INT<br>output valid time” to “valid time on pin INT<br>”|||
|||**–**|sub-section “Interrupt INT<br>”: changed parameter description||for symbol trst(INT)|
||||from “INT<br>reset delay time” to “reset time|on pin INT<br>”||
|||**•** Added Section 19“<br>Soldering: PCB footprints<br>”||||
|||||||
|PCF8574 v.4||20021122<br>Product specification||-|PCF8574 v.3|
|(9397 750 10462)||||||
|PCF8574 v.3||20020729<br>Product specification||-|PCF8574 v.2|
|(9397 750 09911)||||||
|PCF8574 v.2||19970402<br>Product specification||-|PCF8574_PCF8574A v.1|
|(9397 750 01758)||||||
|PCF8574_PCF8574A v.1||199409|Product specification|-|-|
|(9397 750 70011)||||||
© NXP B.V. 2013. All rights reserved.
PCF8574_PCF8574A **Product data sheet**
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## **22. Legal information**
## **22.1 Data sheet status**
|**Document status[1]**<br>**[2]**|**Product statu**~~**s**~~**[3]**|**Definition**|
|---|---|---|
|Objective [short] data sheet|Development|This document contains data from the objective specification for product development.|
|Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.|
|Product [short] data sheet|Production|This document contains the product specification.|
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
## **22.2 Definitions**
**Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.
**Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
**Product specification —** The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
## **22.3 Disclaimers**
**Limited warranty and liability —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors.
**Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
**Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.
**Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.
**Limiting values —** Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.
**Terms and conditions of commercial sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.
**No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
PCF8574_PCF8574A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. **Product data sheet 31 of 33**
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## **NXP Semiconductors**
## **Remote 8-bit I/O expander for I[2] C-bus with interrupt**
**Export control —** This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.
**Non-automotive qualified products —** Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.
**Translations —** A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
## **22.4 Trademarks**
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
**I[2] C-bus —** logo is a trademark of NXP B.V.
## **23. Contact information**
For more information, please visit: **http://www.nxp.com**
For sales office addresses, please send an email to: **salesaddresses@nxp.com**
© NXP B.V. 2013. All rights reserved.
PCF8574_PCF8574A **Product data sheet**
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**Remote 8-bit I/O expander for I[2] C-bus with interrupt**
## **24. Contents**
|**1**|**General description . . . . . . . . . . . . . . . . . . . . . . 1**|18.3|Manual soldering . . . . . . . . . . . . . . . . . . . . . . 24|
|---|---|---|---|
|**2**|**Features and benefits . . . . . . . . . . . . . . . . . . . . 1**|18.4|Package related soldering information. . . . . . 25|
|**3**|**Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2**|**19**|**Soldering: PCB footprints . . . . . . . . . . . . . . . 26**|
|**4**|**Ordering information. . . . . . . . . . . . . . . . . . . . . 2**|**20**|**Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 28**|
|4.1|Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2|**21**|**Revision history . . . . . . . . . . . . . . . . . . . . . . . 29**|
|**5**|**Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3**|**22**|**Legal information . . . . . . . . . . . . . . . . . . . . . . 31**|
|**6**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . 4**|22.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31|
|6.1<br>6.2<br>**7**<br>7.1|Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4<br>Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4<br>**Functional description . . . . . . . . . . . . . . . . . . . 5**<br>Device address. . . . . . . . . . . . . . . . . . . . . . . . . 5|22.2<br>22.3<br>22.4<br>**23**|Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 31<br>Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 31<br>Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 32<br>**Contact information . . . . . . . . . . . . . . . . . . . . 32**|
|7.1.1|Address maps. . . . . . . . . . . . . . . . . . . . . . . . . . 5|**24**|**Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33**|
|**8**|**I/O programming . . . . . . . . . . . . . . . . . . . . . . . . 6**|||
|8.1|Quasi-bidirectional I/Os . . . . . . . . . . . . . . . . . . 6|||
|8.2|Writing to the port (Output mode) . . . . . . . . . . . 8|||
|8.3|Reading from a port (Input mode) . . . . . . . . . . 9|||
|8.4|Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9|||
|8.5|Interrupt output (INT<br>) . . . . . . . . . . . . . . . . . . . 10|||
|**9**|**Characteristics of the I2C-bus . . . . . . . . . . . . 11**|||
|9.1|Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 11|||
|9.1.1|START and STOP conditions . . . . . . . . . . . . . 11|||
|9.2|System configuration . . . . . . . . . . . . . . . . . . . 11|||
|9.3|Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 12|||
|**10**|**Application design-in information . . . . . . . . . 13**|||
|10.1|Bidirectional I/O expander applications . . . . . 13|||
|10.2|How to read and write to I/O expander|||
||(example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13|||
|10.3|High current-drive load applications . . . . . . . . 14|||
|10.4|Migration path. . . . . . . . . . . . . . . . . . . . . . . . . 14|||
|**11**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15**|||
|**12**|**Thermal characteristics . . . . . . . . . . . . . . . . . 15**|||
|**13**|**Static characteristics. . . . . . . . . . . . . . . . . . . . 16**|||
|**14**|**Dynamic characteristics . . . . . . . . . . . . . . . . . 17**|||
|**15**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19**|||
|**16**|**Handling information. . . . . . . . . . . . . . . . . . . . 22**|||
|**17**|**Soldering of SMD packages . . . . . . . . . . . . . . 22**|||
|17.1|Introduction to soldering . . . . . . . . . . . . . . . . . 22|||
|17.2|Wave and reflow soldering . . . . . . . . . . . . . . . 22|||
|17.3|Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 22|||
|17.4|Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 23|||
|**18**|**Soldering of through-hole mount packages . 24**|||
|18.1|Introduction to soldering through-hole mount|||
||packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24|||
|18.2|Soldering by dipping or by solder wave . . . . . 24|||
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.
**© NXP B.V. 2013.**
**All rights reserved.**
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 27 May 2013 Document identifier: PCF8574_PCF8574A**
Updated at February 9, 2023
NXP Semiconductors is a global leader in secure connectivity solutions, driving innovation across the automotive, industrial, IoT, mobile, and communications infrastructure markets. By developing advanced, purpose-built technologies, NXP enables devices to sense, think, connect, and act intelligently, delivering rigorously tested components that make the connected world safer and more efficient. Within the semiconductor space, NXP is highly regarded for its extensive range of high-performance integrated circuits and discrete devices. The brand's portfolio excels in drivers and interfaces, featuring a comprehensive selection of I/O expanders designed to streamline complex system architectures. For demanding high-frequency and wireless applications, NXP provides industry-leading RF FETs and RF/PIN diodes engineered to deliver exceptional signal integrity, efficiency, and reliability. The NXP product lineup further extends to essential discrete components, including versatile bipolar transistors, JFETs, and small signal diodes optimized for precision switching and amplification. Additionally, the portfolio supports advanced automation and smart applications with precision IC sensors, such as MEMS accelerometers, alongside specialized power management solutions like AC/DC LED driver ICs and single MOSFETs for cutting-edge electronics design.
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