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PCAL9554CPWJ
I/O Expander, 8bit, 400 kHz, I2C, 1.65 V, 5.5 V, TSSOP
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- Manufacturer: NXP
- Product type: I/O Expanders
- No. of Pins: 16Pins
- No. of I/O's: 8I/O's
- Bus Frequency: 400kHz
- IC Interface Type: I2C
- Chip Configuration: 8bit
- Supply Voltage Max: 5.5V
- Supply Voltage Min: 1.65V
- Interface Case Style: TSSOP
| Delivery and price | |
|---|---|
| Units per pack | 100 |
| Price | 1.46 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
**PCAL9554B; PCAL9554C Low-voltage 8-bit I[2] C-bus and SMBus low power I/O port with interrupt, weak pull-up and Agile I/O Rev. 4 — 19 December 2014 Product data sheet** ## **1. General description** The PCAL9554B and PCAL9554C are a low-voltage 8-bit General Purpose Input/Output (GPIO) expanders with interrupt and weak pull-up for I[2] C-bus/SMBus applications. The only difference between the PCAL9554B and PCAL9554C is their I[2] C-bus fixed address, allowing a larger number of the same device on the I[2] C-bus with no chance of address conflicts. NXP I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections to a minimum, for example, in ACPI power switches, sensors, push buttons, LEDs, fan control, etc. In addition to providing a flexible set of GPIOs, the wide VDD range of 1.65 V to 5.5 V allows the PCAL9554B/PCAL9554C to interface with next-generation microprocessors and microcontrollers where supply levels are dropping down to conserve power. The PCAL9554B/PCAL9554C contains the PCA9554A register set of four 8-bit Configuration, Input, Output, and Polarity Inversion registers, and additionally, the PCAL9554B/PCAL9554C has Agile I/O, which are additional features specifically designed to enhance the I/O. These additional features are: programmable output drive strength, latchable inputs, programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register, programmable open-drain or push-pull outputs. The PCAL9554B is a pin-for-pin replacement for the PCA9554, while the PCAL9554C replaces the PCA9554A, however both versions power-up with all I/O interrupted masked. This mask default allows for a board bring-up free of spurious interrupts at power-up. The PCAL9554B/PCAL9554C open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I[2] C-bus. Thus, the PCAL9554B or PCAL9554C can remain a simple slave device. The device outputs have 25 mA sink capabilities for directly driving LEDs while consuming low device current. Three hardware pins (A0, A1, A2) select the fixed I[2] C-bus address and allow up to eight devices to share the same I[2] C-bus/SMBus. The PCAL9554B and PCAL9554C differ only in their base I[2] C-bus addresses permitting a total of 16 of the same devices on the I[2] C-bus, minimizing the chance of address conflict, even in the most complex system. **==> picture [172 x 101] intentionally omitted <==** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **2. Features and benefits** - I[2] C-bus to parallel port expander - Operating power supply voltage range of 1.65 V to 5.5 V - Low standby current consumption: - 1.5 A (typical at 5 V VDD) - 1.0 A (typical at 3.3 V VDD) - Schmitt-trigger action allows slow input transition and better switching noise immunity at the SCL and SDA inputs - Vhys = 0.10 VDD (typical) - 5 V tolerant I/Os - Open-drain active LOW interrupt output (INT) - 400 kHz Fast-mode I[2] C-bus - Internal power-on reset - Power-up with all channels configured as inputs - No glitch on power-up - Latched outputs with 25 mA drive maximum capability for directly driving LEDs - Latch-up performance exceeds 100 mA per JESD78, Class II - ESD protection exceeds JESD22 - 2000 V Human Body Model (A114-A) - 1000 V Charged-Device Model (C101) - Packages offered: TSSOP16 and HVQFN16 ## **2.1 Agile I/O features** - Pin to pin replacement for PCA9554 and PCA9554B, PCA9554A and PCA9554C with interrupts disabled at power-up - Software backward compatible with PCA9554 and PCA9554B, PCA9554A and PCA9554C - Output port configuration: bank selectable push-pull or open-drain output stages - Interrupt status: read-only register identifies the source of an interrupt - Bit-wise I/O programming features: - Output drive strength: four programmable drive strengths to reduce rise and fall times in low capacitance applications - Input latch: Input Port register values changes are kept until the Input Port register is read - Pull-up/pull-down enable: floating input or pull-up/down resistor enable - Pull-up/pull-down selection: 100 k pull-up/down resistor selection - Interrupt mask: mask prevents the generation of the interrupt when input changes state All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. **Rev. 4 — 19 December 2014 2 of 42** PCAL9554B_PCAL9554C **Product data sheet** **2 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **3. Ordering information** **Table 1. Ordering information** |**Type number**|**Topside**<br>**mark**|**Package**|**Package**|**Package**| |---|---|---|---|---| |||**Name**|**Description**|**Version**| |PCAL9554BBS<br>L4B||HVQFN16<br>plastic thermal enhanced very thin quad flat package;<br>no leads; 16 terminals; body 330.85 mm<br>SOT758-1||| |PCAL9554BPW<br>PL9554B||TSSOP16<br>plastic thin shrink small outline package; 16 leads;<br>body width 4.4 mm<br>SOT403-1||| |PCAL9554CBS<br>L4C||HVQFN16<br>plastic thermal enhanced very thin quad flat package;<br>no leads; 16 terminals; body 330.85 mm<br>SOT758-1||| |PCAL9554CPW<br>PL9554C||TSSOP16<br>plastic thin shrink small outline package; 16 leads;<br>body width 4.4 mm<br>SOT403-1||| ## **3.1 Ordering options** ## **Table 2. Ordering options** |**Type number**|**Orderable**|**Package**|**Packing method**|**Minimum**|**Temperature range**| |---|---|---|---|---|---| ||**part number**|||**order**|| |||||**quantity**|| |PCAL9554BBS|PCAL9554BBSHP|HVQFN16|Reel 13” Q2/T3|6000|Tamb=40C to +85C| ||||*Standard mark SMD||| |PCAL9554BPW|PCAL9554BPWJ|TSSOP16|Reel 13” Q1/T1|2500|Tamb=40C to +85C| ||||*Standard mark SMD||| |PCAL9554CBS|PCAL9554CBSHP|HVQFN16|Reel 13” Q2/T3|6000|Tamb=40C to +85C| ||||*Standard mark SMD||| |PCAL9554CPW|PCAL9554CPWJ|TSSOP16|Reel 13” Q1/T1|2500|Tamb=40C to +85C| ||||*Standard mark SMD||| ## **4. Block diagram** **==> picture [355 x 176] intentionally omitted <==** **----- Start of picture text -----**<br> A0 P0<br>A1 8-bit P1<br>A2 P2<br>INPUT/ P3<br>SCL INPUT I [2] C-BUS/SMBus OUTPUT<br>SDA FILTER CONTROL write pulse PORTS P4<br>P5<br>P6<br>read pulse<br>P7<br>VDD POWER-ON VDD<br>RESET<br>VSS PCAL9554B LP INT<br>PCAL9554C FILTER<br>002aah204<br>Remark: All I/Os are set to inputs at reset.<br>**----- End of picture text -----**<br> **Fig 1. Block diagram of PCAL9554B/PCAL9554C** © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **3 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **5. Pinning information** ## **5.1 Pinning** **==> picture [396 x 187] intentionally omitted <==** **----- Start of picture text -----**<br> terminal 1<br>index area<br>A0 1 16 VDD A2 1 12 SCL<br>A1 2 15 SDA<br>P0 2 PCAL9554BBS 11 INT<br>A2 3 14 SCL PCAL9554CBS<br>P1 3 10 P7<br>P0 4 PCAL9554BPW 13 INT<br>P1 5 PCAL9554CPW 12 P7 P2 4 9 P6<br>P2 6 11 P6<br>P3 7 10 P5<br>VSS 8 9 P4 002aah206<br>002aah205 Transparent top view<br>Fig 2. Pin configuration for TSSOP16 Fig 3. Pin configuration for HVQFN16<br>A1 A0 VDD SDA<br>16 15 14 13<br>5 6 7 8<br>P3 SS P4 P5<br>V<br>**----- End of picture text -----**<br> ## **5.2 Pin description** ## **Table 3. Pin description** |**Symbol**|**Pin**|**Pin**|**Description**| |---|---|---|---| ||**TSSOP16**|**HVQFN16**|| |A0|1<br>15<br>address input 0||| |A1|2<br>16<br>address input 1||| |A2|3<br>1<br>address input 2||| |P~~0~~[1]|4<br>2<br>Port P input/output 0||| |P~~1~~[1]|5<br>3<br>Port P input/output 1||| |P~~2~~[1]|6<br>4<br>Port P input/output 2||| |P~~3~~[1]|7<br>5<br>Port P input/output 3||| |VSS|8<br>6[2]<br>supply ground||| |P~~4~~[1]|9<br>7<br>Port P input/output 4||| |P~~5~~[1]|10<br>8<br>Port P input/output 5||| |P~~6~~[1]|11<br>9<br>Port P input/output 6||| |P~~7~~[1]|12<br>10<br>Port P input/output 7||| |INT|13<br>11<br>interrupt output (open-drain)||| |SCL|14<br>12<br>serial clock line||| |SDA|15<br>13<br>serial data line||| |VDD|16<br>14<br>supply voltage||| - [1] All I/O are configured as input at power-on. - [2] HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** **Rev. 4 — 19 December 2014** **4 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **6. Functional description** “ ” Refer to Figure 1 Block diagram of PCAL9554B/PCAL9554C . ## **6.1 Device address** **==> picture [359 x 103] intentionally omitted <==** **----- Start of picture text -----**<br> slave address slave address<br>0 1 0 0 A2 A1 A0 R/W 0 1 1 1 A2 A1 A0 R/W<br>fixed hardware fixed hardware<br>selectable selectable<br>002aah207 002aah208<br>a. PCAL9554B address b. PCAL9554C address<br>Fig 4. Device address<br>**----- End of picture text -----**<br> A2, A1 and A0 are the hardware address package pins and are held to either HIGH (logic 1) or LOW (logic 0) to assign one of the eight possible slave addresses. The last bit of the slave address (R/W) defines the operation (read or write) to be performed. A HIGH (logic 1) selects a read operation, while a LOW (logic 0) selects a write operation. ## **6.2 Pointer register and command byte** Following the successful acknowledgement of the address byte, the bus master sends a command byte, which is stored in the Pointer register in the PCAL9554B/PCAL9554C. Two bits of this data byte state the operation (read or write) and the internal registers (Input, Output, Polarity Inversion, or Configuration) that will be affected. Bit 6 in conjunction with the lower three bits of the Command byte are used to point to the extended features of the device (Agile I/O). This register is write only. **==> picture [261 x 50] intentionally omitted <==** **----- Start of picture text -----**<br> B7 B6 B5 B4 B3 B2 B1 B0<br>002aaf540<br>Fig 5. Pointer register bits<br>**----- End of picture text -----**<br> © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **5 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **Table 4. Command byte** |**Pointer register bits**|**Pointer register bits**|**Pointer register bits**|**Pointer register bits**|**Pointer register bits**|**Pointer register bits**|**Pointer register bits**|**Pointer register bits**|**Command byte**<br>**(hexadecimal)**|**Register**|**Protocol**|**Power-up**<br>**default**| |---|---|---|---|---|---|---|---|---|---|---|---| |**B7**|**B6**|**B5**|**B4**|**B3**|**B2**|**B1**|**B0**||||| |0<br>0<br>0<br>0<br>0<br>0<br>0<br>0<br>00h<br>Input port<br>read byte<br>xxxx xxxx[1]|||||||||||| |0<br>0<br>0<br>0<br>0<br>0<br>0<br>1<br>01h<br>Output port<br>read/write byte<br>1111 1111|||||||||||| |0<br>0<br>0<br>0<br>0<br>0<br>1<br>0<br>02h<br>Polarity Inversion<br>read/write byte<br>0000 0000|||||||||||| |0<br>0<br>0<br>0<br>0<br>0<br>1<br>1<br>03h<br>Configuration<br>read/write byte<br>1111 1111|||||||||||| |0<br>1<br>0<br>0<br>0<br>0<br>0<br>0<br>40h<br>Output drive strength 0<br>read/write byte<br>1111 1111|||||||||||| |0<br>1<br>0<br>0<br>0<br>0<br>0<br>1<br>41h<br>Output drive strength 1<br>read/write byte<br>1111 1111|||||||||||| |0<br>1<br>0<br>0<br>0<br>0<br>1<br>0<br>42h<br>Input latch<br>read/write byte<br>0000 0000|||||||||||| |0<br>1<br>0<br>0<br>0<br>0<br>1<br>1<br>43h<br>Pull-up/pull-down enable<br>read/write byte<br>1111 1111|||||||||||| |0<br>1<br>0<br>0<br>0<br>1<br>0<br>0<br>44h<br>Pull-up/pull-down selection<br>read/write byte<br>1111 1111|||||||||||| |0<br>1<br>0<br>0<br>0<br>1<br>0<br>1<br>45h<br>Interrupt mask<br>read/write byte<br>1111 1111|||||||||||| |0<br>1<br>0<br>0<br>0<br>1<br>1<br>0<br>46h<br>Interrupt status<br>read byte<br>0000 0000|||||||||||| |0<br>1<br>0<br>0<br>1<br>1<br>1<br>1<br>4Fh<br>Output port configuration<br>read/write byte<br>0000 0000|||||||||||| [1] Undefined. ## **6.3 Interface definition** **Table 5. Interface definition** |**Byte**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**| |---|---|---|---|---|---|---|---|---| ||**7 (MSB)**|**6**|**5**|**4**|**3**|**2**|**1**|**0 (LSB)**| |I2C-bus slave address|L<br>H<br>L/H<br>L/H<br>A2<br>A1<br>A0<br>R/W|||||||| |I/O data bus|P7<br>P6<br>P5<br>P4<br>P3<br>P2<br>P1<br>P0|||||||| ## **6.4 Register descriptions** ## **6.4.1 Input port register (00h)** The Input port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. The Input port register is read only; writes to this register have no effect. The default value ‘X’ is determined by the externally applied logic level. An Input port register read operation is “ ” performed as described in Section 7.2 Read commands . **Table 6. Input port register (address 00h)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|I7|I6|I5|I4|I3|I2|I1|I0| |**Default**|X<br>X<br>X<br>X<br>X<br>X<br>X<br>X|||||||| ## **6.4.2 Output port register (01h)** The Output port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads from this register reflect the value that was written to this register, **not** the actual pin value. © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **6 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** **Table 7. Output port register (address 01h)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|O7|O6|O5|O4|O3|O2|O1|O0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||||||| ## **6.4.3 Polarity inversion register (02h)** The Polarity inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with ‘1’), the corresponding port pin’s polarity is inverted. If a bit in this register is cleared (written with a ‘0’), the corresponding port pin’s original polarity is retained. **Table 8. Polarity inversion register (address 02h)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|N7|N6|N5|N4|N3|N2|N1|N0| |**Default**|0<br>0<br>0<br>0<br>0<br>0<br>0<br>0|||||||| ## **6.4.4 Configuration register (03h)** The Configuration register (register 3) configures the direction of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as a high-impedance input. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. **Table 9. Configuration register (address 03h)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|C7|C6|C5|C4|C3|C2|C1|C0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||||||| ## **6.4.5 Output drive strength registers (40h, 41h)** The Output drive strength registers control the output drive level of the GPIO. Each GPIO can be configured independently to a certain output current level by two register control bits. For example, Port 7 is controlled by register 41 CC7 (bits [7:6]), Port 6 is controlled by register 41 CC6 (bits [5:4]). The output drive level of the GPIO is programmed 00b = 0.25, 01b = 0.5, 10b = 0.75 or 11b = 1 of the drive capability of the I/O. See Section 8.2 “Output drive strength control” for more details. |**Table 10.**<br>**Current control register (address 40h)**|**Table 10.**<br>**Current control register (address 40h)**|**Table 10.**<br>**Current control register (address 40h)**|**Table 10.**<br>**Current control register (address 40h)**|**Table 10.**<br>**Current control register (address 40h)**| |---|---|---|---|---| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||| |**Symbol**|CC3|CC2|CC1|CC0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||| |**Table 11.**<br>**Current control register (address 41h)**||||| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||| |**Symbol**|CC7|CC6|CC5|CC4| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||| © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **7 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **6.4.6 Input latch register (42h)** The Input latch register enables and disables the input latch of the I/O pins. These registers are effective only when the pin is configured as an input port. When an input latch register bit is 0, the corresponding input pin state is not latched. A state change in the corresponding input pin generates an interrupt. A read of the input port register clears the interrupt. If the input goes back to its initial logic state before the input port register is read, then the interrupt is cleared. When an input latch register bit is 1, the corresponding input pin state is latched. A change of state of the input generates an interrupt and the input logic value is loaded into the corresponding bit of the input port register (registers 0). A read of the input port register clears the interrupt. If the input pin returns to its initial logic state before the input port register is read, then the interrupt is not cleared and the corresponding bit of the input port register keeps the logic value that initiated the interrupt. See Figure 11. For example, if the P4 input was as logic 0 and the input goes to logic 1 then back to logic 0, the input port register will capture this change and an interrupt is generated (if unmasked). When the read is performed on the input port register, the interrupt is cleared, assuming there were no additional input(s) that have changed, and bit 4 of the input port register will read ‘1’. The next read of the input port register bit 4 should now read ‘0’. An interrupt remains active when a non-latched input simultaneously switches state with a latched input and then returns to its original state. A read of the input port register reflects only the change of state of the latched input and also clears the interrupt. The interrupt is not cleared if the input latch register changes from latched to non-latched configuration. If the input pin is changed from latched to non-latched input, a read from the input port register reflects the current port logic level. If the input pin is changed from non-latched to latched input, the read from the input port register reflects the latched logic level. ## **Table 12. Input latch register (address 42h)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|L7|L6|L5|L4|L3|L2|L1|L0| |**Default**|0<br>0<br>0<br>0<br>0<br>0<br>0<br>0|||||||| ## **6.4.7 Pull-up/pull-down enable register (43h)** This register allows the user to enable or disable pull-up/pull-down resistors on the I/O pins. Setting the bit to logic 1 enables the selection of pull-up/pull-down resistors. Setting the bit to logic 0 disconnects the pull-up/pull-down resistors from the I/O pins. Also, the resistors will be disconnected when the outputs are configured as open-drain outputs (see Section 6.4.11). Use the pull-up/pull-down registers to select either a pull-up or pull-down resistor. ## **Table 13. Pull-up/pull-down enable register (address 43h)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|PE7|PE6|PE5|PE4|PE3|PE2|PE1|PE0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||||||| The default value enables pull-up resistors on all I/O pins to match with the non-Agile I/O devices PCA9554B and PCA9554C. © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **8 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **6.4.8 Pull-up/pull-down selection register (44h)** The I/O port can be configured to have pull-up or pull-down resistor by programming the pull-up/pull-down selection register. Setting a bit to logic 1 selects a 100 k pull-up resistor for that I/O pin. Setting a bit to logic 0 selects a 100 k pull-down resistor for that I/O pin. If the pull-up/down feature is disconnected, writing to this register will have no effect on I/O pin. Typical value is 100 k with minimum of 50 k and maximum of 150 k. **Table 14. Pull-up/pull-down selection register (address 44h)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|PUD7|PUD6|PUD5|PUD4|PUD3|PUD2|PUD1|PUD0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||||||| ## **6.4.9 Interrupt mask register (45h)** Interrupt mask register is set to logic 1 upon power-on, disabling interrupts during system start-up. Interrupts may be enabled by setting corresponding mask bits to logic 0. If an input changes state and the corresponding bit in the Interrupt mask register is set to 1, the interrupt is masked and the interrupt pin (INT) will not be asserted. If the corresponding bit in the Interrupt mask register is set to 0, the interrupt pin will be asserted. When an input changes state and the resulting interrupt is masked (interrupt mask bit is 1), setting the input mask register bit to 0 will cause the interrupt pin to be asserted. If the interrupt mask bit of an input that is currently the source of an interrupt is set to 1, the interrupt pin will be de-asserted. **Table 15. Interrupt mask register (address 45h)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|M7|M6|M5|M4|M3|M2|M1|M0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||||||| ## **6.4.10 Interrupt status register (46h)** This read-only register is used to identify the source of an interrupt. When read, a logic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0 indicates that the input pin is not the source of an interrupt. When a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt status bit will return logic 0. **Table 16. Interrupt status register (address 46h)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|S7|S6|S5|S4|S3|S2|S1|S0| |**Default**|0<br>0<br>0<br>0<br>0<br>0<br>0<br>0|||||||| ## **6.4.11 Output port configuration register (4Fh)** The output port configuration register selects port-wise push-pull or open-drain I/O stage. A logic 0 configures the I/O as push-pull (Q1 and Q2 are active, see Figure 6). A logic 1 configures the I/O as open-drain (Q1 is disabled, Q2 is active). The recommended command sequence is to program this register (4Fh) before the Configuration register (03h) sets the port pins as outputs. All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** **Rev. 4 — 19 December 2014** **9 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** **Table 17. Output port configuration register (address 4Fh)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---| |**Symbol**|reserved|ODEN0| |**Default**|0<br>0<br>0<br>0<br>0<br>0<br>0<br>0|| ## **6.5 I/O port** When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output port register. In this case, there are low-impedance paths between the I/O pin and either VDD or VSS. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation. **==> picture [379 x 331] intentionally omitted <==** **----- Start of picture text -----**<br> data from output port<br>shift register configuration register data<br>register VDD<br>data from D Q Q1 ESD<br>shift register<br>FF protection<br>write diode<br>configuration CK Q D Q<br>P0 to P7<br>pulse<br>FF Q2 ESD<br>write pulse CK protection<br>diode<br>output port VSS<br>register<br>D Q<br>input port<br>FF register data<br>read pulse CK<br>VDD INTERRUPT<br>input port MASK to INT<br>register<br>PULL-UP/PULL-DOWN 100 kΩ<br>CONTROL<br>D Q<br>input latch<br>register LATCH<br>data from<br>D Q EN<br>shift register read pulse<br>FF input port<br>write input latch<br>latch pulse CK polarity inversion<br>register<br>data from D Q<br>shift register<br>FF<br>write polarity<br>CK<br>pulse 002aah101<br>**----- End of picture text -----**<br> On power-up or reset, all registers return to default values. **Fig 6. Simplified schematic of the I/Os (P0 to P7)** © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **10 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **6.6 Power-on reset** When power (from 0 V) is applied to VDD, an internal power-on reset holds the PCAL9554B/PCAL9554C in a reset condition until VDD has reached VPOR. At that time, the reset condition is released and the PCAL9554B/PCAL9554C registers and I[2] C-bus/SMBus state machine initialize to their default states. After that, VDD must be lowered to below VPOR and back up to the operating voltage for a power-reset cycle. See Section 8.4 “Power-on reset requirements”. ## **6.7 Interrupt output (INT)** An interrupt is generated by any rising or falling edge of the port inputs in the Input mode. After time tv(INT), the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or when data is read from the port that generated the interrupt (see Figure 10). Resetting occurs in the Read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT. A pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the Input port register. The INT output has an open-drain structure and requires a pull-up resistor to VDD. INT should be connected to the voltage source of the device that requires the interrupt information. When using the input latch feature, the input pin state is latched. The interrupt is reset only when data is read from the port that generated the interrupt. The reset occurs in the Read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **11 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **7. Bus transactions** The PCAL9554B/PCAL9554C is an I[2] C-bus slave device. Data is exchanged between the master and PCAL9554B/PCAL9554C through write and read commands using I[2] C-bus. The two communication lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. ## **7.1 Write commands** Data is transmitted to the PCAL9554B/PCAL9554C by sending the device address and setting the Least Significant Bit (LSB) to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one write transmission. **==> picture [423 x 134] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>STOP<br>condition<br>slave address [(1)] command byte data to port<br>SDA S 0 1 0 0 A2 A1 A0 0 A 0 0 0 0 0 0 0 1 A DATA 1 A P<br>START condition R/W acknowledge acknowledge acknowledge<br>from slave from slave from slave<br>write to port<br>tv(Q)<br>data out from port DATA 1 VALID<br>002aah124<br>**----- End of picture text -----**<br> (1) PCAL9554B address shown. Address for PCAL9554C is 0111,A2,A1,A0. **Fig 7. Write to Output port register** **==> picture [409 x 91] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>STOP<br>condition<br>slave address [(1)] command byte data to register<br>SDA S 0 1 0 0 A2 A1 A0 0 A 0 0 0 0 0 0 1/0 1/0 A DATA 1 A P<br>START condition R/W acknowledge acknowledge acknowledge<br>from slave from slave from slave<br>002aah125<br>**----- End of picture text -----**<br> (1) PCAL9554B address shown. Address for PCAL9554C is 0111,A2,A1,A0. **Fig 8. Write to Configuration or Polarity inversion registers** © NXP Semiconductors N.V. 2014. All rights reserved. **12 of 42** PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **7.2 Read commands** To read data from the PCAL9554B/PCAL9554C, the bus master must first send the PCAL9554B/PCAL9554C address with the least significant bit set to a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which register is to be accessed. After a restart the device address is sent again, but this time the LSB is set to a logic 1. Data from the register defined by the command byte then is sent by the PCAL9554B/PCAL9554C (see Figure 9 and Figure 10). Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limit on the number of data bytes received in one read transmission, but on the final byte received the bus master must not acknowledge the data. **==> picture [433 x 132] intentionally omitted <==** **----- Start of picture text -----**<br> slave address [(1)]<br>SDA S 0 1 0 0 A2 A1 A0 0 A COMMAND BYTE A (cont.)<br>START condition R/W acknowledge from slave acknowledge from slave<br>slave address [(1)] data from register data from register<br>(cont.) S 0 1 0 0 A2 A1 A0 1 A DATA (first byte) A DATA (last byte) NA P<br>(repeated) R/W acknowledge no acknowledge STOP<br>START condition acknowledge from master from master condition<br>from slave at this moment master-transmitter becomes master-receiver<br>and slave-receiver becomes slave-transmitter 002aah126<br>**----- End of picture text -----**<br> (1) PCAL9554B address shown. Address for PCAL9554C is 0111,A2,A1,A0. **Fig 9. Read from register** **==> picture [465 x 157] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>no acknowledge<br>slave address [(1)] data from port data from port from master<br>SDA S 0 1 0 0 A2 A1 A0 1 A DATA 1 A DATA 4 1 P<br>START condition R/W acknowledge from slave acknowledge from master STOP<br>read from condition<br>port<br>data into<br>DATA 1 DATA 2 DATA 3 DATA 4 DATA 5<br>port<br>th(D) tsu(D) INT is cleared by<br>read from port<br>INT STOP not needed<br>tv(INT) trst(INT) to clear INT<br>002aah127<br>**----- End of picture text -----**<br> Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been programmed with 00h (read Input port register). This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from P port (see Figure 9). (1) PCAL9554B address shown. Address for PCAL9554C is 0111,A2,A1,A0. **Fig 10. Read Input port register (non-latched)** All information provided in this document is subject to legal disclaimers. > © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** **Rev. 4 — 19 December 2014** **13 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** **==> picture [475 x 210] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>no acknowledge<br>from master<br>slave address [(1)] data from port data from port<br>SDA S 0 1 0 0 A2 A1 A0 1 A DATA 1 A DATA 2 1 P<br>START condition R/W acknowledge from slave acknowledge from master STOP<br>read from condition<br>port<br>data into<br>DATA 1 DATA 2 DATA 1<br>port<br>th(D) tsu(D) INT is cleared by<br>read from port<br>INT STOP not needed<br>to clear INT<br>tv(INT) trst(INT) 002aah209<br>Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest acknowledge<br>phase is valid (output mode). It is assumed that the command byte has previously been programmed with 00h (read Input port<br>register).<br>**----- End of picture text -----**<br> This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from P port (see Figure 9). - (1) PCAL9554B address shown. Address for PCAL9554C is 0111,A2,A1,A0. **Fig 11. Read Input port register (latch enabled)** © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **14 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **8. Application design-in information** **==> picture [435 x 236] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>(3.3 V) 100 kΩ SUB-SYSTEM 1<br>10 kΩ 10 kΩ 10 kΩ 2 kΩ<br>VDD VDD (× 3) [(1)] (e.g., temp sensor)<br>MASTER INT<br>PCAL9554B<br>CONTROLLER<br>SCL SCL P0<br>SUB-SYSTEM 2<br>SDA SDA P1 (e.g., counter)<br>INT INT<br>P2 RESET<br>P3<br>A<br>VSS P4 controlled<br>enable<br>switch<br>P5 (e.g., CBT device)<br>A2<br>P6 B<br>A1<br>A0 P7<br>SUB-SYSTEM 3<br>VSS (e.g., alarm system)<br>ALARM<br>VDD<br>002aah211<br>**----- End of picture text -----**<br> Device address is 0100 000x for this example using PCAL9554B (address for PCAL9554C is 0111 000x). P0, P2, P3 configured as outputs. P1, P4, P5 configured as inputs. P6, P7 are not used and need 100 k pull-up resistors to protect them from floating or the internal pull-up or pull-down selected. (1) No resistors are required for inputs (on P port) that may float due to the weak pull-up integrated into the device. **Fig 12. Typical application** ## **8.1 Minimizing IDD when the I/Os are used to control LEDs** When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 12. Since the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower than VDD. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 13 shows a high value resistor in parallel with the LED, which is not needed with the PCAL9554B or PCAL9554C that integrate a weak pull-up resistor on all pins. Figure 14 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VDD and prevents additional supply current consumption when the LED is off. © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **15 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** **==> picture [396 x 166] intentionally omitted <==** **----- Start of picture text -----**<br> 3.3 V 5 V<br>VDD<br>VDD LED 100 kΩ VDD LED<br>Pn Pn<br>002aag164 002aag165<br>Fig 13. High value resistor in parallel with Fig 14. Device supplied by a lower voltage<br>the LED<br>**----- End of picture text -----**<br> ## **8.2 Output drive strength control** The Output drive strength registers allow the user to control the output drive level of the GPIO. Each GPIO can be configured independently to one of the four possible output current levels. By programming these bits the user is changing the number of transistor pairs or ‘fingers’ that drive the I/O pad. Figure 15 shows a simplified output stage. The behavior of the pad is affected by the Configuration register, the output port data, and the current control register. When the Current Control register bits are programmed to 10b, then only two of the fingers are active, reducing the current drive capability by 50 %. **==> picture [465 x 297] intentionally omitted <==** **----- Start of picture text -----**<br> PMOS_EN0<br>VDD<br>PMOS_EN1<br>Current Control PMOS_EN[3:0]<br>DECODER<br>register<br>NMOS_EN[3:0]<br>PMOS_EN2<br>Configuration<br>register<br>PMOS_EN3<br>P0 to P7<br>Output port<br>register<br>NMOS_EN3<br>NMOS_EN2<br>NMOS_EN1<br>NMOS_EN0 002aah108<br>Fig 15. Simplified output stage<br>**----- End of picture text -----**<br> All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** **Rev. 4 — 19 December 2014** **16 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** Reducing the current drive capability may be desirable to reduce system noise. When the output switches (transitions from H/L), there is a peak current that is a function of the output drive selection. This peak current runs through VDD and VSS package inductance and will create noise (some radiated, but more critically Simultaneous Switching Noise (SSN)). In other words, switching many outputs at the same time will create ground and supply noise. The output drive strength control through the Current Control registers allows the user to mitigate SSN issues without the need of additional external components. ## **8.3 12 V tolerant I/Os** The PCAL9554B/PCAL9554C device SCR group reference diode can go up to 10 V before latch back to 8 V. The ESD gate oxide will protect the device, but not if used continually. Therefore, to achieve 12 V tolerant I/Os, the external protection circuitry (diode) must be used as shown in Figure 16. **==> picture [157 x 157] intentionally omitted <==** **----- Start of picture text -----**<br> +5 V +12 V<br>A0 VDD<br>A1 SDA<br>A2 SCL<br>P0 PCAL9554B INT<br>P1 PCAL9554C P7<br>P2 P6<br>P3 P5<br>VSS P4<br>002aah210<br>**----- End of picture text -----**<br> **Fig 16. External protection circuitry** © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **17 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **8.4 Power-on reset requirements** In the event of a glitch or data corruption, PCAL9554B/PCAL9554C can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. The two types of power-on reset are shown in Figure 17 and Figure 18. **==> picture [380 x 114] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>ramp-up ramp-down re-ramp-up<br>td(rst)<br>time<br>(dV/dt)r (dV/dt)f time to re-ramp (dV/dt)r<br>when VDD drops<br>below 0.2 V or to VSS 002aah329<br>Fig 17. VDD is lowered below 0.2 V or 0 V and then ramped up to VDD<br>**----- End of picture text -----**<br> **==> picture [360 x 114] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>ramp-down ramp-up<br>VI drops below POR levels td(rst)<br>time<br>time to re-ramp<br>(dV/dt)f (dV/dt)r<br>when VDD drops<br>to VPOR(min) − 50 mV 002aah330<br>Fig 18. VDD is lowered below the POR threshold, then ramped back up to VDD<br>**----- End of picture text -----**<br> Table 18 specifies the performance of the power-on reset feature for PCAL9554B/PCAL9554C for both types of power-on reset. © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **18 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** **Table 18. Recommended supply sequencing and ramp rates** _Tamb = 25_ _C (unless otherwise noted). Not tested; specified by design._ |**Symbol**<br>**Parameter**|**Condition**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**| |---|---| |(dV/dt)f<br>fall rate of change of voltage|Figure 17<br>0.1<br>-<br>2000<br>ms| |(dV/dt)r<br>rise rate of change of voltage|Figure 17<br>0.1<br>-<br>2000<br>ms| |td(rst)<br>reset delay time|Figure 17<br>; re-ramp time when<br>VDDdrops to VSS<br>1<br>-<br>-<br>s| ||Figure 18<br>; re-ramp time when<br>VDDdrops to VPOR(min)50 mV<br>1<br>-<br>-<br>s| |VDD(gl)<br>glitch supply voltage difference|Figure 19<br>[1]<br>-<br>-<br>1.0<br>V| |tw(gl)VDD<br>supply voltage glitch pulse width|Figure 19<br>[2]<br>-<br>-<br>10<br>s| |VPOR(trip)<br>power-on reset trip voltage|falling VDD<br>0.7<br>-<br>-<br>V| ||rising VDD<br>-<br>-<br>1.4<br>V| [1] Level that VDD can glitch down to with a ramp rate of 0.4 s/V, but not cause a functional disruption when tw(gl)VDD < 1 s. [2] Glitch width that will not cause a functional disruption when VDD(gl) = 0.5 VDD. Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (tw(gl)VDD) and glitch height (VDD(gl)) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 19 and Table 18 provide more information on how to measure these specifications. **==> picture [358 x 92] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>∆VDD(gl)<br>time<br>tw(gl)VDD 002aah331<br>Fig 19. Glitch width and glitch height<br>**----- End of picture text -----**<br> VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I[2] C-bus/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VDD being lowered to or from 0 V. Figure 20 and Table 18 provide more details on this specification. **==> picture [273 x 147] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>VPOR (rising VDD)<br>VPOR (falling VDD)<br>POR<br>Fig 20. Power-on reset voltage (VPOR)<br>**----- End of picture text -----**<br> **==> picture [33 x 73] intentionally omitted <==** **----- Start of picture text -----**<br> time<br>time<br>002aah332<br>**----- End of picture text -----**<br> All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** **Rev. 4 — 19 December 2014** **19 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **8.5 Device current consumption with internal pull-up and pull-down resistors** The PCAL9554B; PCAL9554C integrates programmable pull-up and pull-down resistors to eliminate external components when pins are configured as inputs and pull-up or pull-down resistors are required (for example, nothing is driving the inputs to the power supply rails. Since these pull-up and pull-down resistors are internal to the device itself, they contribute to the current consumption of the device and must be considered in the overall system design. The pull-up or pull-down function is selected in register 44h, while the resistor is connected by the enable register 43h. The configuration of the resistors is shown in Figure 6. If the resistor is configured as a pull-up, that is, connected to VDD, a current will flow from the VDD pin through the resistor to ground when the pin is held LOW. This current will appear as additional IDD upsetting any current consumption measurements. In the same manner, if the resistor is configured as a pull-down and the pin is held HIGH, current will flow from the power supply through the pin to the VSS pin. While this current will not be measured as part of IDD, one must be mindful of the 200 mA limiting value through VSS. The pull-up and pull-down resistors are simple resistors and the current is linear with voltage. The resistance specification for these devices spans from 50 k with a nominal 100 k value. Any current flow through these resistors is additive by the number of pins held HIGH or LOW and the current can be calculated by Ohm’s law. See Figure 24 for a graph of supply current versus the number of pull-up resistors. © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **20 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **9. Limiting values** ## **Table 19. Limiting values** _In accordance with the Absolute Maximum Rating System (IEC 60134)._ |**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Max**<br>**Unit**| |---|---| |VDD<br>supply voltage|0.5<br>+6.5<br>V| |VI<br>input voltage|[1]<br>0.5<br>+6.5<br>V| |VO<br>output voltage|[1]<br>0.5<br>+6.5<br>V| |IIK<br>input clamping current|A0, A1, A2, SCL; VI< 0 V<br>-<br>20<br>mA| |IOK<br>output clamping current|INT<br>; VO< 0 V<br>-<br>20<br>mA| |IIOK<br>input/output clamping current|P port; VO< 0 V or VO> VDD<br>-<br>20<br>mA| ||SDA; VO< 0 V or VO> VDD<br>-<br>20<br>mA| |IOL<br>LOW-level output current|continuous; I/O port<br>-<br>50<br>mA| ||continuous; SDA, INT<br>-<br>25<br>mA| |IOH<br>HIGH-level output current|continuous; P port<br>-<br>25<br>mA| |IDD<br>supply current|-<br>160<br>mA| |ISS<br>ground supply current|-<br>200<br>mA| |Ptot<br>total power dissipation|-<br>200<br>mW| |Tstg<br>storage temperature|65<br>+150<br>C| |Tj(max)<br>maximum junction temperature|-<br>125<br>C| [1] The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. ## **10. Recommended operating conditions** |**Table 20.**<br>**Operating conditions**|| |---|---| |**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Max**<br>**Unit**| |VDD<br>supply voltage|1.65<br>5.5<br>V| |VIH<br>HIGH-level input voltage|SCL, SDA<br>0.7VDD<br>5.5<br>V| ||A0, A1, A2, P port<br>0.7VDD<br>5.5<br>V| |VIL<br>LOW-level input voltage|SCL, SDA<br>0.5<br>0.3VDD<br>V| ||A0, A1, A2, P port<br>0.5<br>0.3VDD<br>V| |IOH<br>HIGH-level output current|P port<br>-<br>10<br>mA| |IOL<br>LOW-level output current|P port<br>-<br>25<br>mA| |Tamb<br>ambient temperature|operating in free air<br>40<br>+85<br>C| ## **11. Thermal characteristics** ## **Table 21. Thermal characteristics** |**Symbol**<br>**Parameter**|**Conditions**<br>**Max**<br>**Unit**| |---|---| |Zth(j-a)<br>transient thermal impedance from junction to ambient|HVQFN16 package<br>[1]<br>53<br>K/W| ||TSSOP16 package<br>[1]<br>108<br>K/W| [1] The package thermal impedance is calculated in accordance with JESD 51-7. © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **21 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **12. Static characteristics** ## **Table 22. Static characteristics** |**Table 22.**<br>**Static characteristics**|**Table 22.**<br>**Static characteristics**| |---|---| |_Tamb =__40__C to +85__C; VDD = 1.65 V to 5.5 V; unless otherwise specified._|| |**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Ty**~~**p**~~**[1]**<br>**Max**<br>**Unit**| |VIK<br>input clamping voltage|II=18 mA<br>1.2<br>-<br>-<br>V| |VPOR<br>power-on reset voltage|VI= VDDor VSS; IO= 0 mA<br>-<br>1.1<br>1.4<br>V| |VOH<br>HIGH-level output voltage[2]|P port; IOH=8 mA; CCX = 11b| ||VDD= 1.65 V<br>1.2<br>-<br>-<br>V| ||VDD= 2.3 V<br>1.8<br>-<br>-<br>V| ||VDD= 3 V<br>2.6<br>-<br>-<br>V| ||VDD= 4.5 V<br>4.1<br>-<br>-<br>V| ||P port; IOH=2.5 mA and CCX = 00b;<br>IOH=5 mA and CCX = 01b;<br>IOH=7.5 mA and CCX = 10b;<br>IOH=10 mA and CCX = 11b| ||VDD= 1.65 V<br>1.1<br>-<br>-<br>V| ||VDD= 2.3 V<br>1.7<br>-<br>-<br>V| ||VDD= 3 V<br>2.5<br>-<br>-<br>V| ||VDD= 4.5 V<br>4.0<br>-<br>-<br>V| |VOL<br>LOW-level output voltag~~e~~[2]|P port; IOL= 8 mA; CCX = 11b| ||VDD= 1.65 V<br>-<br>-<br>0.45<br>V| ||VDD= 2.3 V<br>-<br>-<br>0.25<br>V| ||VDD= 3 V<br>-<br>-<br>0.25<br>V| ||VDD= 4.5 V<br>-<br>-<br>0.2<br>V| ||P port; IOL= 2.5 mA and CCX = 00b;<br>IOL= 5 mA and CCX = 01b;<br>IOL= 7.5 mA and CCX = 10b;<br>IOL= 10 mA and CCX = 11b| ||VDD= 1.65 V<br>-<br>-<br>0.5<br>V| ||VDD= 2.3 V<br>-<br>-<br>0.3<br>V| ||VDD= 3 V<br>-<br>-<br>0.25<br>V| ||VDD= 4.5 V<br>-<br>-<br>0.2<br>V| |IOL<br>LOW-level output current|VOL= 0.4 V; VDD= 1.65 V to 5.5 V| ||SDA<br>3<br>-<br>-<br>mA| ||INT<br>3<br>1~~5~~[3]<br>-<br>mA| |II<br>input current|VDD= 1.65 V to 5.5 V| ||SCL, SDA; VI= VDDor VSS<br>-<br>-<br>0.1<br>A| ||A0, A1, A2; VI= VDDor VSS<br>-<br>-<br>1<br>A| |IIH<br>HIGH-level input current|P port; VI= VDD; VDD= 1.65 V to 5.5 V<br>-<br>-<br>1<br>A| |IIL<br>LOW-level input current|P port; VI= VSS; VDD= 1.65 V to 5.5 V<br>-<br>-<br>1<br>A| © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4 — 19 December 2014** **22 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** **Table 22. Static characteristics** _…continued_ _Tamb =_ _40_ _C to +85_ _C; VDD = 1.65 V to 5.5 V; unless otherwise specified._ |**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Ty**~~**p**~~**[1]**<br>**Max**<br>**Unit**| |---|---| |IDD<br>supply current|SDA, P port, A0, A1, A2;<br>VIon SCL, SDA = VDDor VSS;<br>VIon P port and A0, A1, A2 = VDD;<br>IO= 0 mA; I/O = inputs; fSCL= 400 kHz| ||VDD= 3.6 V to 5.5 V<br>-<br>10<br>25<br>A| ||VDD= 2.3 V to 3.6 V<br>-<br>6.5<br>15<br>A| ||VDD= 1.65 V to 2.3 V<br>-<br>4<br>9<br>A| ||SCL, SDA, P port, A0, A1, A2;<br>VIon SCL, SDA = VDDor VSS;<br>VIon P port and A0, A1, A2 = VDD;<br>IO= 0 mA; I/O = inputs; fSCL= 0 kHz| ||VDD= 3.6 V to 5.5 V<br>-<br>1.5<br>7<br>A| ||VDD= 2.3 V to 3.6 V<br>-<br>1<br>3.2<br>A| ||VDD= 1.65 V to 2.3 V<br>-<br>0.5<br>1.7<br>A| ||Active mode; P port, A0, A1, A2;<br>VIon P port and A0, A1, A2 = VDD;<br>IO= 0 mA; I/O = inputs;<br>fSCL= 400 kHz, continuous register read| ||VDD= 3.6 V to 5.5 V<br>-<br>60<br>125<br>A| ||VDD= 2.3 V to 3.6 V<br>-<br>40<br>75<br>A| ||VDD= 1.65 V to 2.3 V<br>-<br>20<br>45<br>A| ||with pull-ups enabled;<br>P port, A0, A1, A2;<br>VIon SCL, SDA = VDDor VSS;<br>VIon P port = VSS;<br>VIon A0, A1, A2 = VDDor VSS;<br>IO= 0 mA; I/O = inputs with pull-up enabled;<br>fSCL= 0 kHz| ||VDD= 1.65 V to 5.5 V<br>-<br>0.55<br>0.75<br>mA| |IDD<br>additional quiescent<br>supply current|SCL, SDA; one input at VDD0.6 V, other<br>inputs at VDDor VSS; VDD= 1.65 V to 5.5 V<br>-<br>-<br>25<br>A| ||P port, A0, A1; one input at VDD0.6 V,<br>other inputs at VDDor VSS;<br>VDD= 1.65 V to 5.5 V<br>-<br>-<br>80<br>A| |Ci<br>input capacitance|VI= VDDor VSS; VDD= 1.65 V to 5.5 V<br>-<br>6<br>7<br>pF| |Cio<br>input/output capacitance|SDA, SCL;<br>VI/O= VDDor VSS; VDD= 1.65 V to 5.5 V<br>-<br>7<br>8<br>pF| ||P port;<br>VI/O= VDDor VSS; VDD= 1.65 V to 5.5 V<br>-<br>7.5<br>8.5<br>pF| |Rpu(int)<br>internal pull-up resistance|input/output<br>50<br>100<br>150<br>k| |Rpd(int)<br>internal pull-down resistance|input/output<br>50<br>100<br>150<br>k| [1] For IDD, all typical values are at nominal supply voltage (1.8 V, 2.5 V, 3.3 V, 3.6 V or 5 V VDD) and Tamb = 25 C. Except for IDD, the typical values are at VDD = 3.3 V and Tamb = 25 C. [2] The total current sourced by all I/Os must be limited to 160 mA, and total current sunk by all I/Os must be limited to 200 mA. [3] Typical value for Tamb = 25 C. VOL = 0.4 V and VDD = 3.3 V. Typical value for VDD < 2.5 V, VOL = 0.6 V. © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **23 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **12.1 Typical characteristics** **==> picture [497 x 398] intentionally omitted <==** **----- Start of picture text -----**<br> 002aah333 002aah334<br>20 1400<br>(μA)IDD IDD(stb)<br>(nA)<br>16 VDD = 5.5 V<br>VDD = 5.5 V5.0 V 1000 5.0 V3.6 V<br>12 33.3 V.6 V 800 3.3 V<br>2.5 V<br>2.3 V<br>600<br>8<br>400<br>2.5 V<br>4 2.3 V<br>VDD = 1.8 V1.65 V 200 1.8 V1.65 V<br>0 0<br>−40 −15 10 35 60 85 −40 −15 10 35 60 85<br>Tamb (°C) Tamb (°C)<br>Fig 21. Supply current versus ambient temperature Fig 22. Standby supply current versus<br>ambient temperature<br>002aah335 002aah212<br>20 0.8<br>(μA)IDD IDD Tamb = −40 °C 25 °C<br>16 (mA) 85 °C<br>0.6<br>12<br>0.4<br>8<br>0.2<br>4<br>0 0<br>1.5 2.5 3.5 4.5 5.5 0 2 4 6 8<br>VDD (V) number of I/O held LOW<br>Tamb = 25 C<br>Fig 23. Supply current versus supply voltage Fig 24. Supply current versus number of I/O held LOW<br>**----- End of picture text -----**<br> © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **24 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** ## **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aaf578<br>35<br>Isink<br>(mA)<br>30<br>Tamb = −40 °C<br>25 25 ° C<br>85 °C<br>20<br>15<br>10<br>5<br>0<br>0 0.1 0.2 0.3<br>VOL (V)<br>**----- End of picture text -----**<br> ## a. VDD = 1.65 V **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aaf579<br>35<br>Isink<br>(mA)<br>30<br>Tamb = −40 °C<br>25 25 °C<br>85 °C<br>20<br>15<br>10<br>5<br>0<br>0 0.1 0.2 0.3<br>VOL (V)<br>**----- End of picture text -----**<br> ## b. VDD = 1.8 V **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aaf580<br>50<br>Isink<br>(mA)<br>40<br>Tamb = −40 °C<br>25 °C<br>30 85 °C<br>20<br>10<br>0<br>0 0.1 0.2 0.3<br>VOL (V)<br>**----- End of picture text -----**<br> **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aaf581<br>60<br>Isink Tamb = − 40 ° C<br>(mA) 25 °C<br>85 °C<br>40<br>20<br>0<br>0 0.1 0.2 0.3<br>VOL (V)<br>**----- End of picture text -----**<br> ## c. VDD = 2.5 V ## d. VDD = 3.3 V **==> picture [481 x 170] intentionally omitted <==** **----- Start of picture text -----**<br> 002aaf582 002aaf583<br>70 70<br>Isink Isink<br>(mA) 60 Tamb = −40 ° C (mA) 60 Tamb = −40 °C<br>25 °C 25 °C<br>50 85 ° C 50 85 ° C<br>40 40<br>30 30<br>20 20<br>10 10<br>0 0<br>0 0.1 0.2 0.3 0 0.1 0.2 0.3<br>VOL (V) VOL (V)<br>e. VDD = 5.0 V f. VDD = 5.5 V<br>**----- End of picture text -----**<br> **Fig 25. I/O sink current versus LOW-level output voltage with CCX.X = 11b** © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **25 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** ## **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aah110<br>30<br>Isource<br>(mA) Tamb = −40 °C<br>25 °C<br>20 85 °C<br>10<br>0<br>0 0.2 0.4 0.6<br>VDD − VOH (V)<br>**----- End of picture text -----**<br> ## a. VDD = 1.65 V **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aah111<br>35<br>Isource<br>(mA) 30 Tamb = −40 ° C<br>25 °C<br>25 85 ° C<br>20<br>15<br>10<br>5<br>0<br>0 0.2 0.4 0.6<br>VDD − VOH (V)<br>**----- End of picture text -----**<br> ## b. VDD = 1.8 V **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aah112<br>60<br>Isource<br>(mA)<br>Tamb = −40 °C<br>25 °C<br>40<br>85 °C<br>20<br>0<br>0 0.2 0.4 0.6<br>VDD − VOH (V)<br>**----- End of picture text -----**<br> **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aah113<br>70<br>Isource<br>(mA) 60 Tamb = −40 ° C<br>25 °C<br>50 85 ° C<br>40<br>30<br>20<br>10<br>0<br>0 0.2 0.4 0.6<br>VDD − VOH (V)<br>**----- End of picture text -----**<br> ## c. VDD = 2.5 V d. VDD = 3.3 V **==> picture [481 x 170] intentionally omitted <==** **----- Start of picture text -----**<br> 002aah114 002aah115<br>90 90<br>Isource(mA) T amb = −40 °C Isource(mA) T amb = −40 °C<br>25 °C 25 °C<br>85 °C 85 °C<br>60 60<br>30 30<br>0 0<br>0 0.2 0.4 0.6 0 0.2 0.4 0.6<br>VDD − VOH (V) VDD − VOH (V)<br>e. VDD = 5.0 V f. VDD = 5.5 V<br>**----- End of picture text -----**<br> **Fig 26. I/O source current versus HIGH-level output voltage with CCX.X = 11b** © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **26 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** **==> picture [481 x 169] intentionally omitted <==** **----- Start of picture text -----**<br> 002aah056 002aah343<br>120 200<br>(mV)VOL VDD − VOH (mV)<br>100<br>160<br>(1)<br>80<br>120 V DD = 1.8 V<br>5 V<br>60<br>(2) 80<br>40<br>(4) 40<br>20<br>(3)<br>0 0<br>−40 −15 10 35 60 85 −40 −15 10 35 60 85<br>Tamb (°C) Tamb (°C)<br>(1) VDD = 1.8 V; Isink = 10 mA Isource = 10 mA<br>**----- End of picture text -----**<br> - (2) VDD = 5 V; Isink = 10 mA - (3) VDD = 1.8 V; Isink = 1 mA - (4) VDD = 5 V; Isink = 1 mA **Fig 27. LOW-level output voltage versus temperature Fig 28. I/O high voltage versus temperature** © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **27 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **13. Dynamic characteristics** **Table 23. I[2] C-bus interface timing requirements** _Over recommended operating free air temperature range, unless otherwise specified. See Figure 29._ |**Symbol**<br>**Parameter**<br>**Conditions**|**Standard-m**<br>**I2C-bus**|**Standard-m**<br>**I2C-bus**|**ode**<br>||**Fast-mode**<br>**I2C-bus**|**Fast-mode**<br>**I2C-bus**|**Unit**| |---|---|---|---|---|---|---|---| ||**Min**|**M**|**ax**||**Min**|**Max**|| |fSCL<br>SCL clock frequency|0<br>100<br>0<br>400<br>kHz||||||| |tHIGH<br>HIGH period of the SCL clock|4<br>-<br>0.6<br>-<br>s||||||| |tLOW<br>LOW period of the SCL clock|4.7<br>-<br>1.3<br>-<br>s||||||| |tSP<br>pulse width of spikes that must<br>be suppressed by the input filter|0<br>50<br>0<br>50<br>ns||||||| |tSU;DAT<br>data set-up time|250<br>-<br>100<br>-<br>ns||||||| |tHD;DAT<br>data hold time|0<br>-<br>0<br>-<br>ns||||||| |tr<br>rise time of both SDA and SCL signals|-<br>1000<br>20<br>300<br>ns||||||| |tf<br>fall time of both SDA and SCL signals|-<br>300<br>20<br>(VDD/ 5.5 V)<br>300<br>ns||||||| |tBUF<br>bus free time between a STOP and<br>START condition|4.7<br>-<br>1.3<br>-<br>s||||||| |tSU;STA<br>set-up time for a repeated START<br>condition|4.7<br>-<br>0.6<br>-<br>s||||||| |tHD;STA<br>hold time (repeated) START condition|4<br>-<br>0.6<br>-<br>s||||||| |tSU;STO<br>set-up time for STOP condition|4<br>-<br>0.6<br>-<br>s||||||| |tVD;DAT<br>data valid time<br>SCL LOW to<br>SDA output valid|-<br>3.45<br>-<br>0.9<br>s||||||| |tVD;ACK<br>data valid acknowledge time<br>ACK signal<br>from SCL LOW<br>to SDA (out) LOW|-<br>3.45<br>-<br>0.9<br>s||||||| **Table 24. Switching characteristics** _Over recommended operating free air temperature range; CL_ _100 pF; unless otherwise specified. See Figure 29._ |**Symbol**<br>**Parameter**<br>**Conditions**|**Standard-mode**<br>**I2C-bus**|**Standard-mode**<br>**I2C-bus**|**Fast-mode**<br>**I2C-bus**|**Fast-mode**<br>**I2C-bus**|**Unit**| |---|---|---|---|---|---| ||**Min**|**Max**|**Min**|**Max**|| |tv(INT)<br>valid time on pin INT<br>from P port to INT|-<br>1<br>-<br>1<br>s||||| |trst(INT)<br>reset time on pin INT<br>from SCL to INT|-<br>1<br>-<br>1<br>s||||| |tv(Q)<br>data output valid time<br>from SCL to P port|-<br>400<br>-<br>400<br>ns||||| |tsu(D)<br>data input set-up time<br>from P port to SCL|0<br>-<br>0<br>-<br>ns||||| |th(D)<br>data input hold time<br>from P port to SCL|300<br>-<br>300<br>-<br>ns||||| © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4 — 19 December 2014** **28 of 42** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **PCAL9554B; PCAL9554C** ## **14. Parameter measurement information** **==> picture [425 x 332] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>RL = 1 kΩ<br>SDA<br>DUT<br>CL = 50 pF<br>002aag803<br>SDA load configuration<br>two bytes for read Input port register [(1)]<br>STOP START Address Address R/W ACK Data Data STOP<br>condition condition Bit 7 Bit 1 Bit 0 (A) Bit 7 Bit 0 condition<br>(P) (S) (MSB) (LSB) (MSB) (LSB) (P)<br>002aag952<br>Transaction format<br>tLOW tHIGH tSP<br>0.7 × VDD<br>SCL<br>0.3 × VDD<br>tBUF tr tf tVD;DATtf(o) tVD;ACK tSU;STA tSU;STO<br>0.7 × VDD<br>SDA<br>0.3 × VDD<br>tf tr tVD;ACK<br>tHD;STA tSU;DAT tHD;DAT<br>repeat START condition<br>STOP condition<br>002aag804<br>**----- End of picture text -----**<br> ## a. SDA load configuration ## b. Transaction format ## c. Voltage waveforms CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns. All parameters and waveforms are not applicable to all devices. Byte 1 = I[2] C-bus address; Byte 2, byte 3 = P port data. (1) See Figure 9. **Fig 29. I[2] C-bus interface load circuit and voltage waveforms** © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **29 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** ## **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** **==> picture [445 x 404] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>RL = 4.7 kΩ<br>INT<br>DUT<br>CL = 100 pF<br>002aah069<br>a. Interrupt load configuration<br>acknowledge acknowledge no acknowledge<br>from slave from slave from master<br>START condition R/W STOP<br>8 bits (one data byte) condition<br>slave address [(1)] from port data from port<br>SDA S 0 1 0 0 A2 A1 A0 1 A DATA 1 A DATA 2 1 P<br>SCL 1 2 3 4 5 6 7 8 9<br>B<br>trst(INT) trst(INT) B<br>INT<br>A<br>tv(INT) A tsu(D)<br>data into<br>ADDRESS DATA 1 DATA 2<br>port<br>0.7 × VDD<br>INT 0.5 × VDD SCL R/W A<br>0.3 × VDD<br>tv(INT) trst(INT)<br>Pn 0.5 × VDD INT 0.5 × VDD<br>View A - A View B - B<br>002aah130<br>**----- End of picture text -----**<br> ## b. Voltage waveforms ## CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns. All parameters and waveforms are not applicable to all devices. (1) PCAL9554B address shown. Address for PCAL9554C is 0111,A2,A1,A0. **Fig 30. Interrupt load circuit and voltage waveforms** © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **30 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** ## **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** **==> picture [265 x 360] intentionally omitted <==** **----- Start of picture text -----**<br> Pn 500 Ω<br>DUT 2 × VDD<br>CL = 50 pF 500 Ω<br>002aag805<br>0.7 × VDD<br>SCL P0 A P7<br>0.3 × VDD<br>SDA<br>tv(Q)<br>Pn<br>unstable last stable bit<br>data<br>002aag806<br>= 0)<br>0.7 × VDD<br>SCL P0 A P7<br>0.3 × VDD<br>tsu(D) th(D)<br>Pn<br>002aag807<br>**----- End of picture text -----**<br> ## a. P port load configuration ## b. Write mode (R/W = 0) ## c. Read mode (R/W = 1) CL includes probe and jig capacitance. tv(Q) is measured from 0.7 VDD on SCL to 50 % I/O (Pn) output. All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns. The outputs are measured one at a time, with one transition per measurement. All parameters and waveforms are not applicable to all devices. ## **Fig 31. P port load circuit and voltage waveforms** © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **31 of 42** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **PCAL9554B; PCAL9554C** ## **15. Package outline** **Fig 32. Package outline SOT403-1 (TSSOP16)** PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** © NXP Semiconductors N.V. 2014. All rights reserved. **32 of 42** **NXP Semiconductors** ## **PCAL9554B; PCAL9554C** ## **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** **==> picture [37 x 15] intentionally omitted <==** **----- Start of picture text -----**<br> UNIT A()<br>max.<br>**----- End of picture text -----**<br> **==> picture [199 x 10] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 33. Package outline SOT758-1 (HVQFN16)<br>**----- End of picture text -----**<br> PCAL9554B_PCAL9554C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. **Product data sheet** **Rev. 4 — 19 December 2014** **33 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **16. Handling information** All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in _JESD625-A_ or equivalent standards. ## **17. Soldering of SMD packages** This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note _AN10365 “Surface mount reflow soldering description”_ . ## **17.1 Introduction to soldering** Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. ## **17.2 Wave and reflow soldering** Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: - Through-hole components - Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: - Board specifications, including the board finish, solder masks and vias - Package footprints, including solder thieves and orientation - The moisture sensitivity level of the packages - Package placement - Inspection and repair - Lead-free soldering versus SnPb soldering ## **17.3 Wave soldering** Key characteristics in wave soldering are: All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. **Rev. 4 — 19 December 2014 34 of 42** PCAL9554B_PCAL9554C **Product data sheet** **34 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** - Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave - Solder bath specifications, including temperature and impurities ## **17.4 Reflow soldering** Key characteristics in reflow soldering are: - Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 34) than a SnPb process, thus reducing the process window - Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board - Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 25 and 26 ## **Table 25. SnPb eutectic process (from J-STD-020D)** |**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**| |---|---|---| ||**Volume (mm3)**|| ||**< 350**|**350**| |< 2.5|235|220| |2.5|220|220| ## **Table 26. Lead-free process (from J-STD-020D)** |**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**| |---|---|---|---| ||**Volume (mm3)**||| ||**< 350**|**350 to 2000**|**> 2000**| |< 1.6|260|260|260| |1.6 to 2.5|260|250|245| |> 2.5|250|245|245| Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 34. © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4 — 19 December 2014** **35 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** **==> picture [352 x 223] intentionally omitted <==** **----- Start of picture text -----**<br> maximum peak temperature<br>= MSL limit, damage level<br>temperature<br>minimum peak temperature<br>= minimum soldering temperature<br>peak<br> temperature<br>time<br>001aac844<br>MSL: Moisture Sensitivity Level<br>Fig 34. Temperature profiles for large and small components<br>**----- End of picture text -----**<br> For further information on temperature profiles, refer to Application Note _AN10365 “Surface mount reflow soldering description”_ . © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 4 — 19 December 2014** **36 of 42** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **PCAL9554B; PCAL9554C** ## **18. Soldering: PCB footprints** **Fig 35. PCB footprint for SOT403-1 (TSSOP16); reflow soldering** All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** **Rev. 4 — 19 December 2014** **37 of 42** **PCAL9554B; PCAL9554C Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **NXP Semiconductors** ## **Fig 36. PCB footprint for SOT758-1 (HVQFN16); reflow soldering** © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **38 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **19. Abbreviations** **Table 27. Abbreviations** |**Acronym**|**Description**| |---|---| |ACPI|Advanced Configuration and Power Interface| |CBT|Cross-Bar Technology| |CDM|Charged-Device Model| |CMOS|Complementary Metal-Oxide Semiconductor| |DUT|Device Under Test| |ESD|ElectroStatic Discharge| |FET|Field-Effect Transistor| |FF|Flip-Flop| |GPIO|General Purpose Input/Output| |HBM|Human Body Model| |I2C-bus|Inter-Integrated Circuit bus| |I/O|Input/Output| |LED|Light Emitting Diode| |LP|Low-Pass| |LSB|Least Significant Bit| |MSB|Most Significant Bit| |POR|Power-On Reset| |SCR|Silicon Controlled Rectifier| |SMBus|System Management Bus| ## **20. Revision history** ## **Table 28. Revision history** |**Document ID**|**Release date**|**Data sheet status**<br>**Change notice**|**Supersedes**| |---|---|---|---| |PCAL9554B_PCAL9554C v.4|20141219|Product data sheet<br>-|PCAL9554B_PCAL9554C v.3| |Modifications:|**•** Table 4“<br>Command byte<br>”<br>,register “Pull-up/pull-down enable”:||| ||**–**<br>Power-up default corrected from “0000 0000” to “1111 1111” (correction to||| ||documentation, no functional change to device).||| |PCAL9554B_PCAL9554C v.3|20130805|Product data sheet<br>-|PCAL9554B_PCAL9554C v.2| |PCAL9554B_PCAL9554C v.2|20121210|Product data sheet<br>-|PCAL9554B_PCAL9554C v.1| |PCAL9554B_PCAL9554C v.1|20121003|Product data sheet<br>-|-| © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **39 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **21. Legal information** ## **21.1 Data sheet status** |**Document status[1]**<br>**[2]**|**Product statu**~~**s**~~**[3]**|**Definition**| |---|---|---| |Objective [short] data sheet|Development|This document contains data from the objective specification for product development.| |Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.| |Product [short] data sheet|Production|This document contains the product specification.| [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. ## **21.2 Definitions** **Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. **Product specification —** The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. ## **21.3 Disclaimers** **Limited warranty and liability —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors. **Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. **Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. **Limiting values —** Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. **Terms and conditions of commercial sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. **No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. PCAL9554B_PCAL9554C All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. **Product data sheet Rev. 4 — 19 December 2014 40 of 42** **Rev. 4 — 19 December 2014** **40 of 42** ## **NXP Semiconductors** ## **PCAL9554B; PCAL9554C** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** **Export control —** This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. **Non-automotive qualified products —** Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. **Translations —** A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. ## **21.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. ## **22. Contact information** For more information, please visit: **http://www.nxp.com** For sales office addresses, please send an email to: **salesaddresses@nxp.com** © NXP Semiconductors N.V. 2014. All rights reserved. PCAL9554B_PCAL9554C **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 4 — 19 December 2014** **41 of 42** **PCAL9554B; PCAL9554C** **NXP Semiconductors** **Low-voltage 8-bit I[2] C-bus/SMBus low power I/O port** ## **23. Contents** |**1**|**General description . . . . . . . . . . . . . . . . . . . . . . 1**| |---|---| |**2**|**Features and benefits . . . . . . . . . . . . . . . . . . . . 2**| |2.1|Agile I/O features . . . . . . . . . . . . . . . . . . . . . . . 2| |**3**|**Ordering information. . . . . . . . . . . . . . . . . . . . . 3**| |3.1|Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3| |**4**|**Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3**| |**5**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . 4**| |5.1|Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4| |5.2|Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4| |**6**|**Functional description . . . . . . . . . . . . . . . . . . . 5**| |6.1|Device address. . . . . . . . . . . . . . . . . . . . . . . . . 5| |6.2|Pointer register and command byte . . . . . . . . . 5| |6.3|Interface definition . . . . . . . . . . . . . . . . . . . . . . 6| |6.4|Register descriptions . . . . . . . . . . . . . . . . . . . . 6| |6.4.1|Input port register (00h) . . . . . . . . . . . . . . . . . . 6| |6.4.2|Output port register (01h) . . . . . . . . . . . . . . . . . 6| |6.4.3|Polarity inversion register (02h) . . . . . . . . . . . . 7| |6.4.4|Configuration register (03h) . . . . . . . . . . . . . . . 7| |6.4.5|Output drive strength registers (40h, 41h) . . . . 7| |6.4.6|Input latch register (42h). . . . . . . . . . . . . . . . . . 8| |6.4.7|Pull-up/pull-down enable register (43h) . . . . . . 8| |6.4.8|Pull-up/pull-down selection register (44h). . . . . 9| |6.4.9|Interrupt mask register (45h) . . . . . . . . . . . . . . 9| |6.4.10|Interrupt status register (46h) . . . . . . . . . . . . . . 9| |6.4.11|Output port configuration register (4Fh) . . . . . . 9| |6.5|I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10| |6.6|Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 11| |6.7|Interrupt output (INT<br>) . . . . . . . . . . . . . . . . . . . 11| |**7**|**Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 12**| |7.1|Write commands. . . . . . . . . . . . . . . . . . . . . . . 12| |7.2|Read commands . . . . . . . . . . . . . . . . . . . . . . 13| |**8**|**Application design-in information . . . . . . . . . 15**| |8.1|Minimizing IDDwhen the I/Os are used to control| ||LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15| |8.2|Output drive strength control . . . . . . . . . . . . . 16| |8.3|12 V tolerant I/Os . . . . . . . . . . . . . . . . . . . . . . 17| |8.4|Power-on reset requirements . . . . . . . . . . . . . 18| |8.5|Device current consumption with internal pull-up| ||and pull-down resistors. . . . . . . . . . . . . . . . . . 20| |**9**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 21**| |**10**|**Recommended operating conditions. . . . . . . 21**| |**11**|**Thermal characteristics . . . . . . . . . . . . . . . . . 21**| |**12**|**Static characteristics. . . . . . . . . . . . . . . . . . . . 22**| |12.1|Typical characteristics . . . . . . . . . . . . . . . . . . 24| |**13**|**Dynamic characteristics . . . . . . . . . . . . . . . . . 28**| |**14**|**Parameter measurement information . . . . . . 29**| |---|---| |**15**|**Package outline. . . . . . . . . . . . . . . . . . . . . . . . 32**| |**16**|**Handling information . . . . . . . . . . . . . . . . . . . 34**| |**17**|**Soldering of SMD packages. . . . . . . . . . . . . . 34**| |17.1|Introduction to soldering. . . . . . . . . . . . . . . . . 34| |17.2|Wave and reflow soldering. . . . . . . . . . . . . . . 34| |17.3|Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 34| |17.4|Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 35| |**18**|**Soldering: PCB footprints . . . . . . . . . . . . . . . 37**| |**19**|**Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 39**| |**20**|**Revision history . . . . . . . . . . . . . . . . . . . . . . . 39**| |**21**|**Legal information . . . . . . . . . . . . . . . . . . . . . . 40**| |21.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . 40| |21.2|Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 40| |21.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 40| |21.4|Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 41| |**22**|**Contact information . . . . . . . . . . . . . . . . . . . . 41**| |**23**|**Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42**| Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. **© NXP Semiconductors N.V. 2014.** **All rights reserved.** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 19 December 2014 Document identifier: PCAL9554B_PCAL9554C**
Updated at February 9, 2023
NXP Semiconductors is a global leader in secure connectivity solutions, driving innovation across the automotive, industrial, IoT, mobile, and communications infrastructure markets. By developing advanced, purpose-built technologies, NXP enables devices to sense, think, connect, and act intelligently, delivering rigorously tested components that make the connected world safer and more efficient. Within the semiconductor space, NXP is highly regarded for its extensive range of high-performance integrated circuits and discrete devices. The brand's portfolio excels in drivers and interfaces, featuring a comprehensive selection of I/O expanders designed to streamline complex system architectures. For demanding high-frequency and wireless applications, NXP provides industry-leading RF FETs and RF/PIN diodes engineered to deliver exceptional signal integrity, efficiency, and reliability. The NXP product lineup further extends to essential discrete components, including versatile bipolar transistors, JFETs, and small signal diodes optimized for precision switching and amplification. Additionally, the portfolio supports advanced automation and smart applications with precision IC sensors, such as MEMS accelerometers, alongside specialized power management solutions like AC/DC LED driver ICs and single MOSFETs for cutting-edge electronics design.
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