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PCAL6416AEVJ
I/O Expander, 16bit, 400 kHz, I2C, 1.65 V, 5.5 V, VFBGA
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- Manufacturer: NXP
- Product type: I/O Expanders
- No. of Pins: 24Pins
- No. of I/O's: 16I/O's
- Bus Frequency: 400kHz
- IC Interface Type: I2C
- Chip Configuration: 16bit
- Supply Voltage Max: 5.5V
- Supply Voltage Min: 1.65V
- Interface Case Style: VFBGA
| Delivery and price | |
|---|---|
| Units per pack | 100 |
| Price | 1.02 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
**Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander with interrupt output, reset, and configuration registers Rev. 5 — 10 December 2013 Product data sheet** ## **PCAL6416A** ## **1. General description** The PCAL6416A is a 16-bit general-purpose I/O expander that provides remote I/O expansion for most microcontroller families via the I[2] C-bus interface. NXP I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections to a minimum, for example, in battery-powered mobile applications for interfacing to sensors, push buttons, keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage level to I/O devices operating at a different (usually higher) voltage level. The PCAL6416A has built-in level shifting feature that makes these devices extremely flexible in mixed signal environments where communication between incompatible I/O voltages is required. Its wide VDD range of 1.65 V to 5.5 V on the dual power rail allows seamless communications with next-generation low voltage microprocessors and microcontrollers on the interface side (SDA/SCL) and peripherals at a higher voltage on the port side. There are two supply voltages for PCAL6416A: VDD(I2C-bus) and VDD(P). VDD(I2C-bus) provides the supply voltage for the interface at the master side (for example, a microcontroller) and the VDD(P) provides the supply for core circuits and Port P. The bidirectional voltage level translation in the PCAL6416A is provided through VDD(I2C-bus). VDD(I2C-bus) should be connected to the VDD of the external SCL/SDA lines. This indicates the VDD level of the I[2] C-bus to the PCAL6416A, while the voltage level on Port P of the PCAL6416A is determined by the VDD(P). The PCAL6416A contains the PCA6416A register set of four pairs of 8-bit Configuration, Input, Output, and Polarity Inversion registers and additionally, the PCAL6416A has Agile I/O, which are additional features specifically designed to enhance the I/O. These additional features are: programmable output drive strength, latchable inputs, programmable pull-up/pull-down resistors, maskable interrupt, interrupt status register, programmable open-drain or push-pull outputs. The PCAL6416A is a pin-to-pin replacement to the PCA6416A, however, the PCAL6416A powers up with all I/O interrupts masked. This mask default allows for a board bring-up free of spurious interrupts at power-up. At power-on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register, saving external logic gates. Programmable pull-up and pull-down resistors eliminate the need for discrete components. **==> picture [172 x 101] intentionally omitted <==** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** The system master can reset the PCAL6416A in the event of a time-out or other improper operation by asserting a LOW in the RESET input. The power-on reset puts the registers in their default state and initializes the I[2] C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part. The PCAL6416A open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I[2] C-bus. Thus, the PCAL6416A can remain a simple slave device. The input latch feature holds or latches the input pin state and keeps the logic values that created the interrupt until the master can service the interrupt. This minimizes the host’s interrupt service response for fast moving inputs. The device Port P outputs have 25 mA sink capabilities for directly driving LEDs while consuming low device current. One hardware pin (ADDR) can be used to program and vary the fixed I[2] C-bus address and allow up to two devices to share the same I[2] C-bus or SMBus. ## **2. Features and benefits** - I[2] C-bus to parallel port expander - Operating power supply voltage range of 1.65 V to 5.5 V - Allows bidirectional voltage-level translation and GPIO expansion between: 1.8 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P - 2.5 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P - 3.3 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P - 5 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P - Low standby current consumption: - 1.5 A typical at 5 V VDD - 1.0 A typical at 3.3 V VDD - Schmitt trigger action allows slow input transition and better switching noise immunity at the SCL and SDA inputs - Vhys = 0.18 V (typical) at 1.8 V - Vhys = 0.25 V (typical) at 2.5 V - Vhys = 0.33 V (typical) at 3.3 V - Vhys = 0.5 V (typical) at 5 V - 5 V tolerant I/O ports - Active LOW reset input (RESET) - Open-drain active LOW interrupt output (INT) - 400 kHz Fast-mode I[2] C-bus - Internal power-on reset - Power-up with all channels configured as inputs - No glitch on power-up - Noise filter on SCL/SDA inputs © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **2 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** - Latched outputs with 25 mA drive maximum capability for directly driving LEDs - Latch-up performance exceeds 100 mA per JESD 78, Class II - ESD protection exceeds JESD 22 - 2000 V Human-Body Model (A114-A) - 1000 V Charged-Device Model (C101) - Packages offered: TSSOP24, HWQFN24, UFBGA24, VFBGA24, XFBGA24 ## **2.1 Agile I/O features** - Software backward compatible with PCA6416A with interrupts disabled at power-up - Pin-to-pin drop-in replacement with PCA6416A - Output port configuration: bank selectable push-pull or open-drain output stages - Interrupt status: read-only register identifies the source of an interrupt - Bit-wise I/O programming features: - Output drive strength: four programmable drive strengths to reduce rise and fall times in low-capacitance applications - Input latch: Input Port register values changes are kept until the Input Port register is read - Pull-up/pull-down enable: floating input or pull-up/pull-down resistor enable - Pull-up/pull-down selection: 100 k pull-up/pull-down resistor selection - Interrupt mask: mask prevents the generation of the interrupt when input changes state to prevent spurious interrupts ## **3. Ordering information** **Table 1. Ordering information** |**Type number**|**Topside**<br>**mark**|**Package**|**Package**|**Package**| |---|---|---|---|---| |||**Name**|**Description**|**Version**| |PCAL6416AEV<br>L16A||VFBGA24<br>plastic very thin fine-pitch ball grid array package; 24 balls;<br>body 330.85 mm<br>SOT1199-1||| |PCAL6416AEX<br>L16||XFBGA24<br>plastic, extremely thin fine-pitch ball grid array package;<br>24 balls; body 220.5 mm<br>SOT1342-1||| |PCAL6416AER<br>S6~~X~~[1]||UFBGA24<br>plastic, ultra thin fine-pitch ball grid array package; 24 balls;<br>body 220.65 mm<br>SOT1361-1||| |PCAL6416AHF<br>L16A||HWQFN24<br>plastic thermal enhanced very very thin quad flat package;<br>no leads; 24 terminals; body 440.75 mm<br>SOT994-1||| |PCAL6416APW<br>PCAL6416A||TSSOP24<br>plastic thin shrink small outline package; 24 leads;<br>body width 4.4 mm<br>SOT355-1||| - [1] ‘X’ rotates from 1 to 5 and indicates the work week of the indicated month. © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **Product data sheet** **3 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **3.1 Ordering options** **Table 2. Ordering options** |**Type number**|**Orderable**<br>**part number**<br>**Package**<br>**Packing method**<br>**Minimum**<br>**order**<br>**quantity**<br>**Temperature range**| |---|---| |PCAL6416AEV|PCAL6416AEVJ<br>VFBGA24<br>Reel 13” Q1/T1<br>*Standard mark SMD<br>6000<br>Tamb=40C to +85C| |PCAL6416AEX|PCAL6416AEXX<br>XFBGA24<br>Reel 7” Q1/T1<br>*Standard mark SMD<br>5000<br>Tamb=40C to +85C| |PCAL6416AER|PCAL6416AERJ<br>UFBGA24<br>Reel 13” Q1/T1<br>*Standard mark SMD<br>10000<br>Tamb=40C to +85C| ||PCAL6416AERX<br>UFBGA24<br>Reel 7” Q1/T1<br>*Standard mark SMD<br>3000<br>Tamb=40C to +85C| |PCAL6416AHF|PCAL6416AHF,128<br>HWQFN24<br>Reel 13” Q2/T3<br>*Standard mark SMD<br>6000<br>Tamb=40C to +85C| |PCAL6416APW|PCAL6416APW,118<br>TSSOP24<br>Reel 13” Q1/T1<br>*Standard mark SMD<br>2500<br>Tamb=40C to +85C| ## **4. Block diagram** **==> picture [380 x 239] intentionally omitted <==** **----- Start of picture text -----**<br> PCAL6416A<br>INTERRUPT<br>INT LP FILTER<br>LOGIC<br>ADDR<br>SCL INPUT I [2] C-BUS SHIFT I/O P0_0 to P0_7<br>FILTER CONTROL REGISTER 16 BITS PORT<br>SDA P1_0 to P1_7<br>VDD(I2C-bus) write pulse<br>VDD(P) POWER-ON read pulse<br>I/O control<br>RESET<br>RESET<br>VSS<br>002aaf962<br>All I/Os are set to inputs at reset.<br>Fig 1. Block diagram of PCAL6416A (positive logic)<br>**----- End of picture text -----**<br> © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **Product data sheet** **4 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **5. Pinning information** ## **5.1 Pinning** **==> picture [397 x 517] intentionally omitted <==** **----- Start of picture text -----**<br> INT 1 24 VDD(P)<br>terminal 1<br>VDD(I2C-bus) 2 23 SDA index area<br>RESET 3 22 SCL<br>P0_0 4 21 ADDR P0_0 1 18 ADDR<br>P0_1 5 20 P1_7 P0_1 2 17 P1_7<br>P0_2 6 19 P1_6 P0_2 3 16 P1_6<br>PCAL6416APW PCAL6416AHF<br>P0_3 7 18 P1_5 P0_3 4 15 P1_5<br>P0_4 8 17 P1_4 P0_4 5 14 P1_4<br>P0_5 9 16 P1_3 P0_5 6 13 P1_3<br>P0_6 10 15 P1_2<br>P0_7 11 14 P1_1<br>VSS 12 13 P1_0 002aaf964<br>002aaf963 Transparent top view<br>The exposed center pad, if used, must be<br>connected only as a secondary ground or<br>must be left electrically open.<br>Fig 2. Pin configuration for TSSOP24 Fig 3. Pin configuration for HWQFN24<br>ball A1 PCAL6416AEV<br>index area<br>1 2 3 4 5<br>A<br>B<br>1 2 3 4 5<br>C A P0_0 RESET INT SDA SCL<br>B P0_2 VDD(I2C-bus) VDD(P) ADDR<br>D<br>C P0_3 P0_4 P0_1 P1_7 P1_6<br>E<br>D P0_5 P0_7 P1_2 P1_4 P1_5<br>002aaf966 E P0_6 VSS P1_0 P1_1 P1_3<br>Transparent top view 002aag244<br>An empty cell indicates no ball<br>is populated at that grid point.<br>Fig 4. Pin configuration for VFBGA24 Fig 5. Ball mapping for 3 mm 3 mm<br>(3 mm 3 mm) VFBGA24 (transparent top view)<br>RESET VDD(I2C-bus) INT VDD(P) SDA SCL<br>24 23 22 21 20 19<br>7 8 9 10 11 12<br>SS<br>V<br>P0_6 P0_7 P1_0 P1_1 P1_2<br>**----- End of picture text -----**<br> © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **5 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** |XFBGA24 with 0.175 mm ball size.<br>**Fig 6.**<br>**Pin configuration for XFBGA24**<br>**(2 mm** **2 mm); EX option**<br>**PCAL6416AEX**<br>Transparent top view<br>E<br>D<br>C<br>B<br>A<br>2<br>4<br>1<br>3<br>5<br>ball A1<br>index area<br>_002aah190_|XFBGA24 with 0.175 mm ball size.<br>**Fig 6.**<br>**Pin configuration for XFBGA24**<br>**(2 mm** **2 mm); EX option**<br>**PCAL6416AEX**<br>Transparent top view<br>E<br>D<br>C<br>B<br>A<br>2<br>4<br>1<br>3<br>5<br>ball A1<br>index area<br>_002aah190_|UFBGA24 with 0.24 mm ball size.<br>**Fig 7.**<br>**Pin configuration for UFBGA24**<br>**(2 mm** **2 mm); ER option**<br>**PCAL6416AER**<br>Transparent top view<br>E<br>D<br>C<br>B<br>A<br>2<br>4<br>1<br>3<br>5<br>ball A1<br>index area<br>_aaa-009837_| |---|---|---| |A<br>B<br>C<br>D<br>E|P1_6<br>RESET<br>SDA<br>SCL<br>1<br>2<br>3<br>4<br>5<br>P0_0<br>VDD(I2C-bus)<br>VDD(P)<br>ADDR<br>P0_2<br>P0_3<br>P0_1<br>P1_7<br>P1_5<br>P0_4<br>P1_0<br>P1_4<br>P1_3<br>P0_5<br>VSS<br>P0_6<br>P1_1<br>P1_2<br>P0_7<br>_002aah145_<br>INT|| |An empty cell indicates no ball is populated at that grid point.<br>**Fig 8.**<br>**Ball mapping for 2 mm** **2 mm XFBGA24 and UFBGA24 (transparent top view)**||| An empty cell indicates no ball is populated at that grid point. **Fig 8. Ball mapping for 2 mm** **2 mm XFBGA24 and UFBGA24 (transparent top view)** © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 5 — 10 December 2013** **6 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **5.2 Pin description** **Table 3. Pin description** |**Symbol**|**Pin**|**Pin**|**Pin**|**Pin**|**Description**| |---|---|---|---|---|---| ||**TSSOP24**|**HWQFN24**|**VFBGA24**|**UFBGA24,**<br>**XFBGA24**|| |INT|1<br>22<br>A3<br>B3<br>Interrupt output. Connect to VDD(I2C-bus)or VDD(P)<br>through a pull-up resistor.||||| |VDD(I2C-bus)|2<br>23<br>B3<br>A2<br>Supply voltage of I2C-bus. Connect directly to the VDD<br>of the external I2C master. Provides voltage-level<br>translation.||||| |RESET|3<br>24<br>A2<br>A1<br>Active LOW reset input. Connect to VDD(I2C-bus)<br>through a pull-up resistor if no active connection is<br>used.||||| |P0_~~0~~[1]|4<br>1<br>A1<br>B1<br>Port 0 input/output 0.||||| |P0_~~1~~[1]|5<br>2<br>C3<br>C3<br>Port 0 input/output 1.||||| |P0_~~2~~[1]|6<br>3<br>B1<br>C1<br>Port 0 input/output 2.||||| |P0_~~3~~[1]|7<br>4<br>C1<br>C2<br>Port 0 input/output 3.||||| |P0_~~4~~[1]|8<br>5<br>C2<br>D1<br>Port 0 input/output 4.||||| |P0_~~5~~[1]|9<br>6<br>D1<br>E1<br>Port 0 input/output 5.||||| |P0_~~6~~[1]|10<br>7<br>E1<br>E2<br>Port 0 input/output 6.||||| |P0_~~7~~[1]|11<br>8<br>D2<br>D2<br>Port 0 input/output 7.||||| |VSS|12<br>9<br>E2<br>E3<br>Ground.||||| |P1_~~0~~[2]|13<br>10<br>E3<br>D3<br>Port 1 input/output 0.||||| |P1_~~1~~[2]|14<br>11<br>E4<br>E4<br>Port 1 input/output 1.||||| |P1_~~2~~[2]|15<br>12<br>D3<br>E5<br>Port 1 input/output 2.||||| |P1_~~3~~[2]|16<br>13<br>E5<br>D5<br>Port 1 input/output 3.||||| |P1_~~4~~[2]|17<br>14<br>D4<br>D4<br>Port 1 input/output 4.||||| |P1_~~5~~[2]|18<br>15<br>D5<br>C5<br>Port 1 input/output 5.||||| |P1_~~6~~[2]|19<br>16<br>C5<br>C4<br>Port 1 input/output 6.||||| |P1_~~7~~[2]|20<br>17<br>C4<br>B5<br>Port 1 input/output 7.||||| |ADDR|21<br>18<br>B5<br>A5<br>Address input. Connect directly to VDD(P)or ground.||||| |SCL|22<br>19<br>A5<br>A4<br>Serial clock bus. Connect to VDD(I2C-bus)through a<br>pull-up resistor.||||| |SDA|23<br>20<br>A4<br>B4<br>Serial data bus. Connect to VDD(I2C-bus)through a<br>pull-up resistor.||||| |VDD(P)|24<br>21<br>B4<br>A3<br>Supply voltage of PCAL6416A for Port P.||||| [1] Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-on, all I/O are configured as input. [2] Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-on, all I/O are configured as input. © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **7 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **6. Voltage translation** Table 4 shows how to set up VDD levels for the necessary voltage translation between the I[2] C-bus and the PCAL6416A. |**Table 4.**|**Voltage translation**|| |---|---|---| |**VDD(I2C-bus)**|**(SDA and SCL of I2C master)**|**VDD(P) (Port P)**| |1.8 V||1.8 V| |1.8 V||2.5 V| |1.8 V||3.3 V| |1.8 V||5 V| |2.5 V||1.8 V| |2.5 V||2.5 V| |2.5 V||3.3 V| |2.5 V||5 V| |3.3 V||1.8 V| |3.3 V||2.5 V| |3.3 V||3.3 V| |3.3 V||5 V| |5 V||1.8 V| |5 V||2.5 V| |5 V||3.3 V| |5 V||5 V| © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 5 — 10 December 2013** **8 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **7. Functional description** “ ” Refer to Figure 1 Block diagram of PCAL6416A (positive logic) . ## **7.1 Device address** The address of the PCAL6416A is shown in Figure 9. **==> picture [167 x 60] intentionally omitted <==** **----- Start of picture text -----**<br> slave address<br>AD<br>0 1 0 0 0 0 R/W<br>DR<br>fixed<br>hardware selectable<br>002aah045<br>**----- End of picture text -----**<br> **==> picture [125 x 10] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 9. PCAL6416A address<br>**----- End of picture text -----**<br> ADDR is the hardware address package pin and is held to either HIGH (logic 1) or LOW (logic 0) to assign one of the two possible slave addresses. The last bit of the slave address (R/W) defines the operation (read or write) to be performed. A HIGH (logic 1) selects a read operation, while a LOW (logic 0) selects a write operation. ## **7.2 Interface definition** ## **Table 5. Interface definition** |**Byte**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**| |---|---|---|---|---|---|---|---|---| ||**7 (MSB)**|**6**|**5**|**4**|**3**|**2**|**1**|**0 (LSB)**| |I2C-bus slave address|L<br>H<br>L<br>L<br>L<br>L<br>ADDR<br>R/W|||||||| |I/O data bus|P0.7<br>P0.6<br>P0.5<br>P0.4<br>P0.3<br>P0.2<br>P0.1<br>P0.0|||||||| ||P1.7<br>P1.6<br>P1.5<br>P1.4<br>P1.3<br>P1.2<br>P1.1<br>P1.0|||||||| ## **7.3 Pointer register and command byte** Following the successful acknowledgement of the address byte, the bus master sends a command byte, which is stored in the Pointer register in the PCAL6416A. The lower three bits of this data byte state the operation (read or write) and the internal registers (Input, Output, Polarity Inversion, or Configuration) that will be affected. Bit 6 in conjunction with the lower three bits of the Command byte are used to point to the extended features of the device (Agile IO). This register is write only. **==> picture [139 x 27] intentionally omitted <==** **----- Start of picture text -----**<br> B7 B6 B5 B4 B3 B2 B1 B0<br>002aaf540<br>**----- End of picture text -----**<br> **==> picture [121 x 10] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 10. Pointer register bits<br>**----- End of picture text -----**<br> © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 5 — 10 December 2013** **9 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **Table 6. Command byte** |**Pointer register bits**|**Pointer register bits**|**Pointer register bits**|**Pointer register bits**|**Pointer register bits**|**Pointer register bits**|**Pointer register bits**|**Pointer register bits**|**Command byte**<br>**(hexadecimal)**|**Register**|**Protocol**|**Power-up**<br>**default**| |---|---|---|---|---|---|---|---|---|---|---|---| |**B7**|**B6**|**B5**|**B4**|**B3**|**B2**|**B1**|**B0**||||| |0<br>0<br>0<br>0<br>0<br>0<br>0<br>0<br>00h<br>Input port 0<br>read byte<br>xxxx xxx~~x~~[1]|||||||||||| |0<br>0<br>0<br>0<br>0<br>0<br>0<br>1<br>01h<br>Input port 1<br>read byte<br>xxxx xxxx|||||||||||| |0<br>0<br>0<br>0<br>0<br>0<br>1<br>0<br>02h<br>Output port 0<br>read/write byte<br>1111 1111|||||||||||| |0<br>0<br>0<br>0<br>0<br>0<br>1<br>1<br>03h<br>Output port 1<br>read/write byte<br>1111 1111|||||||||||| |0<br>0<br>0<br>0<br>0<br>1<br>0<br>0<br>04h<br>Polarity Inversion port 0<br>read/write byte<br>0000 0000|||||||||||| |0<br>0<br>0<br>0<br>0<br>1<br>0<br>1<br>05h<br>Polarity Inversion port 1<br>read/write byte<br>0000 0000|||||||||||| |0<br>0<br>0<br>0<br>0<br>1<br>1<br>0<br>06h<br>Configuration port 0<br>read/write byte<br>1111 1111|||||||||||| |0<br>0<br>0<br>0<br>0<br>1<br>1<br>1<br>07h<br>Configuration port 1<br>read/write byte<br>1111 1111|||||||||||| |0<br>1<br>0<br>0<br>0<br>0<br>0<br>0<br>40h<br>Output drive strength<br>register 0<br>read/write byte<br>1111 1111|||||||||||| |0<br>1<br>0<br>0<br>0<br>0<br>0<br>1<br>41h<br>Output drive strength<br>register 0<br>read/write byte<br>1111 1111|||||||||||| |0<br>1<br>0<br>0<br>0<br>0<br>1<br>0<br>42h<br>Output drive strength<br>register 1<br>read/write byte<br>1111 1111|||||||||||| |0<br>1<br>0<br>0<br>0<br>0<br>1<br>1<br>43h<br>Output drive strength<br>register 1<br>read/write byte<br>1111 1111|||||||||||| |0<br>1<br>0<br>0<br>0<br>1<br>0<br>0<br>44h<br>Input latch register 0<br>read/write byte<br>0000 0000|||||||||||| |0<br>1<br>0<br>0<br>0<br>1<br>0<br>1<br>45h<br>Input latch register 1<br>read/write byte<br>0000 0000|||||||||||| |0<br>1<br>0<br>0<br>0<br>1<br>1<br>0<br>46h<br>Pull-up/pull-down enable<br>register 0<br>read/write byte<br>0000 0000|||||||||||| |0<br>1<br>0<br>0<br>0<br>1<br>1<br>1<br>47h<br>Pull-up/pull-down enable<br>register 1<br>read/write byte<br>0000 0000|||||||||||| |0<br>1<br>0<br>0<br>1<br>0<br>0<br>0<br>48h<br>Pull-up/pull-down<br>selection register 0<br>read/write byte<br>1111 1111|||||||||||| |0<br>1<br>0<br>0<br>1<br>0<br>0<br>1<br>49h<br>Pull-up/pull-down<br>selection register 1<br>read/write byte<br>1111 1111|||||||||||| |0<br>1<br>0<br>0<br>1<br>0<br>1<br>0<br>4Ah<br>Interrupt mask register 0<br>read/write byte<br>1111 1111|||||||||||| |0<br>1<br>0<br>0<br>1<br>0<br>1<br>1<br>4Bh<br>Interrupt mask register 1<br>read/write byte<br>1111 1111|||||||||||| |0<br>1<br>0<br>0<br>1<br>1<br>0<br>0<br>4Ch<br>Interrupt status register 0<br>read byte<br>0000 0000|||||||||||| |0<br>1<br>0<br>0<br>1<br>1<br>0<br>1<br>4Dh<br>Interrupt status register 1<br>read byte<br>0000 0000|||||||||||| |0<br>1<br>0<br>0<br>1<br>1<br>1<br>1<br>4Fh<br>Output port configuration<br>register<br>read/write byte<br>0000 0000|||||||||||| [1] Undefined. © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **10 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **7.4 Register descriptions** ## **7.4.1 Input port register pair (00h, 01h)** The Input port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. The Input port registers are read only; writes to these registers have no effect. The default value ‘X’ is determined by the externally applied logic level. An Input port register read operation is performed as described in Section 8.2. ## **Table 7. Input port 0 register (address 00h)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|I0.7|I0.6|I0.5|I0.4|I0.3|I0.2|I0.1|I0.0| |**Default**|X<br>X<br>X<br>X<br>X<br>X<br>X<br>X|||||||| |**Table 8.**<br>**Input port 1 register (address 01h)**||||||||| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||| |**Symbol**|I1.7|I1.6|I1.5|I1.4|I1.3|I1.2|I1.1|I1.0| |**Default**|X<br>X<br>X<br>X<br>X<br>X<br>X<br>X|||||||| ## **7.4.2 Output port register pair (02h, 03h)** The Output port registers (registers 2 and 3) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads from these registers reflect the value that was written to these registers, **not** the actual pin value. A register pair write operation is described in Section 8.1. A register pair read operation is described in Section 8.2. **Table 9. Output port 0 register (address 02h)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|O0.7|O0.6|O0.5|O0.4|O0.3|O0.2|O0.1|O0.0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||||||| |**Table 10.**<br>**Output port 1 register (address 03h)**||||||||| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||| |**Symbol**|O1.7|O1.6|O1.5|O1.4|O1.3|O1.2|O1.1|O1.0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||||||| © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **11 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **7.4.3 Polarity inversion register pair (04h, 05h)** The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined as inputs by the Configuration register. If a bit in these registers is set (written with ‘1’), the corresponding port pin’s polarity is inverted in the input register. If a bit in this register is cleared (written with a ‘0’), the corresponding port pin’s polarity is retained. A register pair write operation is described in Section 8.1. A register pair read operation is described in Section 8.2. **Table 11. Polarity inversion port 0 register (address 04h)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|N0.7|N0.6|N0.5|N0.4|N0.3|N0.2|N0.1|N0.0| |**Default**|0<br>0<br>0<br>0<br>0<br>0<br>0<br>0|||||||| |**Table 12.**<br>**Polarity inversion port 1 register (address 05h)**||||||||| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||| |**Symbol**|N1.7|N1.6|N1.5|N1.4|N1.3|N1.2|N1.1|N1.0| |**Default**|0<br>0<br>0<br>0<br>0<br>0<br>0<br>0|||||||| ## **7.4.4 Configuration register pair (06h, 07h)** The Configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a bit in these registers is set to 1, the corresponding port pin is enabled as a high-impedance input. If a bit in these registers is cleared to 0, the corresponding port pin is enabled as an output. A register pair write operation is described in Section 8.1. A register pair read operation is described in Section 8.2. ## **Table 13. Configuration port 0 register (address 06h)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|C0.7|C0.6|C0.5|C0.4|C0.3|C0.2|C0.1|C0.0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||||||| |**Table 14.**<br>**Configuration port 1 register (address 07h)**||||||||| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||| |**Symbol**|C1.7|C1.6|C1.5|C1.4|C1.3|C1.2|C1.1|C1.0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||||||| © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **Product data sheet** **12 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **7.4.5 Output drive strength register pairs (40h, 41h, 42h, 43h)** The Output drive strength registers control the output drive level of the GPIO. Each GPIO can be configured independently to a certain output current level by two register control bits. For example Port 0.7 is controlled by register 41 CC0.7 (bits [7:6]), Port 0.6 is controlled by register 41 CC0.6 (bits [5:4]). The output drive level of the GPIO is programmed 00b = 0.25, 01b = 0.5, 10b = 0.75 or 11b = 1 of the drive capability of the I/O. See Section 9.2 “Output drive strength control” for more details. A register pair write operation is described in Section 8.1. A register pair read operation is described in Section 8.2. |**Table 15.**<br>**Current control port 0 register (address 40h)**|**Table 15.**<br>**Current control port 0 register (address 40h)**|**Table 15.**<br>**Current control port 0 register (address 40h)**|**Table 15.**<br>**Current control port 0 register (address 40h)**|**Table 15.**<br>**Current control port 0 register (address 40h)**| |---|---|---|---|---| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||| |**Symbol**|CC0.3|CC0.2|CC0.1|CC0.0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||| |**Table 16.**<br>**Current control port 0 register (address 41h)**||||| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||| |**Symbol**|CC0.7|CC0.6|CC0.5|CC0.4| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||| |**Table 17.**<br>**Current control port 1 register (address 42h)**||||| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||| |**Symbol**|CC1.3|CC1.2|CC1.1|CC1.0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||| |**Table 18.**<br>**Current control port 1 register (address 43h)**||||| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||| |**Symbol**|CC1.7|CC1.6|CC1.5|CC1.4| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||| ## **7.4.6 Input latch register pair (44h, 45h)** The input latch registers (registers 44 and 45) enable and disable the input latch of the I/O pins. These registers are effective only when the pin is configured as an input port. When an input latch register bit is 0, the corresponding input pin state is not latched. A state change in the corresponding input pin generates an interrupt. A read of the input register clears the interrupt. If the input goes back to its initial logic state before the input port register is read, then the interrupt is cleared. When an input latch register bit is 1, the corresponding input pin state is latched. A change of state of the input generates an interrupt and the input logic value is loaded into the corresponding bit of the input port register (registers 0 and 1). A read of the input port register clears the interrupt. If the input pin returns to its initial logic state before the input port register is read, then the interrupt is not cleared and the corresponding bit of the input port register keeps the logic value that initiated the interrupt. See Figure 17. For example, if the P0_4 input was as logic 0 and the input goes to logic 1 then back to logic 0, the input port 0 register will capture this change and an interrupt is generated (if unmasked). When the read is performed on the input port 0 register, the interrupt is © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **13 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** cleared, assuming there were no additional input(s) that have changed, and bit 4 of the input port 0 register will read ‘1’. The next read of the input port register bit 4 register should now read ‘0’. An interrupt remains active when a non-latched input simultaneously switches state with a latched input and then returns to its original state. A read of the input register reflects only the change of state of the latched input and also clears the interrupt. The interrupt is not cleared if the input latch register changes from latched to non-latched configuration. If the input pin is changed from latched to non-latched input, a read from the input port register reflects the current port logic level. If the input pin is changed from non-latched to latched input, the read from the input register reflects the latched logic level. A register pair write operation is described in Section 8.1. A register pair read operation is described in Section 8.2. **Table 19. Input latch port 0 register (address 44h)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|L0.7|L0.6|L0.5|L0.4|L0.3|L0.2|L0.1|L0.0| |**Default**|0<br>0<br>0<br>0<br>0<br>0<br>0<br>0|||||||| |**Table 20.**<br>**Input latch port 1 register (address 45h)**||||||||| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||| |**Symbol**|L1.7|L1.6|L1.5|L1.4|L1.3|L1.2|L1.1|L1.0| |**Default**|0<br>0<br>0<br>0<br>0<br>0<br>0<br>0|||||||| ## **7.4.7 Pull-up/pull-down enable register pair (46h, 47h)** These registers allow the user to enable or disable pull-up/pull-down resistors on the I/O pins. Setting the bit to logic 1 enables the selection of pull-up/pull-down resistors. Setting the bit to logic 0 disconnects the pull-up/pull-down resistors from the I/O pins. Also, the resistors will be disconnected when the outputs are configured as open-drain outputs (see Section 7.4.11). Use the pull-up/pull-down registers to select either a pull-up or pull-down resistor. A register pair write operation is described in Section 8.1. A register pair read operation is described in Section 8.2. **Table 21. Pull-up/pull-down enable port 0 register (address 46h)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|PE0.7|PE0.6|PE0.5|PE0.4|PE0.3|PE0.2|PE0.1|PE0.0| |**Default**|0<br>0<br>0<br>0<br>0<br>0<br>0<br>0|||||||| |**Table 22.**<br>**Pull-up/pull-down enable port 1 register (address 47h)**||||||||| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||| |**Symbol**|PE1.7|PE1.6|PE1.5|PE1.4|PE1.3|PE1.2|PE1.1|PE1.0| |**Default**|0<br>0<br>0<br>0<br>0<br>0<br>0<br>0|||||||| © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **14 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **7.4.8 Pull-up/pull-down selection register pair (48h, 49h)** The I/O port can be configured to have pull-up or pull-down resistor by programming the pull-up/pull-down selection register. Setting a bit to logic 1 selects a 100 k pull-up resistor for that I/O pin. Setting a bit to logic 0 selects a 100 k pull-down resistor for that I/O pin. If the pull-up/down feature is disconnected, writing to this register will have no effect on I/O pin. Typical value is 100 k with minimum of 50 k and maximum of 150 k. A register pair write operation is described in Section 8.1. A register pair read operation is described in Section 8.2. ## **Table 23. Pull-up/pull-down selection port 0 register (address 48h)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|PUD0.7|PUD0.6|PUD0.5|PUD0.4|PUD0.3|PUD0.2|PUD0.1|PUD0.0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||||||| |**Table 24.**<br>**Pull-up/pull-down selection port 1 register (address 49h)**||||||||| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||| |**Symbol**|PUD1.7|PUD1.6|PUD1.5|PUD1.4|PUD1.3|PUD1.2|PUD1.1|PUD1.0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||||||| ## **7.4.9 Interrupt mask register pair (4Ah, 4Bh)** Interrupt mask registers are set to logic 1 upon power-on, disabling interrupts during system start-up. Interrupts may be enabled by setting corresponding mask bits to logic 0. If an input changes state and the corresponding bit in the Interrupt mask register is set to 1, the interrupt is masked and the interrupt pin will not be asserted. If the corresponding bit in the Interrupt mask register is set to 0, the interrupt pin will be asserted. When an input changes state and the resulting interrupt is masked (interrupt mask bit is 1), setting the input mask register bit to 0 will cause the interrupt pin to be asserted. If the interrupt mask bit of an input that is currently the source of an interrupt is set to 1, the interrupt pin will be de-asserted. A register pair write operation is described in Section 8.1. A register pair read operation is described in Section 8.2. **Table 25. Interrupt mask port 0 register (address 4Ah) bit description** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|M0.7|M0.6|M0.5|M0.4|M0.3|M0.2|M0.1|M0.0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||||||| |**Table 26.**<br>**Interrupt mask port 1 register (address 4Bh) bit description**||||||||| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||| |**Symbol**|M1.7|M1.6|M1.5|M1.4|M1.3|M1.2|M1.1|M1.0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||||||| © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 5 — 10 December 2013** **15 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **7.4.10 Interrupt status register pair (4Ch, 4Dh)** These read-only registers are used to identify the source of an interrupt. When read, a logic 1 indicates that the corresponding input pin was the source of the interrupt. A logic 0 indicates that the input pin is not the source of an interrupt. When a corresponding bit in the interrupt mask register is set to 1 (masked), the interrupt status bit will return logic 0. A register pair write operation is described in Section 8.1. A register pair read operation is described in Section 8.2. **Table 27. Interrupt status port 0 register (address 4Ch) bit description** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|S0.7|S0.6|S0.5|S0.4|S0.3|S0.2|S0.1|S0.0| |**Default**|0<br>0<br>0<br>0<br>0<br>0<br>0<br>0|||||||| |**Table 28.**<br>**Interrupt status port 1 register (address 4Dh) bit description**||||||||| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||| |**Symbol**|S1.7|S1.6|S1.5|S1.4|S1.3|S1.2|S1.1|S1.0| |**Default**|0<br>0<br>0<br>0<br>0<br>0<br>0<br>0|||||||| ## **7.4.11 Output port configuration register (4Fh)** The output port configuration register selects port-wise push-pull or open-drain I/O stage. A logic 0 configures the I/O as push-pull (Q1 and Q2 are active, see Figure 11). A logic 1 configures the I/O as open-drain (Q1 is disabled, Q2 is active) and the recommended command sequence is to program this register (4Fh) before the configuration register (06h and 07h) sets the port pins as outputs. ODEN0 configures Port 0_x and ODEN1 configures Port 1_x. **Table 29. Output port configuration register (address 4Fh)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---| |**Symbol**|reserved|ODEN1|ODEN0| |**Default**|0<br>0<br>0<br>0<br>0<br>0<br>0<br>0||| ## **7.5 I/O port** When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above VDD(P) to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output port register. In this case, there are low-impedance paths between the I/O pin and either VDD(P) or VSS. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation. © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **Product data sheet** **16 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** **==> picture [379 x 352] intentionally omitted <==** **----- Start of picture text -----**<br> data from output port<br>shift register configuration register data<br>register VDD(P)<br>data from D Q Q1 ESD<br>shift register<br>FF protection<br>write diode<br>configuration CK Q D Q<br>P0_0 to P0_7<br>pulse<br>FF Q2 ESD P1_0 to P1_7<br>write pulse CK protection<br>diode<br>output port VSS<br>register<br>D Q<br>input port<br>FF register data<br>read pulse CK<br>VDD(P) INTERRUPT<br>input port MASK to INT<br>register<br>PULL-UP/PULL-DOWN 100 kΩ<br>CONTROL<br>D Q<br>input latch<br>register LATCH<br>data from<br>D Q EN<br>shift register read pulse<br>FF input port<br>write input latch<br>latch pulse CK polarity inversion<br>register<br>data from D Q<br>shift register<br>FF<br>write polarity<br>CK<br>pulse 002aag971<br>On power-up or reset, all registers return to default values.<br>**----- End of picture text -----**<br> **Fig 11. Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)** ## **7.6 Power-on reset** When power (from 0 V) is applied to VDD(P), an internal power-on reset holds the PCAL6416A in a reset condition until VDD(P) has reached VPOR. At that time, the reset condition is released and the PCAL6416A registers and I[2] C-bus/SMBus state machine initializes to their default states. After that, VDD(P) must be lowered to below VPOR and back up to the operating voltage for a power-reset cycle. See Section 9.3 “Power-on reset ” requirements . ## **7.7 Reset input (RESET)** The RESET input can be asserted to initialize the system while keeping the VDD(P) at its operating level. A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The PCAL6416A registers and I[2] C-bus/SMBus state machine are changed to their default state once RESET is LOW (0). When RESET is HIGH (1), the I/O levels at the P port can be changed externally or through the master. This input requires a pull-up resistor to VDD(I2C-bus) if no active connection is used. © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **17 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **7.8 Interrupt output (INT)** An interrupt is generated by any rising or falling edge of the port inputs in the Input mode. After time tv(INT), the signal INT is valid. The interrupt is reset when data on the port changes back to the original value or when data is read from the port that generated the interrupt (see Figure 17). Resetting occurs in the Read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Any change of the I/Os after resetting is detected and is transmitted as INT. A pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the Input Port register. The INT output has an open-drain structure and requires pull-up resistor to VDD(P) or VDD(I2C-bus), depending on the application. INT should be connected to the voltage source of the device that requires the interrupt information. When using the input latch feature, the input pin state is latched. The interrupt is reset only when data is read from the port that generated the interrupt. The reset occurs in the Read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. ## **8. Bus transactions** The PCAL6416A is an I[2] C-bus slave device. Data is exchanged between the master and PCAL6416A through write and read commands using I[2] C-bus. The two communication lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. ## **8.1 Write commands** Data is transmitted to the PCAL6416A by sending the device address and setting the Least Significant Bit (LSB) to a logic 0 (see Figure 9 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. Twenty-two registers within the PCAL6416A are configured to operate as eleven register pairs. The eleven pairs are input port, output port, polarity inversion, configuration, output drive strength (two 16-bit registers), input latch, pull-up/pull-down enable, pull-up/pull-down selection, interrupt mask, and interrupt status registers. After sending data to one register, the next data byte is sent to the other register in the pair (see Figure 12 and Figure 13). For example, if the first byte is sent to Output Port 1 (register 3), the next byte is stored in Output Port 0 (register 2). There is no limit on the number of data bytes sent in one write transmission. In this way, the host can continuously update a register pair independently of the other registers. © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 5 — 10 December 2013** **18 of 61** ## **==> picture [538 x 159] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>STOP<br>condition<br>slave address command byte data to port 0 data to port 1<br>AD<br>SDA S 0 1 0 0 0 0 0 A 0 0 0 0 0 0 1 0 A 0.7 DATA 0 0.0 A 1.7 DATA 1 1.0 A P<br>DR<br>START condition R/W acknowledge acknowledge acknowledge acknowledge<br>from slave from slave from slave from slave<br>write to port<br>tv(Q)<br>data out from port 0 DATA 0 VALID<br>tv(Q)<br>data out from port 1 DATA 1 VALID<br>002aaf556<br>**----- End of picture text -----**<br> ## **Fig 12. Write to Output port register** **==> picture [129 x 6] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>**----- End of picture text -----**<br> **==> picture [526 x 99] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>STOP<br>condition<br>slave address command byte data to register data to register<br>AD<br>SDA S 0 1 0 0 0 0 0 A 0 1/0 0 0 1/0 1/0 1/0 1/0 A DATA 0 A DATA 1 A P<br>DR<br>MSB LSB MSB LSB<br>START condition R/W acknowledge acknowledge acknowledge acknowledge<br>from slave from slave from slave from slave<br>002aag972<br>**----- End of picture text -----**<br> **Fig 13. Write to device registers** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **8.2 Read commands** To read data from the PCAL6416A, the bus master must first send the PCAL6416A address with the least significant bit set to a logic 0 (see Figure 9 for device address). The command byte is sent after the address and determines which register is to be accessed. After a restart, the device address is sent again, but this time the least significant bit is set to a logic 1. Data from the register defined by the command byte is sent by the PCAL6416A (see Figure 14 and Figure 17). Data is clocked into the register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but the data now reflects the information in the other register in the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0.There is no limit on the number of data bytes received in one read transmission, but on the final byte received the bus master must not acknowledge the data. After a subsequent restart, the command byte contains the value of the next register to be read in the pair. For example, if Input Port 1 was read last before the restart, the register that is read after the restart is the Input Port 0. **==> picture [437 x 167] intentionally omitted <==** **----- Start of picture text -----**<br> slave address command byte<br>SDA S 0 1 0 0 0 0 AD 0 A 0 1/0 0 0 1/0 1/0 1/0 1/0 A (cont.)<br>DR<br>START condition R/W acknowledge<br>from slave<br>acknowledge<br>from slave<br>data from lower or data from upper or<br>upper byte of register lower byte of register<br>slave address<br>MSB LSB MSB LSB<br>(cont.) S 0 1 0 0 0 0 DRAD 1 A DATA (first byte) A DATA (last byte) NA P<br>(repeated) R/W acknowledge no acknowledge STOP<br>START condition from master from master condition<br>acknowledge<br>from slave<br>at this moment master-transmitter becomes master-receiver<br>and slave-receiver becomes slave-transmitter<br>002aah046<br>**----- End of picture text -----**<br> **Fig 14. Read from device registers** © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 5 — 10 December 2013** **20 of 61** **==> picture [618 x 228] intentionally omitted <==** **----- Start of picture text -----**<br> data into port 0<br>data into port 1<br>INT<br>tv(INT) trst(INT)<br>SCL 1 2 3 4 5 6 7 8 9<br>R/W STOP condition<br>slave address I0.x I1.x I0.x I1.x<br>AD<br>SDA S 0 1 0 0 0 0 1 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 1 P<br>DR<br>START condition acknowledge acknowledge acknowledge acknowledge non acknowledge<br>from slave from master from master from master from master<br>read from port 0<br>read from port 1<br>002aah143<br>**----- End of picture text -----**<br> **Remark:** Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to ‘00’ (read input port register). This figure eliminates the command byte transfers and a restart between the initial slave address call and actual data transfer from P port (see Figure 14). **Fig 15. Read input port register (non-latched), scenario 1** ## **==> picture [618 x 220] intentionally omitted <==** **----- Start of picture text -----**<br> data into port 0 DATA 00 DATA 01 DATA 02 DATA 03<br>th(D) tsu(D)<br>data into port 1 DATA 10 DATA 11 DATA 12<br>th(D) tsu(D)<br>INT<br>tv(INT) trst(INT)<br>SCL 1 2 3 4 5 6 7 8 9<br>R/W STOP condition<br>slave address I0.x I1.x I0.x I1.x<br>AD<br>SDA S 0 1 0 0 0 0 1 A DATA 00 A DATA 10 A DATA 03 A DATA 12 1 P<br>DR<br>START condition acknowledge acknowledge acknowledge acknowledge non acknowledge<br>from slave from master from master from master from master<br>read from port 0<br>read from port 1<br>002aah144<br>**----- End of picture text -----**<br> **Remark:** Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to ‘00’ (read input port register). This figure eliminates the command byte transfers and a restart between the initial slave address call and actual data transfer from P port (see Figure 14). **Fig 16. Read input port register (non-latched), scenario 2** ## **==> picture [618 x 220] intentionally omitted <==** **----- Start of picture text -----**<br> data into port 0 DATA 01 DATA 02 DATA 01<br>tsu(D)<br>data into port 1 DATA 10 DATA 11 DATA 10<br>th(D)<br>INT<br>tv(INT) trst(INT)<br>SCL 1 2 3 4 5 6 7 8 9<br>R/W STOP condition<br>slave address I0.x I1.x I0.x I1.x<br>AD<br>SDA S 0 1 0 0 0 0 1 A DATA 01 A DATA 10 A DATA 02 A DATA 11 1 P<br>DR<br>START condition acknowledge acknowledge acknowledge acknowledge non acknowledge<br>from slave from master from master from master from master<br>read from port 0<br>read from port 1<br>002aah054<br>**----- End of picture text -----**<br> **Remark:** Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to ‘00’ (read input port register). This figure eliminates the command byte transfers and a restart between the initial slave address call and actual data transfer from P port (see Figure 14). **Fig 17. Read input port register (latch enabled), scenario 3** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **9. Application design-in information** **==> picture [457 x 291] intentionally omitted <==** **----- Start of picture text -----**<br> VDD(I2C-bus) VDD(P)<br>10 kΩ (×7)<br>VDD(I2C-bus) = 1.8 V ALARM [(1) ]<br>SUBSYSTEM 1<br>10 kΩ 10 kΩ 10 kΩ 10 kΩ (e.g., alarm system)<br>VDD VDD(I2C-bus) VDD(P) A<br>MASTER<br>CONTROLLER P0_0 enable controlled<br>SCL SCL P0_1 switch<br>SDA SDA PCAL6416A<br>INT INT B<br>RESET RESET<br>P0_2<br>P0_3<br>GND<br>P0_4<br>P0_5<br>P0_6<br>P0_7<br>P1_0 KEYPAD<br>P1_1<br>P1_2<br>P1_3<br>ADDR<br>P1_4<br>P1_5<br>P1_6<br>GND P1_7<br>002aaf965<br>**----- End of picture text -----**<br> Device address configured as 0100 000x for this example. P0_0 and P0_2 through P1_0 are configured as inputs. P0_1 and P1_1 through P1_7 are configured as outputs. - (1) External resistors are required for inputs (on P port) that may float. Also, internal pull-up or pull-down may be used to eliminate the need for external components. If a driver to an input will never let the input float, a resistor is not needed. If an output in the P port is configured as a push-pull output there is no need for external pull-up resistors. If an output in the P port is configured as an open-drain output, external pull-up resistors are required. **Fig 18. Typical application** ## **9.1 Minimizing IDD when the I/Os are used to control LEDs** When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 18. Since the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less than VDD(P). The supply current, IDD(P), increases as VI becomes lower than V . DD(P) Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 19 shows a high value resistor in parallel with the LED. Figure 20 shows VDD(P) less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VDD(P) and prevents additional supply current consumption when the LED is off. © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **24 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** **==> picture [397 x 166] intentionally omitted <==** **----- Start of picture text -----**<br> 3.3 V 5 V<br>VDD<br>VDD(P) LED 100 kΩ VDD(P) LED<br>Pn Pn<br>002aah278 002aah279<br>Fig 19. High value resistor in parallel with Fig 20. Device supplied by a lower voltage<br>the LED<br>**----- End of picture text -----**<br> ## **9.2 Output drive strength control** The Output drive strength registers allow the user to control the output drive level of the GPIO. Each GPIO can be configured independently to one of the four possible output current levels. By programming these bits the user is changing the number of transistor pairs or ‘fingers’ that drive the I/O pad. Figure 21 shows a simplified output stage. The behavior of the pad is affected by the Configuration register, the output port data, and the current control register. When the Current Control register bits are programmed to 10b, then only two of the fingers are active, reducing the current drive capability by 50 %. **==> picture [465 x 297] intentionally omitted <==** **----- Start of picture text -----**<br> PMOS_EN0<br>VDD(P)<br>PMOS_EN1<br>Current Control PMOS_EN[3:0]<br>DECODER<br>register<br>NMOS_EN[3:0]<br>PMOS_EN2<br>Configuration<br>register<br>PMOS_EN3<br>P0_0 to P0_7<br>P1_0 to P1_7<br>Output port<br>register<br>NMOS_EN3<br>NMOS_EN2<br>NMOS_EN1<br>NMOS_EN0 002aah053<br>Fig 21. Simplified output stage<br>**----- End of picture text -----**<br> All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** **Rev. 5 — 10 December 2013** **25 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** Reducing the current drive capability may be desirable to reduce system noise. When the output switches (transitions from H/L), there is a peak current that is a function of the output drive selection. This peak current runs through VDD and VSS package inductance and will create noise (some radiated, but more critically Simultaneous Switching Noise (SSN)). In other words, switching many outputs at the same time will create ground and supply noise. The output drive strength control through the Output Drive Strength registers allows the user to mitigate SSN issues without the need of additional external components. ## **9.3 Power-on reset requirements** In the event of a glitch or data corruption, PCAL6416A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. The two types of power-on reset are shown in Figure 22 and Figure 23. **==> picture [381 x 117] intentionally omitted <==** **----- Start of picture text -----**<br> VDD(P)<br>ramp-up ramp-down re-ramp-up<br>td(rst)<br>time<br>(dV/dt)r (dV/dt)f time to re-ramp (dV/dt)r<br>when VDD(P) drops<br>below 0.2 V or to VSS 002aag960<br>Fig 22. VDD(P) is lowered below 0.2 V or to 0 V and then ramped up to VDD(P)<br>**----- End of picture text -----**<br> **==> picture [336 x 92] intentionally omitted <==** **----- Start of picture text -----**<br> VDD(P)<br>ramp-down ramp-up<br>VI drops below POR levels td(rst)<br>time<br>time to re-ramp<br>(dV/dt)f (dV/dt)r<br>when VDD(P) drops<br>to VPOR(min) − 50 mV 002aag961<br>**----- End of picture text -----**<br> **==> picture [351 x 11] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 23. VDD(P) is lowered below the POR threshold, then ramped back up to VDD(P)<br>**----- End of picture text -----**<br> Table 30 specifies the performance of the power-on reset feature for PCAL6416A for both types of power-on reset. © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 5 — 10 December 2013** **26 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** **Table 30. Recommended supply sequencing and ramp rates** _Tamb = 25_ _C (unless otherwise noted). Not tested; specified by design._ |**Symbol**<br>**Parameter**|**Condition**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**| |---|---| |(dV/dt)f<br>fall rate of change of voltage|Figure 22<br>0.1<br>-<br>2000<br>ms| |(dV/dt)r<br>rise rate of change of voltage|Figure 22<br>0.1<br>-<br>2000<br>ms| |td(rst)<br>reset delay time|Figure 22<br>;re-ramp time when<br>VDD(P)drops below 0.2 V or to VSS)<br>1<br>-<br>-<br>s| ||Figure 23<br>;re-ramp time when VDD(P)<br>drops to VPOR(min)50 mV)<br>1<br>-<br>-<br>s| |VDD(gl)<br>glitch supply voltage difference|Figure 24<br>[1]<br>-<br>-<br>1.0<br>V| |tw(gl)VDD<br>supply voltage glitch pulse width|Figure 24<br>[2]<br>-<br>-<br>10<br>s| |VPOR(trip)<br>power-on reset trip voltage|falling VDD(P)<br>0.7<br>-<br>-<br>V| ||rising VDD(P)<br>-<br>-<br>1.4<br>V| [1] Level that VDD(P) can glitch down to with a ramp rate = 0.4 s/V, but not cause a functional disruption when tw(gl)VDD < 1 s. [2] Glitch width that will not cause a functional disruption when VDD(gl) = 0.5 VDD(P). Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (tw(gl)VDD) and glitch height (VDD(gl)) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 24 and Table 30 provide more information on how to measure these specifications. **==> picture [360 x 92] intentionally omitted <==** **----- Start of picture text -----**<br> VDD(P)<br>∆VDD(gl)<br>time<br>tw(gl)VDD 002aag962<br>Fig 24. Glitch width and glitch height<br>**----- End of picture text -----**<br> VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I[2] C-bus/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VDD(P) being lowered to or from 0 V. Figure 25 and Table 30 provide more details on this specification. **==> picture [281 x 147] intentionally omitted <==** **----- Start of picture text -----**<br> VDD(P)<br>VPOR (rising VDD(P))<br>VPOR (falling VDD(P))<br>POR<br>Fig 25. Power-on reset voltage (VPOR)<br>**----- End of picture text -----**<br> **==> picture [32 x 74] intentionally omitted <==** **----- Start of picture text -----**<br> time<br>time<br>002aag963<br>**----- End of picture text -----**<br> All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** **Rev. 5 — 10 December 2013** **27 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **9.4 Device current consumption with internal pull-up and pull-down resistors** The PCAL6416A integrates programmable pull-up and pull-down resistors to eliminate external components when pins are configured as inputs and pull-up or pull-down resistors are required (for example, nothing is driving the inputs to the power supply rails. Since these pull-up and pull-down resistors are internal to the device itself, they contribute to the current consumption of the device and must be considered in the overall system design. The pull-up or pull-down function is selected in registers 48h and 49h, while the resistor is connected by the enable registers 46h and 47h. The configuration of the resistors is shown in Figure 11. If the resistor is configured as a pull-up, that is, connected to VDD, a current will flow from the VDD(P) pin through the resistor to ground when the pin is held LOW. This current will appear as additional IDD upsetting any current consumption measurements. In the same manner, if the resistor is configured as a pull-down and the pin is held HIGH, current will flow from the power supply through the pin to the VSS pin. While this current will not be measured as part of IDD, one must be mindful of the 200 mA limiting value through VSS. The pull-up and pull-down resistors are simple resistors and the current is linear with voltage. The resistance specification for these devices spans from 50 k with a nominal 100 k value. Any current flow through these resistors is additive by the number of pins held HIGH or LOW and the current can be calculated by Ohm’s law. See Figure 29 for a graph of supply current versus the number of pull-up resistors. ## **9.5 I[2] C-bus error recovery techniques** There are a number of techniques to recover from error conditions on the I[2] C-bus. Slave devices like the PCAL6416A use a state machine to implement the I[2] C protocol and expect a certain sequence of events to occur to function properly. Unexpected events at the I[2] C master can wreak havoc with the slaves connected on the bus. However, it is usually possible to recover deterministically to a known bus state with careful protocol manipulation. A hard slave reset, either through power-on reset or by activating the RESET pin, will set the device back into the default state. Of course, this means the input/output pins and their configuration will be lost, which might cause some system issues. A STOP condition, which is only initiated by the master, will reset the slave state machine into a known condition where SDA is not driven LOW by the slave and logically, the slave is waiting for a START condition. A STOP condition is defined as SDA transitioning from LOW to HIGH while SCL is HIGH. If the master is interrupted during a packet transmission, the slave may be sending data or performing an Acknowledge, driving the I[2] C-bus SDA line LOW. Since SDA is LOW, it effectively blocks any other I[2] C-bus transaction. A deterministic method to clear this situation, once the master recognizes a ‘stuck bus’ state, is for the master to blindly transmit nine clocks on SCL. If the slave was transmitting data or acknowledging, nine or © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **28 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** more clocks ensures the slave state machine returns to a known, idle state since the protocol calls for eight data bits and one ACK bit. It does not matter when the slave state machine finishes its transmission, extra clocks will be recognized as STOP conditions. The PCAL6416A SCL pin is an input only. If SCL is stuck LOW, then only the bus master or a slave performing a clock stretch operation can cause this condition. With careful design of the bus master error recovery firmware, many I[2] C-bus protocol problems can be avoided. ## **10. Limiting values** **Table 31. Limiting values** _In accordance with the Absolute Maximum Rating System (IEC 60134)._ |**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Max**<br>**Unit**|**Conditions**<br>**Min**<br>**Max**<br>**Unit**| |---|---|---| |VDD(I2C-bus)<br>I2C-bus supply voltage||0.5<br>+6.5<br>V| |VDD(P)<br>supply voltage port P||0.5<br>+6.5<br>V| |VI<br>input voltage||[1]<br>0.5<br>+6.5<br>V| |VO<br>output voltage||[1]<br>0.5<br>+6.5<br>V| |IIK<br>input clamping current|ADDR,|RESET<br>, SCL; VI< 0 V<br>-<br>20<br>mA| |IOK<br>output clamping current|INT<br>; VO< 0 V<br>-<br>20<br>mA|| |IIOK<br>input/output clamping current|P port; VO< 0 V or VO> VDD(P)<br>-<br>20<br>mA|| ||SDA; VO< 0 V or VO> VDD(I2C-bus)<br>-<br>20<br>mA|| |IOL<br>LOW-level output current|continuous; P port; VO= 0 V to VDD(P)<br>-<br>50<br>mA|| ||continuous; SDA, INT<br>;<br>VO= 0 V to VDD(I2C-bus)<br>-<br>25<br>mA|| |IOH<br>HIGH-level output current|continuous; P port; VO= 0 V to VDD(P)<br>-<br>25<br>mA|| |IDD<br>supply current|continuous through VSS<br>-<br>200<br>mA|| |IDD(P)<br>supply current port P|continuous through VDD(P)<br>-<br>160<br>mA|| |IDD(I2C-bus)<br>I2C-bus supply current|continuous through VDD(I2C-bus)<br>-<br>10<br>mA|| |Tstg<br>storage temperature|65<br>+150<br>C|| |Tj(max)<br>maximum junction temperature|-<br>125<br>C|| [1] The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **Product data sheet** **29 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **11. Recommended operating conditions** ## **Table 32. Operating conditions** |**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Max**<br>**Unit**|**Conditions**<br>**Min**<br>**Max**<br>**Unit**| |---|---|---| |VDD(I2C-bus)<br>I2C-bus supply voltage||1.65<br>5.5<br>V| |VDD(P)<br>supply voltage port P||1.65<br>5.5<br>V| |VIH<br>HIGH-level input voltage|SCL, SDA,|RESET<br>0.7VDD(I2C-bus)<br>5.5<br>V| ||ADDR, P1_7 to P0_0<br>0.7VDD(P)<br>5.5<br>V|| |VIL<br>LOW-level input voltage|SCL, SDA,|RESET<br>0.5<br>0.3VDD(I2C-bus)<br>V| ||ADDR, P1_7 to P0_0<br>0.5<br>0.3VDD(P)<br>V|| |IOH<br>HIGH-level output current|P1_7 to P0_0<br>-<br>10<br>mA|| |IOL<br>LOW-level output current|P1_7 to P0_0<br>-<br>25<br>mA|| |Tamb<br>ambient temperature|operating in free air<br>40<br>+85<br>C|| ## **12. Thermal characteristics** **Table 33. Thermal characteristics** |**Symbol**<br>**Parameter**|**Conditions**<br>**Max**<br>**Unit**| |---|---| |Zth(j-a)<br>transient thermal impedance<br>from junction to ambient|TSSOP24 package<br>[1]<br>88<br>K/W| ||HWQFN24 package<br>[1]<br>66<br>K/W| ||VFBGA24 package<br>[1]<br>171<br>K/W| [1] The package thermal impedance is calculated in accordance with JESD 51-7. © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 5 — 10 December 2013** **30 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **13. Static characteristics** **Table 34. Static characteristics** _Tamb =_ _40_ _C to +85_ _C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified._ |**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Ty**~~**p**~~**[1]**<br>**Max**<br>**Unit**|**Conditions**<br>**Min**<br>**Ty**~~**p**~~**[1]**<br>**Max**<br>**Unit**| |---|---|---| |VIK<br>input clamping voltage|II=18 mA<br>1.2<br>-<br>-<br>V|| |VPOR<br>power-on reset voltage|VI= VDD(P)or VSS; IO= 0 mA<br>-<br>1.1<br>1.4<br>V|| |VOH<br>HIGH-level output<br>voltage[2]|P port; IOH=8 mA; CCX.X = 11b|| ||VDD(P)= 1.65 V<br>1.2<br>-<br>-<br>V|| ||VDD(P)= 2.3 V<br>1.8<br>-<br>-<br>V|| ||VDD(P)= 3 V<br>2.6<br>-<br>-<br>V|| ||VDD(P)= 4.5 V<br>4.1<br>-<br>-<br>V|| ||P port; IOH=2.5 mA and CCX.X = 00b;<br>IOH=5 mA and CCX.X = 01b;<br>IOH=7.5 mA and CCX.X = 10b;<br>IOH=10 mA and CCX.X = 11b;|| ||VDD(P)= 1.65 V<br>1.1<br>-<br>-<br>V|| ||VDD(P)= 2.3 V<br>1.7<br>-<br>-<br>V|| ||VDD(P)= 3 V<br>2.5<br>-<br>-<br>V|| ||VDD(P)= 4.5 V<br>4.0<br>-<br>-<br>V|| |VOL<br>LOW-level<br>output voltag~~e~~[2]|P port; IOL= 8 mA; CCX.X = 11b|| ||VDD(P)= 1.65 V<br>-<br>-<br>0.45<br>V|| ||VDD(P)= 2.3 V<br>-<br>-<br>0.25<br>V|| ||VDD(P)= 3 V<br>-<br>-<br>0.25<br>V|| ||VDD(P)= 4.5 V<br>-<br>-<br>0.2<br>V|| ||P port; IOL= 2.5 mA and CCX.X = 00b;<br>IOL= 5 mA and CCX.X = 01b;<br>IOL= 7.5 mA and CCX.X = 10b;<br>IOL= 10 mA and CCX.X = 11b;|| ||VDD(P)= 1.65 V<br>-<br>-<br>0.5<br>V|| ||VDD(P)= 2.3 V<br>-<br>-<br>0.3<br>V|| ||VDD(P)= 3 V<br>-<br>-<br>0.25<br>V|| ||VDD(P)= 4.5 V<br>-<br>-<br>0.2<br>V|| |IOL<br>LOW-level<br>output current[3]|VOL= 0.4 V; VDD(P)= 1.65 V to 5.5 V|| ||SDA|3<br>-<br>-<br>mA| ||INT|3<br>1~~5~~[4]<br>-<br>mA| |II<br>input current|VDD(P)= 1.65|V to 5.5 V| ||SCL, SDA,|RESET<br>; VI= VDD(I2C-bus)or VSS<br>-<br>-<br>1<br>A| ||ADDR; VI=|VDD(P)or VSS<br>-<br>-<br>1<br>A| |IIH<br>HIGH-level input current|P port; VI= VDD(P); VDD(P)= 1.65 V to 5.5 V<br>-<br>-<br>1<br>A|| |IIL<br>LOW-level input current|P port; VI= VSS; VDD(P)= 1.65 V to 5.5 V<br>-<br>-<br>1<br>A|| © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 5 — 10 December 2013** **31 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** **Table 34. Static characteristics** _…continued_ _Tamb =_ _40_ _C to +85_ _C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified._ |**Symbol**<br>**Parameter**|**Conditions**|**Conditions**|**Min**<br>**Ty**~~**p**~~**[1]**<br>**Max**<br>**Unit**|**Min**<br>**Ty**~~**p**~~**[1]**<br>**Max**<br>**Unit**| |---|---|---|---|---| |IDD<br>supply current|IDD(I2C-bus)+ IDD(P);<br>SDA, P port, ADDR,RESET<br>;<br>VIon SDA and RESET<br>= VDD(I2C-bus)or VSS;<br>VIon P port and ADDR = VDD(P);<br>IO= 0 mA; I/O = inputs; fSCL= 400 kHz|||| ||VDD(P)= 3.6 V to 5.5 V<br>-<br>10<br>25<br>A|||| ||VDD(P)= 2.3 V to 3.6 V<br>-<br>6.5<br>15<br>A|||| ||VDD(P)= 1.65 V to 2.3 V<br>-<br>4<br>9<br>A|||| ||IDD(I2C-bus)+ IDD(P);<br>SCL, SDA, P port, ADDR,RESET<br>;<br>VIon SCL, SDA and RESET<br>= VDD(I2C-bus)or VSS;<br>VIon P port and ADDR = VDD(P);<br>IO= 0 mA; I/O = inputs; fSCL= 0 kHz|||| ||VDD(P)= 3.6 V to 5.5 V<br>-<br>1.5<br>7<br>A|||| ||VDD(P)= 2.3 V to 3.6 V<br>-<br>1<br>3.2<br>A|||| ||VDD(P)= 1.65 V to 2.3 V<br>-<br>0.5<br>1.7<br>A|||| ||Active mode; IDD(I2C-bus)+ IDD(P);<br>P port,ADDR, RESET<br>;<br>VIon RESET<br>= VDD(I2C-bus);<br>VIon P port and ADDR = VDD(P);<br>IO= 0 mA; I/O = inputs;<br>fSCL= 400 kHz, continuous register read|||| ||VDD(P)= 3.6 V to 5.5 V|||-<br>60<br>125<br>A| ||VDD(P)= 2.3 V to 3.6 V|||-<br>40<br>75<br>A| ||VDD(P)= 1.65 V to 2.3 V|||-<br>20<br>45<br>A| ||with pull-ups enabled (PCAL6416A only);<br>IDD(I2C-bus)+ IDD(P); Pport,ADDR, RESET<br>;<br>VIon SCL, SDA and RESET<br>= VDD(I2C-bus)or VSS;<br>VIon P port = VSS;<br>VIon ADDR = VDD(I2C-bus)or VSS;<br>IO= 0 mA; I/O = inputs with pull-up enabled;<br>fSCL= 0 kHz|||| ||VDD(P)=|1.65 V to 5.5 V<br>-<br>1.1<br>1.5<br>mA||| |IDD<br>additional quiescent<br>supply curren~~t~~[5]|SCL, SDA, RESET<br>;<br>one input at VDD(I2C-bus)0.6 V,<br>other inputs at VDD(I2C-bus)or VSS;<br>VDD(P)= 1.65 V to 5.5 V<br>-<br>-<br>25<br>A|||| ||P port, ADDR; one input at VDD(P)0.6 V,<br>other inputs at VDD(P)or VSS;<br>VDD(P)= 1.65 V to 5.5 V<br>-<br>-<br>80<br>A|||| |Ci<br>input capacitance|VI= VDD(I2C-bus)or VSS; VDD(P)= 1.65 V to 5.5 V<br>-<br>6<br>7<br>pF|||| |Cio<br>input/output capacitance|VI/O= VDD(I2C-bus)or VSS; VDD(P)= 1.65 V to 5.5 V<br>-<br>7<br>8<br>pF|||| ||VI/O= VDD(P)or VSS; VDD(P)= 1.65 V to 5.5 V<br>-<br>7.5<br>8.5<br>pF|||| |Rpu(int)<br>internal pull-up<br>resistance|input/output<br>50<br>100<br>150<br>k|||| |Rpd(int)<br>internal pull-down<br>resistance|input/output<br>50<br>100<br>150<br>k|||| PCAL6416A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. **Product data sheet** **Rev. 5 — 10 December 2013** **32 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** - [1] For IDD, all typical values are at nominal supply voltage (1.8 V, 2.5 V, 3.3 V, 3.6 V or 5 V VDD) and Tamb = 25 C. Except for IDD, the typical values are at VDD(P) = VDD(I2C-bus) = 3.3 V and Tamb = 25 C. - [2] The total current sourced by all I/Os must be limited to 160 mA. - [3] Each I/O must be externally limited to a maximum of 25 mA and each octal (P0_0 to P0_7 and P1_0 to P1_7) must be limited to a maximum current of 100 mA, for a device total of 200 mA. - [4] Typical value for Tamb = 25 C. VOL = 0.4 V and VDD(I2C-bus) = VDD(P) = 3.3 V. Typical value for VDD(I2C-bus) = VDD(P) < 2.5 V, VOL = 0.6 V. - [5] Internal pull-up/pull-down resistors disabled. ## **13.1 Typical characteristics** **==> picture [497 x 426] intentionally omitted <==** **----- Start of picture text -----**<br> 20 002aag973 1400 002aag974<br>(μA)IDD IDD(stb)<br>(nA)<br>16 VDD(P) = 5.5 V<br>VDD(P) = 5.5 V5.0 V 1000 5.0 V3.6 V<br>12 33.3 V.6 V 800 3.3 V<br>2.5 V<br>2.3 V<br>600<br>8<br>400<br>2.5 V<br>4 2.3 V<br>VDD(P) = 1.8 V1.65 V 200 1.8 V1.65 V<br>0 0<br>−40 −15 10 35 60 85 −40 −15 10 35 60 85<br>Tamb (°C) Tamb (°C)<br>IDD = IDD(I2C-bus) + IDD(P)<br>Fig 26. Supply current versus ambient temperature Fig 27. Standby supply current versus<br>ambient temperature<br>20 002aag975 1.2 002aah201<br>IDD Tamb = −40 °C<br>(μA) IDD(P) 25 °C<br>16 (mA) 85 °C<br>0.8<br>12<br>8<br>0.4<br>4<br>0 0<br>1.5 2.5 3.5 4.5 5.5 0 4 8 12 16<br>VDD(P) (V) number of I/O held LOW<br>Tamb = 25 C<br>IDD = IDD(I2C-bus) + IDD(P)<br>Fig 28. Supply current versus supply voltage Fig 29. Supply current versus number of I/O held LOW<br>**----- End of picture text -----**<br> © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **Product data sheet** **33 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aaf578<br>35<br>Isink<br>(mA)<br>30<br>Tamb = −40 °C<br>25 25 ° C<br>85 °C<br>20<br>15<br>10<br>5<br>0<br>0 0.1 0.2 0.3<br>VOL (V)<br>**----- End of picture text -----**<br> ## a. VDD(P) = 1.65 V **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aaf579<br>35<br>Isink<br>(mA)<br>30<br>Tamb = −40 °C<br>25 25 °C<br>85 °C<br>20<br>15<br>10<br>5<br>0<br>0 0.1 0.2 0.3<br>VOL (V)<br>**----- End of picture text -----**<br> ## b. VDD(P) = 1.8 V **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aaf580<br>50<br>Isink<br>(mA)<br>40<br>Tamb = −40 °C<br>25 °C<br>30 85 °C<br>20<br>10<br>0<br>0 0.1 0.2 0.3<br>VOL (V)<br>**----- End of picture text -----**<br> **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aaf581<br>60<br>Isink Tamb = − 40 ° C<br>(mA) 25 °C<br>85 °C<br>40<br>20<br>0<br>0 0.1 0.2 0.3<br>VOL (V)<br>**----- End of picture text -----**<br> ## c. VDD(P) = 2.5 V d. VDD(P) = 3.3 V **==> picture [481 x 171] intentionally omitted <==** **----- Start of picture text -----**<br> 002aaf582 002aaf583<br>70 70<br>Isink Isink<br>(mA) 60 Tamb = −40 ° C (mA) 60 Tamb = −40 °C<br>25 °C 25 °C<br>50 85 ° C 50 85 ° C<br>40 40<br>30 30<br>20 20<br>10 10<br>0 0<br>0 0.1 0.2 0.3 0 0.1 0.2 0.3<br>VOL (V) VOL (V)<br>e. VDD(P) = 5.0 V f. VDD(P) = 5.5 V<br>**----- End of picture text -----**<br> **Fig 30. I/O sink current versus LOW-level output voltage with CCX.X = 11b** © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **34 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aaf561<br>30<br>Isource<br>(mA) Tamb = −40 °C<br>25 °C<br>20 85 °C<br>10<br>0<br>0 0.2 0.4 0.6<br>VDD(P) − VOH (V)<br>**----- End of picture text -----**<br> ## a. VDD(P) = 1.65 V **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aaf562<br>35<br>Isource<br>(mA) 30 Tamb = −40 ° C<br>25 °C<br>25 85 ° C<br>20<br>15<br>10<br>5<br>0<br>0 0.2 0.4 0.6<br>VDD(P) − VOH (V)<br>**----- End of picture text -----**<br> ## b. VDD(P) = 1.8 V **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aaf563<br>60<br>Isource<br>(mA)<br>Tamb = −40 °C<br>25 °C<br>40<br>85 °C<br>20<br>0<br>0 0.2 0.4 0.6<br>VDD(P) − VOH (V)<br>**----- End of picture text -----**<br> **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aaf564<br>70<br>Isource<br>(mA) 60 Tamb = −40 ° C<br>25 °C<br>50 85 ° C<br>40<br>30<br>20<br>10<br>0<br>0 0.2 0.4 0.6<br>VDD(P) − VOH (V)<br>**----- End of picture text -----**<br> c. VDD(P) = 2.5 V d. VDD(P) = 3.3 V **==> picture [481 x 171] intentionally omitted <==** **----- Start of picture text -----**<br> 002aaf565 002aaf566<br>90 90<br>Isource(mA) T amb = −40 °C Isource(mA) T amb = −40 °C<br>25 °C 25 °C<br>85 °C 85 °C<br>60 60<br>30 30<br>0 0<br>0 0.2 0.4 0.6 0 0.2 0.4 0.6<br>VDD(P) − VOH (V) VDD(P) − VOH (V)<br>e. VDD(P) = 5.0 V f. VDD(P) = 5.5 V<br>**----- End of picture text -----**<br> **Fig 31. I/O source current versus HIGH-level output voltage with CCX.X = 11b** © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 5 — 10 December 2013** **35 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** **==> picture [497 x 252] intentionally omitted <==** **----- Start of picture text -----**<br> 002aah056 002aah057<br>120 200<br>(mV)VOL VDD(P) − VOH (mV)<br>100<br>160<br>(1)<br>80<br>120 V DD(P) = 1.8 V<br>5 V<br>60<br>(2) 80<br>40<br>(4) 40<br>20<br>(3)<br>0 0<br>−40 −15 10 35 60 85 −40 −15 10 35 60 85<br>Tamb (°C) Tamb (°C)<br>(1) VDD(P) = 1.8 V; Isink = 10 mA Isource = 10 mA<br>(2) VDD(P) = 5 V; Isink = 10 mA<br>(3) VDD(P) = 1.8 V; Isink = 1 mA<br>(4) VDD(P) = 5 V; Isink = 1 mA<br>Fig 32. LOW-level output voltage versus temperature Fig 33. I/O high voltage versus temperature with<br>with CCX.X = 11b CCX.X = 11b<br>**----- End of picture text -----**<br> © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 5 — 10 December 2013** **36 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **14. Dynamic characteristics** ## **Table 35. I[2] C-bus interface timing requirements** _Over recommended operating free air temperature range, unless otherwise specified. See Figure 35._ |**Symbol**<br>**Parameter**<br>**Conditions**|**Standard-mode**<br>**I2C-bus**|**Standard-mode**<br>**I2C-bus**|**Fast-mode**<br>**I2C-bus**|**Fast-mode**<br>**I2C-bus**|**Unit**| |---|---|---|---|---|---| ||**Min**|**Max**|**Min**|**Max**|| |fSCL<br>SCL clock frequency|0<br>100<br>0<br>400<br>kHz||||| |tHIGH<br>HIGH period of the SCL clock|4<br>-<br>0.6<br>-<br>s||||| |tLOW<br>LOW period of the SCL clock|4.7<br>-<br>1.3<br>-<br>s||||| |tSP<br>pulse width of spikes that must<br>be suppressed by the input filter|0<br>50<br>0<br>50<br>ns||||| |tSU;DAT<br>data set-up time|250<br>-<br>100<br>-<br>ns||||| |tHD;DAT<br>data hold time|0<br>-<br>0<br>-<br>ns||||| |tr<br>rise time of both SDA and SCL signals|-<br>1000<br>20<br>300<br>ns||||| |tf<br>fall time of both SDA and SCL signals|-<br>300<br>20<br>(VDD/ 5.5 V)<br>300<br>ns||||| |tBUF<br>bus free time between a STOP and<br>START condition|4.7<br>-<br>1.3<br>-<br>s||||| |tSU;STA<br>set-up time for a repeated START<br>condition|4.7<br>-<br>0.6<br>-<br>s||||| |tHD;STA<br>hold time (repeated) START condition|4<br>-<br>0.6<br>-<br>s||||| |tSU;STO<br>set-up time for STOP condition|4<br>-<br>0.6<br>-<br>s||||| |tVD;DAT<br>data valid time<br>SCL LOW to SDA<br>output valid|-<br>3.45<br>-<br>0.9<br>s||||| |tVD;ACK<br>data valid acknowledge time<br>ACK signal<br>from SCL LOW<br>to SDA (out) LOW|-<br>3.45<br>-<br>0.9<br>s||||| ## **Table 36. Reset timing requirements** _Over recommended operating free air temperature range, unless otherwise specified. See Figure 37._ |**Symbol**<br>**Parameter**<br>**Conditions**|**Standard-mode**<br>**I2C-bus**|**Standard-mode**<br>**I2C-bus**|**Fast-mode**<br>**I2C-bus**|**Fast-mode**<br>**I2C-bus**|**Unit**| |---|---|---|---|---|---| ||**Min**|**Max**|**Min**|**Max**|| |tw(rst)<br>reset pulse width|30<br>-<br>30<br>-<br>ns||||| |trec(rst)<br>reset recovery time|200<br>-<br>200<br>-<br>ns||||| |trst<br>reset time<br>[1]|600<br>-<br>600<br>-<br>ns||||| [1] Minimum time for SDA to become HIGH or minimum time to wait before doing a START. © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 5 — 10 December 2013** **37 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** **Table 37. Switching characteristics** _Over recommended operating free air temperature range; CL_ _100 pF; unless otherwise specified. See Figure 36._ |**Symbol**<br>**Parameter**<br>**Conditions**|**Standard-mode**<br>**I2C-bus**|**Standard-mode**<br>**I2C-bus**|**Fast-mode**<br>**I2C-bus**|**Fast-mode**<br>**I2C-bus**|**Unit**| |---|---|---|---|---|---| ||**Min**|**Max**|**Min**|**Max**|| |tv(INT)<br>valid time on pin INT<br>from P port to INT|-<br>1<br>-<br>1<br>s||||| |trst(INT)<br>reset time on pin INT<br>from SCL to INT|-<br>1<br>-<br>1<br>s||||| |tv(Q)<br>data output valid time<br>from SCL to P port|-<br>400<br>-<br>400<br>ns||||| |tsu(D)<br>data input set-up time<br>from P port to SCL|0<br>-<br>0<br>-<br>ns||||| |th(D)<br>data input hold time<br>from P port to SCL|300<br>-<br>300<br>-<br>ns||||| ## **15. Parameter measurement information** **==> picture [447 x 421] intentionally omitted <==** **----- Start of picture text -----**<br> VDD(I2C-bus)<br>RL = 1 kΩ<br>SDA<br>DUT<br>CL = 50 pF<br>002aag977<br>a. SDA load configuration<br>two bytes for read Input port register [(1)]<br>STOP START Address Address R/W ACK Data Data STOP<br>condition condition Bit 7 Bit 1 Bit 0 (A) Bit 7 Bit 0 condition<br>(P) (S) (MSB) (LSB) (MSB) (LSB) (P)<br>002aag952<br>b. Transaction format<br>tLOW tHIGH tSP<br>0.7 × VDD(I2C-bus)<br>SCL<br>0.3 × VDD(I2C-bus)<br>tBUF tr tf tVD;DATtf(o) tVD;ACK tSU;STA tSU;STO<br>0.7 × VDD(I2C-bus)<br>SDA<br>0.3 × VDD(I2C-bus)<br>tf tr tVD;ACK<br>tHD;STA tSU;DAT tHD;DAT<br>repeat START condition<br>STOP condition<br>002aag978<br>c. Voltage waveforms<br>CL includes probe and jig capacitance.<br>All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.<br>All parameters and waveforms are not applicable to all devices.<br>Byte 1 = I [2] C-bus address; Byte 2, byte 3 = P port data.<br>(1) See Figure 17.<br>**----- End of picture text -----**<br> **==> picture [260 x 11] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 34. I [2] C-bus interface load circuit and voltage waveforms<br>**----- End of picture text -----**<br> All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** **Rev. 5 — 10 December 2013** **38 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** **==> picture [445 x 405] intentionally omitted <==** **----- Start of picture text -----**<br> VDD(I2C-bus)<br>RL = 4.7 kΩ<br>INT<br>DUT<br>CL = 100 pF<br>002aag979<br>a. Interrupt load configuration<br>acknowledge acknowledge no acknowledge<br>from slave from slave from master<br>START condition R/W STOP<br>8 bits (one data byte) condition<br>slave address from port data from port<br>AD<br>SDA S 0 1 0 0 0 0 1 A DATA 1 A DATA 2 1 P<br>DR<br>SCL 1 2 3 4 5 6 7 8 9<br>B<br>trst(INT) trst(INT) B<br>INT<br>A<br>tv(INT) A tsu(D)<br>data into<br>ADDRESS DATA 1 DATA 2<br>port<br>0.7 × VDD(I2C-bus)<br>INT 0.5 × VDD(I2C-bus) SCL R/W A<br>0.3 × VDD(I2C-bus)<br>tv(INT) trst(INT)<br>Pn 0.5 × VDD(P) INT 0.5 × VDD(I2C-bus)<br>View A - A View B - B<br>002aag980<br>**----- End of picture text -----**<br> ## b. Voltage waveforms ## CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns. All parameters and waveforms are not applicable to all devices. ## **Fig 35. Interrupt load circuit and voltage waveforms** © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 5 — 10 December 2013** **39 of 61** **PCAL6416A** **NXP Semiconductors** ## **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** **==> picture [289 x 360] intentionally omitted <==** **----- Start of picture text -----**<br> Pn 500 Ω<br>DUT 2 × VDD(P)<br>CL = 50 pF 500 Ω<br>002aag981<br>0.7 × VDD(I2C-bus)<br>SCL P0 A P7<br>0.3 × VDD(I2C-bus)<br>SDA<br>tv(Q)<br>Pn<br>unstable last stable bit<br>data<br>002aag982<br>= 0)<br>0.7 × VDD(I2C-bus)<br>SCL P0 A P7<br>0.3 × VDD(I2C-bus)<br>tsu(D) th(D)<br>Pn 0.5 × VDD(P)<br>002aag983<br>**----- End of picture text -----**<br> ## a. P port load configuration ## b. Write mode (R/W = 0) ## c. Read mode (R/W = 1) ## CL includes probe and jig capacitance. tv(Q) is measured from 0.7 VDD on SCL to 50 % I/O (Pn) output. All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns. The outputs are measured one at a time, with one transition per measurement. All parameters and waveforms are not applicable to all devices. ## **Fig 36. P port load circuit and voltage waveforms** © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **Product data sheet** **40 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** **==> picture [451 x 303] intentionally omitted <==** **----- Start of picture text -----**<br> VDD(I2C-bus)<br>RL = 1 kΩ<br>SDA Pn 500 Ω<br>DUT DUT 2 × VDD(P)<br>CL = 50 pF CL = 50 pF 500 Ω<br>002aag977 002aag981<br>a. SDA load configuration b. P port load configuration<br>START<br>SCL ACK or read cycle<br>SDA<br>0.3 × VDD(I2C-bus)<br>trst<br>RESET 0.5 × VDD(I2C-bus)<br>trec(rst) tw(rst) trec(rst)<br>trst<br>Pn 0.5 × VDD(P)<br>002aag984<br>**----- End of picture text -----**<br> ## c. RESET timing ## CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns. The outputs are measured one at a time, with one transition per measurement. I/Os are configured as inputs. All parameters and waveforms are not applicable to all devices. ## **Fig 37. Reset load circuits and voltage waveforms** © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 5 — 10 December 2013** **41 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **16. Package outline** ## **Fig 38. Package outline SOT994-1 (HWQFN24)** All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** **Rev. 5 — 10 December 2013** **42 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** **Fig 39. Package outline SOT355-1 (TSSOP24)** PCAL6416A All information provided in this document is subject to legal disclaimers. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. **Product data sheet** **Rev. 5 — 10 December 2013** **43 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **Fig 40. Package outline SOT1199-1 (VFBGA24)** PCAL6416A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. **Product data sheet** **Rev. 5 — 10 December 2013** **44 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** **==> picture [251 x 10] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 41. Package outline SOT1342-1 (XFBGA24); EX option<br>**----- End of picture text -----**<br> All information provided in this document is subject to legal disclaimers.provided in this document is subject to legal disclaimers.rovided in this document is subject to legal disclaimers.ject to legal disclaimers.ect to legal disclaimers.gal disclaimers.al disclaimers. © NXP B.V. 2013. All rights reserved.ghts reserved.hts reserved. PCAL6416A All information provided in this document is subject to legal disclaimers.provided in this document is subject to legal disclaimers.rovided in this document is subject to legal disclaimers.ject to legal disclaimers.ect to legal disclaimers.gal disclaimers.al disclaimers. © NXP B.V. 2013. All rights reserved.ghts reserved.hts reserved. **Product data sheet Rev. 5 — 10 December 2013 45 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **Fig 42. Package outline SOT1361-1 (UFBGA24); ER option** PCAL6416A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. **Product data sheet** **Rev. 5 — 10 December 2013** **46 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **17. Soldering of SMD packages** This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note _AN10365 “Surface mount reflow soldering description”_ . ## **17.1 Introduction to soldering** Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. ## **17.2 Wave and reflow soldering** Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: - Through-hole components - Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: - Board specifications, including the board finish, solder masks and vias - Package footprints, including solder thieves and orientation - The moisture sensitivity level of the packages - Package placement - Inspection and repair - Lead-free soldering versus SnPb soldering ## **17.3 Wave soldering** Key characteristics in wave soldering are: - Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave - Solder bath specifications, including temperature and impurities © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **Product data sheet** **47 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **17.4 Reflow soldering** Key characteristics in reflow soldering are: - Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 43) than a SnPb process, thus reducing the process window - Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board - Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 38 and 39 ## **Table 38. SnPb eutectic process (from J-STD-020D)** |**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**| |---|---|---| ||**Volume (mm3)**|| ||**< 350**|**350**| |< 2.5|235<br>220|| |2.5|220<br>220|| ## **Table 39. Lead-free process (from J-STD-020D)** |**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**| |---|---|---|---| ||**Volume (mm3)**||| ||**< 350**|**350 to 2000**|**> 2000**| |< 1.6|260<br>260<br>260||| |1.6 to 2.5|260<br>250<br>245||| |> 2.5|250<br>245<br>245||| Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 43. © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **Product data sheet** **48 of 61** **PCAL6416A** **NXP Semiconductors** ## **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** **==> picture [352 x 223] intentionally omitted <==** **----- Start of picture text -----**<br> maximum peak temperature<br>= MSL limit, damage level<br>temperature<br>minimum peak temperature<br>= minimum soldering temperature<br>peak<br> temperature<br>time<br>001aac844<br>MSL: Moisture Sensitivity Level<br>Fig 43. Temperature profiles for large and small components<br>**----- End of picture text -----**<br> For further information on temperature profiles, refer to Application Note _AN10365 “Surface mount reflow soldering description”_ . © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 5 — 10 December 2013** **49 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **18. Soldering: PCB footprints** **Fig 44. PCB footprint for SOT1199-1 (VFBGA24); reflow soldering** All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** **Rev. 5 — 10 December 2013** **50 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **Fig 45. PCB footprint for SOT355-1 (TSSOP24); reflow soldering** © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **51 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **Fig 46.** ## **PCB footprint for SOT994-1 (HWQFN24); reflow soldering** © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **52 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **Fig 47. PCB footprint for SOT1342-1 (XFBGA24); reflow soldering** © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **53 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** **Fig 48.** ## **PCB footprint for SOT1342-1 (XFBGA24, Solder Mask Defined version), EX option; reflow soldering** © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **54 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** **Fig 49. PCB footprint for SOT1342-1 (XFBGA24, Non-Solder Mask Defined version), EX option; reflow soldering** © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **55 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** **Fig 50. PCB footprint for SOT1361-1 (UFBGA24, Solder Mask Defined version), ER option; reflow soldering** © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **56 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** **Fig 51. PCB footprint for SOT1361-1 (UFBGA24, Non-Solder Mask Defined version), ER option; reflow soldering** © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **57 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **19. Abbreviations** **Table 40. Abbreviations** |**Acronym**|**Description**| |---|---| |ESD|ElectroStatic Discharge| |FET|Field-Effect Transistor| |GPIO|General Purpose Input/Output| |I2C-bus|Inter-Integrated Circuit bus| |I/O|Input/Output| |LED|Light-Emitting Diode| |LSB|Least Significant Bit| |MSB|Most Significant Bit| |PCB|Printed-Circuit Board| |POR|Power-On Reset| |SMBus|System Management Bus| ## **20. Revision history** ## **Table 41. Revision history** |**Document ID**|**Release date**<br>**Data sheet status**<br>**Change notice**||**Supersedes**||| |---|---|---|---|---|---| |PCAL6416A v.5|20131210<br>Product data sheet<br>-||PCAL6416A v.4||| |Modifications:|**•** Section 2“<br>Features and benefits<br>”<br>,last bullet item: inserted “UFBGA24”||||| ||**•** Table 1“<br>Ordering information<br>”<br>:added Type number PCAL6416AER and Table note [1]||||| ||**•** Table 2“<br>Ordering options<br>”<br>:||||| ||**–**<br>added Type number PCAL6416AER||||| ||**–**<br>updated ‘Packing method’ descriptions||||| ||(change to verbiage only, no change to packing method)||||| ||**•** Added (new) Figure 7“<br>Pin configuration for UFBGA24 (2 mm|´|2 mm); ER option<br>”||| ||**•** Updated title of Figure 8“<br>Ball mapping for 2 mm<br>´<br>2 mm XFBGA24 and UFBGA24 (transparent||||| ||top view)<br>”<br> (to include UFBGA24 also)||||| ||**•** Added (new) Figure 44“<br>PCB footprint for SOT1199-1 (VFBGA24); reflow soldering<br>”||||| ||**•** Added (new) Figure 48“<br>PCB footprint for SOT1342-1 (XFBGA24, Solder Mask Defined||||| ||version), EX option; reflow soldering<br>”||||| ||**•** Added (new) Figure 49“<br>PCB footprint for SOT1342-1 (XFBGA24, Non-Solder Mask Defined||||| ||version), EX option; reflow soldering<br>”||||| ||**•** Added (new) Figure 50“<br>PCB footprint for SOT1361-1 (UFBGA24, Solder Mask Defined||||| ||version), ER option; reflow soldering<br>”||||| ||**•** Added (new) Figure 51“<br>PCB footprint for SOT1361-1 (UFBGA24, Non-Solder Mask Defined||||| ||version), ER option; reflow soldering<br>”||||| ||||||| |PCAL6416A v.4|20130506<br>Product data sheet<br>-||PCAL6416A v.3||| |PCAL6416A v.3|20121224<br>Product data sheet<br>-||PCAL6416A v.2||| |PCAL6416A v.2|20121005<br>Product data sheet<br>-||PCAL6416A v.1||| |PCAL6416A v.1|20120808<br>Product data sheet<br>-||-||| © NXP B.V. 2013. All rights reserved. PCAL6416A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 5 — 10 December 2013** **58 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **21. Legal information** ## **21.1 Data sheet status** |**Document status[1]**<br>**[2]**|**Product statu**~~**s**~~**[3]**|**Definition**| |---|---|---| |Objective [short] data sheet|Development|This document contains data from the objective specification for product development.| |Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.| |Product [short] data sheet|Production|This document contains the product specification.| [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. ## **21.2 Definitions** **Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. **Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. **Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. **Product specification —** The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. ## **21.3 Disclaimers** **Limited warranty and liability —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. **Limiting values —** Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. **Terms and conditions of commercial sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors. **Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 5 — 10 December 2013** **59 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** **Export control —** This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. **Non-automotive qualified products —** Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. **Translations —** A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. ## **21.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. **I[2] C-bus —** logo is a trademark of NXP B.V. ## **22. Contact information** For more information, please visit: **http://www.nxp.com** For sales office addresses, please send an email to: **salesaddresses@nxp.com** © NXP B.V. 2013. All rights reserved. PCAL6416A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 5 — 10 December 2013** **60 of 61** **PCAL6416A** **NXP Semiconductors** **Low-voltage translating 16-bit I[2] C-bus/SMBus I/O expander** ## **23. Contents** |**1**|**General description . . . . . . . . . . . . . . . . . . . . . . 1**| |---|---| |**2**|**Features and benefits . . . . . . . . . . . . . . . . . . . . 2**| |2.1|Agile I/O features . . . . . . . . . . . . . . . . . . . . . . . 3| |**3**|**Ordering information. . . . . . . . . . . . . . . . . . . . . 3**| |3.1|Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4| |**4**|**Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4**| |**5**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . 5**| |5.1|Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5| |5.2|Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7| |**6**|**Voltage translation. . . . . . . . . . . . . . . . . . . . . . . 8**| |**7**|**Functional description . . . . . . . . . . . . . . . . . . . 9**| |7.1|Device address. . . . . . . . . . . . . . . . . . . . . . . . . 9| |7.2|Interface definition . . . . . . . . . . . . . . . . . . . . . . 9| |7.3|Pointer register and command byte . . . . . . . . . 9| |7.4|Register descriptions . . . . . . . . . . . . . . . . . . . 11| |7.4.1|Input port register pair (00h, 01h) . . . . . . . . . . 11| |7.4.2|Output port register pair (02h, 03h) . . . . . . . . 11| |7.4.3|Polarity inversion register pair (04h, 05h). . . . 12| |7.4.4|Configuration register pair (06h, 07h). . . . . . . 12| |7.4.5|Output drive strength register pairs (40h, 41h,| ||42h, 43h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13| |7.4.6|Input latch register pair (44h, 45h) . . . . . . . . . 13| |7.4.7|Pull-up/pull-down enable register pair| ||(46h, 47h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14| |7.4.8|Pull-up/pull-down selection register pair (48h,| ||49h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15| |7.4.9|Interrupt mask register pair (4Ah, 4Bh). . . . . . 15| |7.4.10|Interrupt status register pair (4Ch, 4Dh) . . . . . 16| |7.4.11|Output port configuration register (4Fh) . . . . . 16| |7.5|I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16| |7.6|Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 17| |7.7|Reset input (RESET<br>). . . . . . . . . . . . . . . . . . . 17| |7.8|Interrupt output (INT<br>) . . . . . . . . . . . . . . . . . . . 18| |**8**|**Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 18**| |8.1|Write commands. . . . . . . . . . . . . . . . . . . . . . . 18| |8.2|Read commands . . . . . . . . . . . . . . . . . . . . . . 20| |**9**|**Application design-in information . . . . . . . . . 24**| |9.1|Minimizing IDDwhen the I/Os are used to| ||control LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . 24| |9.2|Output drive strength control . . . . . . . . . . . . . 25| |9.3|Power-on reset requirements . . . . . . . . . . . . . 26| |9.4|Device current consumption with internal| ||pull-up and pull-down resistors. . . . . . . . . . . . 28| |9.5|I2C-bus error recovery techniques . . . . . . . . . 28| |**10**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 29**| |**11**|**Recommended operating conditions. . . . . . . 30**| |**12**|**Thermal characteristics . . . . . . . . . . . . . . . . . 30**| |---|---| |**13**|**Static characteristics . . . . . . . . . . . . . . . . . . . 31**| |13.1|Typical characteristics . . . . . . . . . . . . . . . . . . 33| |**14**|**Dynamic characteristics. . . . . . . . . . . . . . . . . 37**| |**15**|**Parameter measurement information . . . . . . 38**| |**16**|**Package outline. . . . . . . . . . . . . . . . . . . . . . . . 42**| |**17**|**Soldering of SMD packages. . . . . . . . . . . . . . 47**| |17.1|Introduction to soldering. . . . . . . . . . . . . . . . . 47| |17.2|Wave and reflow soldering. . . . . . . . . . . . . . . 47| |17.3|Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 47| |17.4|Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 48| |**18**|**Soldering: PCB footprints . . . . . . . . . . . . . . . 50**| |**19**|**Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 58**| |**20**|**Revision history . . . . . . . . . . . . . . . . . . . . . . . 58**| |**21**|**Legal information . . . . . . . . . . . . . . . . . . . . . . 59**| |21.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . 59| |21.2|Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 59| |21.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 59| |21.4|Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 60| |**22**|**Contact information . . . . . . . . . . . . . . . . . . . . 60**| |**23**|**Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61**| Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. **© NXP B.V. 2013.** **All rights reserved.** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 10 December 2013 Document identifier: PCAL6416A**
Updated at February 9, 2023
NXP Semiconductors is a global leader in secure connectivity solutions, driving innovation across the automotive, industrial, IoT, mobile, and communications infrastructure markets. By developing advanced, purpose-built technologies, NXP enables devices to sense, think, connect, and act intelligently, delivering rigorously tested components that make the connected world safer and more efficient. Within the semiconductor space, NXP is highly regarded for its extensive range of high-performance integrated circuits and discrete devices. The brand's portfolio excels in drivers and interfaces, featuring a comprehensive selection of I/O expanders designed to streamline complex system architectures. For demanding high-frequency and wireless applications, NXP provides industry-leading RF FETs and RF/PIN diodes engineered to deliver exceptional signal integrity, efficiency, and reliability. The NXP product lineup further extends to essential discrete components, including versatile bipolar transistors, JFETs, and small signal diodes optimized for precision switching and amplification. Additionally, the portfolio supports advanced automation and smart applications with precision IC sensors, such as MEMS accelerometers, alongside specialized power management solutions like AC/DC LED driver ICs and single MOSFETs for cutting-edge electronics design.
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