PCA9675PW,118

## **PCA9675** 

## **Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt Rev. 2 — 3 October 2011 Product data sheet** 

## **1. General description** 

The PCA9675 provides general purpose remote I/O expansion for most microcontroller families via the two-line bidirectional bus (I[2] C-bus) and is a part of the Fast-mode Plus family. 

The PCA9675 is a drop in upgrade for the PCF8575 providing higher Fast-mode Plus (Fm+) I[2] C-bus speeds (1 MHz versus 400 kHz) so that the output can support PWM dimming of LEDs, higher I[2] C-bus drive (30 mA versus 3 mA) so that many more devices can be on the bus without the need for bus buffers, higher total package sink capacity (400 mA versus 100 mA) that supports having all 25 mA LEDs on at the same time and more device addresses (64 versus 8) are available to allow many more devices on the bus without address conflicts. 

The device consists of a 16-bit quasi-bidirectional port and an I[2] C-bus interface. The PCA9675 has a low current consumption and includes latched outputs with high current drive capability for directly driving LEDs. 

It also possesses an interrupt line (INT) which can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I[2] C-bus. The internal Power-On Reset (POR) or software reset sequence initializes the I/Os as inputs. 

## **2. Features and benefits** 

- 1 MHz I[2] C-bus interface 

- Compliant with the I[2] C-bus Fast and Standard modes 

- SDA with 30 mA sink capability for 4000 pF buses 

- 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os 

- 16-bit remote I/O pins that default to inputs at power-up 

- Latched outputs with 25 mA sink capability for directly driving LEDs 

- Total package sink capability of 400 mA 

- Active LOW open-drain interrupt output 

- 64 programmable slave addresses using 3 address pins 

- Readable device ID (manufacturer, device type, and revision) 

- Low standby current 

- 40 C to +85 C operation 

- ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101 

- Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA 

**==> picture [172 x 101] intentionally omitted <==**

**PCA9675** 

**NXP Semiconductors** 

**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

 Packages offered: SO24, TSSOP24, HVQFN24, DHVQFN24 

## **3. Applications** 

- LED signs and displays 

- Servers 

- Industrial control 

- PLCs 

- Cellular telephones 

- Gaming machines 

- Instrumentation and test measurement 

## **4. Ordering information** 

**Table 1. Ordering information** 

|**Type number**|**Topside**<br>**mark**|**Package**|**Package**|**Package**|
|---|---|---|---|---|
|||**Name**|**Description**|**Version**|
|PCA9675D<br>PCA9675D||SO24<br>plastic small outline package; 24 leads; body width 7.5 mm<br>SOT137-1|||
|PCA9675PW<br>PCA9675PW||TSSOP24<br>plastic thin shrink small outline package; 24 leads;<br>body width 4.4 mm<br>SOT355-1|||
|PCA9675BQ<br>9675||DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad<br>flat package; no leads; 24 terminals; body 3.55.50.85 mm<br>SOT815-1|||
|PCA9675BS<br>9675||HVQFN24<br>plastic thermal enhanced very thin quad flat package; no leads;<br>24 terminals; body 440.85 mm<br>SOT616-1|||



© NXP B.V. 2011. All rights reserved. 

PCA9675 

All information provided in this document is subject to legal disclaimers. 

**Rev. 2 — 3 October 2011** 

**Product data sheet** 

**2 of 34** 

**PCA9675** 

**NXP Semiconductors** 

**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

## **5. Block diagram** 

**==> picture [347 x 192] intentionally omitted <==**

**----- Start of picture text -----**<br>
PCA9675<br>INTERRUPT<br>INT LP FILTER<br>LOGIC<br>AD0<br>AD1<br>AD2<br>P00 to P07<br>SCL INPUT I [2] C-BUS SHIFT I/O<br>16 BITS<br>FILTER CONTROL REGISTER PORT<br>SDA P10 to P17<br>write pulse<br>read pulse<br>POWER-ON<br>VDD RESET<br>VSS<br>002aab627<br>**----- End of picture text -----**<br>


## **Fig 1. Block diagram of PCA9675** 

**==> picture [350 x 178] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>write pulse IOH<br>100  μ A<br>Itrt(pu)<br>data from Shift Register D Q<br>FF P00 to P07<br>CI IOL P10 to P17<br>S<br>power-on reset VSS<br>D Q<br>FF<br>read pulse CI<br>S<br>to interrupt logic<br>data to Shift Register<br>002aab631<br>**----- End of picture text -----**<br>


**Fig 2. Simplified schematic diagram of P00 to P17** 

© NXP B.V. 2011. All rights reserved. 

PCA9675 

All information provided in this document is subject to legal disclaimers. 

**Rev. 2 — 3 October 2011** 

**Product data sheet** 

**3 of 34** 

**PCA9675** 

**NXP Semiconductors** 

**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

## **6. Pinning information** 

## **6.1 Pinning** 

**==> picture [397 x 434] intentionally omitted <==**

**----- Start of picture text -----**<br>
INT 1 24 VDD INT 1 24 VDD<br>AD1 2 23 SDA AD1 2 23 SDA<br>AD2 3 22 SCL AD2 3 22 SCL<br>P00 4 21 AD0 P00 4 21 AD0<br>P01 5 20 P17 P01 5 20 P17<br>P02 6 19 P16 P02 6 19 P16<br>PCA9675D PCA9675PW<br>P03 7 18 P15 P03 7 18 P15<br>P04 8 17 P14 P04 8 17 P14<br>P05 9 16 P13 P05 9 16 P13<br>P06 10 15 P12 P06 10 15 P12<br>P07 11 14 P11 P07 11 14 P11<br>VSS 12 13 P10 VSS 12 13 P10<br>002aab628 002aab629<br>Fig 3. Pin configuration for SO24 Fig 4. Pin configuration for TSSOP24<br>terminal 1<br>index area<br>AD1 2 23 SDA<br>terminal 1 AD2 3 22 SCL<br>index area P00 4 21 AD0<br>P01 5 20 P17<br>P00 1 18 AD0 P02 6 19 P16<br>PCA9675BQ<br>P01 2 17 P17 P03 7 18 P15<br>P02 3 16 P16 P04 8 17 P14<br>PCA9675BS<br>P03 4 15 P15 P05 9 16 P13<br>P04 5 14 P14 P06 10 15 P12<br>P05 6 13 P13 P07 11 14 P11<br>002aac269<br>002aab630<br>Transparent top view Transparent top view<br>Fig 5. Pin configuration for HVQFN24 Fig 6. Pin configuration for DHVQFN24<br>INT VDD<br>1 24<br>AD2 AD1 INT VDD SDA SCL<br>24 23 22 21 20 19<br>7 8 9 10 11 12 12 13<br>P06 P07 VSS P10 P11 P12 VSS P10<br>**----- End of picture text -----**<br>


© NXP B.V. 2011. All rights reserved. 

PCA9675 

All information provided in this document is subject to legal disclaimers. 

**Rev. 2 — 3 October 2011** 

**Product data sheet** 

**4 of 34** 

**PCA9675** 

**NXP Semiconductors** 

**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

## **6.2 Pin description** 

|**Pin description**|**Pin description**|**Pin description**|**Pin description**|
|---|---|---|---|
|**Table 2.**<br>**Pin description**||||
|**Symbol**|**Pin**||**Description**|
||**SO24, TSSOP24,**<br>**DHVQFN24**|**HVQFN24**||
|INT|1<br>22<br>interrupt output (active LOW)|||
|AD1|2<br>23<br>address input 1|||
|AD2|3<br>24<br>address input 2|||
|P00|4<br>1<br>quasi-bidirectional I/O 00|||
|P01|5<br>2<br>quasi-bidirectional I/O 01|||
|P02|6<br>3<br>quasi-bidirectional I/O 02|||
|P03|7<br>4<br>quasi-bidirectional I/O 03|||
|P04|8<br>5<br>quasi-bidirectional I/O 04|||
|P05|9<br>6<br>quasi-bidirectional I/O 05|||
|P06|10<br>7<br>quasi-bidirectional I/O 06|||
|P07|11<br>8<br>quasi-bidirectional I/O 07|||
|VSS|1~~2~~[1]<br>9[1]<br>supply ground|||
|P10|13<br>10<br>quasi-bidirectional I/O 10|||
|P11|14<br>11<br>quasi-bidirectional I/O 11|||
|P12|15<br>12<br>quasi-bidirectional I/O 12|||
|P13|16<br>13<br>quasi-bidirectional I/O 13|||
|P14|17<br>14<br>quasi-bidirectional I/O 14|||
|P15|18<br>15<br>quasi-bidirectional I/O 15|||
|P16|19<br>16<br>quasi-bidirectional I/O 16|||
|P17|20<br>17<br>quasi-bidirectional I/O 17|||
|AD0|21<br>18<br>address input 0|||
|SCL|22<br>19<br>serial clock line input|||
|SDA|23<br>20<br>serial data line input/output|||
|VDD|24<br>21<br>supply voltage|||



- [1] HVQFN24 and DHVQFN24 package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region. 

© NXP B.V. 2011. All rights reserved. 

PCA9675 **Product data sheet** 

All information provided in this document is subject to legal disclaimers. **Rev. 2 — 3 October 2011** 

**5 of 34** 

**PCA9675** 

**NXP Semiconductors** 

**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

## **7. Functional description** 

“ ” Refer to Figure 1 Block diagram of PCA9675 . 

## **7.1 Device address** 

Following a START condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). The address of the PCA9675 is shown in Figure 7. Slave address pins AD2, AD1, and AD0 choose 1 of 64 slave addresses. To conserve power, no internal pull-up resistors are incorporated on AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in “ ” Table 3 PCA9675 address map . 

**Remark:** The General Call address (0000 0000b) and the Device ID address (1111 100Xb) are reserved and cannot be used as device address. Failure to follow this requirement will cause the PCA9675 not to acknowledge. 

**Remark:** Reserved I[2] C-bus addresses must be used with caution since they can interfere with: 

- “reserved for future use” I[2] C-bus addresses (0000 011, 1111 101, 1111 110, 1111 111) 

- slave devices that use the 10-bit addressing scheme (1111 0xx) 

- High speed mode (Hs-mode) master code (0000 1xx) 

**==> picture [261 x 74] intentionally omitted <==**

**----- Start of picture text -----**<br>
slave address<br>A6 A5 A4 A3 A2 A1 A0 R/W<br>programmable<br>002aab636<br>Fig 7. PCA9675 address<br>**----- End of picture text -----**<br>


The last bit of the first byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. 

When AD2, AD1 and AD0 are held to VDD or VSS, the same address as the PCF8575 is applied. 

## **7.1.1 Address maps** 

|**Table**|**3.**|**PCA9675**|**PCA9675**|**address**|**map**|||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
|**AD2**||**AD1**|**AD0**|**A6**|**A5**|**A4**|**A3**|**A2**|**A1**|**A0**|**Address (hex)**|
|VSS||SCL|VSS|0|0|1|0|0|0|0|20h|
|VSS||SCL|VDD|0|0|1|0|0|0|1|22h|
|VSS||SDA|VSS|0|0|1|0|0|1|0|24h|
|VSS||SDA|VDD|0|0|1|0|0|1|1|26h|
|VDD||SCL|VSS|0|0|1|0|1|0|0|28h|
|VDD||SCL|VDD|0|0|1|0|1|0|1|2Ah|
|VDD||SDA|VSS|0|0|1|0|1|1|0|2Ch|
|VDD||SDA|VDD|0|0|1|0|1|1|1|2Eh|



All information provided in this document is subject to legal disclaimers. 

© NXP B.V. 2011. All rights reserved. 

PCA9675 

**Rev. 2 — 3 October 2011** 

**Product data sheet** 

**6 of 34** 

**PCA9675** 

**NXP Semiconductors** 

**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

|**Table**|**3.**|**PCA9675**|**PCA9675**|**address**|**map**|_…continued_||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
|**AD2**||**AD1**|**AD0**|**A6**|**A5**|**A4**|**A3**|**A2**|**A1**|**A0**|**Address (hex)**|
|VSS||SCL|SCL|0|0|1|1|0|0|0|30h|
|VSS||SCL|SDA|0|0|1|1|0|0|1|32h|
|VSS||SDA|SCL|0|0|1|1|0|1|0|34h|
|VSS||SDA|SDA|0|0|1|1|0|1|1|36h|
|VDD||SCL|SCL|0|0|1|1|1|0|0|38h|
|VDD||SCL|SDA|0|0|1|1|1|0|1|3Ah|
|VDD||SDA|SCL|0|0|1|1|1|1|0|3Ch|
|VDD||SDA|SDA|0|0|1|1|1|1|1|3Eh|
|VSS||VSS|VSS|0|1|0|0|0|0|0|40h|
|VSS||VSS|VDD|0|1|0|0|0|0|1|42h|
|VSS||VDD|VSS|0|1|0|0|0|1|0|44h|
|VSS||VDD|VDD|0|1|0|0|0|1|1|46h|
|VDD||VSS|VSS|0|1|0|0|1|0|0|48h|
|VDD||VSS|VDD|0|1|0|0|1|0|1|4Ah|
|VDD||VDD|VSS|0|1|0|0|1|1|0|4Ch|
|VDD||VDD|VDD|0|1|0|0|1|1|1|4Eh|
|VSS||VSS|SCL|0|1|0|1|0|0|0|50h|
|VSS||VSS|SDA|0|1|0|1|0|0|1|52h|
|VSS||VDD|SCL|0|1|0|1|0|1|0|54h|
|VSS||VDD|SDA|0|1|0|1|0|1|1|56h|
|VDD||VSS|SCL|0|1|0|1|1|0|0|58h|
|VDD||VSS|SDA|0|1|0|1|1|0|1|5Ah|
|VDD||VDD|SCL|0|1|0|1|1|1|0|5Ch|
|VDD||VDD|SDA|0|1|0|1|1|1|1|5Eh|
|SCL||SCL|VSS|1|0|1|0|0|0|0|A0h|
|SCL||SCL|VDD|1|0|1|0|0|0|1|A2h|
|SCL||SDA|VSS|1|0|1|0|0|1|0|A4h|
|SCL||SDA|VDD|1|0|1|0|0|1|1|A6h|
|SDA||SCL|VSS|1|0|1|0|1|0|0|A8h|
|SDA||SCL|VDD|1|0|1|0|1|0|1|AAh|
|SDA||SDA|VSS|1|0|1|0|1|1|0|ACh|
|SDA||SDA|VDD|1|0|1|0|1|1|1|AEh|
|SCL||SCL|SCL|1|0|1|1|0|0|0|B0h|
|SCL||SCL|SDA|1|0|1|1|0|0|1|B2h|
|SCL||SDA|SCL|1|0|1|1|0|1|0|B4h|
|SCL||SDA|SDA|1|0|1|1|0|1|1|B6h|
|SDA||SCL|SCL|1|0|1|1|1|0|0|B8h|
|SDA||SCL|SDA|1|0|1|1|1|0|1|BAh|
|SDA||SDA|SCL|1|0|1|1|1|1|0|BCh|
|SDA||SDA|SDA|1|0|1|1|1|1|1|BEh|



All information provided in this document is subject to legal disclaimers. 

© NXP B.V. 2011. All rights reserved. 

PCA9675 

**Rev. 2 — 3 October 2011** 

**Product data sheet** 

**7 of 34** 

**PCA9675** 

**NXP Semiconductors** 

## **Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

|**Table**|**3.**|**PCA9675**|**PCA9675**|**address**|**map**|_…continued_||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
|**AD2**||**AD1**|**AD0**|**A6**|**A5**|**A4**|**A3**|**A2**|**A1**|**A0**|**Address (hex)**|
|SCL||VSS|VSS|1|1|0|0|0|0|0|C0h|
|SCL||VSS|VDD|1|1|0|0|0|0|1|C2h|
|SCL||VDD|VSS|1|1|0|0|0|1|0|C4h|
|SCL||VDD|VDD|1|1|0|0|0|1|1|C6h|
|SDA||VSS|VSS|1|1|0|0|1|0|0|C8h|
|SDA||VSS|VDD|1|1|0|0|1|0|1|CAh|
|SDA||VDD|VSS|1|1|0|0|1|1|0|CCh|
|SDA||VDD|VDD|1|1|0|0|1|1|1|CEh|
|SCL||VSS|SCL|1|1|1|0|0|0|0|E0h|
|SCL||VSS|SDA|1|1|1|0|0|0|1|E2h|
|SCL||VDD|SCL|1|1|1|0|0|1|0|E4h|
|SCL||VDD|SDA|1|1|1|0|0|1|1|E6h|
|SDA||VSS|SCL|1|1|1|0|1|0|0|E8h|
|SDA||VSS|SDA|1|1|1|0|1|0|1|EAh|
|SDA||VDD|SCL|1|1|1|0|1|1|0|ECh|
|SDA||VDD|SDA|1|1|1|0|1|1|1|EEh|



## **7.2 Software Reset call, and Device ID addresses** 

Two other different addresses can be sent to the PCA9675. 

- General Call address: allows to reset the PCA9675 through the I[2] C-bus upon reception of the right I[2] C-bus sequence. See Section 7.2.1 “Software Reset” for more information. 

- Device ID address: allows to read ID information from the device (manufacturer, part identification, revision). See Section 7.2.2 “Device ID (PCA9675 ID field)” for more information. 

**==> picture [397 x 151] intentionally omitted <==**

**----- Start of picture text -----**<br>
R/W<br>0 0 0 0 0 0 0 0<br>002aac155<br>Fig 8. General Call address<br>1 1 1 1 1 0 0 R/W<br>002aab638<br>Fig 9. Device ID address<br>**----- End of picture text -----**<br>


© NXP B.V. 2011. All rights reserved. 

PCA9675 

All information provided in this document is subject to legal disclaimers. 

**Rev. 2 — 3 October 2011** 

**Product data sheet** 

**8 of 34** 

**PCA9675** 

**NXP Semiconductors** 

**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

## **7.2.1 Software Reset** 

The Software Reset Call allows all the devices in the I[2] C-bus to be reset to the power-up state value through a specific formatted I[2] C-bus command. To be performed correctly, it implies that the I[2] C-bus is functional and that there is no device hanging the bus. 

The Software Reset sequence is defined as following: 

1. A START command is sent by the I[2] C-bus master. 

2. The reserved General Call I[2] C-bus address ‘0000 000’ with the R/W bit set to 0 (write) is sent by the I[2] C-bus master. 

3. The PCA9675 device(s) acknowledge(s) after seeing the General Call address ‘0000 0000’ (00h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to the I[2] C-bus master. 

4. Once the General Call address has been sent and acknowledged, the master sends 1 byte. The value of the byte must be equal to 06h. 

   - a. The PCA9675 acknowledges this value only. If the byte is not equal to 06h, the PCA9675 does not acknowledge it. 

If more than 1 byte of data is sent, the PCA9675 does not acknowledge any more. 

5. Once the right byte has been sent and correctly acknowledged, the master sends a STOP command to end the Software Reset sequence: the PCA9675 then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time. If the master sends a Repeated START instead, no reset is performed. 

The I[2] C-bus master must interpret a non-acknowledge from the PCA9675 (at any time) as a ‘Software Reset Abort’. The PCA9675 does not initiate a reset of its registers. 

The unique sequence that initiates a Software Reset is described in Figure 10. 

**==> picture [258 x 98] intentionally omitted <==**

**----- Start of picture text -----**<br>
SWRST Call I [2] C address SWRST data = 06h<br>S 0 0 0 0 0 0 0 0 A 0 0 0 0 0 1 1 0 A P<br>START condition R/W acknowledge<br>from slave(s)<br>acknowledge<br>from slave(s)<br>PCA9675 is(are) reset.<br>Registers are set to default power-up values.<br>002aac156<br>**----- End of picture text -----**<br>


**==> picture [145 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Fig 10. Software Reset sequence<br>**----- End of picture text -----**<br>


© NXP B.V. 2011. All rights reserved. 

PCA9675 

All information provided in this document is subject to legal disclaimers. 

**Rev. 2 — 3 October 2011** 

**Product data sheet** 

**9 of 34** 

**PCA9675** 

**NXP Semiconductors** 

**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

## **7.2.2 Device ID (PCA9675 ID field)** 

The Device ID field is a 3-byte read-only (24 bits) word giving the following information: 

- 8 bits with the manufacturer name, unique per manufacturer (for example, NXP Semiconductors). 

- 13 bits with the part identification, assigned by manufacturer, the 7 MSBs with the category ID and the 6 LSBs with the feature ID (for example, PCA9675 16-bit quasi-output I/O expander). 

- 3 bits with the die revision, assigned by manufacturer (for example, Rev X). 

The Device ID is read-only, hard wired in the device and can be accessed as follows: 

1. START command 

2. The master sends the Reserved Device ID I[2] C-bus address ‘1111 100’ with the R/W bit set to 0 (write). 

3. The master sends the I[2] C-bus slave address of the slave device it needs to identify. The LSB is a ‘Don’t care’ value. Only one device must acknowledge this byte (the one that has the I[2] C-bus slave address). 

4. The master sends a Re-START command. 

**Remark:** A STOP command followed by a START command will reset the slave state machine and the Device ID read cannot be performed. 

**Remark:** A STOP command or a Re-START command followed by an access to another slave device will reset the slave state machine and the Device ID read cannot be performed. 

5. The master sends the Reserved Device ID I[2] C-bus address ‘1111 100’ with the R/W bit set to 1 (read). 

6. The device ID read can be done, starting with the 8 manufacturer bits (first byte + 4 MSB of the second byte), followed by the 13 part identification bits and then the 3 die revision bits (3 LSB of the third byte). 

7. The master ends the reading sequence by NACKing the last byte, thus resetting the slave device state machine and allowing the master to send the STOP command. 

**Remark:** The reading of the Device ID can be stopped anytime by sending a NACK command. 

**Remark:** If the master continues to ACK the bytes after the third byte, the PCA9675 rolls back to the first byte and keeps sending the Device ID sequence until a NACK has been detected. 

For the PCA9675, the Device ID is as shown in Figure 11. 

© NXP B.V. 2011. All rights reserved. 

PCA9675 

All information provided in this document is subject to legal disclaimers. 

**Rev. 2 — 3 October 2011** 

**Product data sheet** 

**10 of 34** 

**PCA9675** 

**NXP Semiconductors** 

**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

**==> picture [277 x 89] intentionally omitted <==**

**----- Start of picture text -----**<br>
manufacturer 0 0 0 0 0 0 0 0<br>part identification 0 0 0 0 0 0 1 0 0 1 1 0 0<br>category identification feature identification<br>revision 0 0 0<br>002aab639<br>**----- End of picture text -----**<br>


## **Fig 11. PCA9675 ID** 

**==> picture [379 x 206] intentionally omitted <==**

**----- Start of picture text -----**<br>
acknowledge from one acknowledge from<br>or several slave(s) slave to be identified<br>acknowledge from<br>device ID address don't care slave to be identified<br>S 1 1 1 1 1 0 0 0 A A6 A5 A4 A3 A2 A1 A0 X A 1 1 1 1 1 0 0 1 A<br>I [2] C-bus slave address of device ID address<br>START condition R/W the device to be identified R/W<br>acknowledge acknowledge no acknowledge<br>from master from master from master<br>M7 M6 M5 M4 M3 M2 M1 M0 A C6 C5 C4 C3 C2 C1 C0 F5 A F4 P3 P2 P1 P0 R2 R1 R0 A P<br>category identification revision = 000<br>manufacturer name = 0000001<br>= 00000000 feature identification STOP<br>= 001100 condition<br>002aab663<br>If more than 2 bytes are read, the slave device loops back to the first byte (manufacturer byte) and<br>keeps sending data until the master generates a ‘no acknowledge’.<br>**----- End of picture text -----**<br>


**Fig 12. Device ID field reading** 

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**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

## **8. I/O programming** 

## **8.1 Quasi-bidirectional I/O architecture** 

The PCA9675’s 16 ports (see Figure 2) are entirely independent and can be used either as input or output ports. Input data is transferred from the ports to the microcontroller in the Read mode (see Figure 15). Output data is transmitted to the ports in the Write mode (see Figure 14). 

Every data transmission from the PCA9675 must consist of an even number of bytes, the first byte will be referred to as P07 to P00, and the second byte as P17 to P10. The third will be referred to as P07 to P00, and so on. 

This quasi-bidirectional I/O can be used as an input or output without the use of a control signal for data directions. At power-on the I/Os are HIGH. In this mode only a current source (IOH) to VDD is active. An additional strong pull-up to VDD (Itrt(pu)) allows fast rising edges into heavily loaded outputs. These devices turn on when an output is written HIGH, and are switched off by the negative edge of SCL. The I/Os should be HIGH before being used as inputs. After power-on, as all the I/Os are set HIGH, all of them can be used as inputs. Any change in setting of the I/Os as either inputs or outputs can be done with the write mode. 

**Remark:** If a HIGH is applied to an I/O which has been written earlier to LOW, a large current (IOL) will flow to VSS. 

## **8.2 Writing to the port (Output mode)** 

To write, the master (microcontroller) first addresses the slave device. By setting the last bit of the byte containing the slave address to logic 0 the Write mode is entered. The PCA9675 acknowledges and the master sends the first data byte for P07 to P00. After the first data byte is acknowledged by the PCA9675, the second data byte P17 to P10 is sent by the master. Once again, the PCA9675 acknowledges the receipt of the data. Each 8-bit data is presented on the port lines after it has been acknowledged by the PCA9675. 

The number of data bytes that can be sent successively is not limited. After every two bytes, the previous data is overwritten. 

The first data byte in every pair refers to Port 0 (P07 to P00), whereas the second data byte in every pair refers to Port 1 (P17 to P10) (see Figure 13). 

**==> picture [345 x 76] intentionally omitted <==**

**----- Start of picture text -----**<br>
first byte second byte<br>07 06 05 04 03 02 01 00 A 17 16 15 14 13 12 11 10 A<br>P07 P06 P05 P04 P03 P02 P01 P00 P17 P16 P15 P14 P13 P12 P11 P10<br>002aab634<br>Fig 13. Correlation between bits and ports<br>**----- End of picture text -----**<br>


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PCA9675 

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**Product data sheet** 

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**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

**==> picture [443 x 261] intentionally omitted <==**

**----- Start of picture text -----**<br>
SCL 1 2 3 4 5 6 7 8 9<br>slave address data to port 0 data to port 1<br>P P P P P P P P P P P P P P<br>SDA S A6 A5 A4 A3 A2 A1 A0 0 A 07 06 1 04 03 02 01 00 A 17 1 15 14 13 12 11 10 A<br>START condition R/W P05 P16 acknowledge<br>acknowledge acknowledge from slave<br>from slave from slave<br>write to port<br>tv(Q) tv(Q)<br>data output from port data A0 and B0 valid data A0 and B0 valid<br>P05 output voltage<br>P05 pull-up output current Itrt(pu)<br>IOH<br>P16 output voltage<br>P16 pull-up output current Itrt(pu)<br>IOH<br>INT<br>td(rst) 002aab632<br>**----- End of picture text -----**<br>


**==> picture [122 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Fig 14. Write mode (output)<br>**----- End of picture text -----**<br>


## **8.3 Reading from a port (Input mode)** 

All ports programmed as input should be set to logic 1. To read, the master (microcontroller) first addresses the slave device after it receives the interrupt. By setting the last bit of the byte containing the slave address to logic 1 the Read mode is entered. The data bytes that follow on the SDA are the values on the ports. 

If the data on the input port changes faster than the master can read, this data may be lost. 

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**==> picture [613 x 234] intentionally omitted <==**

**----- Start of picture text -----**<br>
SCL 1 2 3 4 5 6 7 8 9<br>P0x P1x P0x P1x<br>SDA<br>S 0 1 0 0 A2 A1 A0 1 A DATA 00 A DATA 11 A DATA 00 A DATA 12 1 P<br>START condition R/W acknowledge acknowledge acknowledge no acknowledge<br>from master from master from master from master<br>acknowledge<br>from slave<br>read from port 0<br>data into port 0 DATA 00<br>read from port 1<br>data into port 1 DATA 10 DATA 11 DATA 12<br>INT<br>tv(D) td(rst) 002aab810<br>**----- End of picture text -----**<br>


Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). 

**Fig 15. Read input port register, scenario 1** 

**==> picture [613 x 235] intentionally omitted <==**

**----- Start of picture text -----**<br>
SCL 1 2 3 4 5 6 7 8 9<br>P0x P1x P0x P1x<br>SDA<br>S 0 1 0 0 A2 A1 A0 1 A DATA 00 A DATA 10 A DATA 03 A DATA 12 1 P<br>START condition R/W acknowledge acknowledge acknowledge no acknowledge<br>from master from master from master from master<br>acknowledge<br>from slave<br>read from port 0<br>th(D) tsu(D)<br>data into port 0 DATA 00 DATA 01 DATA 02 DATA 03<br>th(D)<br>read from port 1<br>tsu(D)<br>data into port 1 DATA 10 DATA 11 DATA 12<br>INT<br>tv(D) td(rst) 002aab811<br>**----- End of picture text -----**<br>


Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). 

**Fig 16. Read input port register, scenario 2** 

**PCA9675** 

**NXP Semiconductors** 

**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

## **8.4 Power-on reset** 

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9675 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9675 registers and I[2] C-bus/SMBus state machine will initialize to their default states. Thereafter VDD must be lowered below 0.2 V to reset the device. 

## **8.5 Interrupt output (INT)** 

The PCA9675 provides an open-drain interrupt (INT) which can be fed to a corresponding input of the microcontroller (see Figure 15, Figure 16, and Figure 17). This gives these chips a kind of master function which can initiate an action elsewhere in the system. 

An interrupt is generated by any rising or falling edge of the port inputs. After time t(v)D the signal INT is valid. 

The interrupt disappears when data on the port is changed to the original setting or data is read from or written to the device which has generated the interrupt. 

In the write mode, the interrupt may become deactivated (HIGH) on the rising edge of the write to port pulse. On the falling edge of the write to port pulse the interrupt is definitely deactivated (HIGH). 

The interrupt is reset in the read mode on the rising edge of the read from port pulse. 

During the resetting of the interrupt itself, any changes on the I/Os may not generate an interrupt. After the interrupt is reset any change in I/Os will be detected and transmitted as an INT. 

**==> picture [337 x 76] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD device 1 device 2 device 8<br>PCA9675 PCA9675 PCA9675<br>MICROCOMPUTER<br>INT INT INT<br>INT<br>002aab635<br>**----- End of picture text -----**<br>


**Fig 17. Application of multiple PCA9675s with interrupt** 

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**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

## **9. Characteristics of the I[2] C-bus** 

The I[2] C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 

## **9.1 Bit transfer** 

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 18). 

**==> picture [241 x 88] intentionally omitted <==**

**----- Start of picture text -----**<br>
SDA<br>SCL<br>data line change<br>stable; of data<br>data valid allowed mba607<br>**----- End of picture text -----**<br>


**Fig 18. Bit transfer** 

## **9.1.1 START and STOP conditions** 

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 19.) 

**==> picture [319 x 75] intentionally omitted <==**

**----- Start of picture text -----**<br>
SDA<br>SCL<br>S P<br>START condition STOP condition<br>mba608<br>**----- End of picture text -----**<br>


**Fig 19. Definition of START and STOP conditions** 

## **9.2 System configuration** 

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 20). 

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PCA9675 

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**Product data sheet** 

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**PCA9675** 

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**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

**==> picture [432 x 109] intentionally omitted <==**

**----- Start of picture text -----**<br>
SDA<br>SCL<br>MASTER SLAVE SLAVE MASTER MASTER I [2] C-BUS<br>TRANSMITTER/ RECEIVER TRANSMITTER/ TRANSMITTER TRANSMITTER/ MULTIPLEXER<br>RECEIVER RECEIVER RECEIVER<br>SLAVE<br>002aaa966<br>**----- End of picture text -----**<br>


**Fig 20. System configuration** 

## **9.3 Acknowledge** 

The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. 

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. 

A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. 

**==> picture [340 x 140] intentionally omitted <==**

**----- Start of picture text -----**<br>
data output<br>by transmitter<br>not acknowledge<br>data output<br>by receiver<br>acknowledge<br>SCL from master<br>1 2 8 9<br>S<br>clock pulse for<br>START acknowledgement<br>condition 002aaa987<br>Fig 21. Acknowledgement on the I [2] C-bus<br>**----- End of picture text -----**<br>


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**Product data sheet** 

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**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

## **10. Application design-in information** 

## **10.1 Bidirectional I/O expander applications** 

In the 8-bit I/O expander application shown in Figure 22, P00 and P01 are inputs, and P02 to P07 are outputs. When used in this configuration, during a write, the input (P00 and P01) must be written as HIGH so the external devices fully control the input ports. The desired HIGH or LOW logic levels may be written to the I/Os used as outputs (P02 to P07). During a read, the logic levels of the external devices driving the input ports (P00 and P01) and the previous written logic level to the output ports (P02 to P07) will be read. 

The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of the microprocessor. By sending an interrupt signal on this line, the remote I/O informs the microprocessor that there is incoming data or a change of data on its ports without having to communicate via the I[2] C-bus. 

**==> picture [266 x 129] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>VDD<br>VDD<br>SDA P00 temperature sensor<br>CORE SCL P01 battery status<br>PROCESSOR INT P02 control for latch<br>P03 control for switch<br>P04 control for audio<br>AD0 P05 control for camera<br>AD1 P06 control for MP3<br>AD2 P07<br>002aab812<br>**----- End of picture text -----**<br>


**Fig 22. Bidirectional I/O expander application** 

## **10.2 High current-drive load applications** 

The GPIO has a maximum sinking current of 25 mA per bit. In applications requiring additional drive, two port pins in the same octal may be connected together to sink up to 50 mA current. Both bits must then always be turned on or off together. Up to 8 pins (one octal) can be connected together to drive 200 mA. 

**==> picture [307 x 145] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>VDD VDD<br>SDA P00<br>CORE SCL P01<br>PROCESSOR INT P02<br>P03 LOAD<br>P04<br>AD0 P05<br>AD1 P06<br>AD2 P07<br>002aab813<br>Fig 23. High current-drive load application<br>**----- End of picture text -----**<br>


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**Product data sheet** 

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**PCA9675** 

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**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

## **10.3 Differences between the PCA9675 and the PCF8575** 

The PCA9675 is a drop in replacement for the PCF8575 and can used without electrical or software modifications, but there is a difference in interrupt output release timing during the read operation. 

Write operations are identical. At the completion of each 8-bit write sequence the data is stored in its associated 8-bit write register at ACK or NACK. The first byte goes to P0n while the second goes to P1n. Subsequent writes without a STOP wrap around to P0n then P1n again. Any write will update both read registers and clear interrupts. 

Read operations are identical. Both devices update the byte register with the pin data as each 8-bit read is initiated, the very first read after an address cycle corresponds to ports P0n while the second (even byte) corresponds to P1n and subsequent reads without a STOP wrap around to P0n then P1n again. 

During read operations, the PCA9675 interrupt output will be cleared in a byte-wise fashion as each byte is read. Reading the first byte will clear any interrupts associated with the P0n pins. This first byte read operation will have no effect on interrupts associated with changes of state on the P1n pins. Interrupts associated with the P1n pins will be cleared when the second byte is read. Reading the second byte has no effect on interrupts associated with the changes of state on the P0x pins. The PCF8575 interrupt output will clear after reading both bytes of data regardless of whether data was changed in the first byte or the second byte or both bytes. 

## **11. Limiting values** 

|**Table 4.**|**Limiting values**|||||
|---|---|---|---|---|---|
|_In accordance with the Absolute Maximum_||_Rating System (IEC 60134)._||||
|**Symbol**|**Parameter**|**Conditions**|**Min**|**Max**|**Unit**|
|VDD|supply voltage||0.5|+6|V|
|IDD|supply current||-|100|mA|
|ISS|ground supply current||-|600|mA|
|VI|input voltage||VSS0.5|5.5|V|
|II|input current||-|20|mA|
|IO|output current|[1]|-|50|mA|
|Ptot|total power dissipation||-|600|mW|
|P/out|power dissipation per output||-|200|mW|
|Tstg|storage temperature||65|+150|C|
|Tamb|ambient temperature|operating|40|+85|C|



[1] Total package (maximum) output current is 600 mA. 

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**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

## **12. Static characteristics** 

## **Table 5. Static characteristics** 

_VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb =_  _40_  _C to +85_  _C; unless otherwise specified._ 

|**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**|
|---|---|
|**Supplies**||
|VDD<br>supply voltage|2.3<br>-<br>5.5<br>V|
|IDD<br>supply current|Operating mode; no load;<br>VI= VDDor VSS; fSCL= 1 MHz<br>-<br>250<br>500<br>A|
|Istb<br>standby current|Standby mode; no load;<br>VI= VDDor VSS<br>-<br>2.5<br>10<br>A|
|VPOR<br>power-on reset voltage|[1]<br>-<br>1.6<br>2.0<br>V|
|**Input SCL; input/output SDA**||
|VIL<br>LOW-level input voltage|0.5<br>-<br>+0.3VDD V|
|VIH<br>HIGH-level input voltage|0.7VDD<br>-<br>5.5<br>V|
|IOL<br>LOW-level output current|VOL= 0.4 V<br>20<br>-<br>-<br>mA|
|IL<br>leakage current|VI= VDDor VSS<br>1<br>-<br>+1<br>A|
|Ci<br>input capacitance|VI= VSS<br>-<br>5<br>10<br>pF|
|**I/Os; P00 to P07 and P10 to P17**||
|IOL<br>LOW-level output current|VOL= 0.5 V; VDD= 2.3 V<br>[2]<br>12<br>28<br>-<br>mA|
||VOL= 0.5 V; VDD= 3.0 V<br>[2]<br>17<br>35<br>-<br>mA|
||VOL= 0.5 V; VDD= 4.5 V<br>[2]<br>25<br>42<br>-<br>mA|
|IOL(tot)<br>total LOW-level output current|VOL= 0.5 V; VDD= 4.5 V<br>[2]<br>-<br>-<br>400<br>mA|
|IOH<br>HIGH-level output current|VOH= VSS<br>30<br>102<br>300<br>A|
|Itrt(pu)<br>transient boosted pull-up current|VOH= VSS; see Figure 14<br>0.5<br>1.0<br>-<br>mA|
|Cio(off)<br>off-state input/output<br>capacitance|[3]<br>-<br>9<br>10<br>pF|
|**Interrupt INT**||
|IOL<br>LOW-level output current|VOL= 0.4 V<br>6<br>-<br>-<br>mA|
|Co<br>output capacitance|-<br>2.1<br>5<br>pF|
|**Inputs AD0, AD1, AD2**||
|VIL<br>LOW-level input voltage|0.5<br>-<br>+0.3VDD V|
|VIH<br>HIGH-level input voltage|0.7VDD<br>-<br>5.5<br>V|
|ILI<br>input leakage current|1<br>-<br>+1<br>A|
|Ci<br>input capacitance|-<br>2.4<br>5<br>pF|



[1] The power-on reset circuit resets the I[2] C-bus logic with VDD < VPOR and set all I/Os to logic 1 (with current source to VDD). 

[2] Each bit must be limited to a maximum of 25 mA and the total package limited to 400 mA due to internal busing limits. 

[3] The value is not tested, but verified on sampling basis. 

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PCA9675 

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**Rev. 2 — 3 October 2011** 

**Product data sheet** 

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**PCA9675** 

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**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

## **13. Dynamic characteristics** 

## **Table 6. Dynamic characteristics** 

_VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb =_  _40_  _C to +85_  _C; unless otherwise specified._ 

|**Symbol**<br>**Parameter**<br>**Conditions**|**Standard mode**<br>**I2C-bus**|**Standard mode**<br>**I2C-bus**|**Fast mode**<br>**I2C-bus**|**Fast mode**<br>**I2C-bus**|**Fast mode Plus**<br>**I2C-bus**|**Fast mode Plus**<br>**I2C-bus**|**Unit**|
|---|---|---|---|---|---|---|---|
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|fSCL<br>SCL clock frequency|0<br>100<br>0<br>400<br>0<br>1000<br>kHz|||||||
|tBUF<br>bus free time between a<br>STOP and START condition|4.7<br>-<br>1.3<br>-<br>0.5<br>-<br>s|||||||
|tHD;STA<br>hold time (repeated) START<br>condition|4.0<br>-<br>0.6<br>-<br>0.26<br>-<br>s|||||||
|tSU;STA<br>set-up time for a repeated<br>START condition|4.7<br>-<br>0.6<br>-<br>0.26<br>-<br>s|||||||
|tSU;STO<br>set-up time for STOP<br>condition|4.0<br>-<br>0.6<br>-<br>0.26<br>-<br>s|||||||
|tHD;DAT<br>data hold time|0<br>-<br>0<br>-<br>0<br>-<br>ns|||||||
|tVD;ACK<br>data valid acknowledge time<br>[1]|0.3<br>3.45<br>0.1<br>0.9<br>0.05<br>0.45<br>s|||||||
|tVD;DAT<br>data valid time<br>[2]|300<br>-<br>50<br>-<br>50<br>450<br>ns|||||||
|tSU;DAT<br>data set-up time|250<br>-<br>100<br>-<br>50<br>-<br>ns|||||||
|tLOW<br>LOW period of the SCL clock|4.7<br>-<br>1.3<br>-<br>0.5<br>-<br>s|||||||
|tHIGH<br>HIGH period of the SCL<br>clock|4.0<br>-<br>0.6<br>-<br>0.26<br>-<br>s|||||||
|tf<br>fall time of both SDA and<br>SCL signals<br>[3]<br>[4]|-<br>300<br>20 + 0.1Cb[5]<br>300<br>-<br>120<br>ns|||||||
|tr<br>rise time of both SDA and<br>SCL signals|-<br>1000<br>20 + 0.1Cb[5]<br>300<br>-<br>120<br>ns|||||||
|tSP<br>pulse width of spikes that<br>must be suppressed by the<br>input filter<br>[6]|-<br>50<br>-<br>50<br>-<br>50<br>ns|||||||
|**Port timing; CL****100 pF (see Figure 14**<br>**andFigure 15**<br>**)**||||||||
|tv(Q)<br>data output valid time|-<br>4<br>-<br>4<br>-<br>4<br>s|||||||
|tsu(D)<br>data input set-up time|0<br>-<br>0<br>-<br>0<br>-<br>s|||||||
|th(D)<br>data input hold time|4<br>-<br>4<br>-<br>4<br>-<br>s|||||||
|**Interrupt timing; CL****100 pF (see Figure 14**<br> **andFigure**|**15**<br>**)**|||||||
|tv(D)<br>data input valid time|-<br>4<br>-<br>4<br>-<br>4<br>s|||||||
|td(rst)<br>reset delay time|-<br>4<br>-<br>4<br>-<br>4<br>s|||||||



[1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. 

[2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. 

[3] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the undefined region SCL’s falling edge. 

[4] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. 

[5] Cb = total capacitance of one bus line in pF. 

- [6] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns. 

© NXP B.V. 2011. All rights reserved. 

PCA9675 

All information provided in this document is subject to legal disclaimers. 

**Rev. 2 — 3 October 2011** 

**Product data sheet** 

**22 of 34** 

**PCA9675** 

**NXP Semiconductors** 

**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

**==> picture [397 x 175] intentionally omitted <==**

**----- Start of picture text -----**<br>
START bit 7 STOP<br>protocol condition MSB bit 6 bit 0 acknowledge condition<br>(A6) (R/W) (A)<br>(S) (A7) (P)<br>tSU;STA tLOW tHIGH<br>1 / fSCL<br>SCL 0.7 × VDD<br>0.3 × VDD<br>tBUF tf<br>tr<br>SDA 0.7 × VDD<br>0.3 × VDD<br>tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO<br>002aab175<br>Rise and fall times refer to VIL and VIH.<br>**----- End of picture text -----**<br>


**Fig 24. I[2] C-bus timing diagram** 

© NXP B.V. 2011. All rights reserved. 

PCA9675 

All information provided in this document is subject to legal disclaimers. 

**Rev. 2 — 3 October 2011** 

**Product data sheet** 

**23 of 34** 

**PCA9675** 

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**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

## **14. Package outline** 

**==> picture [285 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
SO24: plastic small outline package; 24 leads; body width 7.5 mm<br>**----- End of picture text -----**<br>


**==> picture [43 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
SOT137-1<br>**----- End of picture text -----**<br>


**==> picture [488 x 603] intentionally omitted <==**

**----- Start of picture text -----**<br>
D E A<br>X<br>c<br>y HE v M A<br>Z<br>24 13<br>Q<br>A2 A<br>A1 (A  )3<br>pin 1 index<br>θ<br>L p<br>L<br>1 12 detail X<br>e w M<br>b p<br>0 5 10 mm<br>scale<br>DIMENSIONS (inch dimensions are derived from the original mm dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(1)] e HE L Lp Q v w y Z (1) θ<br>0.3 2.45 0.49 0.32 15.6 7.6 10.65 1.1 1.1 0.9<br>mm 2.65 0.1 2.25 0.25 0.36 0.23 15.2 7.4 1.27 10.00 1.4 0.4 1.0 0.25 0.25 0.1 0.4 8o<br>0.012 0.096 0.019 0.013 0.61 0.30 0.419 0.043 0.043 0.035 0o<br>inches 0.1 0.01 0.05 0.055 0.01 0.01 0.004<br>0.004 0.089 0.014 0.009 0.60 0.29 0.394 0.016 0.039 0.016<br>Note<br>1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.<br>OUTLINE  REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION  IEC  JEDEC  JEITA PROJECTION<br>99-12-27<br> SOT137-1  075E05  MS-013<br>03-02-19<br>Package outline SOT137-1 (SO24)<br>All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.<br>**----- End of picture text -----**<br>


**Fig 25. Package outline SOT137-1 (SO24)** PCA9675 

**Product data sheet Rev. 2 — 3 October 2011** 

**24 of 34** 

**PCA9675** 

**NXP Semiconductors** 

**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

## **TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm** 

**SOT355-1** 

**==> picture [479 x 570] intentionally omitted <==**

**----- Start of picture text -----**<br>
D E A<br>X<br>c<br>y HE v M A<br>Z<br>24 13<br>Q<br>A2 (A  )3 A<br>pin 1 index A1<br>θ<br>L p<br>L<br>1 12<br>detail X<br>w M<br>e b p<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(2)] e HE L Lp Q v w y Z (1) θ<br>0.15 0.95 0.30 0.2 7.9 4.5 6.6 0.75 0.4 0.5 8o<br>mm 1.1 0.05 0.80 0.25 0.19 0.1 7.7 4.3 0.65 6.2 1 0.50 0.3 0.2 0.13 0.1 0.2 0o<br>Notes<br>1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.<br>2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.<br>OUTLINE  REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION  IEC  JEDEC  JEITA PROJECTION<br>99-12-27<br> SOT355-1  MO-153<br>03-02-19<br>**----- End of picture text -----**<br>


**Fig 26. Package outline SOT355-1 (TSSOP24)** PCA9675 All information provided in this document is subject to legal disclaimers. 

All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. 

**Product data sheet Rev. 2 — 3 October 2011** 

**25 of 34** 

**PCA9675** 

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**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

**DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm** 

**==> picture [43 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
SOT815-1<br>**----- End of picture text -----**<br>


**==> picture [478 x 559] intentionally omitted <==**

**----- Start of picture text -----**<br>
D B A<br>A<br>E A1<br>c<br>detail X<br>terminal 1<br>index area<br>C<br>terminal 1 e1<br>index area e b v M C A B y1 C y<br>w M C<br>2 11<br>L<br>12<br>1<br>Eh e2<br>24<br>13<br>23 14<br>Dh X<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>A [(1)]<br>UNIT max. A1 b c D [(1)] Dh E [(1)] Eh e e1 e2 L v w y y1<br>0.05 0.30 5.6 4.25 3.6 2.25 0.5<br>mm 1 0.2 0.5 4.5 1.5 0.1 0.05 0.05 0.1<br>0.00 0.18 5.4 3.95 3.4 1.95 0.3<br>Note<br>1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.<br>OUTLINE  REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION  IEC  JEDEC  JEITA PROJECTION<br> SOT815-1 - - - - - - - - - 03-04-29<br>**----- End of picture text -----**<br>


**Fig 27. Package outline SOT815-1 (DHVQFN24)** PCA9675 All information provided in this document is subject to legal disclaimers. 

All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. 

**Product data sheet Rev. 2 — 3 October 2011** 

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**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

**HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm** 

**==> picture [43 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
SOT616-1<br>**----- End of picture text -----**<br>


**==> picture [478 x 559] intentionally omitted <==**

**----- Start of picture text -----**<br>
D B A<br>terminal 1<br>index area<br>A<br>A1<br>E c<br>detail X<br>e1 C<br>1/2 e<br>e b v M C A B y1 C y<br>7 12 w M C<br>L<br>13<br>6<br>e<br>Eh e2<br>1/2 e<br>1<br>18<br>terminal 1<br>index area 24 19<br>Dh X<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>A [(1)]<br>UNIT max. A1 b c D [(1)] Dh E [(1)] Eh e e1 e2 L v w y y1<br>0.05 0.30 4.1 2.25 4.1 2.25 0.5<br>mm 1 0.2 0.5 2.5 2.5 0.1 0.05 0.05 0.1<br>0.00 0.18 3.9 1.95 3.9 1.95 0.3<br>Note<br>1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.<br>OUTLINE  REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION  IEC  JEDEC  JEITA PROJECTION<br>01-08-08<br> SOT616-1 - - - MO-220 - - -<br>02-10-22<br>**----- End of picture text -----**<br>


**Fig 28. Package outline SOT616-1 (HVQFN24)** PCA9675 All information provided in this document is subject to legal disclaimers. 

All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. 

**Product data sheet Rev. 2 — 3 October 2011** 

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**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

## **15. Handling information** 

All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in _JESD625-A_ or equivalent standards. 

## **16. Soldering of SMD packages** 

This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note _AN10365 “Surface mount reflow soldering description”_ . 

## **16.1 Introduction to soldering** 

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 

## **16.2 Wave and reflow soldering** 

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: 

- Through-hole components 

- Leaded or leadless SMDs, which are glued to the surface of the printed circuit board 

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. 

The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. 

Key characteristics in both wave and reflow soldering are: 

- Board specifications, including the board finish, solder masks and vias 

- Package footprints, including solder thieves and orientation 

- The moisture sensitivity level of the packages 

- Package placement 

- Inspection and repair 

- Lead-free soldering versus SnPb soldering 

## **16.3 Wave soldering** 

Key characteristics in wave soldering are: 

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PCA9675 

**Rev. 2 — 3 October 2011** 

**Product data sheet** 

**28 of 34** 

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**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

- Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave 

- Solder bath specifications, including temperature and impurities 

## **16.4 Reflow soldering** 

Key characteristics in reflow soldering are: 

- Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 29) than a SnPb process, thus reducing the process window 

- Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board 

- Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 7 and 8 

## **Table 7. SnPb eutectic process (from J-STD-020C)** 

|**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**|
|---|---|---|
||**Volume (mm3)**||
||**< 350**|**350**|
|< 2.5|235<br>220||
|2.5|220<br>220||



## **Table 8. Lead-free process (from J-STD-020C)** 

|**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**|
|---|---|---|---|
||**Volume (mm3)**|||
||**< 350**|**350 to 2000**|**> 2000**|
|< 1.6|260<br>260<br>260|||
|1.6 to 2.5|260<br>250<br>245|||
|> 2.5|250<br>245<br>245|||



Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. 

Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 29. 

© NXP B.V. 2011. All rights reserved. 

PCA9675 

All information provided in this document is subject to legal disclaimers. 

**Rev. 2 — 3 October 2011** 

**Product data sheet** 

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## **Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

**==> picture [352 x 223] intentionally omitted <==**

**----- Start of picture text -----**<br>
maximum peak temperature<br>= MSL limit, damage level<br>temperature<br>minimum peak temperature<br>= minimum soldering temperature<br>peak<br> temperature<br>time<br>001aac844<br>MSL: Moisture Sensitivity Level<br>Fig 29. Temperature profiles for large and small components<br>**----- End of picture text -----**<br>


For further information on temperature profiles, refer to Application Note _AN10365 “Surface mount reflow soldering description”_ . 

## **17. Abbreviations** 

## **Table 9. Abbreviations** 

|**Acronym**|**Description**|
|---|---|
|CDM|Charged-Device Model|
|CMOS|Complementary Metal-Oxide Semiconductor|
|ESD|ElectroStatic Discharge|
|GPIO|General Purpose Input/Output|
|HBM|Human Body Model|
|LED|Light Emitting Diode|
|ID|Identification|
|LSB|Least Significant Bit|
|MSB|Most Significant Bit|
|PLC|Programmable Logic Controller|
|RAID|Redundant Array of Independent Disks|



© NXP B.V. 2011. All rights reserved. 

PCA9675 

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**Product data sheet** 

**30 of 34** 

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**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

## **18. Revision history** 

|**Table 10.**|**Revision**|**history**||
|---|---|---|---|
|**Document**|**ID**|**Release date**<br>**Data sheet status**<br>**Change notice**|**Supersedes**|
|PCA9675 v.2||20111003<br>Product data sheet<br>-|PCA9675 v.1|
|Modifications:||**•** removed discontinued type numbers PCA9675DB (SSOP24) and PCA9675DK (SSOP24 [also||
|||known as QSOP24])||
|||**•** Section 2“<br>Features and benefits<br>”<br>:||
|||**–**<br>13th bullet item: deleted phrase “200 V MM per JESD22-A115”||
|||**–**<br>15th bullet item: deleted “SSOP24, QSOP24”||
|||**•** Table 1“<br>Ordering information<br>”<br>:||
|||**–**<br>deleted type number PCA9675DB (and table note [1])||
|||**–**<br>deleted type number PCA9675DK (and table note [2])||
|||**•** Section 6.1“<br>Pinning<br>”<br>:||
|||**–**<br>deleted (old) Figure 5, “Pin configuration for SSOP24 (QSOP24)”||
|||**–**<br>deleted (old) Figure 6, “Pin configuration for SSOP24”||
|||**•** Table 2“<br>Pin description<br>”<br>:deleted “SSOP” from heading of second column||
|||**•** Figure 24“<br>~~I~~<br>2<br>C-bus timing diagram<br>”<br> modified: added 0.7VDDand 0.3VDDlevel lines||
|||**•** Section 14“<br>Package outline<br>”<br>:||
|||**–**<br>deleted (old) Figure 28, “Package outline SOT340-1 (SSOP24)”||
|||**–**<br>deleted (old) Figure 29, “Package outline SOT556-1 (SSOP24)”||
|PCA9675 v.1||20070201<br>Product data sheet<br>-|-|



© NXP B.V. 2011. All rights reserved. 

PCA9675 

All information provided in this document is subject to legal disclaimers. **Rev. 2 — 3 October 2011** 

**Product data sheet** 

**31 of 34** 

**PCA9675** 

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**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

## **19. Legal information** 

## **19.1 Data sheet status** 

|**Document status[1]**<br>**[2]**|**Product statu**~~**s**~~**[3]**|**Definition**|
|---|---|---|
|Objective [short] data sheet|Development|This document contains data from the objective specification for product development.|
|Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.|
|Product [short] data sheet|Production|This document contains the product specification.|



[1] Please consult the most recently issued document before initiating or completing a design. 

[2] The term ‘short data sheet’ is explained in section “Definitions”. 

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 

## **19.2 Definitions** 

**Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 

**Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 

**Product specification —** The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 

## **19.3 Disclaimers** 

**Limited warranty and liability —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. 

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors. 

**Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 

**Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or 

malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 

**Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. 

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. 

**Limiting values —** Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 

**Terms and conditions of commercial sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 

**No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 

**Export control —** This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 

PCA9675 All information provided in this document is subject to legal disclaimers. **Product data sheet Rev. 2 — 3 October 2011** 

© NXP B.V. 2011. All rights reserved. 

**32 of 34** 

**PCA9675** 

**NXP Semiconductors** 

## **Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

**Non-automotive qualified products —** Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. 

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s 

own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 

## **19.4 Trademarks** 

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 

**I[2] C-bus  —** logo is a trademark of NXP B.V. 

## **20. Contact information** 

For more information, please visit: **http://www.nxp.com** 

For sales office addresses, please send an email to: **salesaddresses@nxp.com** 

© NXP B.V. 2011. All rights reserved. 

PCA9675 

All information provided in this document is subject to legal disclaimers. 

**Rev. 2 — 3 October 2011** 

**Product data sheet** 

**33 of 34** 

**PCA9675** 

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**Remote 16-bit I/O expander for Fm+ I[2] C-bus with interrupt** 

## **21. Contents** 

|**1**|**General description . . . . . . . . . . . . . . . . . . . . . .  1**|
|---|---|
|**2**|**Features and benefits . . . . . . . . . . . . . . . . . . . .  1**|
|**3**|**Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .  2**|
|**4**|**Ordering information. . . . . . . . . . . . . . . . . . . . .  2**|
|**5**|**Block diagram  . . . . . . . . . . . . . . . . . . . . . . . . . .  3**|
|**6**|**Pinning information. . . . . . . . . . . . . . . . . . . . . .  4**|
|6.1|Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4|
|6.2|Pin description  . . . . . . . . . . . . . . . . . . . . . . . . .  5|
|**7**|**Functional description  . . . . . . . . . . . . . . . . . . .  6**|
|7.1|Device address. . . . . . . . . . . . . . . . . . . . . . . . .  6|
|7.1.1|Address maps. . . . . . . . . . . . . . . . . . . . . . . . . .  6|
|7.2|Software Reset call, and Device ID|
||addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  8|
|7.2.1|Software Reset . . . . . . . . . . . . . . . . . . . . . . . . .  9|
|7.2.2|Device ID (PCA9675 ID field) . . . . . . . . . . . . .  10|
|**8**|**I/O programming . . . . . . . . . . . . . . . . . . . . . . .  12**|
|8.1|Quasi-bidirectional I/O architecture  . . . . . . . .  12|
|8.2|Writing to the port (Output mode) . . . . . . . . . .  12|
|8.3|Reading from a port (Input mode)  . . . . . . . . .  13|
|8.4|Power-on reset . . . . . . . . . . . . . . . . . . . . . . . .  16|
|8.5|Interrupt output (INT<br>)  . . . . . . . . . . . . . . . . . . .  16|
|**9**|**Characteristics of the I2C-bus  . . . . . . . . . . . .  17**|
|9.1|Bit transfer  . . . . . . . . . . . . . . . . . . . . . . . . . . .  17|
|9.1.1|START and STOP conditions . . . . . . . . . . . . .  17|
|9.2|System configuration  . . . . . . . . . . . . . . . . . . .  17|
|9.3|Acknowledge  . . . . . . . . . . . . . . . . . . . . . . . . .  18|
|**10**|**Application design-in information . . . . . . . . .  19**|
|10.1|Bidirectional I/O expander applications  . . . . .  19|
|10.2|High current-drive load applications . . . . . . . .  19|
|10.3|Differences between the PCA9675 and the|
||PCF8575  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20|
|**11**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . .  20**|
|**12**|**Static characteristics. . . . . . . . . . . . . . . . . . . .  21**|
|**13**|**Dynamic characteristics . . . . . . . . . . . . . . . . .  22**|
|**14**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . .  24**|
|**15**|**Handling information. . . . . . . . . . . . . . . . . . . .  28**|
|**16**|**Soldering of SMD packages . . . . . . . . . . . . . .  28**|
|16.1|Introduction to soldering . . . . . . . . . . . . . . . . .  28|
|16.2|Wave and reflow soldering . . . . . . . . . . . . . . .  28|
|16.3|Wave soldering. . . . . . . . . . . . . . . . . . . . . . . .  28|
|16.4|Reflow soldering . . . . . . . . . . . . . . . . . . . . . . .  29|
|**17**|**Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . .  30**|
|**18**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . .  31**|
|**19**|**Legal information. . . . . . . . . . . . . . . . . . . . . . .  32**|



|19.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . .  32|
|---|---|
|19.2|Definitions  . . . . . . . . . . . . . . . . . . . . . . . . . . .  32|
|19.3|Disclaimers  . . . . . . . . . . . . . . . . . . . . . . . . . .  32|
|19.4|Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .  33|
|**20**|**Contact information  . . . . . . . . . . . . . . . . . . . .  33**|
|**21**|**Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  34**|



Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 

**© NXP B.V. 2011.** 

**All rights reserved.** 

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 3 October 2011 Document identifier: PCA9675**