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PCA9557D,112
I/O Expander, 8bit, 400 kHz, I2C, SMBus, 2.3 V, 5.5 V, SOIC
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- Manufacturer: NXP
- Product type: I/O Expanders
- No. of Pins: 16Pins
- No. of I/O's: 8I/O's
- Bus Frequency: 400kHz
- IC Interface Type: I2C, SMBus
- Chip Configuration: 8bit
- Supply Voltage Max: 5.5V
- Supply Voltage Min: 2.3V
- Interface Case Style: SOIC
| Delivery and price | |
|---|---|
| Units per pack | 2500 |
| Price | 0.419 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
**Product data sheet** ## **PCA9557** ## **8-bit I[2] C-bus and SMBus I/O port with reset** **Rev. 7 — 10 December 2013** ## **1. General description** The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for SMBus and I[2] C-bus applications. The PCA9557 consists of an 8-bit input port register, 8-bit output port register, and an I[2] C-bus/SMBus interface. It has low current consumption and a high-impedance open-drain output pin, IO0. The system master can enable the PCA9557’s I/O as either input or output by writing to the configuration register. The system master can also invert the PCA9557 inputs by writing to the active HIGH polarity inversion register. Finally, the system master can reset the PCA9557 in the event of a time-out by asserting a LOW in the reset input. The power-on reset puts the registers in their default state and initializes the I[2] C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without de-powering the part. ## **2. Features and benefits** - Lower voltage, higher performance migration path for the PCA9556 - 8 general purpose input/output expander/collector - Input/output configuration register - Active HIGH polarity inversion register - I[2] C-bus and SMBus interface logic - Internal power-on reset - Noise filter on SCL/SDA inputs - Active LOW reset input - 3 address pins allowing up to 8 devices on the I[2] C-bus/SMBus - High-impedance open-drain on IO0 - No glitch on power-up - Power-up with all channels configured as inputs - Low standby current - Operating power supply voltage range of 2.3 V to 5.5 V - 5 V tolerant inputs/outputs - 0 kHz to 400 kHz clock frequency - ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101 - Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA - Three packages offered: SO16, TSSOP16, HVQFN16 **==> picture [172 x 101] intentionally omitted <==** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** ## **3. Ordering information** ## **Table 1. Ordering information** |**Type number**|**Topside**<br>**marking**|**Package**|**Package**|**Package**| |---|---|---|---|---| |||**Name**|**Description**|**Version**| |PCA9557BS<br>9557||HVQFN16<br>plastic thermal enhanced very thin quad flat package; no leads;<br>16 terminals; body 440.85 mm<br>SOT629-1||| |PCA9557D<br>PCA9557D||SO16<br>plastic small outline package; 16 leads; body width 3.9 mm<br>SOT109-1||| |PCA9557PW<br>PCA9557||TSSOP16<br>plastic thin shrink small outline package; 16 leads;<br>body width 4.4 mm<br>SOT403-1||| ## **3.1 Ordering options** ## **Table 2. Ordering options** |**Type number**|**Orderable**<br>**part number**<br>**Package**<br>**Packing method**<br>**Minimum**<br>**order**<br>**quantity**<br>**Temperature range**| |---|---| |PCA9557BS|PCA9557BS,118<br>HVQFN16<br>Reel 13” Q1/T1<br>*Standard mark SMD<br>6000<br>Tamb=40C to +85C| |PCA9557D|PCA9557D,112<br>SO16<br>Standard marking<br>* IC’s tube - DSC bulk pack<br>1000<br>Tamb=40C to +85C| ||PCA9557D,118<br>SO16<br>Reel 13” Q1/T1<br>*Standard mark SMD<br>2500<br>Tamb=40C to +85C| |PCA9557PW|PCA9557PW,112<br>TSSOP16<br>Standard marking<br>* IC’s tube - DSC bulk pack<br>2400<br>Tamb=40C to +85C| ||PCA9557PW,118<br>TSSOP16<br>Reel 13” Q1/T1<br>*Standard mark SMD<br>2500<br>Tamb=40C to +85C| ## **4. Block diagram** **==> picture [352 x 160] intentionally omitted <==** **----- Start of picture text -----**<br> PCA9557<br>A0<br>IO0<br>A1<br>IO1<br>A2<br>8-bit IO2<br>SCL INPUT INPUT/ IO3<br>SDA FILTER I [2] C-BUS/SMBus OUTPUT IO4<br>CONTROL<br>write pulse PORTS IO5<br>IO6<br>VDD read pulse IO7<br>VSS POWER-ON<br>RESET<br>RESET<br>002aad275<br>**----- End of picture text -----**<br> **Fig 1. Block diagram of PCA9557** © NXP B.V. 2013. All rights reserved. PCA9557 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 7 — 10 December 2013** **2 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** **==> picture [379 x 330] intentionally omitted <==** **----- Start of picture text -----**<br> data from<br>shift register<br>configuration<br>register<br>data from<br>D Q<br>shift register<br>FF output port<br>register data<br>write configuration D Q<br>CK Q<br>pulse<br>FF<br>IO0<br>write pulse CK<br>ESD protection<br>output port diode<br>register<br>VSS<br>input port<br>register<br>D Q input port<br>register data<br>FF<br>CK<br>read pulse<br>polarity inversion<br>register<br>data from<br>D Q polarity inversion<br>shift register<br>register data<br>FF<br>write polarity<br>CK<br>pulse<br>002aad277<br>On power-up or reset, all registers return to default values.<br>**----- End of picture text -----**<br> **Fig 2. Simplified schematic of IO0** © NXP B.V. 2013. All rights reserved. PCA9557 **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 7 — 10 December 2013** **3 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** **==> picture [379 x 330] intentionally omitted <==** **----- Start of picture text -----**<br> data from<br>shift register output port<br>register data<br>configuration<br>register VDD<br>data from<br>D Q<br>shift register<br>FF ESD protection<br>diode<br>write configuration D Q<br>CK Q<br>pulse<br>FF<br>IO1 to IO7<br>write pulse CK<br>ESD protection<br>output port diode<br>register<br>VSS<br>input port<br>register<br>D Q input port<br>register data<br>FF<br>CK<br>read pulse<br>polarity inversion<br>register<br>data from<br>D Q polarity inversion<br>shift register<br>register data<br>FF<br>write polarity<br>CK<br>pulse<br>002aad278<br>On power-up or reset, all registers return to default values.<br>**----- End of picture text -----**<br> **Fig 3. Simplified schematic of IO1 to IO7** © NXP B.V. 2013. All rights reserved. PCA9557 **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 7 — 10 December 2013** **4 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** ## **5. Pinning information** ## **5.1 Pinning** **==> picture [397 x 366] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 16 VDD<br>SDA 2 15 RESET<br>A0 3 14 IO7<br>SCL 1 16 VDD<br>A1 4 13 IO6 SDA 2 15 RESET<br>PCA9557D A0 3 14 IO7<br>A2 5 12 IO5<br>A1 4 13 IO6<br>PCA9557PW<br>IO0 6 11 IO4 A2 5 12 IO5<br>IO0 6 11 IO4<br>IO1 7 10 IO3<br>IO1 7 10 IO3<br>VSS 8 9 IO2 VSS 8 9 IO2<br>002aad272 002aad273<br>Fig 4. Pin configuration for SO16 Fig 5. Pin configuration for TSSOP16<br>terminal 1<br>index area<br>A0 1 12 IO7<br>A1 2 11 IO6<br>PCA9557BS<br>A2 3 10 IO5<br>IO0 4 9 IO4<br>002aad274<br>Transparent top view<br>DD<br>SDA SCL V RESET<br>16 15 14 13<br>5 6 7 8<br>IO1 VSS IO2 IO3<br>**----- End of picture text -----**<br> **Fig 6. Pin configuration for HVQFN16** ## **5.2 Pin description** ## **Table 3. Pin description** |**Symbol**|**Pin**|**Pin**|**Description**| |---|---|---|---| ||**SO16, TSSOP16**|**HVQFN16**|| |SCL|1<br>15<br>serial clock line||| |SDA|2<br>16<br>serial data line||| |A0|3<br>1<br>address input 0||| |A1|4<br>2<br>address input 1||| |A2|5<br>3<br>address input 2||| |IO0|6<br>4<br>input/output 0 (open-drain)||| |IO1|7<br>5<br>input/output 1||| All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. PCA9557 **Product data sheet** **Rev. 7 — 10 December 2013** **5 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** **Table 3. Pin description** _…continued_ |**Symbol**|**Pin**|**Pin**|**Description**| |---|---|---|---| ||**SO16, TSSOP16**|**HVQFN16**|| |VSS|8<br>~~6~~[1]<br>supply ground||| |IO2|9<br>7<br>input/output 2||| |IO3|10<br>8<br>input/output 3||| |IO4|11<br>9<br>input/output 4||| |IO5|12<br>10<br>input/output 5||| |IO6|13<br>11<br>input/output 6||| |IO7|14<br>12<br>input/output 7||| |RESET|15<br>13<br>active LOW reset input||| |VDD|16<br>14<br>supply voltage||| - [1] HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to the supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region. ## **6. System diagram** **==> picture [447 x 268] intentionally omitted <==** **----- Start of picture text -----**<br> INPUT POLARITY CONFIG. OUTPUT<br>PORT INVERSION PORT<br>1.1 k Ω<br>1.1 k Ω<br>Q7 Q7 Q7 Q7 IO0<br>RESET<br>Q6 Q6 Q6 Q6 IO1<br>1.6 k Ω<br>SCL<br>Q5 Q5 Q5 Q5 IO2<br>1.6 k Ω I [2] C-BUS/SMBus<br>INTERFACE Q4 Q4 Q4 Q4 IO3<br>SDA<br>LOGIC<br>1.1 k Ω Q3 Q3 Q3 Q3 IO4<br>or<br>A2<br>Q2 Q2 Q2 Q2 IO5<br>1.1 k Ω<br>A1 or Q1 Q1 Q1 Q1 IO6<br>1.1 k Ω Q0 Q0 Q0 Q0 IO7<br>or<br>A0<br>002aad276<br>**----- End of picture text -----**<br> **Fig 7. System diagram** © NXP B.V. 2013. All rights reserved. PCA9557 **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 7 — 10 December 2013** **6 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** ## **7. Functional description** “ ” Refer to Figure 1 Block diagram of PCA9557 . ## **7.1 Device address** Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9557 is shown in Figure 8. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. **==> picture [138 x 57] intentionally omitted <==** **----- Start of picture text -----**<br> slave address<br>0 0 1 1 A2 A1 A0 R/W<br>fixed programmable<br>002aad279<br>**----- End of picture text -----**<br> **==> picture [143 x 9] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 8. PCA9557 device address<br>**----- End of picture text -----**<br> The last bit of the slave address defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. ## **7.2 Control register** Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9557, which will be stored in the control register. This register can be written and read via the I[2] C-bus. **==> picture [266 x 57] intentionally omitted <==** **----- Start of picture text -----**<br> bit: 7 6 5 4 3 2 1 0<br>0 0 0 0 0 0 D1 D0<br>002aad280<br>Fig 9. Control register<br>**----- End of picture text -----**<br> |**Table**|**4.**|**Register definition**|**Register definition**||| |---|---|---|---|---|---| |**D1**||**D0**|**Name**|**Access**|**Description**| |0||0|Register 0|read-only|Input port register| |0||1|Register 1|read/write|Output port register| |1||0|Register 2|read/write|Polarity inversion register| |1||1|Register 3|read/write|Configuration register| © NXP B.V. 2013. All rights reserved. PCA9557 All information provided in this document is subject to legal disclaimers. **Rev. 7 — 10 December 2013** **Product data sheet** **7 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** ## **7.3 Register descriptions** ## **7.3.1 Register 0 - Input port register** This register is a read-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. Writes to this register have no effect. |**Table 5.**<br>**Register 0 - Input port register bit allocation**|**Table 5.**<br>**Register 0 - Input port register bit allocation**|**Table 5.**<br>**Register 0 - Input port register bit allocation**|**Table 5.**<br>**Register 0 - Input port register bit allocation**|**Table 5.**<br>**Register 0 - Input port register bit allocation**|**Table 5.**<br>**Register 0 - Input port register bit allocation**|**Table 5.**<br>**Register 0 - Input port register bit allocation**|**Table 5.**<br>**Register 0 - Input port register bit allocation**|**Table 5.**<br>**Register 0 - Input port register bit allocation**| |---|---|---|---|---|---|---|---|---| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||| |**Symbol**|I7|I6|I5|I4|I3|I2|I1|I0| ## **7.3.2 Register 1 - Output port register** This register reflects the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, **not** the actual pin value. **Table 6. Register 1 - Output port register bit allocation** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|O7|O6|O5|O4|O3|O2|O1|O0| |**Default**|0<br>0<br>0<br>0<br>0<br>0<br>0<br>0|||||||| ## **7.3.3 Register 2 - Polarity inversion register** This register enables polarity inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with logic 1), the corresponding port pin’s polarity is inverted. If a bit in this register is cleared (written with logic 0), the corresponding port pin’s original polarity is retained. **Table 7. Register 2 - Polarity inversion register bit allocation** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|N7|N6|N5|N4|N3|N2|N1|N0| |**Default**|1<br>1<br>1<br>1<br>0<br>0<br>0<br>0|||||||| ## **7.3.4 Register 3 - Configuration register** This register configures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. **Table 8. Register 3 - Configuration register bit allocation** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|C7|C6|C5|C4|C3|C2|C1|C0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||||||| © NXP B.V. 2013. All rights reserved. PCA9557 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 7 — 10 December 2013** **8 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** ## **7.4 Power-on reset** When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9557 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9557 registers and I[2] C-bus/SMBus state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. ## **7.5 RESET input** A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The PCA9557 registers and SMBus/I[2] C-bus state machine will be held in their default state until the RESET input is once again HIGH. This input requires a pull-up resistor to VDD if no active connection is used. ## **8. Characteristics of the I[2] C-bus** The I[2] C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. ## **8.1 Bit transfer** One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 10). **==> picture [312 x 110] intentionally omitted <==** **----- Start of picture text -----**<br> SDA<br>SCL<br>data line change<br>stable; of data<br>data valid allowed mba607<br>Fig 10. Bit transfer<br>**----- End of picture text -----**<br> ## **8.1.1 START and STOP conditions** Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 11). © NXP B.V. 2013. All rights reserved. PCA9557 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 7 — 10 December 2013** **9 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** **==> picture [351 x 98] intentionally omitted <==** **----- Start of picture text -----**<br> SDA<br>SCL<br>S P<br>START condition STOP condition<br>mba608<br>Fig 11. Definition of START and STOP conditions<br>**----- End of picture text -----**<br> ## **8.2 System configuration** A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 12). **==> picture [457 x 133] intentionally omitted <==** **----- Start of picture text -----**<br> SDA<br>SCL<br>MASTER SLAVE SLAVE MASTER MASTER I [2] C-BUS<br>TRANSMITTER/ RECEIVER TRANSMITTER/ TRANSMITTER TRANSMITTER/ MULTIPLEXER<br>RECEIVER RECEIVER RECEIVER<br>SLAVE<br>002aaa966<br>Fig 12. System configuration<br>**----- End of picture text -----**<br> ## **8.3 Acknowledge** The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. © NXP B.V. 2013. All rights reserved. PCA9557 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 7 — 10 December 2013** **10 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** **==> picture [297 x 117] intentionally omitted <==** **----- Start of picture text -----**<br> data output<br>by transmitter<br>not acknowledge<br>data output<br>by receiver<br>acknowledge<br>SCL from master<br>1 2 8 9<br>S<br>clock pulse for<br>START acknowledgement<br>condition 002aaa987<br>**----- End of picture text -----**<br> **Fig 13. Acknowledgement on the I[2] C-bus** ## **8.4 Bus transactions** Data is transmitted to the PCA9557 registers using Write Byte transfers (see Figure 14 and Figure 15). Data is read from the PCA9557 registers using Read and Receive Byte transfers (see Figure 16 and Figure 17). **==> picture [422 x 133] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>STOP<br>condition<br>slave address command byte data to port<br>SDA S 0 0 1 1 A2 A1 A0 0 A 0 0 0 0 0 0 0 1 A DATA 1 A P<br>START condition R/W acknowledge acknowledge acknowledge<br>from slave from slave from slave<br>write to port<br>tv(Q)<br>data out from port DATA 1 VALID<br>002aad281<br>**----- End of picture text -----**<br> ## **Fig 14. Write to output port register** **==> picture [421 x 93] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>STOP<br>condition<br>slave address command byte data to register<br>SDA S 0 0 1 1 A2 A1 A0 0 A 0 0 0 0 0 0 1 1/0 A DATA A P<br>START condition R/W acknowledge acknowledge acknowledge<br>from slave from slave from slave<br>002aad282<br>**----- End of picture text -----**<br> **Fig 15. Write to I/O configuration or polarity inversion registers** All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. PCA9557 **Product data sheet** **Rev. 7 — 10 December 2013** **11 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** **==> picture [433 x 155] intentionally omitted <==** **----- Start of picture text -----**<br> slave address command byte<br>SDA S 0 0 1 1 A2 A1 A0 0 A A (cont.)<br>START condition R/W acknowledge<br>acknowledge from slave<br>from slave<br>slave address data from register data from register<br>(cont.) S 0 0 1 1 A2 A1 A0 1 A DATA (first byte) A DATA (last byte) NA P<br>(repeated) R/W acknowledge no acknowledge STOP<br>START condition acknowledge from master from master condition<br>from slave<br>at this moment master-transmitter becomes master-receiver<br>and slave-receiver becomes slave-transmitter<br>002aad283<br>**----- End of picture text -----**<br> **==> picture [117 x 10] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 16. Read from register<br>**----- End of picture text -----**<br> **==> picture [443 x 144] intentionally omitted <==** **----- Start of picture text -----**<br> no acknowledge<br>from master<br>slave address data from port data from port<br>SDA S 0 0 1 1 A2 A1 A0 1 A DATA 1 A DATA 4 NA P<br>START condition R/W acknowledge acknowledge STOP<br>from slave from master condition<br>read from<br>port<br>th(D) tsu(D)<br>data into<br>DATA 1 DATA 2 DATA 3 DATA 4<br>port<br>002aad284<br>**----- End of picture text -----**<br> **Remark:** This figure assumes the command byte has previously been programmed with 00h. Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input data is lost. **Fig 17. Read input port register** © NXP B.V. 2013. All rights reserved. PCA9557 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 7 — 10 December 2013** **12 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** ## **9. Application design-in information** **==> picture [471 x 342] intentionally omitted <==** **----- Start of picture text -----**<br> VDD (5 V)<br>100 k Ω<br>1.8 k Ω 1.8 k Ω 2 k Ω 2 k Ω 620 Ω<br>( × 5)<br>VDD VDD<br>MASTER<br>PCA9557<br>CONTROLLER SUBSYSTEM 1<br>SCL SCL IO0 (e.g., temp. sensor)<br>SDA SDA IO1 INT<br>IO2<br>RESET<br>RESET RESET IO3<br>SUBSYSTEM 2<br>IO4<br>(e.g., counter)<br>VSS IO5<br>IO6 A<br>IO7<br>enable controlled switch<br>A2 (e.g., CBT device)<br>A1<br>A0 B<br>VSS ALARM<br>SUBSYSTEM 3<br>(e.g., alarm system)<br>VDD<br>002aad285<br>Device address configured as 0011 100x for this example.<br>IO0, IO2, IO3 configured as outputs.<br>IO1, IO4, IO5 configured as inputs.<br>IO6, IO7 are not used.<br>Fig 18. Typical application<br>**----- End of picture text -----**<br> ## **9.1 Minimizing IDD when the I/Os are used to control LEDs** When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 18. Since the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower than VDD. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 19 shows a high value resistor in parallel with the LED. Figure 20 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VDD and prevents additional supply current consumption when the LED is off. © NXP B.V. 2013. All rights reserved. PCA9557 All information provided in this document is subject to legal disclaimers. **Rev. 7 — 10 December 2013** **Product data sheet** **13 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** **==> picture [312 x 116] intentionally omitted <==** **----- Start of picture text -----**<br> 3.3 V 5 V<br>VDD<br>VDD LED 100 k Ω VDD LED<br>IOn IOn<br>002aac660 002aac661<br>**----- End of picture text -----**<br> **Fig 19. High value resistor in parallel with Fig 20. Device supplied by a lower voltage the LED** ## **10. Limiting values** ## **Table 9. Limiting values** _In accordance with the Absolute Maximum Rating System (IEC 60134)._ |**Symbol**<br>**Parameter**|**Conditions**|**Min**<br>**Max**<br>**Unit**| |---|---|---| |VDD<br>supply voltage||0.5<br>+6<br>V| |VI<br>input voltage||VSS0.5<br>5.5<br>V| |II<br>input current||-<br>20<br>mA| |IIHL(max)<br>maximum allowed input current<br>through protection diode (IO1 to IO7)|VIVDDor VIVSS|-<br>400<br>A| |VI/O<br>voltage on an input/output pin|I/O as an input, except IO0|VSS0.5<br>5.5<br>V| ||IO0 as an input|VSS0.5<br>5.5<br>V| |II/O<br>input/output current|IO0 as an input|-<br>+400<br>A| |||-<br>20<br>mA| |IO(IOn)<br>output current on pin IOn||-<br>50<br>mA| |IDD<br>supply current||-<br>85<br>mA| |ISS<br>ground supply current||-<br>100<br>mA| |Ptot<br>total power dissipation||-<br>200<br>mW| |Tstg<br>storage temperature||65<br>+150<br>C| |Tamb<br>ambient temperature|operating|40<br>+85<br>C| © NXP B.V. 2013. All rights reserved. PCA9557 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 7 — 10 December 2013** **14 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** ## **11. Static characteristics** **Table 10. Static characteristics** _VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb =_ _40_ _C to +85_ _C; unless otherwise specified._ |**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**| |---|---| |**Supplies**|| |VDD<br>supply voltage|2.3<br>-<br>5.5<br>V| |IDD<br>supply current|operating mode; VDD= 5.5 V;<br>no load; fSCL= 100 kHz<br>-<br>19<br>25<br>A| |IstbL<br>LOW-level standby current|standby mode; VDD= 5.5 V;<br>no load; VI= VSS; fSCL= 0 kHz;<br>I/O = inputs<br>-<br>0.25<br>1<br>A| |IstbH<br>HIGH-level standby current|standby mode; VDD= 5.5 V;<br>no load; VI= VDD; fSCL= 0 kHz;<br>I/O = inputs<br>-<br>0.25<br>1<br>A| |Istb<br>additional standby current|standby mode; VDD= 5.5 V;<br>every LED I/O at VI= 4.3 V;<br>fSCL= 0 kHz<br>-<br>0.8<br>1<br>mA| |VPOR<br>power-on reset voltage|no load; VI= VDDor VSS<br>[1]<br>-<br>1.65<br>2.1<br>V| |**Input SCL; input/output SDA**|| |VIL<br>LOW-level input voltage|0.5<br>-<br>+0.3VDD<br>V| |VIH<br>HIGH-level input voltage|0.7VDD<br>-<br>5.5<br>V| |IOL<br>LOW-level output current|VOL= 0.4 V; VDD= 2.3 V<br>3<br>-<br>-<br>mA| |IL<br>leakage current|VI= VDDor VSS<br>1<br>-<br>+1<br>A| |Ci<br>input capacitance|VI= VSS<br>-<br>6<br>10<br>pF| |**I/Os**|| |VIL<br>LOW-level input voltage|0.5<br>-<br>+0.8<br>V| |VIH<br>HIGH-level input voltage|2.0<br>-<br>5.5<br>V| |IOL<br>LOW-level output current|VOL= 5.5 V; VDD= 2.3 V<br>[2]<br>8<br>10<br>-<br>mA| |IOH<br>HIGH-level output current|except pin IO0; VOH= 2.4 V<br>[3]<br>4<br>-<br>-<br>mA| ||pin IO0; VOH= 4.6 V<br>-<br>-<br>1<br>A| ||pin IO0; VOH= 3.3 V<br>-<br>-<br>1<br>A| |ILI<br>input leakage current|VDD= 5.5 V; VI= VSS<br>-<br>-<br>100<br>A| |Ci<br>input capacitance|-<br>3.7<br>5<br>pF| |Co<br>output capacitance|-<br>3.7<br>5<br>pF| |**Select inputs A0, A1, A2 and RESET**|| |VIL<br>LOW-level input voltage|0.5<br>-<br>+0.8<br>V| |VIH<br>HIGH-level input voltage|2.0<br>-<br>5.5<br>V| |ILI<br>input leakage current|1<br>-<br>+1<br>A| [1] VDD must be lowered to 0.2 V in order to reset part. [2] The total amount sunk by all I/Os must be limited to 100 mA and 25 mA per bit. [3] The total current sourced by all I/Os must be limited to 85 mA and 20 mA per bit. © NXP B.V. 2013. All rights reserved. PCA9557 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 7 — 10 December 2013** **15 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** ## **12. Dynamic characteristics** ## **Table 11. Dynamic characteristics** |**Symbol**<br>**Parameter**|**Conditions**|**Standard-mode**<br>**I2C-bus**|**Standard-mode**<br>**I2C-bus**|**Fast-mode I2C-bus**|**Fast-mode I2C-bus**|**Unit**| |---|---|---|---|---|---|---| |||**Min**|**Max**|**Min**|**Max**|| |fSCL<br>SCL clock frequency||0<br>100<br>0<br>400<br>kHz||||| |tBUF<br>bus free time between a STOP and<br>START condition||4.7<br>-<br>1.3<br>-<br>s||||| |tHD;STA<br>hold time (repeated) START condition||4.0<br>-<br>0.6<br>-<br>s||||| |tSU;STA<br>set-up time for a repeated START<br>condition||4.7<br>-<br>0.6<br>-<br>s||||| |tSU;STO<br>set-up time for STOP condition||4.0<br>-<br>0.6<br>-<br>s||||| |tHD;DAT<br>data hold time||0<br>-<br>0<br>-<br>ns||||| |tVD;ACK<br>data valid acknowledge time|[1]|-<br>1<br>-<br>0.9<br>s||||| |tVD;DAT<br>data valid time|[2]|-<br>1<br>-<br>0.9<br>s||||| |tSU;DAT<br>data set-up time||250<br>-<br>100<br>-<br>ns||||| |tLOW<br>LOW period of the SCL clock||4.7<br>-<br>1.3<br>-<br>s||||| |tHIGH<br>HIGH period of the SCL clock||4.0<br>-<br>0.6<br>-<br>s||||| |tf<br>fall time of both SDA and SCL signals||-<br>300<br>20 + 0.1Cb[3]<br>300<br>ns||||| |tr<br>rise time of both SDA and SCL signals||-<br>1000<br>20 + 0.1Cb[3]<br>300<br>ns||||| |tSP<br>pulse width of spikes that must be<br>suppressed by the input filter||-<br>50<br>-<br>50<br>ns||||| |**Port timing**||||||| |tv(Q)<br>data output valid time|pin IO0|-<br>250<br>-<br>250<br>ns||||| ||pins IO1 to IO7|-<br>200<br>-<br>200<br>ns||||| |tsu(D)<br>data input set-up time||0<br>-<br>0<br>-<br>ns||||| |th(D)<br>data input hold time||200<br>-<br>200<br>-<br>ns||||| |**Reset timing**||||||| |tw(rst)<br>reset pulse width||6<br>-<br>6<br>-<br>ns||||| |trec(rst)<br>reset recovery time||0<br>-<br>0<br>-<br>ns||||| |trst<br>reset time||400<br>-<br>400<br>-<br>ns||||| [1] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW. [2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. [3] Cb = total capacitance of one bus line in pF. © NXP B.V. 2013. All rights reserved. PCA9557 All information provided in this document is subject to legal disclaimers. **Rev. 7 — 10 December 2013** **Product data sheet** **16 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** **==> picture [479 x 133] intentionally omitted <==** **----- Start of picture text -----**<br> 0.7 × VDD<br>SDA<br>0.3 × VDD<br>tBUF tr tf tHD;STA tSP<br>tLOW<br>0.7 × VDD<br>SCL<br>0.3 × VDD<br>tHD;STA tSU;STA tSU;STO<br>P S tHD;DAT tHIGH tSU;DAT Sr P<br>002aaa986<br>**----- End of picture text -----**<br> **Fig 21. Definition of timing on the I[2] C-bus** **==> picture [396 x 179] intentionally omitted <==** **----- Start of picture text -----**<br> START ACK or read cycle<br>SCL<br>SDA<br>30 %<br>trst<br>RESET 50 % 50 % 50 %<br>trec(rst) tw(rst)<br>trst<br>IOn 50 % I/O configured<br>as inputs<br>002aad289<br>**----- End of picture text -----**<br> **Fig 22. Definition of RESET timing** © NXP B.V. 2013. All rights reserved. PCA9557 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 7 — 10 December 2013** **17 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** ## **13. Package outline** **Fig 23. Package outline SOT109-1 (SO16)** PCA9557 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 7 — 10 December 2013** **==> picture [84 x 5] intentionally omitted <==** **----- Start of picture text -----**<br> © NXP B.V. 2013. All rights reserved.<br>**----- End of picture text -----**<br> **18 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** **Fig 24. Package outline SOT403-1 (TSSOP16)** PCA9557 All information provided in this document is subject to legal disclaimers. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. **Rev. 7 — 10 December 2013** **Product data sheet** **19 of 30** **PCA9557 8-bit I[2] C-bus and SMBus I/O port with reset** **NXP Semiconductors** **==> picture [37 x 17] intentionally omitted <==** **----- Start of picture text -----**<br> UNIT A()<br>max.<br>**----- End of picture text -----**<br> **==> picture [199 x 10] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 25. Package outline SOT629-1 (HVQFN16)<br>**----- End of picture text -----**<br> PCA9557 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 7 — 10 December 2013** © NXP B.V. 2013. All rights reserved. **20 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** ## **14. Handling information** All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in _JESD625-A_ or equivalent standards. ## **15. Soldering of SMD packages** This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note _AN10365 “Surface mount reflow soldering description”_ . ## **15.1 Introduction to soldering** Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. ## **15.2 Wave and reflow soldering** Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: - Through-hole components - Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: - Board specifications, including the board finish, solder masks and vias - Package footprints, including solder thieves and orientation - The moisture sensitivity level of the packages - Package placement - Inspection and repair - Lead-free soldering versus SnPb soldering ## **15.3 Wave soldering** Key characteristics in wave soldering are: All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. PCA9557 **Product data sheet** **Rev. 7 — 10 December 2013** **21 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** - Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave - Solder bath specifications, including temperature and impurities ## **15.4 Reflow soldering** Key characteristics in reflow soldering are: - Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 26) than a SnPb process, thus reducing the process window - Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board - Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13 ## **Table 12. SnPb eutectic process (from J-STD-020D)** |**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**| |---|---|---| ||**Volume (mm3)**|| ||**< 350**|**350**| |< 2.5|235<br>220|| |2.5|220<br>220|| ## **Table 13. Lead-free process (from J-STD-020D)** |**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**| |---|---|---|---| ||**Volume (mm3)**||| ||**< 350**|**350 to 2000**|**> 2000**| |< 1.6|260<br>260<br>260||| |1.6 to 2.5|260<br>250<br>245||| |> 2.5|250<br>245<br>245||| Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 26. © NXP B.V. 2013. All rights reserved. PCA9557 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 7 — 10 December 2013** **22 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** **==> picture [352 x 223] intentionally omitted <==** **----- Start of picture text -----**<br> maximum peak temperature<br>= MSL limit, damage level<br>temperature<br>minimum peak temperature<br>= minimum soldering temperature<br>peak<br> temperature<br>time<br>001aac844<br>MSL: Moisture Sensitivity Level<br>Fig 26. Temperature profiles for large and small components<br>**----- End of picture text -----**<br> For further information on temperature profiles, refer to Application Note _AN10365 “Surface mount reflow soldering description”_ . © NXP B.V. 2013. All rights reserved. PCA9557 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 7 — 10 December 2013** **23 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** ## **16. Soldering: PCB footprints** **==> picture [260 x 10] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 27. PCB footprint for SOT109-1 (SO16); reflow soldering<br>**----- End of picture text -----**<br> PCA9557 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. **Product data sheet** **Rev. 7 — 10 December 2013** **24 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** ## **Fig 28. PCB footprint for SOT403-1 (TSSOP16); reflow soldering** © NXP B.V. 2013. All rights reserved. PCA9557 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 7 — 10 December 2013** **25 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** ## **Fig 29. PCB footprint for SOT629-1 (HVQFN16); reflow soldering** All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. PCA9557 **Product data sheet** **Rev. 7 — 10 December 2013** **26 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** ## **17. Abbreviations** ## **Table 14. Abbreviations** |**Acronym**|**Description**| |---|---| |CBT|Cross Bar Technology| |CDM|Charged-Device Model| |CMOS|Complementary Metal-Oxide Semiconductor| |ESD|ElectroStatic Discharge| |HBM|Human Body Model| |I2C-bus|Inter-Integrated Circuit bus| |I/O|Input/Output| |LED|Light-Emitting Diode| |MM|Machine Model| |PCB|Printed-Circuit Board| |POR|Power-On Reset| |SMBus|System Management Bus| ## **18. Revision history** ## **Table 15. Revision history** |**Document ID**|**Release date**|**Data sheet status**|**Change notice**|**Supersedes**| |---|---|---|---|---| |PCA9557 v.7|20131210|Product data sheet|-|PCA9557 v.6| |Modifications:|**•** Section 2“<br>Features and benefits<br>”<br>,17th bullet item: deleted phrase “150 V MM per JESD22-A115”|||| ||**•** Table 1“<br>Ordering information<br>”<br>:added column ‘Topside marking’ (moved fromTable 2<br>)|||| ||**•** Table 2“<br>Ordering options<br>”<br>:|||| ||**–**<br>deleted column|‘Topside mark’ (moved to|Table 1<br>)|| ||**–**<br>added columns|‘Orderable part number’, ‘Package’, ‘Packing method’ and ‘Minimum order||| ||quantity’|||| ||**•** Table 10“<br>Static characteristics<br>”<br>,sub-section||“Input SCL; input/output SDA”:|| ||**–**<br>IOL: added “VDD|= 2.3 V” to Conditions||| ||**•** Table 10“<br>Static characteristics<br>”<br>,sub-section||“I/Os”:|| ||**–**<br>IOL: added “VOL|= 0.55 V; VDD= 2.3 V” to|Conditions|| ||**•** Table 11“<br>Dynamic characteristics<br>”<br>,tVD;DAT: Unit corrected from “ms” to “s” (this is a correction to|||| ||documentation only, no change to device)|||| ||**•** AddedSection 16“<br>Soldering: PCB footprints<br>”|||| |||||| |PCA9557 v.6|20080611|Product data sheet|-|PCA9557 v.5| |PCA9557 v.5|20070912|Product data sheet|-|PCA9557 v.4| |PCA9557 v.4|20041124|Product data sheet|-|PCA9557 v.3| |(9397 750 13336)||||| |PCA9557 v.3|20021213|Product data|ECN 853-2308 29160|PCA9557 v.2| |(9397 750 10872)|||of 06 Nov 2002|| |PCA9557 v.2|20020513|Product data|ECN 853-2308 28188|PCA9557 v.1| |(9397 750 09819)|||of 13 May 2002|| |PCA9557 v.1|20011212|Product data|ECN 853-2308 27449|-| ||||of 12 Dec 2001|| All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. PCA9557 **Product data sheet** **Rev. 7 — 10 December 2013** **27 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** ## **19. Legal information** ## **19.1 Data sheet status** |**Document status[1]**<br>**[2]**|**Product statu**~~**s**~~**[3]**|**Definition**| |---|---|---| |Objective [short] data sheet|Development|This document contains data from the objective specification for product development.| |Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.| |Product [short] data sheet|Production|This document contains the product specification.| [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. ## **19.2 Definitions** **Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. **Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. **Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. **Product specification —** The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. ## **19.3 Disclaimers** **Limited warranty and liability —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. **Limiting values —** Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. **Terms and conditions of commercial sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors. **Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. © NXP B.V. 2013. All rights reserved. PCA9557 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 7 — 10 December 2013** **28 of 30** **PCA9557** **NXP Semiconductors** ## **8-bit I[2] C-bus and SMBus I/O port with reset** **Export control —** This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. **Non-automotive qualified products —** Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. **Translations —** A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. ## **19.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. **I[2] C-bus —** logo is a trademark of NXP B.V. ## **20. Contact information** For more information, please visit: **http://www.nxp.com** For sales office addresses, please send an email to: **salesaddresses@nxp.com** © NXP B.V. 2013. All rights reserved. PCA9557 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 7 — 10 December 2013** **29 of 30** **PCA9557** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus I/O port with reset** ## **21. Contents** |**1**|**General description . . . . . . . . . . . . . . . . . . . . . . 1**| |---|---| |**2**|**Features and benefits . . . . . . . . . . . . . . . . . . . . 1**| |**3**|**Ordering information. . . . . . . . . . . . . . . . . . . . . 2**| |3.1|Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2| |**4**|**Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2**| |**5**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . 5**| |5.1|Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5| |5.2|Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5| |**6**|**System diagram . . . . . . . . . . . . . . . . . . . . . . . . . 6**| |**7**|**Functional description . . . . . . . . . . . . . . . . . . . 7**| |7.1|Device address. . . . . . . . . . . . . . . . . . . . . . . . . 7| |7.2|Control register . . . . . . . . . . . . . . . . . . . . . . . . . 7| |7.3|Register descriptions . . . . . . . . . . . . . . . . . . . . 8| |7.3.1|Register 0 - Input port register . . . . . . . . . . . . . 8| |7.3.2|Register 1 - Output port register . . . . . . . . . . . . 8| |7.3.3|Register 2 - Polarity inversion register . . . . . . . 8| |7.3.4|Register 3 - Configuration register . . . . . . . . . . 8| |7.4|Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9| |7.5|RESET<br>input. . . . . . . . . . . . . . . . . . . . . . . . . . . 9| |**8**|**Characteristics of the I2C-bus . . . . . . . . . . . . . 9**| |8.1|Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9| |8.1.1|START and STOP conditions . . . . . . . . . . . . . . 9| |8.2|System configuration . . . . . . . . . . . . . . . . . . . 10| |8.3|Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 10| |8.4|Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 11| |**9**|**Application design-in information . . . . . . . . . 13**| |9.1|Minimizing IDDwhen the I/Os are used to| ||control LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . 13| |**10**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14**| |**11**|**Static characteristics. . . . . . . . . . . . . . . . . . . . 15**| |**12**|**Dynamic characteristics . . . . . . . . . . . . . . . . . 16**| |**13**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18**| |**14**|**Handling information. . . . . . . . . . . . . . . . . . . . 21**| |**15**|**Soldering of SMD packages . . . . . . . . . . . . . . 21**| |15.1|Introduction to soldering . . . . . . . . . . . . . . . . . 21| |15.2|Wave and reflow soldering . . . . . . . . . . . . . . . 21| |15.3|Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 21| |15.4|Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 22| |**16**|**Soldering: PCB footprints. . . . . . . . . . . . . . . . 24**| |**17**|**Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 27**| |**18**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . . 27**| |**19**|**Legal information. . . . . . . . . . . . . . . . . . . . . . . 28**| |19.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28| |19.2|Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28| |19.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 28| |---|---| |19.4|Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 29| |**20**|**Contact information . . . . . . . . . . . . . . . . . . . . 29**| |**21**|**Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30**| Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **© NXP B.V. 2013.** **All rights reserved.** **Date of release: 10 December 2013 Document identifier: PCA9557**
Updated at February 9, 2023
NXP Semiconductors is a global leader in secure connectivity solutions, driving innovation across the automotive, industrial, IoT, mobile, and communications infrastructure markets. By developing advanced, purpose-built technologies, NXP enables devices to sense, think, connect, and act intelligently, delivering rigorously tested components that make the connected world safer and more efficient. Within the semiconductor space, NXP is highly regarded for its extensive range of high-performance integrated circuits and discrete devices. The brand's portfolio excels in drivers and interfaces, featuring a comprehensive selection of I/O expanders designed to streamline complex system architectures. For demanding high-frequency and wireless applications, NXP provides industry-leading RF FETs and RF/PIN diodes engineered to deliver exceptional signal integrity, efficiency, and reliability. The NXP product lineup further extends to essential discrete components, including versatile bipolar transistors, JFETs, and small signal diodes optimized for precision switching and amplification. Additionally, the portfolio supports advanced automation and smart applications with precision IC sensors, such as MEMS accelerometers, alongside specialized power management solutions like AC/DC LED driver ICs and single MOSFETs for cutting-edge electronics design.
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