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PCA9539BS,115
I/O Expander, 16bit, 400 kHz, I2C, SMBus, 2.3 V, 5.5 V, HVQFN
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- Manufacturer: NXP
- Product type: I/O Expanders
- No. of Pins: 24Pins
- No. of I/O's: 16I/O's
- Bus Frequency: 400kHz
- IC Interface Type: I2C, SMBus
- Chip Configuration: 16bit
- Supply Voltage Max: 5.5V
- Supply Voltage Min: 2.3V
- Interface Case Style: HVQFN
| Delivery and price | |
|---|---|
| Units per pack | 1000 |
| Price | 1.07 € |
| Current stock | 1000+ |
| Lead time | 7 days |
Datasheet
## **PCA9539; PCA9539R 16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **Rev. 8.2 — 27 February 2017** **Product data sheet** ## **1. General description** The PCA9539; PCA9539R is a 24-pin CMOS device that provides 16 bits of General Purpose parallel Input/Output (GPIO) expansion with interrupt and reset for I[2] C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I[2] C-bus I/O expanders. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc. The PCA9539; PCA9539R consists of two 8-bit configuration (input or output selection), input, output and polarity inversion (active HIGH or active LOW operation) registers. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity inversion register. All registers can be read by the system master. The PCA9539; PCA9539R is identical to the PCA9555 except for the removal of the internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are held LOW, replacement of A2 with RESET and a different address range. The PCA9539; PCA9539R open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. In the PCA9539, the RESET pin causes the same reset/default I/O input configuration to occur without de-powering the device, holding the registers and I[2] C-bus state machine in their default state until the RESET input is once again HIGH. This input requires a pull-up to VDD. In the PCA9539R however, only the device state machine is initialized by the RESET pin and the internal general-purpose registers remain unchanged. Using the PCA9539R RESET pin will only reset the I[2] C-bus interface should it be stuck LOW to regain access to the I[2] C-bus. This allows the I/O pins to retain their last configured state so that they can keep any lines in their previously defined state and not cause system errors while the I[2] C-bus is being restored. Two hardware pins (A0, A1) vary the fixed I[2] C-bus address and allow up to four devices to share the same I[2] C-bus/SMBus. ## **2. Features and benefits** - 16-bit I[2] C-bus GPIO with interrupt and reset - Operating power supply voltage range of 2.3 V to 5.5 V (3.0 V to 5.5 V for PCA9539PW/Q900 and PCA9539RPW/Q900) - 5 V tolerant I/Os **==> picture [172 x 101] intentionally omitted <==** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** - Polarity inversion register - Active LOW interrupt output - Active LOW reset input - Low standby current - Noise filter on SCL/SDA inputs - No glitch on power-up - Internal power-on reset - 16 I/O pins which default to 16 inputs - 0 Hz to 400 kHz clock frequency - ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101 - Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA - Offered in three different packages: SO24, TSSOP24, and HVQFN24 ## **3. Ordering information** ## **Table 1. Ordering information** |**Type number**|**Topside**<br>**marking**|**Package**|**Package**|**Package**| |---|---|---|---|---| |||**Name**|**Description**|**Version**| |PCA9539BS|9539|HVQFN24|plastic thermal enhanced very thin quad flat package;<br>no leads; 24 terminals; body 440.85 mm|SOT616-1| |PCA9539RBS|539R|HVQFN24|plastic thermal enhanced very thin quad flat package;<br>no leads; 24 terminals; body 440.85 mm|SOT616-1| |PCA9539D|PCA9539D|SO24|plastic small outline package; 24 leads;<br>body width 7.5 mm|SOT137-1| |PCA9539PW|PCA9539PW|TSSOP24|plastic thin shrink small outline package; 24 leads;<br>body width 4.4 mm|SOT355-1| |PCA9539PW/Q900[1]|PCA9539PW|TSSOP24|plastic thin shrink small outline package; 24 leads;<br>body width 4.4 mm|SOT355-1| |PCA9539RPW|PA9539RPW|TSSOP24|plastic thin shrink small outline package; 24 leads;<br>body width 4.4 mm|SOT355-1| |PCA9539RPW/Q900[1]|PA9539RPW|TSSOP24|plastic thin shrink small outline package; 24 leads;<br>body width 4.4 mm|SOT355-1| [1] PCA9539PW/Q900 and PCA9539RPW/Q900 are AEC-Q100 compliant. Contact **I2C.support@nxp.com** for PPAP. ## **3.1 Ordering options** **Table 2. Ordering options** |**Type number**|**Orderable**<br>**part number**|**Package**|**Packing method**|**Minimum**<br>**order**<br>**quantity**|**Temperature**| |---|---|---|---|---|---| |PCA9539BS|PCA9539BS,115|HVQFN24|Reel 7” Q1/T1<br>*standard mark SM~~D~~[1]|1500|Tamb=40C to +85C| ||PCA9539BS,118|HVQFN24|Reel 13” Q1/T1<br>*standard mark SM~~D~~[1]|6000|Tamb=40C to +85C| ||PCA9539BSHP|HVQFN24|Reel 13” Q2/T3<br>*standard mark SM~~D~~[2]|6000|Tamb=40C to +85C| All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** **Rev. 8.2 — 27 February 2017** **2 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **Table 2. Ordering options** _…continued_ |**Type number**|**Orderable**<br>**part number**|**Package**|**Packing method**|**Minimum**<br>**order**<br>**quantity**|**Temperature**| |---|---|---|---|---|---| |PCA9539RBS|PCA9539RBS,118|HVQFN24|Reel 13” Q1/T1<br>*standard mark SM~~D~~[1]|6000|Tamb=40C to +85C| |PCA9539D|PCA9539D,112|SO24|Standard marking *<br>IC’s tube -<br>DSC bulk pack|1200|Tamb=40C to +85C| ||PCA9539D,118|SO24|Reel 13” Q1/T1<br>*standard mark SM~~D~~[1]|1000|Tamb=40C to +85C| |PCA9539PW|PCA9539PW,112|TSSOP24|Standard marking *<br>IC’s tube -<br>DSC bulk pack|1575|Tamb=40C to +85C| ||PCA9539PW,118|TSSOP24|Reel 13” Q1/T1<br>*standard mark SM~~D~~[1]|2500|Tamb=40C to +85C| |PCA9539PW/Q900|PCA9539PW/Q900,118|TSSOP24|Reel 13” Q1/T1<br>*standard mark SM~~D~~[1]|2500|Tamb=40C to +125C| |PCA9539RPW|PCA9539RPW,118|TSSOP24|Reel 13” Q1/T1<br>*standard mark SM~~D~~[1]|2500|Tamb=40C to +85C| |PCA9539RPW/Q900|PCA9539RPWJ|TSSOP24|Reel 13” Q1/T1<br>*standard mark SM~~D~~[1]|2500|Tamb=40C to +125C| [1] Pin 1 in Quadrant 1; see Figure 2. [2] Pin 1 in Quadrant 2; see Figure 3. ## **3.1.1 Pin 1 quadrant indication** **==> picture [396 x 214] intentionally omitted <==** **----- Start of picture text -----**<br> way into<br>the reel Q1 Q2 Quadrant designations round<br>Q1 = upper left sprocket<br>Q2 = upper right holes<br>Q3 = lower left<br>Q3 Q4<br>Q4 = lower right<br>aaa-010180<br>Fig 1. Carrier tape pin 1 quadrant designations<br>����� �����<br>���������� ����������<br>Fig 2. Pin 1 in Q1 Fig 3. Pin 1 in Q2<br>**----- End of picture text -----**<br> © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 8.2 — 27 February 2017** **3 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** ## **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **4. Block diagram** **==> picture [378 x 321] intentionally omitted <==** **----- Start of picture text -----**<br> PCA9539<br>IO1_0<br>PCA9539R<br>IO1_1<br>A0 8-bit IO1_2<br>A1 INPUT/ IO1_3<br>OUTPUT<br>PORTS IO1_4<br>write pulse IO1_5<br>IO1_6<br>read pulse<br>IO1_7<br>I [2] C-BUS/SMBus<br>CONTROL<br>SCL INPUT IO0_0<br>FILTER IO0_1<br>SDA 8-bit IO0_2<br>INPUT/ IO0_3<br>OUTPUT<br>PORTS IO0_4<br>write pulse IO0_5<br>IO0_6<br>read pulse<br>VDD POWER-ON IO0_7<br>RESET<br>RESET VDD<br>VSS<br>LP INT<br>FILTER<br>002aad722<br>Remark: All I/Os are set to inputs at reset.<br>Fig 4. Block diagram of PCA9539; PCA9539R<br>**----- End of picture text -----**<br> © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 8.2 — 27 February 2017** **4 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **5. Pinning information** ## **5.1 Pinning** **==> picture [396 x 419] intentionally omitted <==** **----- Start of picture text -----**<br> INT 1 24 VDD INT 1 24 VDD<br>A1 2 23 SDA A1 2 23 SDA<br>RESET 3 22 SCL RESET 3 22 SCL<br>IO0_0 4 21 A0 IO0_0 4 21 A0<br>IO0_1 5 20 IO1_7 IO0_1 5 20 IO1_7<br>IO0_2 6 19 IO1_6 IO0_2 6 PCA9539PW 19 IO1_6<br>PCA9539D PCA9539PW/Q900<br>IO0_3 7 18 IO1_5 IO0_3 7 PCA9539RPW 18 IO1_5<br>IO0_4 8 17 IO1_4 IO0_4 8 17 IO1_4<br>IO0_5 9 16 IO1_3 IO0_5 9 16 IO1_3<br>IO0_6 10 15 IO1_2 IO0_6 10 15 IO1_2<br>IO0_7 11 14 IO1_1 IO0_7 11 14 IO1_1<br>VSS 12 13 IO1_0 VSS 12 13 IO1_0<br>002aad719 002aad720<br>Fig 5. Pin configuration for SO24 Fig 6. Pin configuration for TSSOP24<br>PCA9539BS<br>PCA9539RBS<br>terminal 1<br>index area<br>IO0_0 1 18 A0<br>IO0_1 2 17 IO1_7<br>IO0_2 3 16 IO1_6<br>IO0_3 4 15 IO1_5<br>IO0_4 5 14 IO1_4<br>IO0_5 6 13 IO1_3<br>002aad721<br>Transparent top view<br>Fig 7. Pin configuration for HVQFN24<br>DD<br>RESET A1 INT V SDA SCL<br>24 23 22 21 20 19<br>7 8 9 10 11 12<br>SS<br>V<br>IO0_6 IO0_7 IO1_0 IO1_1 IO1_2<br>**----- End of picture text -----**<br> © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 8.2 — 27 February 2017** **5 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **5.2 Pin description** |**Pin description**|**Pin description**|**Pin description**|**Pin description**| |---|---|---|---| |**Table 3.**<br>**Pin description**|||| |**Symbol**|**Pin**||**Description**| ||**SO24, TSSOP24**|**HVQFN24**|| |INT|1|22|interrupt output (open-drain)| |A1|2|23|address input 1| |RESET|3|24|active LOW reset input. Driving this pin LOW<br>causes:<br>**•** PCA9539 to reset its state machine and<br>registers<br>**•** PCA9539R to reset its state machine, but<br>has no effect on its registers| |IO0_0|4|1|port 0 input/output 0| |IO0_1|5|2|port 0 input/output 1| |IO0_2|6|3|port 0 input/output 2| |IO0_3|7|4|port 0 input/output 3| |IO0_4|8|5|port 0 input/output 4| |IO0_5|9|6|port 0 input/output 5| |IO0_6|10|7|port 0 input/output 6| |IO0_7|11|8|port 0 input/output 7| |VSS|12|~~9~~[1]|supply ground| |IO1_0|13|10|port 1 input/output 0| |IO1_1|14|11|port 1 input/output 1| |IO1_2|15|12|port 1 input/output 2| |IO1_3|16|13|port 1 input/output 3| |IO1_4|17|14|port 1 input/output 4| |IO1_5|18|15|port 1 input/output 5| |IO1_6|19|16|port 1 input/output 6| |IO1_7|20|17|port 1 input/output 7| |A0|21|18|address input 0| |SCL|22|19|serial clock line input| |SDA|23|20|serial data line open-drain input/output| |VDD|24|21|supply voltage| - [1] HVQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 8.2 — 27 February 2017** **6 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **6. Functional description** “ ” Refer to Figure 4 Block diagram of PCA9539; PCA9539R . ## **6.1 Device address** **==> picture [138 x 56] intentionally omitted <==** **----- Start of picture text -----**<br> slave address<br>1 1 1 0 1 A1 A0 R/W<br>fixed programmable<br>002aad724<br>**----- End of picture text -----**<br> **Fig 8. PCA9539; PCA9539R device address** ## **6.2 Registers** ## **6.2.1 Command byte** The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read. ## **Table 4. Command byte** |**Command**|**Register**| |---|---| |0|Input port 0| |1|Input port 1| |2|Output port 0| |3|Output port 1| |4|Polarity inversion port 0| |5|Polarity inversion port 1| |6|Configuration port 0| |7|Configuration port 1| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 8.2 — 27 February 2017** **7 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **6.2.2 Registers 0 and 1: Input port registers** This register is an input-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default value ‘X’ is determined by the externally applied logic level. **Table 5. Input port 0 register** |**Bit**|**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|I0.7|I0.6|I0.5|I0.4|I0.3|I0.2|I0.1|I0.0| |**Default**|X|X|X|X|X|X|X|X| |**Table 6.**<br>**Input port 1 register**||||||||| |**Bit**|**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**| |**Symbol**|I1.7|I1.6|I1.5|I1.4|I1.3|I1.2|I1.1|I1.0| |**Default**|X|X|X|X|X|X|X|X| ## **6.2.3 Registers 2 and 3: Output port registers** This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Registers 6 and 7. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, **not** the actual pin value. ## **Table 7. Output port 0 register** |**Bit**|**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|O0.7|O0.6|O0.5|O0.4|O0.3|O0.2|O0.1|O0.0| |**Default**|1|1|1|1|1|1|1|1| |**Table 8.**<br>**Output port 1 register**||||||||| |**Bit**|**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**| |**Symbol**|O1.7|O1.6|O1.5|O1.4|O1.3|O1.2|O1.1|O1.0| |**Default**|1|1|1|1|1|1|1|1| ## **6.2.4 Registers 4 and 5: Polarity inversion registers** This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set (written with ‘1’), the Input port data polarity is inverted. If a bit in this register is cleared (written with a ‘0’), the Input port data polarity is retained. ## **Table 9. Polarity inversion port 0 register** |**Bit**|**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|N0.7|N0.6|N0.5|N0.4|N0.3|N0.2|N0.1|N0.0| |**Default**|0|0|0|0|0|0|0|0| |**Table 10.**<br>**Polarity inversion port 1 register**||||||||| |**Bit**|**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**| |**Symbol**|N1.7|N1.6|N1.5|N1.4|N1.3|N1.2|N1.1|N1.0| |**Default**|0|0|0|0|0|0|0|0| All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** **Rev. 8.2 — 27 February 2017** **8 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **6.2.5 Registers 6 and 7: Configuration registers** This register configures the directions of the I/O pins. If a bit in this register is set (written with ‘1’), the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin is enabled as an output. At reset, the device's ports are inputs. ## **Table 11. Configuration port 0 register** |**Bit**|**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|C0.7|C0.6|C0.5|C0.4|C0.3|C0.2|C0.1|C0.0| |**Default**|1|1|1|1|1|1|1|1| |**Table 12.**<br>**Configuration port 1 register**||||||||| |**Bit**|**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**| |**Symbol**|C1.7|C1.6|C1.5|C1.4|C1.3|C1.2|C1.1|C1.0| |**Default**|1|1|1|1|1|1|1|1| ## **6.3 Power-on reset** When power is applied to VDD, an internal power-on reset holds the PCA9539; PCA9539R in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9539; PCA9539R registers and SMBus state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the operating voltage. ## **6.4 RESET input** A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). In the PCA9539 the registers and SMBus/I[2] C-bus state machine will be held in their default state until the RESET input is once again HIGH. This input typically requires a pull-up to VDD. In the PCA9539R, only the device state machine is initialized. The internal general-purpose registers remain unchanged. Using the PCA9539R hardware reset pin will only reset the I[2] C-bus interface should it be stuck LOW to regain access to the I[2] C-bus. This allows the I/O pins to retain their last configured state so that they can keep any lines in their previously defined state and not cause system errors while the I[2] C-bus is being restored. ## **6.5 I/O port** When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of the Output port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance path that exists between the pin and either VDD or VSS. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 8.2 — 27 February 2017** **9 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **==> picture [377 x 306] intentionally omitted <==** **----- Start of picture text -----**<br> data from output port<br>shift register register data<br>configuration<br>register VDD<br>data from D Q Q1<br>shift register<br>FF<br>write<br>D Q<br>configuration CK Q<br>pulse FF<br>I/O pin<br>write pulse CK Q2<br>output port input port VSS<br>register register<br>D Q<br>input port<br>FF register data<br>read pulse CK<br>to INT<br>polarity inversion<br>register<br>data from<br>D Q polarity<br>shift register inversion<br>FF register data<br>write polarity<br>CK<br>pulse<br>002aad723<br>At power-on reset, all registers return to default values.<br>Fig 9. Simplified schematic of I/Os<br>**----- End of picture text -----**<br> ## **6.6 Bus transactions** ## **6.6.1 Writing to the port registers** Data is transmitted to the PCA9539; PCA9539R by sending the device address and setting the least significant bit to a logic 0 (see Figure 8 “PCA9539; PCA9539R device address”). The command byte is sent after the address and determines which register will receive the data following the command byte. The eight registers within the PCA9539; PCA9539R are configured to operate as four register pairs. The four pairs are Input ports, Output ports, Polarity inversion ports, and Configuration ports. After sending data to one register, the next data byte will be sent to the other register in the pair (see Figure 10 and Figure 11). For example, if the first byte is sent to Output port 1 (register 3), then the next byte will be stored in Output port 0 (register 2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register may be updated independently of the other registers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 8.2 — 27 February 2017** **10 of 38** **==> picture [534 x 176] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>slave address command byte data to port 0 data to port 1<br>SDA S 1 1 1 0 1 A1 A0 0 A 0 0 0 0 0 0 1 0 A 0.7 DATA 0 0.0 A 1.7 DATA 1 1.0 A P<br>START condition R/W acknowledge acknowledge acknowledge STOP<br>from slave from slave from slave condition<br>write to port<br>tv(Q)<br>data out<br>from port 0<br>tv(Q)<br>data out<br>from port 1 DATA VALID<br>002aad725<br>**----- End of picture text -----**<br> **Fig 10. Write to output port registers** **==> picture [511 x 91] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>data to register data to register<br>slave address command byte<br>MSB LSB MSB LSB<br>SDA S 1 1 1 0 1 A1 A0 0 A 0 0 0 0 0 1 1 0 A DATA 0 A DATA 1 A P<br>START condition R/W acknowledge acknowledge acknowledge STOP<br>from slave from slave from slave condition<br>002aad726<br>**----- End of picture text -----**<br> **Fig 11. Write to configuration registers** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **6.6.2 Reading the port registers** In order to read data from the PCA9539; PCA9539R, the bus master must first send the PCA9539; PCA9539R address with the least significant bit set to a logic 0 (see Figure 8 “PCA9539; PCA9539R device address”). The command byte is sent after the address and determines which register will be accessed. After a restart, the device address is sent again, but this time the least significant bit is set to a logic 1. Data from the register defined by the command byte will then be sent by the PCA9539; PCA9539R (see Figure 12, Figure 13 and Figure 14). Data is clocked into the register on the falling edge of the acknowledge clock pulse. After the first byte is read, additional bytes may be read but the data will now reflect the information in the other register in the pair. For example, if you read Input port 1, then the next byte read would be Input port 0. There is no limitation on the number of data bytes received in one read transmission but the final byte received, the bus master must not acknowledge the data. **==> picture [433 x 165] intentionally omitted <==** **----- Start of picture text -----**<br> slave address<br>SDA S 1 1 1 0 1 A1 A0 0 A COMMAND BYTE A (cont.)<br>START condition R/W acknowledge<br>acknowledge from slave<br>from slave<br>data from lower or data from upper or<br>upper byte of register lower byte of register<br>slave address<br>MSB LSB MSB LSB<br>(cont.) S 1 1 1 0 1 A1 A0 1 A DATA (first byte) A DATA (last byte) NA P<br>(repeated) R/W acknowledge no acknowledge STOP<br>START condition acknowledge from master from master condition<br>from slave<br>at this moment master-transmitter becomes master-receiver<br>and slave-receiver becomes slave-transmitter<br>002aad727<br>**----- End of picture text -----**<br> **Remark:** Transfer can be stopped at any time by a STOP condition. **Fig 12. Read from register** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 8.2 — 27 February 2017** **12 of 38** **==> picture [618 x 228] intentionally omitted <==** **----- Start of picture text -----**<br> data into port 0<br>data into port 1<br>INT<br>tv(INT_N) trst(INT_N)<br>SCL 1 2 3 4 5 6 7 8 9<br>R/W STOP condition<br>slave address I0.x I1.x I0.x I1.x<br>SDA S 1 1 1 0 1 A1 A0 1 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 1 P<br>START condition acknowledge acknowledge acknowledge acknowledge non acknowledge<br>from slave from master from master from master from master<br>read from port 0<br>read from port 1<br>002aad728<br>**----- End of picture text -----**<br> - **Remark:** Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to ‘00’ (read input port register). **Fig 13. Read input port register, scenario 1** **==> picture [618 x 220] intentionally omitted <==** **----- Start of picture text -----**<br> data into port 0 DATA 00 DATA 01 DATA 02 DATA 03<br>th(D) tsu(D)<br>data into port 1 DATA 10 DATA 11 DATA 12<br>th(D) tsu(D)<br>INT<br>tv(INT_N) trst(INT_N)<br>SCL 1 2 3 4 5 6 7 8 9<br>R/W STOP condition<br>slave address I0.x I1.x I0.x I1.x<br>SDA S 1 1 1 0 1 A1 A0 1 A DATA 00 A DATA 10 A DATA 03 A DATA 12 1 P<br>START condition acknowledge acknowledge acknowledge acknowledge non acknowledge<br>from slave from master from master from master from master<br>read from port 0<br>read from port 1<br>002aad729<br>**----- End of picture text -----**<br> **Remark:** Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to ‘00’ (read input port register). **Fig 14. Read input port register, scenario 2** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **6.6.3 Interrupt output** The open-drain interrupt output is activated when one of the port pins changes state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the Input port register is read (see Figure 13). A pin configured as an output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt caused by Port 0 will not be cleared by a read of Port 1 or the other way around. **Remark:** Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input port register. ## **7. Characteristics of the I[2] C-bus** The I[2] C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. ## **7.1 Bit transfer** One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 15). **==> picture [241 x 87] intentionally omitted <==** **----- Start of picture text -----**<br> SDA<br>SCL<br>data line change<br>stable; of data<br>data valid allowed mba607<br>**----- End of picture text -----**<br> **Fig 15. Bit transfer** ## **7.1.1 START and STOP conditions** Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 16). **==> picture [319 x 76] intentionally omitted <==** **----- Start of picture text -----**<br> SDA<br>SCL<br>S P<br>START condition STOP condition<br>mba608<br>**----- End of picture text -----**<br> **==> picture [214 x 9] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 16. Definition of START and STOP conditions<br>**----- End of picture text -----**<br> All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** **Rev. 8.2 — 27 February 2017** **15 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **7.2 System configuration** A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 17). **==> picture [432 x 109] intentionally omitted <==** **----- Start of picture text -----**<br> SDA<br>SCL<br>MASTER SLAVE SLAVE MASTER MASTER I [2] C-BUS<br>TRANSMITTER/ RECEIVER TRANSMITTER/ TRANSMITTER TRANSMITTER/ MULTIPLEXER<br>RECEIVER RECEIVER RECEIVER<br>SLAVE<br>002aaa966<br>**----- End of picture text -----**<br> **Fig 17. System configuration** ## **7.3 Acknowledge** The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold time must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. **==> picture [297 x 129] intentionally omitted <==** **----- Start of picture text -----**<br> data output<br>by transmitter<br>not acknowledge<br>data output<br>by receiver<br>acknowledge<br>SCL from master<br>1 2 8 9<br>S<br>clock pulse for<br>START acknowledgement<br>condition 002aaa987<br>**----- End of picture text -----**<br> **Fig 18. Acknowledgement on the I[2] C-bus** All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** **Rev. 8.2 — 27 February 2017** **16 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **8. Application design-in information** **==> picture [467 x 287] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>(5 V) SUB-SYSTEM 1<br>VDD 10 k Ω 10 k Ω 10 k Ω 10 k Ω VDD 2 k Ω 100 k( × 3) Ω (e.g., temp sensor)<br>MASTER INT<br>PCA9539<br>CONTROLLER<br>SCL SCL IO0_0<br>SUB-SYSTEM 2<br>SDA SDA IO0_1 (e.g., counter)<br>INT INT<br>IO0_2 RESET<br>RESET RESET<br>IO0_3<br>A<br>VSS IO0_4 enable controlled<br>switch<br>IO0_5 (e.g., CBT device)<br>B<br>IO0_6<br>IO0_7 SUB-SYSTEM 3<br>IO1_0 (e.g., alarm system)<br>IO1_1 10 DIGIT<br>IO1_2 NUMERIC ALARM<br>IO1_3 KEYPAD<br>IO1_4<br>IO1_5 VDD<br>A1 IO1_6<br>A0 IO1_7<br>VSS<br>002aad730<br>**----- End of picture text -----**<br> Device address configured as 1110 100X for this example. IO0_0, IO0_2, IO0_3 configured as outputs. IO0_1, IO0_4, IO0_5 configured as inputs. IO0_6, IO0_7 and (IO1_0 to IO1_7) configured as inputs. **Fig 19. Typical application** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 8.2 — 27 February 2017** **17 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **8.1 Minimizing IDD when the I/Os are used to control LEDs** When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 19. Since the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower than VDD. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 20 shows a high value resistor in parallel with the LED. Figure 21 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VDD and prevents additional supply current consumption when the LED is off. **==> picture [396 x 169] intentionally omitted <==** **----- Start of picture text -----**<br> 3.3 V 5 V<br>VDD<br>VDD LED 100 k Ω VDD LED<br>LEDn LEDn<br>002aac189 002aac190<br>Fig 20. High value resistor in parallel with Fig 21. Device supplied by a lower voltage<br>the LED<br>**----- End of picture text -----**<br> ## **9. Limiting values** **Table 13. Limiting values** _In accordance with the Absolute Maximum Rating System (IEC 60134)._ |**Symbol**|**Parameter**|**Conditions**|**Min**|**Max**|**Unit**| |---|---|---|---|---|---| |VDD|supply voltage||0.5|+6.0|V| |VI/O|voltage on an input/output pin||VSS0.5|6|V| |IO|output current|on an I/O pin|-|50|mA| |II|input current||-|20|mA| |IDD|supply current||-|160|mA| |ISS|ground supply current||-|200|mA| |Ptot|total power dissipation||-|200|mW| |Tstg|storage temperature||65|+150|C| |Tamb|ambient temperature|operating|||| |||all devices except PCA9539PW/Q900<br>and PCA9539RPW/Q900|40|+85|C| |||PCA9539PW/Q900 and<br>PCA9539RPW/Q900|40|+125|C| |Tj(max)|maximum junction temperature||-|125|C| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 8.2 — 27 February 2017** **18 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **10. Static characteristics** **Table 14. Static characteristics for all devices except PCA9539PW/Q900 and PCA9539RPW/Q900** _VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb =_ _40_ _C to +85_ _C; unless otherwise specified._ |**Symbol**|**Parameter**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---|---| |**Supplies**|||||||| |VDD|supply voltage|||2.3|-|5.5|V| |IDD|supply current||Operating mode; VDD= 5.5 V;<br>no load; fSCL= 100 kHz; I/O = inputs|-|135|200|A| |Istb|standby current||Standby mode; VDD= 5.5 V; no load;<br>VI= VSS; fSCL= 0 kHz; I/O = inputs|-|0.25|1|A| ||||Standby mode; VDD= 5.5 V; no load;<br>VI= VDD; fSCL= 0 kHz; I/O = inputs|-|0.25|1|A| |VPOR|power-on reset voltag~~e~~[1]||no load; VI= VDDor VSS|-|1.5|1.65|V| |**Input SCL; input/output SDA**|||||||| |VIL|LOW-level input voltage|||0.5|-|+0.3VDD|V| |VIH|HIGH-level input voltage|||0.7VDD|-|5.5|V| |IOL|LOW-level output current||VOL= 0.4 V|3|-|-|mA| |IL|leakage current||VI= VDD= VSS|1|-|+1|A| |Ci|input capacitance||VI= VSS|-|6|10|pF| |**I/Os**|||||||| |VIL|LOW-level input voltage|||0.5|-|+0.3VDD|V| |VIH|HIGH-level input voltage|||0.7VDD|-|5.5|V| |IOL|LOW-level output current||VDD= 2.3 V to 5.5 V; VOL= 0.5 V<br>[2]|8|9|-|mA| ||||VDD= 2.3 V to 5.5 V; VOL= 0.7 V<br>[2]|10|11|-|mA| |VOH|HIGH-level output voltage||IOH=8 mA; VDD= 2.3 V<br>[3]|1.8|-|-|V| ||||IOH=10 mA; VDD= 2.3 V<br>[3]|1.7|-|-|V| ||||IOH=8 mA; VDD= 3.0 V<br>[3]|2.6|-|-|V| ||||IOH=10 mA; VDD= 3.0 V<br>[3]|2.5|-|-|V| ||||IOH=8 mA; VDD= 4.75 V<br>[3]|4.1|-|-|V| ||||IOH=10 mA; VDD= 4.75 V<br>[3]|4.0|-|-|V| |ILIH|HIGH-level input leakage current||VDD= 5.5 V; VI= VDD|-|-|1|A| |ILIL|LOW-level input leakage current||VDD= 5.5 V; VI= VSS|-|-|1|A| |Ci|input capacitance|||-|3.7|5|pF| |Co|output capacitance|||-|3.7|5|pF| |**Interrupt INT**|||||||| |IOL|LOW-level output current||VOL= 0.4 V|3|-|-|mA| |**Select inputs A0, A1 and**||**RESET**|||||| |VIL|LOW-level input|voltage||0.5|-|+0.3VDD|V| |VIH|HIGH-level input voltage|||0.7VDD|-|5.5|V| |ILI|input leakage current|||1|-|+1|A| [1] VDD must be lowered to 0.2 V for at least 5 s in order to reset part. [2] Each I/O must be externally limited to a maximum of 25 mA and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be limited to a maximum current of 100 mA for a device total of 200 mA. All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** **Rev. 8.2 — 27 February 2017** **19 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** [3] The total current sourced by all I/Os must be limited to 160 mA (80 mA for IO0_0 through IO0_7 and 80 mA for IO1_0 through IO1_7). **Table 15. Static characteristics for PCA9539PW/Q900 and PCA9539RPW/Q900** _VDD = 3.0 V to 5.5 V; VSS = 0 V; Tamb =_ _40_ _C to +125_ _C; unless otherwise specified._ |**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---| |**Supplies**||||||| |VDD|supply voltage||3.0|-|5.5|V| |IDD|supply current|Operating mode; VDD= 5.5 V;<br>no load; fSCL= 100 kHz; I/O = inputs|-|135|200|A| |Istb|standby current|Standby mode; VDD= 5.5 V; no load;<br>VI= VSS; fSCL= 0 kHz; I/O = inputs|-|0.25|1|A| |||Standby mode; VDD= 5.5 V; no load;<br>VI= VDD; fSCL= 0 kHz; I/O = inputs|-|0.25|1|A| |VPOR|power-on reset voltag~~e~~[1]|no load; VI= VDDor VSS|-|1.5|1.65|V| |**Input SCL; input/output SDA**||||||| |VIL|LOW-level input voltage||0.5|-|+0.3VDD|V| |VIH|HIGH-level input voltage||0.7VDD|-|5.5|V| |IOL|LOW-level output current, SDA|VOL= 0.4 V||||| |||VDD= 5.5 V|3|-|-|mA| |||VDD= 3.0 V|2.5|-|-|mA| |IL|leakage current|VI= VDD= VSS|1|-|+1|A| |Ci|input capacitance|VI= VSS|-|6|10|pF| |**I/Os**||||||| |VIL|LOW-level input voltage||0.5|-|+0.3VDD|V| |VIH|HIGH-level input voltage||0.7VDD|-|5.5|V| |IOL|LOW-level output current|VOL= 0.5 V||||| |||VDD= 4.5 V<br>[2]|8|9|-|mA| |||VDD= 3.0 V<br>[2]|7.5|-|-|mA| |||VOL= 0.7 V||||| |||VDD= 4.5 V<br>[2]|10|11|-|mA| |||VDD= 3.0 V<br>[2]|9.5|-|-|mA| |VOH|HIGH-level output voltage|IOH=8 mA||||| |||VDD= 4.5 V<br>[3]|4.1|-|-|V| |||VDD= 3.0 V<br>[3]|2.5|-|-|V| |||IOH=10 mA||||| |||VDD= 4.5 V<br>[3]|4.0|-|-|V| |||VDD= 3.0 V<br>[3]|2.4|-|-|V| |ILIH|HIGH-level input leakage current|VDD= 5.5 V; VI= VDD|-|-|1|A| |ILIL|LOW-level input leakage current|VDD= 5.5 V; VI= VSS|-|-|1|A| |Ci|input capacitance||-|3.7|5|pF| |Co|output capacitance||-|3.7|5|pF| |**Interrupt INT**||||||| |IOL|LOW-level output current|VOL= 0.4 V|3|-|-|mA| All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** **Rev. 8.2 — 27 February 2017** **20 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **Table 15. Static characteristics for PCA9539PW/Q900 and PCA9539RPW/Q900** _…continued VDD = 3.0 V to 5.5 V; VSS = 0 V; Tamb =_ _40_ _C to +125_ _C; unless otherwise specified._ |**Symbol**|**Parameter**||**Conditions**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---|---| |**Select inputs A0, A1 and**||**RESET**|||||| |VIL|LOW-level input|voltage||0.5|-|+0.3VDD|V| |VIH|HIGH-level input voltage|||0.7VDD|-|5.5|V| |ILI|input leakage current|||1|-|+1|A| [1] VDD must be lowered to 0.2 V for at least 5 s in order to reset part. [2] Each I/O must be externally limited to a maximum of 25 mA and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be limited to a maximum current of 100 mA for a device total of 200 mA. - [3] The total current sourced by all I/Os must be limited to 160 mA (80 mA for IO0_0 through IO0_7 and 80 mA for IO1_0 through IO1_7). ## **11. Dynamic characteristics** ## **Table 16. Dynamic characteristics** |**Symbol**|**Parameter**|**Conditions**|**Standard-mode**<br>**I2C-bus**|**Standard-mode**<br>**I2C-bus**|**Fast-mode I2C-bus**|**Fast-mode I2C-bus**|**Unit**| |---|---|---|---|---|---|---|---| ||||**Min**|**Max**|**Min**|**Max**|| |fSCL|SCL clock frequency||0|100|0|400|kHz| |tBUF|bus free time between a<br>STOP and START condition||4.7|-|1.3|-|s| |tHD;STA|hold time (repeated) START<br>condition||4.0|-|0.6|-|s| |tSU;STA|set-up time for a repeated<br>START condition||4.7|-|0.6|-|s| |tSU;STO|set-up time for STOP<br>condition||4.0|-|0.6|-|s| |tVD;ACK|data valid acknowledge time|[1]|0.3|3.45|0.1|0.9|s| |tHD;DAT|data hold time||0|-|0|-|ns| |tVD;DAT|data valid time|[2]|300|-|50|-|ns| |tSU;DAT|data set-up time||250|-|100|-|ns| |tLOW|LOW period of the SCL clock||4.7|-|1.3|-|s| |tHIGH|HIGH period of the SCL<br>clock||4.0|-|0.6|-|s| |tf|fall time of both SDA and<br>SCL signals|[3]|-|300|20 + 0.1Cb|300|ns| |tr|rise time of both SDA and<br>SCL signals|[3]|-|1000|20 + 0.1Cb|300|ns| |tSP|pulse width of spikes that<br>must be suppressed by the<br>input filter||-|50|-|50|ns| |**Port timing**|||||||| |tv(Q)|data output valid time|[4]|-|200|-|200|ns| |tsu(D)|data input set-up time||150|-|150|-|ns| |th(D)|data input hold time||1|-|1|-|s| All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** **Rev. 8.2 — 27 February 2017** **21 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **Table 16. Dynamic characteristics** _…continued_ |**Symbol**|**Parameter**|**Conditions**|**Standard-mode**<br>**I2C-bus**|**Standard-mode**<br>**I2C-bus**|**Fast-mode I2C-bus**|**Fast-mode I2C-bus**|**Unit**| |---|---|---|---|---|---|---|---| ||||**Min**|**Max**|**Min**|**Max**|| |**Interrupt timing**|||||||| |tv(INT_N)|valid time on pin INT||-|4|-|4|s| |trst(INT_N)|reset time on pin INT||-|4|-|4|s| |**RESET**<br>**timing**|||||||| |tw(rst)|reset pulse width|all devices except<br>PCA9539RPW/Q900|4|-|4|-|ns| |||PCA9539RPW/Q900|6|-|6|-|ns| |trec(rst)|reset recovery time||0|-|0|-|ns| |trst|reset time|[5]<br>[6]|400|-|400|-|ns| - [1] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW. - [2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. - [3] Cb = total capacitance of one bus line in pF. - [4] tv(Q) measured from 0.7VDD on SCL to 50 % I/O output. - [5] Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions. - [6] Upon reset, the full delay will be the sum of trst and the RC time constant of the SDA bus. **==> picture [479 x 133] intentionally omitted <==** **----- Start of picture text -----**<br> 0.7 × VDD<br>SDA<br>0.3 × VDD<br>tBUF tr tf tHD;STA tSP<br>tLOW<br>0.7 × VDD<br>SCL<br>0.3 × VDD<br>tHD;STA tSU;STA tSU;STO<br>P S tHD;DAT tHIGH tSU;DAT Sr P<br>002aaa986<br>**----- End of picture text -----**<br> **Fig 22. Definition of timing on the I[2] C-bus** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8.2 — 27 February 2017** **22 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** ## **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **==> picture [403 x 175] intentionally omitted <==** **----- Start of picture text -----**<br> START ACK or read cycle<br>SCL<br>SDA<br>30 %<br>trst<br>RESET 50 % 50 % 50 %<br>trec(rst) tw(rst)<br>trst<br>after reset,<br>IOn 50 %<br>I/Os reconfigured<br>as inputs<br>002aad732<br>**----- End of picture text -----**<br> **Fig 23. Definition of RESET timing in PCA9539** **==> picture [420 x 167] intentionally omitted <==** **----- Start of picture text -----**<br> START ACK or read cycle<br>SCL<br>SDA<br>30 %<br>trst<br>RESET 50 % 50 % 50 %<br>trec(rst) tw(rst)<br>trst<br>IOn 50 % after reset, I/Os unchanged;<br>device state machine reset<br>002aad733<br>**----- End of picture text -----**<br> **Fig 24. Definition of RESET timing in PCA9539R** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 8.2 — 27 February 2017** **23 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **==> picture [228 x 158] intentionally omitted <==** **----- Start of picture text -----**<br> 70 %<br>SCL 2 1 0 A P<br>30 %<br>SDA<br>tsu(D) th(Q)<br>input 50 %<br>tv(INT_N) trst(INT_N)<br>INT<br>002aad734<br>**----- End of picture text -----**<br> **Fig 25. Expanded view of read input port register** **==> picture [232 x 118] intentionally omitted <==** **----- Start of picture text -----**<br> 70 %<br>SCL 2 1 0 A P<br>SDA<br>tv(Q)<br>output 50 %<br>002aad735<br>**----- End of picture text -----**<br> **Fig 26. Expanded view of write to output port register** **==> picture [381 x 155] intentionally omitted <==** **----- Start of picture text -----**<br> START bit 7 STOP<br>protocol condition MSB bit 6 bit 1 bit 0 acknowledge condition<br>(A6) (D1) (D0) (A)<br>(S) (A7) (P)<br>tSU;STA tLOW tHIGH<br>1 / fSCL<br>SCL 0.7 × VDD<br>0.3 × VDD<br>tBUF tf<br>tr<br>SDA 0.7 × VDD<br>0.3 × VDD<br>tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO<br>002aab285<br>**----- End of picture text -----**<br> Rise and fall times refer to VIL and VIH. **Fig 27. I[2] C-bus timing diagram** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 8.2 — 27 February 2017** **24 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **12. Test information** **==> picture [262 x 123] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>open<br>GND<br>VDD RL<br>500 Ω<br>VI VO<br>PULSE<br>DUT<br>GENERATOR<br>RT CL<br>50 pF<br>002aab284<br>RL = load resistor.<br>CL = load capacitance includes jig and probe capacitance.<br>**----- End of picture text -----**<br> RT = termination resistance should be equal to the output impedance of Zo of the pulse generators. **==> picture [177 x 10] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 28. Test circuitry for switching times<br>**----- End of picture text -----**<br> **==> picture [298 x 84] intentionally omitted <==** **----- Start of picture text -----**<br> RL S1 2VDD<br>from output under test open<br>500 Ω GND<br>CL RL<br>50 pF 500 Ω<br>002aac226<br>Fig 29. Load circuit<br>**----- End of picture text -----**<br> ## **Table 17. Test data** |**Test**|**Load**|**Load**|**Switch**| |---|---|---|---| ||**CL**|**RL**|| |tv(Q)|50 pF|500|2VDD| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 8.2 — 27 February 2017** **25 of 38** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **PCA9539; PCA9539R** ## **13. Package outline** **Fig 30. Package outline SOT137-1 (SO24)** PCA9539_PCA9539R **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 8.2 — 27 February 2017** © NXP Semiconductors N.V. 2017. All rights reserved. **26 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **Fig 31. Package outline SOT355-1 (TSSOP24)** PCA9539_PCA9539R All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. **Product data sheet** **Rev. 8.2 — 27 February 2017** **27 of 38** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **PCA9539; PCA9539R** **==> picture [199 x 10] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 32. Package outline SOT616-1 (HVQFN24)<br>**----- End of picture text -----**<br> PCA9539_PCA9539R **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 8.2 — 27 February 2017** © NXP Semiconductors N.V. 2017. All rights reserved. **28 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **14. Handling information** All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in _JESD625-A_ or equivalent standards. ## **15. Soldering of SMD packages** This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note _AN10365 “Surface mount reflow soldering description”_ . ## **15.1 Introduction to soldering** Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. ## **15.2 Wave and reflow soldering** Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: - Through-hole components - Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: - Board specifications, including the board finish, solder masks and vias - Package footprints, including solder thieves and orientation - The moisture sensitivity level of the packages - Package placement - Inspection and repair - Lead-free soldering versus SnPb soldering ## **15.3 Wave soldering** Key characteristics in wave soldering are: All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** **Rev. 8.2 — 27 February 2017** **29 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** - Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave - Solder bath specifications, including temperature and impurities ## **15.4 Reflow soldering** Key characteristics in reflow soldering are: - Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 33) than a SnPb process, thus reducing the process window - Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board - Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 18 and 19 ## **Table 18. SnPb eutectic process (from J-STD-020D)** |**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**| |---|---|---| ||**Volume (mm3)**|| ||**< 350**|**350**| |< 2.5|235|220| |2.5|220|220| ## **Table 19. Lead-free process (from J-STD-020D)** |**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**| |---|---|---|---| ||**Volume (mm3)**||| ||**< 350**|**350 to 2000**|**> 2000**| |< 1.6|260|260|260| |1.6 to 2.5|260|250|245| |> 2.5|250|245|245| Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 33. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 8.2 — 27 February 2017** **30 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **==> picture [352 x 223] intentionally omitted <==** **----- Start of picture text -----**<br> maximum peak temperature<br>= MSL limit, damage level<br>temperature<br>minimum peak temperature<br>= minimum soldering temperature<br>peak<br> temperature<br>time<br>001aac844<br>MSL: Moisture Sensitivity Level<br>Fig 33. Temperature profiles for large and small components<br>**----- End of picture text -----**<br> For further information on temperature profiles, refer to Application Note _AN10365 “Surface mount reflow soldering description”_ . © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8.2 — 27 February 2017** **31 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **16. Soldering: PCB footprints** **Fig 34. PCB footprint for SOT137-1 (SO24); reflow soldering** All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** **Rev. 8.2 — 27 February 2017** **32 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **Fig 35. PCB footprint for SOT355-1 (TSSOP24); reflow soldering** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 8.2 — 27 February 2017** **33 of 38** **PCA9539; PCA9539R 16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **NXP Semiconductors** ## **Fig 36.** ## **PCB footprint for SOT616-1 (HVQFN24); reflow soldering** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 8.2 — 27 February 2017** **34 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **17. Abbreviations** **Table 20. Abbreviations** |**Acronym**|**Description**| |---|---| |ACPI|Advanced Configuration and Power Interface| |CBT|Cross-Bar Technology| |CDM|Charged-Device Model| |CMOS|Complementary Metal-Oxide Semiconductor| |ESD|ElectroStatic Discharge| |FET|Field-Effect Transistor| |FF|Flip-Flop| |GPIO|General Purpose Input/Output| |HBM|Human Body Model| |I2C-bus|Inter-Integrated Circuit bus| |I/O|Input/Output| |LED|Light Emitting Diode| |SMBus|System Management Bus| ## **18. Revision history** ## **Table 21. Revision history** |**Document ID**|**Release date**|**Data sheet status**|**Change**<br>**notice**|**Supersedes**| |---|---|---|---|---| |PCA9539_PCA9539R v.8.2|20170227|Product data sheet|-|PCA9539_PCA9539R v.8.1| |Modifications:|**•** Added PCA9539RPW/Q900 toFigure 6“<br>Pin configuration for TSSOP24<br>”<br>**•** Table 16“<br>Dynamic characteristics<br>”<br>,tw(rst): added AC parameters for<br>PCA9539RPW/Q900|||| |PCA9539_PCA9539R v.8.1|20161123|Product data sheet|-|PCA9539_PCA9539R v.8| |Modifications:|**•** Added PCA9539RPW/Q900|||| |PCA9539_PCA9539R v.8|20141126|Product data sheet|-|PCA9539_PCA9539R v.7| |Modifications:|**•** Table 15“<br>Static characteristics for PCA9539PW/Q900 and PCA9539RPW/Q900<br>”<br>:<br>updated IOLand VOH; changed operating power supply voltage range from “5.0 V10<br>%” to “3.0 V to 5.5 V” for PCA9539PW/Q900|||| |PCA9539_PCA9539R v.7|20140415|Product data sheet|-|PCA9539_PCA9539R v.6| |PCA9539_PCA9539R v.6|20130206|Product data sheet|-|PCA9539_PCA9539R v.5| |PCA9539_PCA9539R v.5|20080728|Product data sheet|-|PCA9539_PCA9539R v.4| |PCA9539_PCA9539R v.4|20080519|Product data sheet|-|PCA9539 v.3| |PCA9539 v.3|20060921|Product data sheet|-|PCA9539 v.2| |PCA9539 v.2<br>(9397 750 14048)|20040930|Product data sheet|-|PCA9539 v.1| |PCA9539 v.1<br>(9397 750 12898)|20040827|Product data sheet|-|-| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 8.2 — 27 February 2017** **35 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **19. Legal information** ## **19.1 Data sheet status** |**Document status[1]**<br>**[2]**|**Product statu**~~**s**~~**[3]**|**Definition**| |---|---|---| |Objective [short] data sheet|Development|This document contains data from the objective specification for product development.| |Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.| |Product [short] data sheet|Production|This document contains the product specification.| [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. ## **19.2 Definitions** **Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. **Product specification —** The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. ## **19.3 Disclaimers** **Limited warranty and liability —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors. **Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. **Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. **Limiting values —** Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. **Terms and conditions of commercial sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. **No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. PCA9539_PCA9539R All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. **Product data sheet Rev. 8.2 — 27 February 2017 36 of 38** **36 of 38** **PCA9539; PCA9539R** ## **NXP Semiconductors** ## **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **Export control —** This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. **Non-automotive qualified products —** Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. **Translations —** A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. ## **19.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. **I[2] C-bus —** logo is a trademark of NXP B.V. ## **20. Contact information** For more information, please visit: **http://www.nxp.com** For sales office addresses, please send an email to: **salesaddresses@nxp.com** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9539_PCA9539R **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 8.2 — 27 February 2017** **37 of 38** **PCA9539; PCA9539R** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **21. Contents** |**1**|**General description . . . . . . . . . . . . . . . . . . . . . . 1**| |---|---| |**2**|**Features and benefits . . . . . . . . . . . . . . . . . . . . 1**| |**3**|**Ordering information. . . . . . . . . . . . . . . . . . . . . 2**| |3.1|Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2| |3.1.1|Pin 1 quadrant indication . . . . . . . . . . . . . . . . . 3| |**4**|**Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4**| |**5**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . 5**| |5.1|Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5| |5.2|Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6| |**6**|**Functional description . . . . . . . . . . . . . . . . . . . 7**| |6.1|Device address. . . . . . . . . . . . . . . . . . . . . . . . . 7| |6.2|Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7| |6.2.1|Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 7| |6.2.2|Registers 0 and 1: Input port registers . . . . . . . 8| |6.2.3|Registers 2 and 3: Output port registers. . . . . . 8| |6.2.4|Registers 4 and 5: Polarity inversion registers . 8| |6.2.5|Registers 6 and 7: Configuration registers . . . . 9| |6.3|Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9| |6.4|RESET<br>input. . . . . . . . . . . . . . . . . . . . . . . . . . . 9| |6.5|I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9| |6.6|Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 10| |6.6.1|Writing to the port registers. . . . . . . . . . . . . . . 10| |6.6.2|Reading the port registers . . . . . . . . . . . . . . . 12| |6.6.3|Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 15| |**7**|**Characteristics of the I2C-bus . . . . . . . . . . . . 15**| |7.1|Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 15| |7.1.1|START and STOP conditions . . . . . . . . . . . . . 15| |7.2|System configuration . . . . . . . . . . . . . . . . . . . 16| |7.3|Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 16| |**8**|**Application design-in information . . . . . . . . . 17**| |8.1|Minimizing IDDwhen the I/Os are used to| ||control LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . 18| |**9**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18**| |**10**|**Static characteristics. . . . . . . . . . . . . . . . . . . . 19**| |**11**|**Dynamic characteristics . . . . . . . . . . . . . . . . . 21**| |**12**|**Test information. . . . . . . . . . . . . . . . . . . . . . . . 25**| |**13**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26**| |**14**|**Handling information. . . . . . . . . . . . . . . . . . . . 29**| |**15**|**Soldering of SMD packages . . . . . . . . . . . . . . 29**| |15.1|Introduction to soldering . . . . . . . . . . . . . . . . . 29| |15.2|Wave and reflow soldering . . . . . . . . . . . . . . . 29| |15.3|Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 29| |15.4|Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 30| |**16**|**Soldering: PCB footprints. . . . . . . . . . . . . . . . 32**| |**17**|**Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 35**| - **18 Revision history . . . . . . . . . . . . . . . . . . . . . . . 35 19 Legal information . . . . . . . . . . . . . . . . . . . . . . 36** 19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 36 19.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 19.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 36 19.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 37 **20 Contact information . . . . . . . . . . . . . . . . . . . . 37 21 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38** Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. **© NXP Semiconductors N.V. 2017.** **All rights reserved.** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 27 February 2017 Document identifier: PCA9539_PCA9539R**
Updated at February 9, 2023
NXP Semiconductors is a global leader in secure connectivity solutions, driving innovation across the automotive, industrial, IoT, mobile, and communications infrastructure markets. By developing advanced, purpose-built technologies, NXP enables devices to sense, think, connect, and act intelligently, delivering rigorously tested components that make the connected world safer and more efficient. Within the semiconductor space, NXP is highly regarded for its extensive range of high-performance integrated circuits and discrete devices. The brand's portfolio excels in drivers and interfaces, featuring a comprehensive selection of I/O expanders designed to streamline complex system architectures. For demanding high-frequency and wireless applications, NXP provides industry-leading RF FETs and RF/PIN diodes engineered to deliver exceptional signal integrity, efficiency, and reliability. The NXP product lineup further extends to essential discrete components, including versatile bipolar transistors, JFETs, and small signal diodes optimized for precision switching and amplification. Additionally, the portfolio supports advanced automation and smart applications with precision IC sensors, such as MEMS accelerometers, alongside specialized power management solutions like AC/DC LED driver ICs and single MOSFETs for cutting-edge electronics design.
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