Image not available
Illustrative purposes only
PCA9539AHF,128
I/O Expander, 16bit, 400 kHz, I2C, SMBus, 1.65 V, 5.5 V, HWQFN
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: NXP
- Product type: I/O Expanders
- No. of Pins: 24Pins
- No. of I/O's: 16I/O's
- Bus Frequency: 400kHz
- IC Interface Type: I2C, SMBus
- Chip Configuration: 16bit
- Supply Voltage Max: 5.5V
- Supply Voltage Min: 1.65V
- Interface Case Style: HWQFN
| Delivery and price | |
|---|---|
| Units per pack | 100 |
| Price | 0.931 € |
| Current stock | 1000+ |
| Lead time | 7 days |
Datasheet
## **PCA9539A** **Low-voltage 16-bit I[2] C-bus I/O port with interrupt and reset Rev. 2 — 12 August 2013 Product data sheet** ## **1. General description** The PCA9539A is a low-voltage 16-bit General Purpose Input/Output (GPIO) expander with interrupt and reset for I[2] C-bus/SMBus applications. NXP I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections to a minimum, for example, in ACPI power switches, sensors, push buttons, LEDs, fan control, etc. In addition to providing a flexible set of GPIOs, the wide VDD range of 1.65 V to 5.5 V allows the PCA9539A to interface with next-generation microprocessors and microcontrollers where supply levels are dropping down to conserve power. The PCA9539A contains the PCA9539 register set of four pairs of 8-bit Configuration, Input, Output, and Polarity Inversion registers. The PCA9539A is a pin-to-pin replacement to the PCA9539, and other industry-standard part numbers. A more fully featured part, PCAL9539A is also available with Agile I/O features. See the respective data sheet for more details. The PCA9539A open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I[2] C-bus. Thus, the PCA9539A can remain a simple slave device. The device outputs have 25 mA sink capabilities for directly driving LEDs while consuming low device current. The power-on reset sets the registers to their default values and initializes the device state machine. In the PCA9539A, the RESET pin causes the same reset/default I/O input configuration to occur without de-powering the device, holding the registers and I[2] C-bus state machine in their default state until the RESET input is once again HIGH. This input requires a pull-up to VDD. Two hardware pins (A0, A1) select the fixed I[2] C-bus address and allow up to four devices to share the same I[2] C-bus/SMBus. **==> picture [172 x 101] intentionally omitted <==** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** ## **2. Features and benefits** - I[2] C-bus to parallel port expander - Pin and function compatible with PCA9539 - Operating power supply voltage range of 1.65 V to 5.5 V - Low standby current consumption: - 1.5 A (typical at 5 V VDD) - 1.0 A (typical at 3.3 V VDD) - Schmitt-trigger action allows slow input transition and better switching noise immunity at the SCL and SDA inputs - Vhys = 0.10 VDD (typical) - 5 V tolerant I/Os - Active LOW reset input (RESET) - Open-drain active LOW interrupt output (INT) - 400 kHz Fast-mode I[2] C-bus - Internal power-on reset - Power-up with all channels configured as inputs - No glitch on power-up - Latched outputs with 25 mA drive maximum capability for directly driving LEDs - Latch-up performance exceeds 100 mA per JESD78, Class II - ESD protection exceeds JESD22 - 2000 V Human Body Model (A114-A) - 1000 V Charged-Device Model (C101) - Packages offered: TSSOP24, HWQFN24 ## **3. Ordering information** **Table 1. Ordering information** |**Type number**|**Topside**<br>**marking**|**Package**|**Package**|**Package**| |---|---|---|---|---| |||**Name**|**Description**|**Version**| |PCA9539APW<br>PCA9539A||TSSOP24<br>plastic thin shrink small outline package; 24 leads;<br>body width 4.4 mm<br>SOT355-1||| |PCA9539AHF<br>539A||HWQFN24<br>plastic thermal enhanced very very thin quad flat package;<br>no leads; 24 terminals; body 440.75 mm<br>SOT994-1||| ## **3.1 Ordering options** ## **Table 2. Ordering options** |**Type number**|**Orderable**|**Package**|**Packing method**|**Minimum**|**Temperature range**| |---|---|---|---|---|---| ||**part number**|||**order**|| |||||**quantity**|| |PCA9539APW|PCA9539APW,118|TSSOP24|Reel 13” Q1/T1|2500|40C to +85C| ||||*Standard mark SMD||| |PCA9539AHF|PCA9539AHF,128|HWQFN24|Reel 13” Q2/T3|6000|40C to +85C| ||||*Standard mark SMD||| © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **2 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** ## **4. Block diagram** **==> picture [378 x 321] intentionally omitted <==** **----- Start of picture text -----**<br> PCA9539A<br>P1_0<br>P1_1<br>A0 8-bit P1_2<br>A1 INPUT/ P1_3<br>OUTPUT<br>PORTS P1_4<br>write pulse P1_5<br>P1_6<br>read pulse<br>P1_7<br>I [2] C-BUS/SMBus<br>CONTROL<br>SCL INPUT P0_0<br>FILTER P0_1<br>SDA 8-bit P0_2<br>INPUT/ P0_3<br>OUTPUT<br>PORTS P0_4<br>write pulse P0_5<br>P0_6<br>read pulse<br>VDD POWER-ON P0_7<br>RESET<br>RESET VDD<br>VSS<br>LP INT<br>FILTER<br>002aag162<br>Remark: All I/Os are set to inputs at reset.<br>Fig 1. Block diagram of PCA9539A<br>**----- End of picture text -----**<br> © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **3 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** ## **5. Pinning information** ## **5.1 Pinning** **==> picture [397 x 210] intentionally omitted <==** **----- Start of picture text -----**<br> PCA9539AHF<br>INT 1 24 VDD<br>terminal 1<br>A1 2 23 SDA index area<br>RESET 3 22 SCL<br>P0_0 4 21 A0 P0_0 1 18 A0<br>P0_1 5 20 P1_7 P0_1 2 17 P1_7<br>P0_2 6 19 P1_6 P0_2 3 16 P1_6<br>PCA9539APW<br>P0_3 7 18 P1_5 P0_3 4 15 P1_5<br>P0_4 8 17 P1_4 P0_4 5 14 P1_4<br>P0_5 9 16 P1_3 P0_5 6 13 P1_3<br>P0_6 10 15 P1_2<br>P0_7 11 14 P1_1<br>VSS 12 13 P1_0 002aag161<br>002aag160 Transparent top view<br>Fig 2. Pin configuration for TSSOP24 Fig 3. Pin configuration for HWQFN24<br>RESET A1 INT VDD SDA SCL<br>24 23 22 21 20 19<br>7 8 9 10 11 12<br>SS<br>V<br>P0_6 P0_7 P1_0 P1_1 P1_2<br>**----- End of picture text -----**<br> ## **5.2 Pin description** ## **Table 3. Pin description** |**Symbol**|**Pin**|**Pin**|**Type**|**Description**| |---|---|---|---|---| ||**TSSOP24**|**HWQFN24**||| |INT|1<br>22<br>O<br>Interrupt output. Connect to VDDthrough a<br>pull-up resistor.|||| |A1|2<br>23<br>I<br>Address input 1. Connect directly to VDDor VSS.|||| |RESET|3<br>24<br>I<br>Active LOW reset input. Connect to VDDthrough<br>a pull-up resistor if no active connection is used.|||| |P0_~~0~~[2]|4<br>1<br>I/O<br>Port 0 input/output 0.|||| |P0_~~1~~[2]|5<br>2<br>I/O<br>Port 0 input/output 1.|||| |P0_~~2~~[2]|6<br>3<br>I/O<br>Port 0 input/output 2.|||| |P0_~~3~~[2]|7<br>4<br>I/O<br>Port 0 input/output 3.|||| |P0_~~4~~[2]|8<br>5<br>I/O<br>Port 0 input/output 4.|||| |P0_~~5~~[2]|9<br>6<br>I/O<br>Port 0 input/output 5.|||| |P0_~~6~~[2]|10<br>7<br>I/O<br>Port 0 input/output 6.|||| |P0_~~7~~[2]|11<br>8<br>I/O<br>Port 0 input/output 7.|||| |VSS|12<br>~~9~~[1]<br>power<br>Ground.|||| |P1_~~0~~[3]|13<br>10<br>I/O<br>Port 1 input/output 0.|||| |P1_~~1~~[3]|14<br>11<br>I/O<br>Port 1 input/output 1.|||| |P1_~~2~~[3]|15<br>12<br>I/O<br>Port 1 input/output 2.|||| |P1_~~3~~[3]|16<br>13<br>I/O<br>Port 1 input/output 3.|||| |P1_~~4~~[3]|17<br>14<br>I/O<br>Port 1 input/output 4.|||| |P1_~~5~~[3]|18<br>15<br>I/O<br>Port 1 input/output 5.|||| All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. PCA9539A **Product data sheet** **Rev. 2 — 12 August 2013** **4 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** **Table 3. Pin description** _…continued_ |**Symbol**|**Pin**|**Pin**|**Type**|**Description**| |---|---|---|---|---| ||**TSSOP24**|**HWQFN24**||| |P1_~~6~~[3]|19<br>16<br>I/O<br>Port 1 input/output 6.|||| |P1_~~7~~[3]|20<br>17<br>I/O<br>Port 1 input/output 7.|||| |A0|21<br>18<br>I<br>Address input 0. Connect directly to VDDor VSS.|||| |SCL|22<br>19<br>I<br>Serial clock bus. Connect to VDDthrough a<br>pull-up resistor.|||| |SDA|23<br>20<br>I/O<br>Serial data bus. Connect to VDDthrough a<br>pull-up resistor.|||| |VDD|24<br>21<br>power<br>Supply voltage.|||| - [1] HWQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region. - [2] Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-up, all I/O are configured as high-impedance inputs. - [3] Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-up, all I/O are configured as high-impedance inputs. ## **6. Functional description** “ ” Refer to Figure 1 Block diagram of PCA9539A . ## **6.1 Device address** **==> picture [139 x 62] intentionally omitted <==** **----- Start of picture text -----**<br> slave address<br>1 1 1 0 1 A1 A0 R/W<br>fixed hardware<br>selectable<br>002aah062<br>**----- End of picture text -----**<br> ## **Fig 4. PCA9539A device address** A1 and A0 are the hardware address package pins and are held to either HIGH (logic 1) or LOW (logic 0) to assign one of the four possible slave addresses. The last bit of the slave address (R/W) defines the operation (read or write) to be performed. A HIGH (logic 1) selects a read operation, while a LOW (logic 0) selects a write operation. © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Rev. 2 — 12 August 2013** **Product data sheet** **5 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** ## **6.2 Registers** ## **6.2.1 Pointer register and command byte** Following the successful acknowledgement of the address byte, the bus master sends a command byte, which is stored in the Pointer register in the PCA9539A. The lower four bits of this data byte state the operation (read or write) and the internal registers (Input, Output, Polarity Inversion, or Configuration) that will be affected. This register is write only. **==> picture [139 x 26] intentionally omitted <==** **----- Start of picture text -----**<br> B7 B6 B5 B4 B3 B2 B1 B0<br>002aaf540<br>**----- End of picture text -----**<br> **Fig 5. Pointer register bits** **Table 4. Command byte** |**Pointer register bits**|**Pointer register bits**|**Pointer register bits**|**Pointer register bits**|**Pointer register bits**|**Pointer register bits**|**Pointer register bits**|**Pointer register bits**|**Command byte**<br>**(hexadecimal)**|**Register**|**Protocol**|**Power-up**<br>**default**| |---|---|---|---|---|---|---|---|---|---|---|---| |**B7**|**B6**|**B5**|**B4**|**B3**|**B2**|**B1**|**B0**||||| |0<br>0<br>0<br>0<br>0<br>0<br>0<br>0<br>00h<br>Input port 0<br>read byte<br>xxxx xxx~~x~~[1]|||||||||||| |0<br>0<br>0<br>0<br>0<br>0<br>0<br>1<br>01h<br>Input port 1<br>read byte<br>xxxx xxxx|||||||||||| |0<br>0<br>0<br>0<br>0<br>0<br>1<br>0<br>02h<br>Output port 0<br>read/write byte<br>1111 1111|||||||||||| |0<br>0<br>0<br>0<br>0<br>0<br>1<br>1<br>03h<br>Output port 1<br>read/write byte<br>1111 1111|||||||||||| |0<br>0<br>0<br>0<br>0<br>1<br>0<br>0<br>04h<br>Polarity Inversion port 0<br>read/write byte<br>0000 0000|||||||||||| |0<br>0<br>0<br>0<br>0<br>1<br>0<br>1<br>05h<br>Polarity Inversion port 1<br>read/write byte<br>0000 0000|||||||||||| |0<br>0<br>0<br>0<br>0<br>1<br>1<br>0<br>06h<br>Configuration port 0<br>read/write byte<br>1111 1111|||||||||||| |0<br>0<br>0<br>0<br>0<br>1<br>1<br>1<br>07h<br>Configuration port 1<br>read/write byte<br>1111 1111|||||||||||| [1] Undefined. ## **6.2.2 Input port register pair (00h, 01h)** The Input port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. The Input port registers are read only; writes to these registers have no effect. The default value ‘X’ is determined by the externally applied logic level. An Input port register read operation is performed as described in Section 7.2 “Reading the port ” registers . |**Table 5.**<br>**Input port 0 register (address 00h)**|**Table 5.**<br>**Input port 0 register (address 00h)**|**Table 5.**<br>**Input port 0 register (address 00h)**|**Table 5.**<br>**Input port 0 register (address 00h)**|**Table 5.**<br>**Input port 0 register (address 00h)**|**Table 5.**<br>**Input port 0 register (address 00h)**|**Table 5.**<br>**Input port 0 register (address 00h)**|**Table 5.**<br>**Input port 0 register (address 00h)**|**Table 5.**<br>**Input port 0 register (address 00h)**| |---|---|---|---|---|---|---|---|---| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||| |**Symbol**|I0.7|I0.6|I0.5|I0.4|I0.3|I0.2|I0.1|I0.0| |**Default**|X<br>X<br>X<br>X<br>X<br>X<br>X<br>X|||||||| |**Table 6.**<br>**Input port 1 register (address 01h)**||||||||| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||| |**Symbol**|I1.7|I1.6|I1.5|I1.4|I1.3|I1.2|I1.1|I1.0| |**Default**|X<br>X<br>X<br>X<br>X<br>X<br>X<br>X|||||||| © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **6 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** ## **6.2.3 Output port register pair (02h, 03h)** The Output port registers (registers 2 and 3) show the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads from these registers reflect the value that was written to these registers, **not** the actual pin value. A register pair write is described in Section 7.1 and a register pair read is described in Section 7.2. |**Table 7.**<br>**Output port 0 register (address 02h)**|**Table 7.**<br>**Output port 0 register (address 02h)**|**Table 7.**<br>**Output port 0 register (address 02h)**|**Table 7.**<br>**Output port 0 register (address 02h)**|**Table 7.**<br>**Output port 0 register (address 02h)**|**Table 7.**<br>**Output port 0 register (address 02h)**|**Table 7.**<br>**Output port 0 register (address 02h)**|**Table 7.**<br>**Output port 0 register (address 02h)**|**Table 7.**<br>**Output port 0 register (address 02h)**| |---|---|---|---|---|---|---|---|---| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||| |**Symbol**|O0.7|O0.6|O0.5|O0.4|O0.3|O0.2|O0.1|O0.0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||||||| |**Table 8.**<br>**Output port 1 register (address 03h)**||||||||| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||| |**Symbol**|O1.7|O1.6|O1.5|O1.4|O1.3|O1.2|O1.1|O1.0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||||||| ## **6.2.4 Polarity inversion register pair (04h, 05h)** The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined as inputs by the Configuration register. If a bit in these registers is set (written with ‘1’), the corresponding port pin’s polarity is inverted in the Input register. If a bit in this register is cleared (written with a ‘0’), the corresponding port pin’s polarity is retained. A register pair write is described in Section 7.1 and a register pair read is described in Section 7.2. **Table 9. Polarity inversion port 0 register (address 04h)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|N0.7|N0.6|N0.5|N0.4|N0.3|N0.2|N0.1|N0.0| |**Default**|0<br>0<br>0<br>0<br>0<br>0<br>0<br>0|||||||| |**Table 10.**<br>**Polarity inversion port 1 register (address 05h)**||||||||| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||| |**Symbol**|N1.7|N1.6|N1.5|N1.4|N1.3|N1.2|N1.1|N1.0| |**Default**|0<br>0<br>0<br>0<br>0<br>0<br>0<br>0|||||||| ## **6.2.5 Configuration register pair (06h, 07h)** The Configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a bit in these registers is set to 1, the corresponding port pin is enabled as a high-impedance input. If a bit in these registers is cleared to 0, the corresponding port pin is enabled as an output. A register pair write is described in Section 7.1 and a register pair read is described in Section 7.2. **Table 11. Configuration port 0 register (address 06h)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|C0.7|C0.6|C0.5|C0.4|C0.3|C0.2|C0.1|C0.0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||||||| © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **7 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** **Table 12. Configuration port 1 register (address 07h)** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|C1.7|C1.6|C1.5|C1.4|C1.3|C1.2|C1.1|C1.0| |**Default**|1<br>1<br>1<br>1<br>1<br>1<br>1<br>1|||||||| ## **6.3 I/O port** When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output port register. In this case, there are low-impedance paths between the I/O pin and either VDD or VSS. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation. **==> picture [379 x 322] intentionally omitted <==** **----- Start of picture text -----**<br> data from output port<br>shift register register data<br>configuration<br>register<br>VDD<br>data from D Q Q1<br>shift register<br>FF<br>write<br>D Q<br>configuration CK Q<br>pulse FF<br>P0_0 to P0_7<br>write pulse CK Q2 ESD P1_0 to P1_7<br>protection<br>output port diode<br>register input port<br>register VSS<br>D Q<br>input port<br>FF register data<br>read pulse CK<br>to INT<br>polarity<br>inversion<br>register<br>data from<br>D Q polarity<br>shift register inversion<br>FF register data<br>write polarity<br>CK<br>pulse<br>002aah246<br>At power-on reset, all registers return to default values.<br>Fig 6. Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)<br>**----- End of picture text -----**<br> ## **6.4 Power-on reset** When power (from 0 V) is applied to VDD, an internal power-on reset holds the PCA9539A in a reset condition until VDD has reached VPOR. At that time, the reset condition is released and the PCA9539A registers and I[2] C-bus/SMBus state machine initializes to their default states. After that, VDD must be lowered to below VPORF and back up to the operating voltage for a power-reset cycle. See Section 8.2 “Power-on reset requirements”. © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **8 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** ## **6.5 RESET input** The RESET input can be asserted to initialize the system while keeping the VDD at its operating level. A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The PCA9539A registers and I[2] C-bus/SMBus state machine are changed to their default state once RESET is LOW (0). When RESET is HIGH (1), the I/O levels at the ports can be changed externally or through the master. This input requires a pull-up resistor to VDD if no active connection is used. ## **6.6 Interrupt output** An interrupt is generated by any rising or falling edge of the port inputs in the Input mode. After time tv(INT), the signal INT is valid. The interrupt is reset when data on the port changes back to the original value or when data is read form the port that generated the interrupt (see Figure 10). Resetting occurs in the Read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Any change of the I/Os after resetting is detected and is transmitted as INT. A pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the Input Port register. The INT output has an open-drain structure and requires pull-up resistor to VDD. ## **7. Bus transactions** The PCA9539A is an I[2] C-bus slave device. Data is exchanged between the master and PCA9539A through write and read commands using I[2] C-bus. The two communication lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. ## **7.1 Writing to the port registers** Data is transmitted to the PCA9539A by sending the device address and setting the least significant bit to a logic 0 (see Figure 4 “PCA9539A device address”). The command byte is sent after the address and determines which register will receive the data following the command byte. Eight registers within the PCA9539A are configured to operate as four register pairs. The four pairs are input port, output port, polarity inversion, and configuration registers. After sending data to one register, the next data byte is sent to the other register in the pair (see Figure 7 and Figure 8). For example, if the first byte is sent to Output Port 1 (register 3), the next byte is stored in Output Port 0 (register 2). There is no limitation on the number of data bytes sent in one write transmission. In this way, the host can continuously update a register pair independently of the other registers, or the host can simply update a single register. © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **9 of 39** **==> picture [534 x 176] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>slave address command byte data to port 0 data to port 1<br>SDA S 1 1 1 0 1 A1 A0 0 A 0 0 0 0 0 0 1 0 A 0.7 DATA 0 0.0 A 1.7 DATA 1 1.0 A P<br>START condition R/W acknowledge acknowledge acknowledge STOP<br>from slave from slave from slave condition<br>write to port<br>tv(Q)<br>data out<br>from port 0<br>tv(Q)<br>data out<br>from port 1 DATA VALID<br>002aad725<br>**----- End of picture text -----**<br> **Fig 7. Write to output port registers** **==> picture [526 x 98] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>STOP<br>condition<br>slave address command byte data to register data to register<br>SDA S 1 1 1 0 1 A1 A0 0 A 0 0/1 0 0 0/1 0/1 0/1 0/1 A DATA 0 A DATA 1 A P<br>MSB LSB MSB LSB<br>START condition R/W acknowledge acknowledge acknowledge acknowledge<br>from slave from slave from slave from slave<br>002aah063<br>**----- End of picture text -----**<br> **Fig 8. Write to Control registers** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** ## **7.2 Reading the port registers** In order to read data from the PCA9539A, the bus master must first send the PCA9539A address with the least significant bit set to a logic 0 (see Figure 4 “PCA9539A device address”). The command byte is sent after the address and determines which register will be accessed. After a restart, the device address is sent again, but this time the least significant bit is set to a logic 1. Data from the register defined by the command byte is sent by the PCA9539A (see Figure 9, Figure 10 and Figure 11). Data is clocked into the register on the falling edge of the acknowledge clock pulse. After the first byte is read, additional bytes may be read but the data now reflects the information in the other register in the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0. There is no limit on the number of data bytes received in one read transmission, but on the final byte received the bus master must not acknowledge the data. After a subsequent restart, the command byte contains the value of the next register to be read in the pair. For example, if Input Port 1 was read last before the restart, the register that is read after the restart is the Input Port 0. **==> picture [433 x 166] intentionally omitted <==** **----- Start of picture text -----**<br> slave address command byte<br>SDA S 1 1 1 0 1 A1 A0 0 A 0 0/1 0 0 0/1 0/1 0/1 0/1 A (cont.)<br>START condition R/W acknowledge<br>acknowledge from slave<br>from slave<br>data from lower or data from upper or<br>upper byte of register lower byte of register<br>slave address<br>MSB LSB MSB LSB<br>(cont.) S 1 1 1 0 1 A1 A0 1 A DATA (first byte) A DATA (last byte) NA P<br>(repeated) R/W acknowledge no acknowledge STOP<br>START condition acknowledge from master from master condition<br>from slave<br>at this moment master-transmitter becomes master-receiver<br>and slave-receiver becomes slave-transmitter<br>002aah064<br>**----- End of picture text -----**<br> **Remark:** Transfer can be stopped at any time by a STOP condition. **Fig 9. Read from register** © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **11 of 39** **==> picture [7 x 72] intentionally omitted <==** **----- Start of picture text -----**<br> Product data sheet<br>**----- End of picture text -----**<br> **==> picture [4 x 25] intentionally omitted <==** **----- Start of picture text -----**<br> PCA9539A<br>**----- End of picture text -----**<br> **==> picture [657 x 489] intentionally omitted <==** **----- Start of picture text -----**<br> data into port 0<br>data into port 1<br>INT<br>tv(INT) trst(INT)<br>SCL 1 2 3 4 5 6 7 8 9<br>R/W STOP condition<br>slave address I0.x I1.x I0.x I1.x<br>SDA S 1 1 1 0 1 A1 A0 1 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 1 P<br>START condition acknowledge acknowledge acknowledge acknowledge non acknowledge<br>from slave from master from master from master from master<br>read from port 0<br>read from port 1<br>002aah407<br>Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).<br>It is assumed that the command byte has previously been set to ‘00’ (read input port register).<br>This figure eliminates the command byte transfer and a restart between the initial slave address call and the actual data transfer from P port (see Figure 9).<br>Fig 10. Read input port register, scenario 1<br>pjgAll information rovided in this document is subect to leal disclaimers.<br>g© NXP B.V. 2013. All rihts reserved.<br>**----- End of picture text -----**<br> |1<br>1<br>0<br>1<br>A1 A0<br>1<br>A<br>S<br>1<br>START condition<br>R/W<br>acknowledge<br>from slave<br>_002aah408_<br>A<br>SCL<br>SDA<br>**A**<br>read from port 0<br>P<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>I0.x<br>slave address<br>STOP condition<br>acknowledge<br>from master<br>I1.x<br>acknowledge<br>from master<br>A<br>I0.x<br>acknowledge<br>from master<br>1<br>I1.x<br>non acknowledge<br>from master<br>data into port 0<br>read from port 1<br>data into port 1<br>INT<br>tv(INT)<br>trst(INT)<br>DATA 00<br>DATA 10<br>DATA 03<br>DATA 12<br>DATA 00<br>DATA 01<br>th(D)<br>th(D)<br>DATA 02<br>tsu(D)<br>DATA 03<br>tsu(D)<br>DATA 10<br>DATA 11<br>DATA 12|1<br>1<br>0<br>1<br>A1 A0<br>1<br>A<br>S<br>1<br>START condition<br>R/W<br>acknowledge<br>from slave<br>_002aah408_<br>A<br>SCL<br>SDA<br>**A**<br>read from port 0<br>P<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>I0.x<br>slave address<br>STOP condition<br>acknowledge<br>from master<br>I1.x<br>acknowledge<br>from master<br>A<br>I0.x<br>acknowledge<br>from master<br>1<br>I1.x<br>non acknowledge<br>from master<br>data into port 0<br>read from port 1<br>data into port 1<br>INT<br>tv(INT)<br>trst(INT)<br>DATA 00<br>DATA 10<br>DATA 03<br>DATA 12<br>DATA 00<br>DATA 01<br>th(D)<br>th(D)<br>DATA 02<br>tsu(D)<br>DATA 03<br>tsu(D)<br>DATA 10<br>DATA 11<br>DATA 12|1<br>1<br>0<br>1<br>A1 A0<br>1<br>A<br>S<br>1<br>START condition<br>R/W<br>acknowledge<br>from slave<br>_002aah408_<br>A<br>SCL<br>SDA<br>**A**<br>read from port 0<br>P<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>I0.x<br>slave address<br>STOP condition<br>acknowledge<br>from master<br>I1.x<br>acknowledge<br>from master<br>A<br>I0.x<br>acknowledge<br>from master<br>1<br>I1.x<br>non acknowledge<br>from master<br>data into port 0<br>read from port 1<br>data into port 1<br>INT<br>tv(INT)<br>trst(INT)<br>DATA 00<br>DATA 10<br>DATA 03<br>DATA 12<br>DATA 00<br>DATA 01<br>th(D)<br>th(D)<br>DATA 02<br>tsu(D)<br>DATA 03<br>tsu(D)<br>DATA 10<br>DATA 11<br>DATA 12|1<br>1<br>0<br>1<br>A1 A0<br>1<br>A<br>S<br>1<br>START condition<br>R/W<br>acknowledge<br>from slave<br>_002aah408_<br>A<br>SCL<br>SDA<br>**A**<br>read from port 0<br>P<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>I0.x<br>slave address<br>STOP condition<br>acknowledge<br>from master<br>I1.x<br>acknowledge<br>from master<br>A<br>I0.x<br>acknowledge<br>from master<br>1<br>I1.x<br>non acknowledge<br>from master<br>data into port 0<br>read from port 1<br>data into port 1<br>INT<br>tv(INT)<br>trst(INT)<br>DATA 00<br>DATA 10<br>DATA 03<br>DATA 12<br>DATA 00<br>DATA 01<br>th(D)<br>th(D)<br>DATA 02<br>tsu(D)<br>DATA 03<br>tsu(D)<br>DATA 10<br>DATA 11<br>DATA 12|1<br>1<br>0<br>1<br>A1 A0<br>1<br>A<br>S<br>1<br>START condition<br>R/W<br>acknowledge<br>from slave<br>_002aah408_<br>A<br>SCL<br>SDA<br>**A**<br>read from port 0<br>P<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>I0.x<br>slave address<br>STOP condition<br>acknowledge<br>from master<br>I1.x<br>acknowledge<br>from master<br>A<br>I0.x<br>acknowledge<br>from master<br>1<br>I1.x<br>non acknowledge<br>from master<br>data into port 0<br>read from port 1<br>data into port 1<br>INT<br>tv(INT)<br>trst(INT)<br>DATA 00<br>DATA 10<br>DATA 03<br>DATA 12<br>DATA 00<br>DATA 01<br>th(D)<br>th(D)<br>DATA 02<br>tsu(D)<br>DATA 03<br>tsu(D)<br>DATA 10<br>DATA 11<br>DATA 12|1<br>1<br>0<br>1<br>A1 A0<br>1<br>A<br>S<br>1<br>START condition<br>R/W<br>acknowledge<br>from slave<br>_002aah408_<br>A<br>SCL<br>SDA<br>**A**<br>read from port 0<br>P<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>I0.x<br>slave address<br>STOP condition<br>acknowledge<br>from master<br>I1.x<br>acknowledge<br>from master<br>A<br>I0.x<br>acknowledge<br>from master<br>1<br>I1.x<br>non acknowledge<br>from master<br>data into port 0<br>read from port 1<br>data into port 1<br>INT<br>tv(INT)<br>trst(INT)<br>DATA 00<br>DATA 10<br>DATA 03<br>DATA 12<br>DATA 00<br>DATA 01<br>th(D)<br>th(D)<br>DATA 02<br>tsu(D)<br>DATA 03<br>tsu(D)<br>DATA 10<br>DATA 11<br>DATA 12|1<br>1<br>0<br>1<br>A1 A0<br>1<br>A<br>S<br>1<br>START condition<br>R/W<br>acknowledge<br>from slave<br>_002aah408_<br>A<br>SCL<br>SDA<br>**A**<br>read from port 0<br>P<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>I0.x<br>slave address<br>STOP condition<br>acknowledge<br>from master<br>I1.x<br>acknowledge<br>from master<br>A<br>I0.x<br>acknowledge<br>from master<br>1<br>I1.x<br>non acknowledge<br>from master<br>data into port 0<br>read from port 1<br>data into port 1<br>INT<br>tv(INT)<br>trst(INT)<br>DATA 00<br>DATA 10<br>DATA 03<br>DATA 12<br>DATA 00<br>DATA 01<br>th(D)<br>th(D)<br>DATA 02<br>tsu(D)<br>DATA 03<br>tsu(D)<br>DATA 10<br>DATA 11<br>DATA 12|1<br>1<br>0<br>1<br>A1 A0<br>1<br>A<br>S<br>1<br>START condition<br>R/W<br>acknowledge<br>from slave<br>_002aah408_<br>A<br>SCL<br>SDA<br>**A**<br>read from port 0<br>P<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>I0.x<br>slave address<br>STOP condition<br>acknowledge<br>from master<br>I1.x<br>acknowledge<br>from master<br>A<br>I0.x<br>acknowledge<br>from master<br>1<br>I1.x<br>non acknowledge<br>from master<br>data into port 0<br>read from port 1<br>data into port 1<br>INT<br>tv(INT)<br>trst(INT)<br>DATA 00<br>DATA 10<br>DATA 03<br>DATA 12<br>DATA 00<br>DATA 01<br>th(D)<br>th(D)<br>DATA 02<br>tsu(D)<br>DATA 03<br>tsu(D)<br>DATA 10<br>DATA 11<br>DATA 12|1<br>1<br>0<br>1<br>A1 A0<br>1<br>A<br>S<br>1<br>START condition<br>R/W<br>acknowledge<br>from slave<br>_002aah408_<br>A<br>SCL<br>SDA<br>**A**<br>read from port 0<br>P<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>I0.x<br>slave address<br>STOP condition<br>acknowledge<br>from master<br>I1.x<br>acknowledge<br>from master<br>A<br>I0.x<br>acknowledge<br>from master<br>1<br>I1.x<br>non acknowledge<br>from master<br>data into port 0<br>read from port 1<br>data into port 1<br>INT<br>tv(INT)<br>trst(INT)<br>DATA 00<br>DATA 10<br>DATA 03<br>DATA 12<br>DATA 00<br>DATA 01<br>th(D)<br>th(D)<br>DATA 02<br>tsu(D)<br>DATA 03<br>tsu(D)<br>DATA 10<br>DATA 11<br>DATA 12|1<br>1<br>0<br>1<br>A1 A0<br>1<br>A<br>S<br>1<br>START condition<br>R/W<br>acknowledge<br>from slave<br>_002aah408_<br>A<br>SCL<br>SDA<br>**A**<br>read from port 0<br>P<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>I0.x<br>slave address<br>STOP condition<br>acknowledge<br>from master<br>I1.x<br>acknowledge<br>from master<br>A<br>I0.x<br>acknowledge<br>from master<br>1<br>I1.x<br>non acknowledge<br>from master<br>data into port 0<br>read from port 1<br>data into port 1<br>INT<br>tv(INT)<br>trst(INT)<br>DATA 00<br>DATA 10<br>DATA 03<br>DATA 12<br>DATA 00<br>DATA 01<br>th(D)<br>th(D)<br>DATA 02<br>tsu(D)<br>DATA 03<br>tsu(D)<br>DATA 10<br>DATA 11<br>DATA 12|1<br>1<br>0<br>1<br>A1 A0<br>1<br>A<br>S<br>1<br>START condition<br>R/W<br>acknowledge<br>from slave<br>_002aah408_<br>A<br>SCL<br>SDA<br>**A**<br>read from port 0<br>P<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>I0.x<br>slave address<br>STOP condition<br>acknowledge<br>from master<br>I1.x<br>acknowledge<br>from master<br>A<br>I0.x<br>acknowledge<br>from master<br>1<br>I1.x<br>non acknowledge<br>from master<br>data into port 0<br>read from port 1<br>data into port 1<br>INT<br>tv(INT)<br>trst(INT)<br>DATA 00<br>DATA 10<br>DATA 03<br>DATA 12<br>DATA 00<br>DATA 01<br>th(D)<br>th(D)<br>DATA 02<br>tsu(D)<br>DATA 03<br>tsu(D)<br>DATA 10<br>DATA 11<br>DATA 12|1<br>1<br>0<br>1<br>A1 A0<br>1<br>A<br>S<br>1<br>START condition<br>R/W<br>acknowledge<br>from slave<br>_002aah408_<br>A<br>SCL<br>SDA<br>**A**<br>read from port 0<br>P<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>I0.x<br>slave address<br>STOP condition<br>acknowledge<br>from master<br>I1.x<br>acknowledge<br>from master<br>A<br>I0.x<br>acknowledge<br>from master<br>1<br>I1.x<br>non acknowledge<br>from master<br>data into port 0<br>read from port 1<br>data into port 1<br>INT<br>tv(INT)<br>trst(INT)<br>DATA 00<br>DATA 10<br>DATA 03<br>DATA 12<br>DATA 00<br>DATA 01<br>th(D)<br>th(D)<br>DATA 02<br>tsu(D)<br>DATA 03<br>tsu(D)<br>DATA 10<br>DATA 11<br>DATA 12|1<br>1<br>0<br>1<br>A1 A0<br>1<br>A<br>S<br>1<br>START condition<br>R/W<br>acknowledge<br>from slave<br>_002aah408_<br>A<br>SCL<br>SDA<br>**A**<br>read from port 0<br>P<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>I0.x<br>slave address<br>STOP condition<br>acknowledge<br>from master<br>I1.x<br>acknowledge<br>from master<br>A<br>I0.x<br>acknowledge<br>from master<br>1<br>I1.x<br>non acknowledge<br>from master<br>data into port 0<br>read from port 1<br>data into port 1<br>INT<br>tv(INT)<br>trst(INT)<br>DATA 00<br>DATA 10<br>DATA 03<br>DATA 12<br>DATA 00<br>DATA 01<br>th(D)<br>th(D)<br>DATA 02<br>tsu(D)<br>DATA 03<br>tsu(D)<br>DATA 10<br>DATA 11<br>DATA 12|1<br>1<br>0<br>1<br>A1 A0<br>1<br>A<br>S<br>1<br>START condition<br>R/W<br>acknowledge<br>from slave<br>_002aah408_<br>A<br>SCL<br>SDA<br>**A**<br>read from port 0<br>P<br>9<br>8<br>7<br>6<br>5<br>4<br>3<br>2<br>1<br>I0.x<br>slave address<br>STOP condition<br>acknowledge<br>from master<br>I1.x<br>acknowledge<br>from master<br>A<br>I0.x<br>acknowledge<br>from master<br>1<br>I1.x<br>non acknowledge<br>from master<br>data into port 0<br>read from port 1<br>data into port 1<br>INT<br>tv(INT)<br>trst(INT)<br>DATA 00<br>DATA 10<br>DATA 03<br>DATA 12<br>DATA 00<br>DATA 01<br>th(D)<br>th(D)<br>DATA 02<br>tsu(D)<br>DATA 03<br>tsu(D)<br>DATA 10<br>DATA 11<br>DATA 12|DATA 03|DATA 03|DATA 03|DATA 03|DATA 03|DATA 03|DATA 03| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| ||||||||||||||||||STOP condition<br>I1.x|||| |||||||||||||I1.x||||||||| ||S|1|1|1|0|1|A1|A0|1<br>|A|DATA 00|A|DATA 10||**A**|DATA 03|A|DATA 12|1|P| |||||||||||<br>acknowledge<br>from maste||r<br>acknowledge<br>from master|||<br>acknowledge<br>from master||<br>non acknowledge<br>from master|||| ||||||||||||||||||_002aah408_|||| |||||||||||||||||||||| **Remark:** Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to ‘00’ (read input port register). This figure eliminates the command byte transfer and a restart between the initial slave address call and the actual data transfer from P port (see Figure 9). **Fig 11. Read input port register, scenario 2** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** ## **8. Application design-in information** **==> picture [473 x 289] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>(3.3 V) SUB-SYSTEM 1 [(1)]<br>10 kΩ 10 kΩ 10 kΩ 10 kΩ 2 kΩ 100 kΩ (e.g., temp sensor)<br>VDD VDD (×3)<br>MASTER INT<br>CONTROLLER PCA9539A<br>SCL SCL P0_0<br>SUB-SYSTEM 2<br>SDA SDA<br>P0_1 (e.g., counter)<br>INT INT<br>P0_2 RESET<br>RESET RESET<br>P0_3<br>A<br>VSS P0_4 enable controlled<br>switch<br>P0_5 (e.g., CBT device)<br>B<br>P0_6<br>P0_7 SUB-SYSTEM 3 [(1)]<br>P1_0 (e.g., alarm system)<br>P1_1 10 DIGIT<br>P1_2 NUMERIC ALARM<br>P1_3 KEYPAD<br>P1_4<br>P1_5 VDD<br>A1 P1_6<br>A0 P1_7<br>VSS<br>002aag163<br>**----- End of picture text -----**<br> Device address configured as 1110 100X for this example. P0_0, P0_2, P0_3 configured as outputs. P0_1, P0_4, P0_5 configured as inputs. P0_6, P0_7 and P1_0 to P1_7 configured as inputs. - (1) External resistors are required for inputs (on P port) that may float. If a driver to an input will never let the input float, a resistor is not needed. If an output in the P port is configured as a push-pull output there is no need for external pull-up resistors. If an output in the P port is configured as an open-drain output, external pull-up resistors are required. ## **Fig 12. Typical application** ## **8.1 Minimizing IDD when the I/Os are used to control LEDs** When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 12. Since the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower than VDD. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 13 shows a high value resistor in parallel with the LED. Figure 14 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VDD and prevents additional supply current consumption when the LED is off. © NXP B.V. 2013. All rights reserved. PCA9539A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 2 — 12 August 2013** **14 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** **==> picture [397 x 166] intentionally omitted <==** **----- Start of picture text -----**<br> 3.3 V 5 V<br>VDD<br>VDD LED 100 kΩ VDD LED<br>Pn Pn<br>002aag164 002aag165<br>Fig 13. High value resistor in parallel with Fig 14. Device supplied by a lower voltage<br>the LED<br>**----- End of picture text -----**<br> ## **8.2 Power-on reset requirements** In the event of a glitch or data corruption, PCA9539A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application. The two types of power-on reset are shown in Figure 15 and Figure 16. **==> picture [380 x 113] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>ramp-up ramp-down re-ramp-up<br>td(rst)<br>time<br>(dV/dt)r (dV/dt)f time to re-ramp (dV/dt)r<br>when VDD drops<br>below 0.2 V or to VSS 002aah329<br>Fig 15. VDD is lowered below 0.2 V or to 0 V and then ramped up to VDD<br>**----- End of picture text -----**<br> **==> picture [337 x 91] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>ramp-down ramp-up<br>VI drops below POR levels td(rst)<br>time<br>time to re-ramp<br>(dV/dt)f (dV/dt)r<br>when VDD drops<br>to VPOR(min) − 50 mV 002aah330<br>**----- End of picture text -----**<br> **Fig 16. VDD is lowered below the POR threshold, then ramped back up to VDD** Table 13 specifies the performance of the power-on reset feature for PCA9539A for both types of power-on reset. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. PCA9539A **Product data sheet** **Rev. 2 — 12 August 2013** **15 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** **Table 13. Recommended supply sequencing and ramp rates** _Tamb = 25_ _C (unless otherwise noted). Not tested; specified by design._ |**Symbol**<br>**Parameter**|**Condition**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**| |---|---| |(dV/dt)f<br>fall rate of change of voltage|Figure 15<br>0.1<br>-<br>2000<br>ms| |(dV/dt)r<br>rise rate of change of voltage|Figure 15<br>0.1<br>-<br>2000<br>ms| |td(rst)<br>reset delay time|Figure 15<br>;re-ramp time when<br>VDDdrops below 0.2 V or to VSS<br>1<br>-<br>-<br>s| ||Figure 16<br>;re-ramp time when<br>VDDdrops to VPOR(min)50 mV<br>1<br>-<br>-<br>s| |VDD(gl)<br>glitch supply voltage difference|Figure 17<br>[1]<br>-<br>-<br>1<br>V| |tw(gl)VDD<br>supply voltage glitch pulse width|Figure 17<br>[2]<br>-<br>-<br>10<br>s| |VPOR(trip)<br>power-on reset trip voltage|falling VDD<br>0.7<br>-<br>-<br>V| ||rising VDD<br>-<br>-<br>1.4<br>V| [1] Level that VDD can glitch down to with a ramp rate of 0.4 s/V, but not cause a functional disruption when tw(gl)VDD < 1 s. [2] Glitch width that will not cause a functional disruption when VDD(gl) = 0.5 VDD. Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (tw(gl)VDD) and glitch height (VDD(gl)) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 17 and Table 13 provide more information on how to measure these specifications. **==> picture [358 x 92] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>∆VDD(gl)<br>time<br>tw(gl)VDD 002aah331<br>Fig 17. Glitch width and glitch height<br>**----- End of picture text -----**<br> VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I[2] C-bus/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VDD being lowered to or from 0 V. Figure 18 and Table 13 provide more details on this specification. **==> picture [273 x 147] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>VPOR (rising VDD)<br>VPOR (falling VDD)<br>POR<br>Fig 18. Power-on reset voltage (VPOR)<br>**----- End of picture text -----**<br> **==> picture [33 x 73] intentionally omitted <==** **----- Start of picture text -----**<br> time<br>time<br>002aah332<br>**----- End of picture text -----**<br> All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. PCA9539A **Product data sheet** **Rev. 2 — 12 August 2013** **16 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** ## **9. Limiting values** ## **Table 14. Limiting values** _In accordance with the Absolute Maximum Rating System (IEC 60134)._ |**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Max**<br>**Unit**|**Conditions**<br>**Min**<br>**Max**<br>**Unit**| |---|---|---| |VDD<br>supply voltage||0.5<br>+6.5<br>V| |VI<br>input voltage||[1]<br>0.5<br>+6.5<br>V| |VO<br>output voltage||[1]<br>0.5<br>+6.5<br>V| |IIK<br>input clamping current|A0, A1,|RESET<br>, SCL; VI< 0 V<br>-<br>20<br>mA| |IOK<br>output clamping current|INT<br>; VO< 0 V<br>-<br>20<br>mA|| |IIOK<br>input/output clamping current|P port; VO< 0 V or VO> VDD<br>-<br>20<br>mA|| ||SDA; VO< 0 V or VO> VDD<br>-<br>20<br>mA|| |IOL<br>LOW-level output current|continuous; I/O port<br>-<br>50<br>mA|| ||continuous; SDA, INT<br>-<br>25<br>mA|| |IOH<br>HIGH-level output current|continuous; P port<br>-<br>25<br>mA|| |IDD<br>supply current|-<br>160<br>mA|| |ISS<br>ground supply current|-<br>200<br>mA|| |Ptot<br>total power dissipation|-<br>200<br>mW|| |Tstg<br>storage temperature|65<br>+150<br>C|| |Tj(max)<br>maximum junction temperature|-<br>125<br>C|| [1] The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. ## **10. Recommended operating conditions** |**Table 15.**<br>**Operating conditions**||| |---|---|---| |**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Max**<br>**Unit**|| |VDD<br>supply voltage||1.65<br>5.5<br>V| |VIH<br>HIGH-level input voltage|SCL, SDA,|RESET<br>0.7VDD<br>5.5<br>V| ||A0, A1, P1_7 to P0_0<br>0.7VDD<br>5.5<br>V|| |VIL<br>LOW-level input voltage|SCL, SDA,|RESET<br>0.5<br>0.3VDD<br>V| ||A0, A1, P1_7 to P0_0<br>0.5<br>0.3VDD<br>V|| |IOH<br>HIGH-level output current|P1_7 to P0_0<br>-<br>10<br>mA|| |IOL<br>LOW-level output current|P1_7 to P0_0<br>-<br>25<br>mA|| |Tamb<br>ambient temperature|operating in free air<br>40<br>+85<br>C|| ## **11. Thermal characteristics** ## **Table 16. Thermal characteristics** |**Symbol**<br>**Parameter**|**Conditions**<br>**Max**<br>**Unit**| |---|---| |Zth(j-a)<br>transient thermal impedance from junction to ambient|TSSOP24 package<br>[1]<br>88<br>K/W| ||HWQFN24 package<br>[1]<br>66<br>K/W| [1] The package thermal impedance is calculated in accordance with JESD 51-7. © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **17 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** ## **12. Static characteristics** **Table 17. Static characteristics** _Tamb =_ _40_ _C to +85_ _C; VDD = 1.65 V to 5.5 V; unless otherwise specified._ |**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Ty**~~**p**~~**[1]**<br>**Max**<br>**Unit**| |---|---| |VIK<br>input clamping voltage|II=18 mA<br>1.2<br>-<br>-<br>V| |VPOR<br>power-on reset voltage|VI= VDDor VSS; IO= 0 mA<br>-<br>1.1<br>1.4<br>V| |IOL<br>LOW-level output current|VOL= 0.4 V; VDD= 1.65 V to 5.5 V| ||SDA<br>3<br>-<br>-<br>mA| ||INT<br>3<br>1~~5~~[2]<br>-<br>mA| ||P port| ||VOL= 0.5 V; VDD= 1.65 V<br>[3]<br>8<br>10<br>-<br>mA| ||VOL= 0.7 V; VDD= 1.65 V<br>[3]<br>10<br>13<br>-<br>mA| ||VOL= 0.5 V; VDD= 2.3 V<br>[3]<br>8<br>10<br>-<br>mA| ||VOL= 0.7 V; VDD= 2.3 V<br>[3]<br>10<br>13<br>-<br>mA| ||VOL= 0.5 V; VDD= 3.0 V<br>[3]<br>8<br>14<br>-<br>mA| ||VOL= 0.7 V; VDD= 3.0 V<br>[3]<br>10<br>19<br>-<br>mA| ||VOL= 0.5 V; VDD= 4.5 V<br>[3]<br>8<br>17<br>-<br>mA| ||VOL= 0.7 V; VDD= 4.5 V<br>[3]<br>10<br>24<br>-<br>mA| |VOH<br>HIGH-level output voltage|P port| ||IOH=8 mA; VDD= 1.65 V<br>[4]<br>1.2<br>-<br>-<br>V| ||IOH=10 mA; VDD= 1.65 V<br>[4]<br>1.1<br>-<br>-<br>V| ||IOH=8 mA; VDD= 2.3 V<br>[4]<br>1.8<br>-<br>-<br>V| ||IOH=10 mA; VDD= 2.3 V<br>[4]<br>1.7<br>-<br>-<br>V| ||IOH=8 mA; VDD= 3.0 V<br>[4]<br>2.6<br>-<br>-<br>V| ||IOH=10 mA; VDD= 3.0 V<br>[4]<br>2.5<br>-<br>-<br>V| ||IOH=8 mA; VDD= 4.5 V<br>[4]<br>4.1<br>-<br>-<br>V| ||IOH=10 mA; VDD= 4.5 V<br>[4]<br>4.0<br>-<br>-<br>V| |VOL<br>LOW-level output voltage|P port; IOL= 8 mA| ||VDD= 1.65 V<br>-<br>-<br>0.45<br>V| ||VDD= 2.5 V<br>-<br>-<br>0.25<br>V| ||VDD= 3.0 V<br>-<br>-<br>0.25<br>V| ||VDD= 4.5 V<br>-<br>-<br>0.2<br>V| |II<br>input current|VDD= 1.65 V to 5.5 V| ||SCL, SDA; VI= VDDor VSS<br>-<br>-<br>1<br>A| ||A0, A1, A2; VI= VDDor VSS<br>-<br>-<br>1<br>A| |IIH<br>HIGH-level input current|P port; VI= VDD; VDD= 1.65 V to 5.5 V<br>-<br>-<br>1<br>A| |IIL<br>LOW-level input current|P port; VI= VSS; VDD= 1.65 V to 5.5 V<br>-<br>-<br>1<br>A| © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **18 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** **Table 17. Static characteristics** _…continued_ _Tamb =_ _40_ _C to +85_ _C; VDD = 1.65 V to 5.5 V; unless otherwise specified._ |**Symbol**<br>**Parameter**|**Conditions**|**Min**<br>**Ty**~~**p**~~**[1]**<br>**Max**<br>**Unit**|**Min**<br>**Ty**~~**p**~~**[1]**<br>**Max**<br>**Unit**|**Min**<br>**Ty**~~**p**~~**[1]**<br>**Max**<br>**Unit**| |---|---|---|---|---| |IDD<br>supply current|SDA, P port, A0, A1, RESET<br>;<br>VIon SDA = VDDor VSS;<br>VIon P port and A0, A1, RESET<br>= VDD;<br>IO= 0 mA; I/O = inputs; fSCL= 400 kHz|||| ||VDD= 3.6 V to 5.5 V||-<br>10<br>25<br>A|| ||VDD= 2.3 V to 3.6 V||-<br>6.5<br>15<br>A|| ||VDD= 1.65 V to 2.3 V||-<br>4<br>9<br>A|| ||SCL, SDA, P port, A0, A1, RESET<br>;<br>VIon SCL and SDA = VDD or VSS;<br>VIon P port and A0, A1, RESET<br>= VDD;<br>IO= 0 mA; I/O = inputs; fSCL= 0 kHz|||| ||VDD= 3.6 V to 5.5 V|||-<br>1.5<br>7<br>A| ||VDD= 2.3 V to 3.6 V|||-<br>1<br>3.2<br>A| ||VDD= 1.65 V to 2.3 V|||-<br>0.5<br>1.7<br>A| ||Active mode;P port, A0, A1, RESET<br>;<br>VIon RESET<br>= VDD;<br>VIon P port and A0, A1 = VDD;<br>IO= 0 mA; I/O = inputs;<br>fSCL= 400 kHz, continuous register read|||| ||VDD= 3.6 V to 5.5 V<br>-<br>60<br>125<br>A|||| ||VDD= 2.3 V to 3.6 V<br>-<br>40<br>75<br>A|||| ||VDD= 1.65 V to 2.3 V<br>-<br>20<br>45<br>A|||| |IDD<br>additional quiescent<br>supply current|SCL, SDA, RESET<br>; one input at VDD0.6 V,<br>other inputs at VDDor VSS;<br>VDD= 1.65 V to 5.5 V<br>-<br>-<br>25<br>A|||| ||P port, A0, A1; one input at VDD0.6 V,<br>other inputs at VDDor VSS;<br>VDD= 1.65 V to 5.5 V<br>-<br>-<br>80<br>A|||| |Ci<br>input capacitance|VI= VDDor VSS; VDD= 1.65 V to 5.5 V<br>-<br>6<br>7<br>pF|||| |Cio<br>input/output capacitance|VI/O= VDDor VSS; VDD= 1.65 V to 5.5 V<br>-<br>7<br>8<br>pF|||| ||VI/O= VDDor VSS; VDD= 1.65 V to 5.5 V<br>-<br>7.5<br>8.5<br>pF|||| [1] For IDD, all typical values are at nominal supply voltage (1.8 V, 2.5 V, 3.3 V, 3.6 V or 5 V VDD) and Tamb = 25 C. Except for IDD, the typical values are at VDD = 3.3 V and Tamb = 25 C. [2] Typical value for Tamb = 25 C. VOL = 0.4 V and VDD = 3.3 V. Typical value for VDD < 2.5 V, VOL = 0.6 V. [3] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 200 mA. [4] The total current sourced by all I/Os must be limited to 160 mA. © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **19 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** ## **12.1 Typical characteristics** **==> picture [481 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aah333 002aah334<br>20 1400<br>(μA)IDD IDD(stb)<br>(nA)<br>16 VDD = 5.5 V<br>VDD = 5.5 V5.0 V 1000 5.0 V3.6 V<br>12 33.3 V.6 V 800 3.3 V<br>2.5 V<br>2.3 V<br>600<br>8<br>400<br>2.5 V<br>4 2.3 V<br>VDD = 1.8 V1.65 V 200 1.8 V1.65 V<br>0 0<br>−40 −15 10 35 60 85 −40 −15 10 35 60 85<br>Tamb (°C) Tamb (°C)<br>**----- End of picture text -----**<br> **Fig 19. Supply current versus ambient temperature Fig 20. Standby supply current versus ambient temperature** **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aah335<br>20<br>IDD<br>(μA)<br>16<br>12<br>8<br>4<br>0<br>1.5 2.5 3.5 4.5 5.5<br>VDD (V)<br>**----- End of picture text -----**<br> Tamb = 25 C **Fig 21. Supply current versus supply voltage** © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **20 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aaf578<br>35<br>Isink<br>(mA)<br>30<br>Tamb = −40 °C<br>25 25 ° C<br>85 °C<br>20<br>15<br>10<br>5<br>0<br>0 0.1 0.2 0.3<br>VOL (V)<br>**----- End of picture text -----**<br> ## a. VDD = 1.65 V **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aaf579<br>35<br>Isink<br>(mA)<br>30<br>Tamb = −40 °C<br>25 25 °C<br>85 °C<br>20<br>15<br>10<br>5<br>0<br>0 0.1 0.2 0.3<br>VOL (V)<br>**----- End of picture text -----**<br> ## b. VDD = 1.8 V **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aaf580<br>50<br>Isink<br>(mA)<br>40<br>Tamb = −40 °C<br>25 °C<br>30 85 °C<br>20<br>10<br>0<br>0 0.1 0.2 0.3<br>VOL (V)<br>**----- End of picture text -----**<br> **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aaf581<br>60<br>Isink Tamb = − 40 ° C<br>(mA) 25 °C<br>85 °C<br>40<br>20<br>0<br>0 0.1 0.2 0.3<br>VOL (V)<br>**----- End of picture text -----**<br> ## c. VDD = 2.5 V d. VDD = 3.3 V **==> picture [481 x 170] intentionally omitted <==** **----- Start of picture text -----**<br> 002aaf582 002aaf583<br>70 70<br>Isink Isink<br>(mA) 60 Tamb = −40 ° C (mA) 60 Tamb = −40 °C<br>25 °C 25 °C<br>50 85 ° C 50 85 ° C<br>40 40<br>30 30<br>20 20<br>10 10<br>0 0<br>0 0.1 0.2 0.3 0 0.1 0.2 0.3<br>VOL (V) VOL (V)<br>e. VDD = 5.0 V f. VDD = 5.5 V<br>**----- End of picture text -----**<br> **Fig 22. I/O sink current versus LOW-level output voltage** © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **21 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aah337<br>30<br>Isource<br>(mA) Tamb = −40 °C<br>25 °C<br>20 85 °C<br>10<br>0<br>0 0.2 0.4 0.6<br>VDD − VOH (V)<br>**----- End of picture text -----**<br> ## a. VDD = 1.65 V **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aah338<br>35<br>Isource<br>(mA) 30 Tamb = −40 ° C<br>25 °C<br>25 85 ° C<br>20<br>15<br>10<br>5<br>0<br>0 0.2 0.4 0.6<br>VDD − VOH (V)<br>**----- End of picture text -----**<br> ## b. VDD = 1.8 V **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aah339<br>60<br>Isource<br>(mA)<br>Tamb = −40 °C<br>25 °C<br>40<br>85 °C<br>20<br>0<br>0 0.2 0.4 0.6<br>VDD − VOH (V)<br>**----- End of picture text -----**<br> **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aah340<br>70<br>Isource<br>(mA) 60 Tamb = −40 ° C<br>25 °C<br>50 85 ° C<br>40<br>30<br>20<br>10<br>0<br>0 0.2 0.4 0.6<br>VDD − VOH (V)<br>**----- End of picture text -----**<br> ## c. VDD = 2.5 V d. VDD = 3.3 V **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aah341<br>90<br>Isource(mA) T amb = −40 °C<br>25 °C<br>85 °C<br>60<br>30<br>0<br>0 0.2 0.4 0.6<br>VDD − VOH (V)<br>**----- End of picture text -----**<br> e. VDD = 5.0 V **==> picture [233 x 149] intentionally omitted <==** **----- Start of picture text -----**<br> 002aah342<br>90<br>Isource(mA) T amb = −40 °C<br>25 °C<br>85 °C<br>60<br>30<br>0<br>0 0.2 0.4 0.6<br>VDD − VOH (V)<br>**----- End of picture text -----**<br> f. VDD = 5.5 V **Fig 23. I/O source current versus HIGH-level output voltage** © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **22 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** **==> picture [481 x 169] intentionally omitted <==** **----- Start of picture text -----**<br> 002aah056 002aah343<br>120 200<br>(mV)VOL VDD − VOH (mV)<br>100<br>160<br>(1)<br>80<br>120 V DD = 1.8 V<br>5 V<br>60<br>(2) 80<br>40<br>(4) 40<br>20<br>(3)<br>0 0<br>−40 −15 10 35 60 85 −40 −15 10 35 60 85<br>Tamb (°C) Tamb (°C)<br>(1) VDD = 1.8 V; Isink = 10 mADD = 1.8 V; Isink = 10 mA = 1.8 V; Isink = 10 mAsink = 10 mA = 10 mA Isource = 10 mA<br>**----- End of picture text -----**<br> - (1) VDD = 1.8 V; Isink = 10 mADD = 1.8 V; Isink = 10 mA = 1.8 V; Isink = 10 mAsink = 10 mA = 10 mA (2) VDD = 5 V; Isink = 10 mA - (3) VDD = 1.8 V; Isink = 1 mA (4) VDD = 5 V; Isink = 1 mA **Fig 24. LOW-level output voltage versus temperature Fig 25. I/O high voltage versus temperature** © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **23 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** ## **13. Dynamic characteristics** ## **Table 18. I[2] C-bus interface timing requirements** _Over recommended operating free air temperature range, unless otherwise specified. See Figure 26._ |**Symbol**<br>**Parameter**<br>**Conditions**|**Standard-mode**<br>**I2C-bus**|**Standard-mode**<br>**I2C-bus**|**Fast-mode**<br>**I2C-bus**|**Fast-mode**<br>**I2C-bus**|**Unit**| |---|---|---|---|---|---| ||**Min**|**Max**|**Min**|**Max**|| |fSCL<br>SCL clock frequency|0<br>100<br>0<br>400<br>kHz||||| |tHIGH<br>HIGH period of the SCL clock|4<br>-<br>0.6<br>-<br>s||||| |tLOW<br>LOW period of the SCL clock|4.7<br>-<br>1.3<br>-<br>s||||| |tSP<br>pulse width of spikes that must<br>be suppressed by the input filter|0<br>50<br>0<br>50<br>ns||||| |tSU;DAT<br>data set-up time|250<br>-<br>100<br>-<br>ns||||| |tHD;DAT<br>data hold time|0<br>-<br>0<br>-<br>ns||||| |tr<br>rise time of both SDA and SCL signals|-<br>1000<br>20<br>300<br>ns||||| |tf<br>fall time of both SDA and SCL signals|-<br>300<br>20<br>(VDD/ 5.5 V)<br>300<br>ns||||| |tBUF<br>bus free time between a STOP and<br>START condition|4.7<br>-<br>1.3<br>-<br>s||||| |tSU;STA<br>set-up time for a repeated START<br>condition|4.7<br>-<br>0.6<br>-<br>s||||| |tHD;STA<br>hold time (repeated) START condition|4<br>-<br>0.6<br>-<br>s||||| |tSU;STO<br>set-up time for STOP condition|4<br>-<br>0.6<br>-<br>s||||| |tVD;DAT<br>data valid time<br>SCL LOW<br>to SDA output valid|-<br>3.45<br>-<br>0.9<br>s||||| |tVD;ACK<br>data valid acknowledge time<br>ACK signal<br>from SCL LOW<br>to SDA (out) LOW|-<br>3.45<br>-<br>0.9<br>s||||| ## **Table 19. Reset timing requirements** _Over recommended operating free air temperature range, unless otherwise specified. See Figure 28._ |**Symbol**<br>**Parameter**<br>**Conditions**|**Standard-m**<br>**I2C-bus**|**Standard-m**<br>**I2C-bus**|**ode**||**Fast-mode**<br>**I2C-bus**|**Fast-mode**<br>**I2C-bus**|**Unit**| |---|---|---|---|---|---|---|---| ||**Min**|**M**|**ax**||**Min**|**Max**|| |tw(rst)<br>reset pulse width|30<br>-<br>30<br>-<br>ns||||||| |trec(rst)<br>reset recovery time|200<br>-<br>200<br>-<br>ns||||||| |trst<br>reset time<br>[1]|600<br>-<br>600<br>-<br>ns||||||| [1] Minimum time for SDA to become HIGH or minimum time to wait before doing a START. © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **24 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** **Table 20. Switching characteristics** _Over recommended operating free air temperature range; CL_ _100 pF; unless otherwise specified. See Figure 26._ |**Symbol**<br>**Parameter**<br>**Conditions**|**Standard-mode**<br>**I2C-bus**|**Standard-mode**<br>**I2C-bus**|**Fast-mode**<br>**I2C-bus**|**Fast-mode**<br>**I2C-bus**|**Unit**| |---|---|---|---|---|---| ||**Min**|**Max**|**Min**|**Max**|| |tv(INT)<br>valid time on pin INT<br>from P port to INT|-<br>1<br>-<br>1<br>s||||| |trst(INT)<br>reset time on pin INT<br>from SCL to INT|-<br>1<br>-<br>1<br>s||||| |tv(Q)<br>data output valid time<br>from SCL to P port|-<br>400<br>-<br>400<br>ns||||| |tsu(D)<br>data input set-up time<br>from P port to SCL|0<br>-<br>0<br>-<br>ns||||| |th(D)<br>data input hold time<br>from P port to SCL|300<br>-<br>300<br>-<br>ns||||| ## **14. Parameter measurement information** **==> picture [425 x 332] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>RL = 1 kΩ<br>SDA<br>DUT<br>CL = 50 pF<br>002aag803<br>SDA load configuration<br>two bytes for read Input port register [(1)]<br>STOP START Address Address R/W ACK Data Data STOP<br>condition condition Bit 7 Bit 1 Bit 0 (A) Bit 7 Bit 0 condition<br>(P) (S) (MSB) (LSB) (MSB) (LSB) (P)<br>002aag952<br>Transaction format<br>tLOW tHIGH tSP<br>0.7 × VDD<br>SCL<br>0.3 × VDD<br>tBUF tr tf tVD;DATtf(o) tVD;ACK tSU;STA tSU;STO<br>0.7 × VDD<br>SDA<br>0.3 × VDD<br>tf tr tVD;ACK<br>tHD;STA tSU;DAT tHD;DAT<br>repeat START condition<br>STOP condition<br>002aag804<br>**----- End of picture text -----**<br> - a. SDA load configuration - b. Transaction format ## c. Voltage waveforms ## CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns. All parameters and waveforms are not applicable to all devices. Byte 1 = I[2] C-bus address; Byte 2, byte 3 = P port data. - (1) See Figure 9. **Fig 26. I[2] C-bus interface load circuit and voltage waveforms** All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. PCA9539A **Product data sheet** **Rev. 2 — 12 August 2013** **25 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** **==> picture [445 x 404] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>RL = 4.7 kΩ<br>INT<br>DUT<br>CL = 100 pF<br>002aah069<br>a. Interrupt load configuration<br>acknowledge acknowledge no acknowledge<br>from slave from slave from master<br>START condition R/W STOP<br>8 bits (one data byte) condition<br>slave address from port data from port<br>SDA S 1 1 1 0 1 A1 A0 1 A DATA 1 A DATA 2 1 P<br>SCL 1 2 3 4 5 6 7 8 9<br>B<br>trst(INT) trst(INT) B<br>INT<br>A<br>tv(INT) A tsu(D)<br>data into<br>ADDRESS DATA 1 DATA 2<br>port<br>0.7 × VDD<br>INT 0.5 × VDD SCL R/W A<br>0.3 × VDD<br>tv(INT) trst(INT)<br>Pn 0.5 × VDD INT 0.5 × VDD<br>View A - A View B - B<br>002aah070<br>**----- End of picture text -----**<br> ## b. Voltage waveforms ## CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns. All parameters and waveforms are not applicable to all devices. ## **Fig 27. Interrupt load circuit and voltage waveforms** © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **26 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** **==> picture [265 x 360] intentionally omitted <==** **----- Start of picture text -----**<br> Pn 500 Ω<br>DUT 2 × VDD<br>CL = 50 pF 500 Ω<br>002aag805<br>0.7 × VDD<br>SCL P0 A P7<br>0.3 × VDD<br>SDA<br>tv(Q)<br>Pn<br>unstable last stable bit<br>data<br>002aag806<br>= 0)<br>0.7 × VDD<br>SCL P0 A P7<br>0.3 × VDD<br>tsu(D) th(D)<br>Pn<br>002aag807<br>**----- End of picture text -----**<br> ## a. P port load configuration ## b. Write mode (R/W = 0) ## c. Read mode (R/W = 1) CL includes probe and jig capacitance. tv(Q) is measured from 0.7 VDD on SCL to 50 % I/O (Pn) output. All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns. The outputs are measured one at a time, with one transition per measurement. All parameters and waveforms are not applicable to all devices. ## **Fig 28. P port load circuit and voltage waveforms** © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **27 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** **==> picture [434 x 302] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>RL = 1 kΩ<br>SDA Pn 500 Ω<br>DUT DUT 2 × VDD<br>CL = 50 pF CL = 50 pF 500 Ω<br>002aag803 002aag805<br>SDA load configuration b. P port load configuration<br>START<br>SCL ACK or read cycle<br>SDA<br>0.3 × VDD<br>trst<br>RESET 0.5 × VDD<br>trec(rst) tw(rst) trec(rst)<br>trst<br>Pn 0.5 × VDD<br>002aah073<br>**----- End of picture text -----**<br> ## a. SDA load configuration ## c. RESET timing ## CL includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns. The outputs are measured one at a time, with one transition per measurement. I/Os are configured as inputs. All parameters and waveforms are not applicable to all devices. **Fig 29. Reset load circuits and voltage waveforms** © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **28 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** ## **15. Package outline** **Fig 30. Package outline SOT355-1 (TSSOP24)** PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** © NXP B.V. 2013. All rights reserved. **29 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** ## **Fig 31. Package outline SOT994-1 (HWQFN24)** All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. PCA9539A **Product data sheet** **Rev. 2 — 12 August 2013** **30 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** ## **16. Handling information** All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in _JESD625-A_ or equivalent standards. ## **17. Soldering of SMD packages** This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note _AN10365 “Surface mount reflow soldering description”_ . ## **17.1 Introduction to soldering** Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. ## **17.2 Wave and reflow soldering** Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: - Through-hole components - Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: - Board specifications, including the board finish, solder masks and vias - Package footprints, including solder thieves and orientation - The moisture sensitivity level of the packages - Package placement - Inspection and repair - Lead-free soldering versus SnPb soldering ## **17.3 Wave soldering** Key characteristics in wave soldering are: All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. PCA9539A **Product data sheet** **Rev. 2 — 12 August 2013** **31 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** - Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave - Solder bath specifications, including temperature and impurities ## **17.4 Reflow soldering** Key characteristics in reflow soldering are: - Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 32) than a SnPb process, thus reducing the process window - Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board - Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 21 and 22 ## **Table 21. SnPb eutectic process (from J-STD-020D)** |**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**| |---|---|---| ||**Volume (mm3)**|| ||**< 350**|**350**| |< 2.5|235<br>220|| |2.5|220<br>220|| ## **Table 22. Lead-free process (from J-STD-020D)** |**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**| |---|---|---|---| ||**Volume (mm3)**||| ||**< 350**|**350 to 2000**|**> 2000**| |< 1.6|260<br>260<br>260||| |1.6 to 2.5|260<br>250<br>245||| |> 2.5|250<br>245<br>245||| Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 32. © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **32 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** **==> picture [352 x 223] intentionally omitted <==** **----- Start of picture text -----**<br> maximum peak temperature<br>= MSL limit, damage level<br>temperature<br>minimum peak temperature<br>= minimum soldering temperature<br>peak<br> temperature<br>time<br>001aac844<br>MSL: Moisture Sensitivity Level<br>Fig 32. Temperature profiles for large and small components<br>**----- End of picture text -----**<br> For further information on temperature profiles, refer to Application Note _AN10365 “Surface mount reflow soldering description”_ . © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **33 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** ## **18. Soldering: PCB footprints** **Fig 33. PCB footprint for SOT355-1 (TSSOP24); reflow soldering** All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. PCA9539A **Product data sheet** **Rev. 2 — 12 August 2013** **34 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** ## **Fig 34.** ## **PCB footprint for SOT994-1 (HWQFN24); reflow soldering** © NXP B.V. 2013. All rights reserved. PCA9539A **Product data sheet** All information provided in this document is subject to legal disclaimers. **Rev. 2 — 12 August 2013** **35 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** ## **19. Abbreviations** **Table 23. Abbreviations** |**Acronym**|**Description**| |---|---| |ACPI|Advanced Configuration and Power Interface| |CBT|Cross-Bar Technology| |CDM|Charged-Device Model| |CMOS|Complementary Metal-Oxide Semiconductor| |ESD|ElectroStatic Discharge| |FET|Field-Effect Transistor| |FF|Flip-Flop| |GPIO|General Purpose Input/Output| |HBM|Human Body Model| |I2C-bus|Inter-Integrated Circuit bus| |I/O|Input/Output| |LED|Light Emitting Diode| |PCB|Printed-Circuit Board| |POR|Power-On Reset| |SMBus|System Management Bus| ## **20. Revision history** ## **Table 24. Revision history** |**Document ID**|**Release date**<br>**Data sheet status**<br>**Change notice**|**Release date**<br>**Data sheet status**<br>**Change notice**|**Supersedes**| |---|---|---|---| |PCA9539A v.2|20130812<br>Product data|sheet<br>-|PCA9539A v.1| |Modifications:|**•** Table 1“<br>Ordering information<br>”<br>:added column “Topside marking” (moved fromTable 2<br>)||| ||**•** Table 2“<br>Ordering options<br>”<br>:||| ||**–**<br>removed column “Topside|mark” (moved toTable 1<br>)|| ||**–**<br>added columns “Orderable part number”, “Package”, “Packing method”, and “Minimum order||| ||quantity”||| ||**•** Table 17“<br>Static characteristics<br>”<br>:removed “Rpu(int), internal pull-up||resistance” characteristic. This is| ||a correction to documentation only, no change to device function||(internal pull-up resistors are not| ||implemented in this device).||| |PCA9539A v.1|20120926<br>Product data|sheet<br>-|-| © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Rev. 2 — 12 August 2013** **Product data sheet** **36 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** ## **21. Legal information** ## **21.1 Data sheet status** |**Document status[1]**<br>**[2]**|**Product statu**~~**s**~~**[3]**|**Definition**| |---|---|---| |Objective [short] data sheet|Development|This document contains data from the objective specification for product development.| |Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.| |Product [short] data sheet|Production|This document contains the product specification.| [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. ## **21.2 Definitions** **Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. **Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. **Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. **Product specification —** The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. ## **21.3 Disclaimers** **Limited warranty and liability —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. **Limiting values —** Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. **Terms and conditions of commercial sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors. **Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. © NXP B.V. 2013. All rights reserved. All information provided in this document is subject to legal disclaimers. PCA9539A **Product data sheet** **Rev. 2 — 12 August 2013** **37 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** **Export control —** This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. **Non-automotive qualified products —** Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. **Translations —** A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. ## **21.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. **I[2] C-bus —** logo is a trademark of NXP B.V. ## **22. Contact information** For more information, please visit: **http://www.nxp.com** For sales office addresses, please send an email to: **salesaddresses@nxp.com** © NXP B.V. 2013. All rights reserved. PCA9539A All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 2 — 12 August 2013** **38 of 39** **PCA9539A** **NXP Semiconductors** **Low voltage 16-bit I[2] C-bus I/O port with interrupt and reset** ## **23. Contents** |**1**|**General description . . . . . . . . . . . . . . . . . . . . . . 1**|**21**|**Legal information . . . . . . . . . . . . . . . . . . . . . . 37**| |---|---|---|---| |**2**|**Features and benefits . . . . . . . . . . . . . . . . . . . . 2**|21.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . 37| |**3**<br>3.1<br>**4**<br>**5**<br>5.1|**Ordering information. . . . . . . . . . . . . . . . . . . . . 2**<br>Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2<br>**Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3**<br>**Pinning information. . . . . . . . . . . . . . . . . . . . . . 4**<br>Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4|21.2<br>21.3<br>21.4<br>**22**<br>**23**|Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 37<br>Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 37<br>Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 38<br>**Contact information . . . . . . . . . . . . . . . . . . . . 38**<br>**Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39**| |5.2|Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4||| |**6**|**Functional description . . . . . . . . . . . . . . . . . . . 5**||| |6.1|Device address. . . . . . . . . . . . . . . . . . . . . . . . . 5||| |6.2|Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6||| |6.2.1|Pointer register and command byte . . . . . . . . . 6||| |6.2.2|Input port register pair (00h, 01h) . . . . . . . . . . . 6||| |6.2.3|Output port register pair (02h, 03h) . . . . . . . . . 7||| |6.2.4|Polarity inversion register pair (04h, 05h). . . . . 7||| |6.2.5|Configuration register pair (06h, 07h). . . . . . . . 7||| |6.3|I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8||| |6.4|Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8||| |6.5|RESET<br>input. . . . . . . . . . . . . . . . . . . . . . . . . . . 9||| |6.6|Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 9||| |**7**|**Bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 9**||| |7.1|Writing to the port registers. . . . . . . . . . . . . . . . 9||| |7.2|Reading the port registers . . . . . . . . . . . . . . . 11||| |**8**|**Application design-in information . . . . . . . . . 14**||| |8.1|Minimizing IDDwhen the I/Os are used to||| ||control LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . 14||| |8.2|Power-on reset requirements . . . . . . . . . . . . . 15||| |**9**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17**||| |**10**|**Recommended operating conditions. . . . . . . 17**||| |**11**|**Thermal characteristics . . . . . . . . . . . . . . . . . 17**||| |**12**|**Static characteristics. . . . . . . . . . . . . . . . . . . . 18**||| |12.1|Typical characteristics . . . . . . . . . . . . . . . . . . 20||| |**13**|**Dynamic characteristics . . . . . . . . . . . . . . . . . 24**||| |**14**|**Parameter measurement information . . . . . . 25**||| |**15**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . 29**||| |**16**|**Handling information. . . . . . . . . . . . . . . . . . . . 31**||| |**17**|**Soldering of SMD packages . . . . . . . . . . . . . . 31**||| |17.1|Introduction to soldering . . . . . . . . . . . . . . . . . 31||| |17.2|Wave and reflow soldering . . . . . . . . . . . . . . . 31||| |17.3|Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 31||| |17.4|Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 32||| |**18**|**Soldering: PCB footprints. . . . . . . . . . . . . . . . 34**||| |**19**|**Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 36**||| |**20**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . . 36**||| Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. **© NXP B.V. 2013.** **All rights reserved.** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 12 August 2013 Document identifier: PCA9539A**
Updated at February 9, 2023
NXP Semiconductors is a global leader in secure connectivity solutions, driving innovation across the automotive, industrial, IoT, mobile, and communications infrastructure markets. By developing advanced, purpose-built technologies, NXP enables devices to sense, think, connect, and act intelligently, delivering rigorously tested components that make the connected world safer and more efficient. Within the semiconductor space, NXP is highly regarded for its extensive range of high-performance integrated circuits and discrete devices. The brand's portfolio excels in drivers and interfaces, featuring a comprehensive selection of I/O expanders designed to streamline complex system architectures. For demanding high-frequency and wireless applications, NXP provides industry-leading RF FETs and RF/PIN diodes engineered to deliver exceptional signal integrity, efficiency, and reliability. The NXP product lineup further extends to essential discrete components, including versatile bipolar transistors, JFETs, and small signal diodes optimized for precision switching and amplification. Additionally, the portfolio supports advanced automation and smart applications with precision IC sensors, such as MEMS accelerometers, alongside specialized power management solutions like AC/DC LED driver ICs and single MOSFETs for cutting-edge electronics design.
About Novapart
Novapart is a B2B electronic component broker specialising in stock shortages and cost reduction. We source hard-to-find parts and identify compliant alternatives across a catalogue of 410,000+ components from 500+ manufacturers.
Learn more →Stock Shortage Specialist
When a component is unavailable, discontinued or has an unacceptable lead time, we tap into our network of vetted European and Asian distributors to source what you need — without compromising on quality or traceability.
Request a quote →Compliant Alternatives
We identify pin-to-pin, electrically equivalent substitutes that meet the same certifications (RoHS, AEC-Q100, REACH) as your original specification — validated against datasheets, not just part numbers. Often at a lower cost.
BOM Analysis service →