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PCA9538PW/Q900,118
I/O Expander, 8bit, 400 kHz, I2C, SMBus, 3 V, 5.5 V, TSSOP
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- Manufacturer: NXP
- Product type: I/O Expanders
- No. of Pins: 16Pins
- No. of I/O's: 8I/O's
- Bus Frequency: 400kHz
- IC Interface Type: I2C, SMBus
- Chip Configuration: 8bit
- Supply Voltage Max: 5.5V
- Supply Voltage Min: 3V
- Interface Case Style: TSSOP
| Delivery and price | |
|---|---|
| Units per pack | 2500 |
| Price | 0.983 € |
| Current stock | 500+ |
| Lead time | 7 days |
Datasheet
## **PCA9538** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **Rev. 8 — 8 November 2017 Product data sheet** ## **1. General description** The PCA9538 is a 16-pin CMOS device that provides 8 bits of General Purpose parallel Input/Output (GPIO) expansion with interrupt and reset for I[2] C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I[2] C-bus I/O expanders. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push-buttons, LEDs, fans, etc. The PCA9538 consists of an 8-bit Configuration register (input or output selection), 8-bit Input Port register, 8-bit Output Port register and an 8-bit Polarity Inversion register (active HIGH or active LOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. The PCA9538 is identical to the PCA9554 except for the removal of the internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are held LOW, replacement of A2 with RESET and different address range. The PCA9538 open-drain interrupt output (INT) is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. The RESET pin causes the same reset/initialization to occur without de-powering the device. Two hardware pins (A0 and A1) vary the fixed I[2] C-bus address and allow up to four devices to share the same I[2] C-bus/SMBus. ## **2. Features and benefits** - 8-bit I[2] C-bus GPIO with interrupt and reset - Operating power supply voltage range of 2.3 V to 5.5 V (3.0 V to 5.5 V for PCA9538PW/Q900) - 5 V tolerant I/Os - Polarity Inversion register - Active LOW interrupt output - Active LOW reset input - Low standby current - Noise filter on SCL/SDA inputs - No glitch on power-up **==> picture [173 x 100] intentionally omitted <==** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** - Internal power-on reset - 8 I/O pins which default to 8 inputs - 0 Hz to 400 kHz clock frequency - ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101 - Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA - Offered in three different packages: SO16, TSSOP16 and HVQFN16 ## **3. Ordering information** **Table 1. Ordering information** |**Type number**|**Topside**<br>**marking**|**Package**|**Package**|**Package**| |---|---|---|---|---| |||**Name**|**Description**|**Version**| |PCA9538BS|9538|HVQFN16|plastic thermal enhanced very thin quad flat package;<br>no leads; 16 terminals; body 440.85 mm|SOT629-1| |PCA9538D|PCA9538D|SO16|plastic small outline package; 16 leads;<br>body width 7.5 mm|SOT162-1| |PCA9538PW|PCA9538|TSSOP16|plastic thin shrink small outline package; 16 leads;<br>body width 4.4 mm|SOT403-1| |PCA9538PW/Q900[1]|PCA9538|TSSOP16|plastic thin shrink small outline package; 16 leads;<br>body width 4.4 mm|SOT403-1| - [1] PCA9538PW/Q900 is AEC-Q100 compliant. Contact **i2c.support@nxp.com** for PPAP. ## **3.1 Ordering options** ## **Table 2. Ordering options** |**Type number**|**Orderable part number**|**Package**|**Packing method**|**Minimum**<br>**order**<br>**quantity**|**Temperature**| |---|---|---|---|---|---| |PCA9538BS|PCA9538BS,118|HVQFN16|Reel pack, SMD,<br>13-inch|6000|Tamb=40C to +85C| |PCA9538D|PCA9538D,112|SO16|Tube, bulk pack|1920|Tamb=40C to +85C| ||PCA9538D,118|SO16|Reel pack, SMD,<br>13-inch|1000|Tamb=40C to +85C| |PCA9538PW|PCA9538PW,112|TSSOP16|Tube, bulk pack|2400|Tamb=40C to +85C| ||PCA9538PW,118|TSSOP16|Reel pack, SMD,<br>13-inch|2500|Tamb=40C to +85C| |PCA9538PW/Q900|PCA9538PW/Q900,118|TSSOP16|Reel pack, SMD,<br>13-inch|2500|Tamb=40C to +125C| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **2 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **4. Block diagram** **==> picture [364 x 154] intentionally omitted <==** **----- Start of picture text -----**<br> A0 IO0<br>A1 8-bit IO1<br>IO2<br>SCL INPUT I [2] C-BUS/SMBus INPUT/ IO3<br>SDA FILTER CONTROL write pulse OUTPUTPORTS IO4<br>IO5<br>IO6<br>read pulse<br>IO7<br>VDD<br>POWER-ON VDD<br>RESET RESET<br>VSS PCA9538 LP INT<br>FILTER<br>002aae667<br>**----- End of picture text -----**<br> **==> picture [151 x 9] intentionally omitted <==** **----- Start of picture text -----**<br> Remark: All I/Os are set to inputs at reset.<br>**----- End of picture text -----**<br> **Fig 1. Block diagram of PCA9538** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **3 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **5. Pinning information** ## **5.1 Pinning** **==> picture [396 x 334] intentionally omitted <==** **----- Start of picture text -----**<br> A0 1 16 VDD A0 1 16 VDD<br>A1 2 15 SDA A1 2 15 SDA<br>RESET 3 14 SCL RESET 3 14 SCL<br>IO0 4 13 INT IO0 4 PCA9538PW 13 INT<br>PCA9538D<br>IO1 5 12 IO7 IO1 5 PCA9538PW/Q900 12 IO7<br>IO2 6 11 IO6 IO2 6 11 IO6<br>IO3 7 10 IO5 IO3 7 10 IO5<br>VSS 8 9 IO4 VSS 8 9 IO4<br>002aae668 002aae669<br>Fig 2. Pin configuration for SO16 Fig 3. Pin configuration for TSSOP16<br>terminal 1<br>index area<br>RESET 1 12 SCL<br>IO0 2 11 INT<br>PCA9538BS<br>IO1 3 10 IO7<br>IO2 4 9 IO6<br>002aae670<br>Transparent top view<br>Fig 4. Pin configuration for HVQFN16<br>A1 A0 VDD SDA<br>16 15 14 13<br>5 6 7 8<br>IO3 VSS IO4 IO5<br>**----- End of picture text -----**<br> © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **4 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **5.2 Pin description** |**Pin description**|**Pin description**|**Pin description**|**Pin description**| |---|---|---|---| |**Table 3.**<br>**Pin description**|||| |**Symbol**|**Pin**||**Description**| ||**SO16, TSSOP16**|**HVQFN16**|| |A0|1|15|address input 0| |A1|2|16|address input 1| |RESET|3|1|active LOW reset input| |IO0|4|2|input/output 0| |IO1|5|3|input/output 1| |IO2|6|4|input/output 2| |IO3|7|5|input/output 3| |VSS|8|~~6~~[1]|supply ground| |IO4|9|7|input/output 4| |IO5|10|8|input/output 5| |IO6|11|9|input/output 6| |IO7|12|10|input/output 7| |INT|13|11|interrupt output (open-drain)| |SCL|14|12|serial clock line| |SDA|15|13|serial data line| |VDD|16|14|supply voltage| - [1] HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **5 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **6. Functional description** “ ” Refer to Figure 1 Block diagram of PCA9538 . ## **6.1 Device address** **==> picture [138 x 64] intentionally omitted <==** **----- Start of picture text -----**<br> slave address<br>1 1 1 0 0 A1 A0 R/W<br>fixed hardware<br>selectable<br>002aae707<br>**----- End of picture text -----**<br> **==> picture [113 x 9] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 5. PCA9538 address<br>**----- End of picture text -----**<br> ## **6.2 Registers** ## **6.2.1 Command byte** The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the registers will be written or read. ## **Table 4. Command byte** |**Command**|**Protocol**|**Function**| |---|---|---| |0|read byte|Input Port register| |1|read/write byte|Output Port register| |2|read/write byte|Polarity Inversion register| |3|read/write byte|Configuration register| ## **6.2.2 Register 0 - Input Port register** This register is a read-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default value ‘X’ is determined by the externally applied logic level. **Table 5. Register 0 - Input Port register bit description** _Legend: * default value._ |**Bit**|**Symbol**|**Access**|**Value**|**Description**| |---|---|---|---|---| |7|I7|read only|X*|value ‘X’ is determined by externally applied<br>logic level| |6|I6|read only|X*|| |5|I5|read only|X*|| |4|I4|read only|X*|| |3|I3|read only|X*|| |2|I2|read only|X*|| |1|I1|read only|X*|| |0|I0|read only|X*|| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **6 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **6.2.3 Register 1 - Output Port register** This register reflects the outgoing logic levels of the pins defined as outputs by Register 3. Bit values in this register have no effect on pins defined as inputs. Reads from this register return the value that is in the flip-flop controlling the output selection, **not** the actual pin value. **Table 6. Register 1 - Output Port register bit description** _Legend: * default value._ |**Bit**|**Symbol**|**Access**|**Value**|**Description**| |---|---|---|---|---| |7|O7|R|1*|reflects outgoing logic levels of pins defined as outputs<br>by Register 3| |6|O6|R|1*|| |5|O5|R|1*|| |4|O4|R|1*|| |3|O3|R|1*|| |2|O2|R|1*|| |1|O1|R|1*|| |0|O0|R|1*|| ## **6.2.4 Register 2 - Polarity Inversion register** This register allows the user to invert the polarity of the Input Port register data. If a bit in this register is set (written with 1), the corresponding Input Port data is inverted. If a bit in this register is cleared (written with a 0), the Input Port data polarity is retained. **Table 7. Register 2 - Polarity Inversion register bit description** _Legend: * default value._ |**Bit**|**Symbol**|**Access**|**Value**|**Description**| |---|---|---|---|---| |7|N7|R/W|0*|inverts polarity of Input Port register data<br>0 = Input Port register data retained (default value)<br>1 = Input Port register data inverted| |6|N6|R/W|0*|| |5|N5|R/W|0*|| |4|N4|R/W|0*|| |3|N3|R/W|0*|| |2|N2|R/W|0*|| |1|N1|R/W|0*|| |0|N0|R/W|0*|| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **7 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **6.2.5 Register 3 - Configuration register** This register configures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are configured as inputs. **Table 8. Register 3 - Configuration register bit description** _Legend: * default value._ |**Bit**|**Symbol**|**Access**|**Value**|**Description**| |---|---|---|---|---| |7|C7|R/W|1*|configures the directions of the I/O pins<br>0 = corresponding port pin enabled as an output<br>1 = corresponding port pin configured as an input<br>(default value)| |6|C6|R/W|1*|| |5|C5|R/W|1*|| |4|C4|R/W|1*|| |3|C3|R/W|1*|| |2|C2|R/W|1*|| |1|C1|R/W|1*|| |0|C0|R/W|1*|| ## **6.3 Power-on reset** When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9538 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9538 registers and state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the operating voltage. ## **6.4 RESET input** A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The PCA9538 registers and SMBus/I[2] C-bus state machine will be held in their default state until the RESET input is once again HIGH. This input requires a pull-up resistor to VDD if no active connection is used. ## **6.5 Interrupt output** The open-drain interrupt output (INT) is activated when one of the port pins changes state and the pin is configured as an input. The interrupt is de-activated when the input returns to its previous state or the Input Port register is read. Note that changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **8 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **6.6 I/O port** When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the state of the Output Port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance paths that exist between the pin and either VDD or VSS. **==> picture [370 x 290] intentionally omitted <==** **----- Start of picture text -----**<br> data from output port<br>shift register register data<br>configuration<br>register VDD<br>data from D Q Q1<br>shift register<br>FF<br>write<br>D Q<br>configuration CK Q<br>pulse FF<br>I/O pin<br>write pulse CK Q2<br>output port input port VSS<br>register register<br>D Q<br>input port<br>FF register data<br>read pulse CK<br>to INT<br>polarity inversion<br>register<br>data from<br>D Q polarity<br>shift register inversion<br>FF register data<br>write polarity<br>CK<br>pulse<br>002aad723<br>Remark: At power-on reset, all registers return to default values.<br>**----- End of picture text -----**<br> **Fig 6. Simplified schematic of IO0 to IO7** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **9 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **6.7 Bus transactions** Data is transmitted to the PCA9538 registers using the write mode as shown in Figure 7 and Figure 8. Data is read from the PCA9538 registers using the read mode as shown in Figure 9 and Figure 10. These devices do not implement an auto-increment function so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent. **==> picture [496 x 349] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>STOP<br>condition<br>slave address command byte data to port<br>SDA S 1 1 1 0 0 A1 A0 0 A 0 0 0 0 0 0 0 1 A DATA 1 A P<br>START condition R/W acknowledge acknowledge acknowledge<br>from slave from slave from slave<br>write to port<br>tv(Q)<br>data out from port DATA 1 VALID<br>002aae708<br>Expanded diagram is shown in Figure 18.<br>Fig 7. Write to output port register<br>SCL 1 2 3 4 5 6 7 8 9<br>STOP<br>condition<br>slave address command byte data to register<br>SDA S 1 1 1 0 0 A1 A0 0 A 0 0 0 0 0 0 1 1/0 A DATA 1 A P<br>START condition R/W acknowledge acknowledge acknowledge<br>from slave from slave from slave<br>data to register<br>002aae709<br>Fig 8. Write to configuration or polarity inversion registers<br>**----- End of picture text -----**<br> © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **10 of 34** **PCA9538** **NXP Semiconductors** ## **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **==> picture [496 x 460] intentionally omitted <==** **----- Start of picture text -----**<br> slave address<br>SDA S 1 1 1 0 0 A1 A0 0 A COMMAND BYTE A (cont.)<br>START condition R/W acknowledge<br>acknowledge from slave<br>from slave<br>slave address data from register data from register<br>(cont.) S 1 1 1 0 0 A1 A0 1 A DATA (first byte) A DATA (last byte) NA P<br>(repeated) R/W acknowledge no acknowledge STOP<br>START condition acknowledge from master from master condition<br>from slave<br>at this moment master-transmitter becomes master-receiver<br>and slave-receiver becomes slave-transmitter<br>002aae710<br>Fig 9. Read from register<br>SCL 1 2 3 4 5 6 7 8 9<br>no acknowledge<br>from master<br>slave address data from port data from port<br>SDA S 1 1 1 0 0 A1 A0 1 A DATA 1 A DATA 4 NA P<br>START condition R/W acknowledge acknowledge STOP<br>from slave from master condition<br>read from<br>port<br>data into<br>DATA 1 DATA 2 DATA 3 DATA 4<br>port<br>th(D) tsu(D)<br>INT<br>tv(INT) trst(INT)<br>002aae711<br>This figure assumes the command byte has previously been programmed with 00h.<br>Transfer of data can be stopped at any moment by a STOP condition.<br>Expanded diagram is shown in Figure 17.<br>Fig 10. Read input port register<br>**----- End of picture text -----**<br> © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **11 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **7. Application design-in information** **==> picture [440 x 236] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>(5 V) 100 k Ω SUB-SYSTEM 1<br>10 k Ω 10 k Ω 10 k Ω 10 k Ω 2 k Ω ( × 3) (e.g., temp sensor)<br>VDD VDD<br>MASTER INT<br>PCA9538<br>CONTROLLER<br>SCL SCL IO0<br>SUB-SYSTEM 2<br>SDA SDA IO1 (e.g., counter)<br>INT INT<br>IO2 RESET<br>RESET RESET<br>IO3<br>A<br>VSS IO4 controlled<br>enable<br>switch<br>IO5 (e.g., CBT device)<br>A1 IO6 B<br>A0 IO7<br>SUB-SYSTEM 3<br>VSS (e.g., alarm system)<br>ALARM<br>VDD<br>002aae712<br>**----- End of picture text -----**<br> Device address is 1110 000x for this example. IO0, IO2, IO3 configured as outputs. IO1, IO4, IO5 configured as inputs. IO6, IO7 are not used and need 100 k pull-up resistors to protect them from floating. **Fig 11. Typical application** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **12 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **7.1 Minimizing IDD when the I/Os are used to control LEDs** When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 11. Since the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower than VDD. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 12 shows a high value resistor in parallel with the LED. Figure 13 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VDD and prevents additional supply current consumption when the LED is off. **==> picture [396 x 169] intentionally omitted <==** **----- Start of picture text -----**<br> 3.3 V 5 V<br>VDD<br>VDD LED 100 k Ω VDD LED<br>IOn IOn<br>002aac660 002aac661<br>Fig 12. High value resistor in parallel with Fig 13. Device supplied by a lower voltage<br>the LED<br>**----- End of picture text -----**<br> ## **8. Limiting values** **Table 9. Limiting values** _In accordance with the Absolute Maximum Rating System (IEC 60134)._ |**Symbol**|**Parameter**|**Conditions**|**Min**|**Max**|**Unit**| |---|---|---|---|---|---| |VDD|supply voltage||0.5|+6.0|V| |II|input current||-|20|mA| |VI/O|voltage on an input/output pin||VSS0.5|5.5|V| |IO(IOn)|output current on pin IOn||-|50|mA| |IDD|supply current||-|85|mA| |ISS|ground supply current||-|100|mA| |Ptot|total power dissipation||-|200|mW| |Tstg|storage temperature||65|+150|C| |Tamb|ambient temperature|operating|||| |||all devices except PCA9538PW/Q900|40|+85|C| |||PCA9538PW/Q900|40|+125|C| |Tj(max)|maximum junction temperature||-|+125|C| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **13 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **9. Static characteristics** **Table 10. Static characteristics for all devices except PCA9538PW/Q900** _VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb =_ _40_ _C to +85_ _C; unless otherwise specified._ |**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---| |**Supplies**||||||| |VDD|supply voltage||2.3|-|5.5|V| |IDD|supply current|operating mode; VDD= 5.5 V;<br>no load; fSCL= 100 kHz|-|104|175|A| |IstbL|LOW-level standby current|Standby mode; VDD= 5.5 V;<br>no load; VI= VSS;<br>fSCL= 0 kHz; I/O = inputs|-|0.25|1|A| |IstbH|HIGH-level standby current|Standby mode; VDD= 5.5 V;<br>no load; VI= VDD;<br>fSCL= 0 kHz; I/O = inputs|-|0.25|1|A| |VPOR|power-on reset voltage|no load; VI= VDDor VSS<br>[1]|-|1.7|2.2|V| |**Input SCL; input/output SDA**||||||| |VIL|LOW-level input voltage||0.5|-|+0.3VDD|V| |VIH|HIGH-level input voltage||0.7VDD|-|5.5|V| |IOL|LOW-level output current|VOL= 0.4 V|3|7|-|mA| |IL|leakage current|VI= VDD= VSS|1|-|+1|A| |Ci|input capacitance|VI= VSS|-|5|10|pF| |**I/Os**||||||| |VIL|LOW-level input voltage||0.5|-|+0.8|V| |VIH|HIGH-level input voltage||2.0|-|5.5|V| |IOL|LOW-level output current|VOL= 0.5 V||||| |||VDD= 2.3 V<br>[2]|8|10|-|mA| |||VDD= 3.0 V<br>[2]|8|14|-|mA| |||VDD= 4.5 V<br>[2]|8|17|-|mA| |||VOL= 0.7 V||||| |||VDD= 2.3 V<br>[2]|10|13|-|mA| |||VDD= 3.0 V<br>[2]|10|19|-|mA| |||VDD= 4.5 V<br>[2]|10|24|-|mA| |VOH|HIGH-level output voltage|IOH=8 mA||||| |||VDD= 2.3 V<br>[3]|1.8|-|-|V| |||VDD= 3.0 V<br>[3]|2.6|-|-|V| |||VDD= 4.5 V<br>[3]|4.1|-|-|V| |||IOH=10 mA||||| |||VDD= 2.3 V<br>[3]|1.7|-|-|V| |||VDD= 3.0 V<br>[3]|2.5|-|-|V| |||VDD= 4.5 V<br>[3]|4.0|-|-|V| |ILI|input leakage current|VI= VDD= VSS|1|-|+1|A| |Ci|input capacitance||-|5|10|pF| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **14 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **Table 10. Static characteristics for all devices except PCA9538PW/Q900** _…continued VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb =_ _40_ _C to +85_ _C; unless otherwise specified._ |**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---| |**Interrupt INT**||||||| |IOL|LOW-level output current|VOL= 0.4 V|3|13|-|mA| |**Select inputs A0, A1, RESET**||||||| |VIL|LOW-level input voltage||0.5|-|+0.8|V| |VIH|HIGH-level input voltage||2.0|-|5.5|V| |ILI|input leakage current||1|-|+1|A| [1] VDD must be lowered to 0.2 V in order to reset part. [2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA. [3] The total current sourced by all I/Os must be limited to 85 mA. **Table 11. Static characteristics for PCA9538PW/Q900 AEC-Q100 compliant device** _VDD = 3.0 V to 5.5 V; VSS = 0 V; Tamb =_ _40_ _C to +125_ _C; unless otherwise specified._ |**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---| |**Supplies**||||||| |VDD|supply voltage||3.0|-|5.5|V| |IDD|supply current|operating mode; VDD= 5.5 V;<br>no load; fSCL= 100 kHz|-|104|175|A| |IstbL|LOW-level standby current|Standby mode; VDD= 5.5 V;<br>no load; VI= VSS;<br>fSCL= 0 kHz; I/O = inputs|-|0.25|1|A| |IstbH|HIGH-level standby current|Standby mode; VDD= 5.5 V;<br>no load; VI= VDD;<br>fSCL= 0 kHz; I/O = inputs|-|0.25|1|A| |VPOR|power-on reset voltage|no load; VI= VDDor VSS<br>[1]|-|1.7|2.2|V| |**Input SCL; input/output SDA**||||||| |VIL|LOW-level input voltage||0.5|-|+0.3VDD|V| |VIH|HIGH-level input voltage||0.7VDD|-|5.5|V| |IOL|LOW-level output current, SDA|VOL= 0.4 V||||| |||VDD= 5.5 V|3|7|-|mA| |||VDD= 3.0 V|2.5|-|-|mA| |IL|leakage current|VI= VDD= VSS|1|-|+1|A| |Ci|input capacitance|VI= VSS|-|5|10|pF| |**I/Os**||||||| |VIL|LOW-level input voltage||0.5|-|+0.8|V| |VIH|HIGH-level input voltage||2.0|-|5.5|V| |IOL|LOW-level output current|VOL= 0.5 V||||| |||VDD= 4.5 V<br>[2]|8|17|-|mA| |||VDD= 3.0 V<br>[2]|7.5|-|-|mA| |||VOL= 0.7 V||||| |||VDD= 4.5 V<br>[2]|10|24|-|mA| |||VDD= 3.0 V<br>[2]|9.5|-|-|mA| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **15 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **Table 11. Static characteristics for PCA9538PW/Q900 AEC-Q100 compliant device** _…continued VDD = 3.0 V to 5.5 V; VSS = 0 V; Tamb =_ _40_ _C to +125_ _C; unless otherwise specified._ |**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---| |VOH|HIGH-level output voltage|IOH=8 mA||||| |||VDD= 4.5 V<br>[3]|4.1|-|-|V| |||VDD= 3.0 V<br>[3]|2.5|-|-|V| |||IOH=10 mA||||| |||VDD= 4.5 V<br>[3]|4.0|-|-|V| |||VDD= 3.0 V<br>[3]|2.4|-|-|V| |ILI|input leakage current|VI= VDD= VSS|1|-|+1|A| |Ci|input capacitance||-|5|10|pF| |**Interrupt INT**||||||| |IOL|LOW-level output current|VOL= 0.4 V|3|13|-|mA| |**Select inputs A0, A1, RESET**||||||| |VIL|LOW-level input voltage||0.5|-|+0.8|V| |VIH|HIGH-level input voltage||2.0|-|5.5|V| |ILI|input leakage current||1|-|+1|A| [1] VDD must be lowered to 0.2 V in order to reset part. [2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA. [3] The total current sourced by all I/Os must be limited to 85 mA. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **16 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **10. Dynamic characteristics** ## **Table 12. Dynamic characteristics** |**Symbol**|**Parameter**|**Conditions**|**Standard-mode**<br>**I2C-bus**|**Standard-mode**<br>**I2C-bus**|**Fast-mode I2C-bus**|**Fast-mode I2C-bus**|**Unit**| |---|---|---|---|---|---|---|---| ||||**Min**|**Max**|**Min**|**Max**|| |fSCL|SCL clock frequency||0|100|0|400|kHz| |tBUF|bus free time between a STOP and<br>START condition||4.7|-|1.3|-|s| |tHD;STA|hold time (repeated) START condition||4.0|-|0.6|-|s| |tSU;STA|set-up time for a repeated START<br>condition||4.7|-|0.6|-|s| |tSU;STO|set-up time for STOP condition||4.0|-|0.6|-|s| |tHD;DAT|data hold time||0|-|0|-|ns| |tVD;ACK|data valid acknowledge time|[1]|0.3|3.45|0.1|0.9|s| |tVD;DAT|data valid time|[2]|300|-|50|-|ns| |tSU;DAT|data set-up time||250|-|100|-|ns| |tLOW|LOW period of the SCL clock||4.7|-|1.3|-|s| |tHIGH|HIGH period of the SCL clock||4.0|-|0.6|-|s| |tr|rise time of both SDA and SCL signals||-|1000|20 + 0.1Cb[3]|300|ns| |tf|fall time of both SDA and SCL signals||-|300|20 + 0.1Cb[3]|300|ns| |tSP|pulse width of spikes that must be<br>suppressed by the input filter||-|50|-|50|ns| |**Port timing**|||||||| |tv(Q)|data output valid time||-|200|-|200|ns| |tsu(D)|data input set-up time||100|-|100|-|ns| |th(D)|data input hold time||1|-|1|-|s| |**Interrupt timing**|||||||| |tv(INT)|valid time on pin INT||-|4|-|4|s| |trst(INT)|reset time on pin INT||-|4|-|4|s| |**RESET**|||||||| |tw(rst)|reset pulse width||4|-|4|-|ns| |trec(rst)|reset recovery time||0|-|0|-|ns| |trst|reset time||400|-|400|-|ns| [1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. [2] tVD;DAT = minimum time for the SDA data out to be valid following SCL LOW. - [3] Cb = total capacitance of one bus line in pF. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **17 of 34** **PCA9538** **NXP Semiconductors** ## **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **==> picture [480 x 133] intentionally omitted <==** **----- Start of picture text -----**<br> 0.7 × VDD<br>SDA<br>0.3 × VDD<br>tBUF tr tf tHD;STA tSP<br>tLOW<br>0.7 × VDD<br>SCL<br>0.3 × VDD<br>tHD;STA tSU;STA tSU;STO<br>P S tHD;DAT tHIGH tSU;DAT Sr P<br>002aaa986<br>**----- End of picture text -----**<br> **Fig 14. Definition of timing** **==> picture [496 x 427] intentionally omitted <==** **----- Start of picture text -----**<br> START bit 7 STOP<br>protocol condition MSB bit 6 bit 1 bit 0 acknowledge condition<br>(A6) (D1) (D0) (A)<br>(S) (A7) (P)<br>tSU;STA tLOW tHIGH<br>1 / fSCL<br>SCL 0.7 × VDD<br>0.3 × VDD<br>tBUF tf<br>tr<br>SDA 0.7 × VDD<br>0.3 × VDD<br>tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO<br>002aab285<br>Rise and fall times refer to VIL and VIH.<br>Fig 15. I [2] C-bus timing diagram<br>START ACK or read cycle<br>SCL<br>SDA<br>30 %<br>trst<br>RESET 50 % 50 % 50 %<br>trec(rst) tw(rst)<br>trst<br>after reset,<br>IOn 50 %<br>I/Os reconfigured<br>as inputs<br>002aad732<br>Fig 16. Definition of RESET timing<br>**----- End of picture text -----**<br> © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **18 of 34** **PCA9538** **NXP Semiconductors** ## **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **==> picture [228 x 158] intentionally omitted <==** **----- Start of picture text -----**<br> 70 %<br>SCL 2 1 0 A P<br>30 %<br>SDA<br>tsu(D) th(D)<br>input 50 %<br>tv(INT) trst(INT)<br>INT<br>002aae641<br>**----- End of picture text -----**<br> **Fig 17. Expanded view of read input port register** **==> picture [232 x 118] intentionally omitted <==** **----- Start of picture text -----**<br> 70 %<br>SCL 2 1 0 A P<br>SDA<br>tv(Q)<br>output 50 %<br>002aad735<br>**----- End of picture text -----**<br> **Fig 18. Expanded view of write to output port register** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **19 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **11. Test information** **==> picture [263 x 124] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>open<br>VDD RL VSS<br>500 Ω<br>VI VO<br>PULSE<br>DUT<br>GENERATOR<br>RT CL<br>50 pF<br>002aab880<br>RL = load resistor.<br>CL = load capacitance includes jig and probe capacitance.<br>**----- End of picture text -----**<br> RT = termination resistance should be equal to the output impedance Zo of the pulse generators. **Fig 19. Test circuitry for switching times** **==> picture [298 x 84] intentionally omitted <==** **----- Start of picture text -----**<br> RL S1 2VDD<br>from output under test open<br>500 Ω GND<br>CL RL<br>50 pF 500 Ω<br>002aac226<br>Fig 20. Test circuit<br>**----- End of picture text -----**<br> ## **Table 13. Test data** |**Test**|**Load**|**Load**|**Switch**| |---|---|---|---| ||**RL**|**CL**|| |tv(Q)|500|50 pF|2VDD| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **20 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **12. Package outline** ## **SO16: plastic small outline package; 16 leads; body width 7.5 mm** **==> picture [43 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> SOT162-1<br>**----- End of picture text -----**<br> **==> picture [478 x 570] intentionally omitted <==** **----- Start of picture text -----**<br> D E A<br>X<br>c<br>y HE v M A<br>Z<br>16 9<br>Q<br>A2 A<br>A1 (A )3<br>pin 1 index<br>θ<br>L p<br>L<br>1 8 detail X<br>e w M<br>b p<br>0 5 10 mm<br>scale<br>DIMENSIONS (inch dimensions are derived from the original mm dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(1)] e HE L Lp Q v w y Z (1) θ<br>0.3 2.45 0.49 0.32 10.5 7.6 10.65 1.1 1.1 0.9<br>mm 2.65 0.1 2.25 0.25 0.36 0.23 10.1 7.4 1.27 10.00 1.4 0.4 1.0 0.25 0.25 0.1 0.4 8o<br>0.012 0.096 0.019 0.013 0.41 0.30 0.419 0.043 0.043 0.035 0o<br>inches 0.1 0.01 0.05 0.055 0.01 0.01 0.004<br>0.004 0.089 0.014 0.009 0.40 0.29 0.394 0.016 0.039 0.016<br>Note<br>1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>99-12-27<br> SOT162-1 075E03 MS-013<br>03-02-19<br>**----- End of picture text -----**<br> ## **Fig 21. Package outline SOT162-1 (SO16)** All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 **Product data sheet** **Rev. 8 — 8 November 2017** **21 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm** **==> picture [43 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> SOT403-1<br>**----- End of picture text -----**<br> **==> picture [478 x 570] intentionally omitted <==** **----- Start of picture text -----**<br> D E A<br>X<br>c<br>y HE v M A<br>Z<br>16 9<br>Q<br>A2 (A )3 A<br>pin 1 index A1<br>θ<br>L p<br>L<br>1 8<br>detail X<br>w M<br>e b p<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(2)] e HE L Lp Q v w y Z (1) θ<br>mm 1.1 0.150.05 0.950.80 0.25 0.300.19 0.20.1 5.14.9 4.54.3 0.65 6.66.2 1 0.750.50 0.40.3 0.2 0.13 0.1 0.400.06 80oo<br>Notes<br>1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.<br>2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>99-12-27<br> SOT403-1 MO-153<br>03-02-18<br>**----- End of picture text -----**<br> ## **Fig 22. Package outline SOT403-1 (TSSOP16)** All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 **Product data sheet** **Rev. 8 — 8 November 2017** **22 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm** **==> picture [43 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> SOT629-1<br>**----- End of picture text -----**<br> **==> picture [478 x 559] intentionally omitted <==** **----- Start of picture text -----**<br> D B A<br>terminal 1<br>index area A<br>A1<br>E c<br>detail X<br>e1<br>C<br>1/2 e<br>e b v M C A B y1 C y<br>5 8 w M C<br>L<br>9<br>4<br>e<br>Eh e2<br>1/2 e<br>1<br>12<br>terminal 1<br>index area 16 13<br>Dh X<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>A [(1)]<br>UNIT max. A1 b c D [(1)] Dh E [(1)] Eh e e1 e2 L v w y y1<br>0.05 0.38 4.1 2.25 4.1 2.25 0.75<br>mm 1 0.2 0.65 1.95 1.95 0.1 0.05 0.05 0.1<br>0.00 0.23 3.9 1.95 3.9 1.95 0.50<br>Note<br>1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>01-08-08<br> SOT629-1 - - - MO-220 - - -<br>02-10-22<br>**----- End of picture text -----**<br> **Fig 23. Package outline SOT629-1 (HVQFN16)** All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 **Product data sheet** **Rev. 8 — 8 November 2017** **23 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **13. Handling information** All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in _JESD625-A_ or equivalent standards. ## **14. Soldering of SMD packages** This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note _AN10365 “Surface mount reflow soldering description”_ . ## **14.1 Introduction to soldering** Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. ## **14.2 Wave and reflow soldering** Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: - Through-hole components - Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: - Board specifications, including the board finish, solder masks and vias - Package footprints, including solder thieves and orientation - The moisture sensitivity level of the packages - Package placement - Inspection and repair - Lead-free soldering versus SnPb soldering ## **14.3 Wave soldering** Key characteristics in wave soldering are: © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **24 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** - Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave - Solder bath specifications, including temperature and impurities ## **14.4 Reflow soldering** Key characteristics in reflow soldering are: - Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 24) than a SnPb process, thus reducing the process window - Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board - Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 14 and 15 **Table 14. SnPb eutectic process (from J-STD-020D)** |**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**| |---|---|---| ||**Volume (mm3)**|| ||**< 350**|**350**| |< 2.5|235|220| |2.5|220|220| ## **Table 15. Lead-free process (from J-STD-020D)** |**Package thickness (mm)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**|**Package reflow temperature (****C)**| |---|---|---|---| ||**Volume (mm3)**||| ||**< 350**|**350 to 2000**|**> 2000**| |< 1.6|260|260|260| |1.6 to 2.5|260|250|245| |> 2.5|250|245|245| Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 24. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **25 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **==> picture [320 x 207] intentionally omitted <==** **----- Start of picture text -----**<br> maximum peak temperature<br>= MSL limit, damage level<br>temperature<br>minimum peak temperature<br>= minimum soldering temperature<br>peak<br> temperature<br>time<br>001aac844<br>MSL: Moisture Sensitivity Level<br>**----- End of picture text -----**<br> **Fig 24. Temperature profiles for large and small components** For further information on temperature profiles, refer to Application Note _AN10365 “Surface mount reflow soldering description”_ . © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **26 of 34** **PCA9538** **NXP Semiconductors** ## **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **15. Soldering: PCB footprints** ## **Footprint information for reflow soldering of SO16 package** **==> picture [38 x 7] intentionally omitted <==** **----- Start of picture text -----**<br> SOT162-1<br>**----- End of picture text -----**<br> **==> picture [482 x 565] intentionally omitted <==** **----- Start of picture text -----**<br> Hx<br>Gx<br>P2<br>(0.125) (0.125)<br>Hy Gy By Ay<br>C<br>D2 (4x) P1 D1<br>Generic footprint pattern<br>Refer to the package outline drawing for actual layout<br>solder land<br>occupied area<br>DIMENSIONS in mm<br>P1 P2 Ay By C D1 D2 Gx Gy Hx Hy<br>1.270 1.320 11.200 6.400 2.400 0.700 0.800 10.040 8.600 11.900 11.450<br>sot162-1_fr<br>**----- End of picture text -----**<br> **Fig 25. PCB footprint for SOT162-1 (SO16); reflow soldering** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **27 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **==> picture [474 x 560] intentionally omitted <==** **----- Start of picture text -----**<br> Footprint information for reflow soldering of TSSOP16 package SOT403-1<br>Hx<br>Gx<br>P2<br>(0.125) (0.125)<br>Hy Gy By Ay<br>C<br>D2 (4x) P1 D1<br>Generic footprint pattern<br>Refer to the package outline drawing for actual layout<br>solder land<br>occupied area<br>DIMENSIONS in mm<br>P1 P2 Ay By C D1 D2 Gx Gy Hx Hy<br>0.650 0.750 7.200 4.500 1.350 0.400 0.600 5.600 5.300 5.800 7.450<br>**----- End of picture text -----**<br> ## **Footprint information for reflow soldering of TSSOP16 package** **==> picture [32 x 6] intentionally omitted <==** **----- Start of picture text -----**<br> sot403-1_fr<br>**----- End of picture text -----**<br> **Fig 26. PCB footprint for SOT403-1 (TSSOP16); reflow soldering** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **28 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **==> picture [482 x 574] intentionally omitted <==** **----- Start of picture text -----**<br> Footprint information for reflow soldering of HVQFN16 package SOT629-1<br>Hx<br>Gx<br>D P 0.025<br>0.025<br>C<br>(0.105)<br>SPx<br>nSPx<br>SPy<br>Hy Gy SLy By Ay<br>nSPy<br>SPx tot<br>SLx<br>Bx<br>Ax<br>Generic footprint pattern<br>Refer to the package outline drawing for actual layout<br>solder land<br>solder paste deposit<br>solder land plus solder paste<br>occupied area nSPx nSPy<br>2 2<br>Dimensions in mm<br>P Ax Ay Bx By C D SLx SLy SPx tot SPy tot SPx SPy Gx Gy Hx Hy<br>0.650 5.000 5.000 2.800 2.800 1.100 0.300 2.000 2.000 1.200 1.200 0.450 0.450 4.300 4.300 5.250 5.250<br>07-05-07<br>Issue date sot629-1_fr<br>09-06-15<br>SPy tot<br>**----- End of picture text -----**<br> **Fig 27. PCB footprint for SOT629-1 (HVQFN16); reflow soldering** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **29 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **16. Abbreviations** **Table 16. Abbreviations** |**Acronym**|**Description**| |---|---| |ACPI|Advanced Configuration and Power Interface| |CBT|Cross-Bar Technology| |CDM|Charged-Device Model| |CMOS|Complementary Metal-Oxide Semiconductor| |DUT|Device Under Test| |ESD|ElectroStatic Discharge| |FET|Field-Effect Transistor| |FF|Flip-Flop| |GPIO|General Purpose Input/Output| |HBM|Human Body Model| |I2C-bus|Inter-Integrated Circuit bus| |I/O|Input/Output| |LED|Light Emitting Diode| |LP|Low-Pass| |POR|Power-On Reset| |SMBus|System Management Bus| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **30 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **17. Revision history** **Table 17. Revision history** |**Document ID**|**Release date**|**Data sheet status**|**Change notice**|**Supersedes**| |---|---|---|---|---| |PCA9538 v.8|20171108|Product data sheet|201710002I|PCA9538 v.7| |Modifications:|**•** Table 10“<br>Static characteristics for all devices except PCA9538PW/Q900<br>”<br>,Table 11“<br>Static<br>characteristics for PCA9538PW/Q900 AEC-Q100 compliant device<br>”<br>:Corrected VPORtyp and max<br>limit|||| |PCA9538 v.7|20141126|Product data sheet||PCA9538 v.6| |Modifications:|**•** Table 11“<br>Static characteristics for PCA9538PW/Q900 AEC-Q100 compliant device<br>”<br>:updated IOL<br>and VOH; changed operating power supply voltage range from “5.0 V10 %” to “3.0 V to 5.5 V”<br>for PCA9538PW/Q900|||| |PCA9538 v.6|20130206|Product data sheet||PCA9538 v.5| |PCA9538 v.5|20090528|Product data sheet|-|PCA9538 v.4| |PCA9538 v.4|20060921|Product data sheet|-|PCA9538 v.3| |PCA9538 v.3<br>(9397 750 14176)|20041005|Product data sheet|-|PCA9538 v.2| |PCA9538 v.2<br>(9397 750 14049)|20040930|Objective data sheet|-|PCA9538 v.1| |PCA9538 v.1<br>(9397 750 12881)|20040820|Objective data sheet|-|-| © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **31 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **18. Legal information** ## **18.1 Data sheet status** |**Document status[1]**<br>**[2]**|**Product statu**~~**s**~~**[3]**|**Definition**| |---|---|---| |Objective [short] data sheet|Development|This document contains data from the objective specification for product development.| |Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.| |Product [short] data sheet|Production|This document contains the product specification.| [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. ## **18.2 Definitions** **Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. **Product specification —** The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. ## **18.3 Disclaimers** **Limited warranty and liability —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors. **Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. **Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. **Limiting values —** Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. **Terms and conditions of commercial sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. **No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **32 of 34** **PCA9538** **NXP Semiconductors** ## **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** **Export control —** This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. **Non-automotive qualified products —** Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. **Translations —** A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. ## **18.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. **I[2] C-bus —** logo is a trademark of NXP Semiconductors N.V. ## **19. Contact information** For more information, please visit: **http://www.nxp.com** For sales office addresses, please send an email to: **salesaddresses@nxp.com** © NXP Semiconductors N.V. 2017. All rights reserved. PCA9538 All information provided in this document is subject to legal disclaimers. **Product data sheet** **Rev. 8 — 8 November 2017** **33 of 34** **PCA9538** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt and reset** ## **20. Contents** |**1**|**General description . . . . . . . . . . . . . . . . . . . . . . 1**| |---|---| |**2**|**Features and benefits . . . . . . . . . . . . . . . . . . . . 1**| |**3**|**Ordering information. . . . . . . . . . . . . . . . . . . . . 2**| |3.1|Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2| |**4**|**Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3**| |**5**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . 4**| |5.1|Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4| |5.2|Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5| |**6**|**Functional description . . . . . . . . . . . . . . . . . . . 6**| |6.1|Device address. . . . . . . . . . . . . . . . . . . . . . . . . 6| |6.2|Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6| |6.2.1|Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 6| |6.2.2|Register 0 - Input Port register . . . . . . . . . . . . . 6| |6.2.3|Register 1 - Output Port register. . . . . . . . . . . . 7| |6.2.4|Register 2 - Polarity Inversion register . . . . . . . 7| |6.2.5|Register 3 - Configuration register . . . . . . . . . . 8| |6.3|Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8| |6.4|RESET<br>input. . . . . . . . . . . . . . . . . . . . . . . . . . . 8| |6.5|Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 8| |6.6|I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9| |6.7|Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 10| |**7**|**Application design-in information . . . . . . . . . 12**| |7.1|Minimizing IDDwhen the I/Os are used to control| ||LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13| |**8**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13**| |**9**|**Static characteristics. . . . . . . . . . . . . . . . . . . . 14**| |**10**|**Dynamic characteristics . . . . . . . . . . . . . . . . . 17**| |**11**|**Test information. . . . . . . . . . . . . . . . . . . . . . . . 20**| |**12**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21**| |**13**|**Handling information. . . . . . . . . . . . . . . . . . . . 24**| |**14**|**Soldering of SMD packages . . . . . . . . . . . . . . 24**| |14.1|Introduction to soldering . . . . . . . . . . . . . . . . . 24| |14.2|Wave and reflow soldering . . . . . . . . . . . . . . . 24| |14.3|Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 24| |14.4|Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 25| |**15**|**Soldering: PCB footprints. . . . . . . . . . . . . . . . 27**| |**16**|**Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 30**| |**17**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . . 31**| |**18**|**Legal information. . . . . . . . . . . . . . . . . . . . . . . 32**| |18.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . 32| |18.2|Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32| |18.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 32| |18.4|Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 33| |**19**|**Contact information. . . . . . . . . . . . . . . . . . . . . 33**| **20 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34** Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. **© NXP Semiconductors N.V. 2017.** **All rights reserved.** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 8 November 2017 Document identifier: PCA9538**
Updated at February 9, 2023
NXP Semiconductors is a global leader in secure connectivity solutions, driving innovation across the automotive, industrial, IoT, mobile, and communications infrastructure markets. By developing advanced, purpose-built technologies, NXP enables devices to sense, think, connect, and act intelligently, delivering rigorously tested components that make the connected world safer and more efficient. Within the semiconductor space, NXP is highly regarded for its extensive range of high-performance integrated circuits and discrete devices. The brand's portfolio excels in drivers and interfaces, featuring a comprehensive selection of I/O expanders designed to streamline complex system architectures. For demanding high-frequency and wireless applications, NXP provides industry-leading RF FETs and RF/PIN diodes engineered to deliver exceptional signal integrity, efficiency, and reliability. The NXP product lineup further extends to essential discrete components, including versatile bipolar transistors, JFETs, and small signal diodes optimized for precision switching and amplification. Additionally, the portfolio supports advanced automation and smart applications with precision IC sensors, such as MEMS accelerometers, alongside specialized power management solutions like AC/DC LED driver ICs and single MOSFETs for cutting-edge electronics design.
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