PCA9536D,118

**Product data sheet** 

**==> picture [35 x 38] intentionally omitted <==**

## **PCA9536 4-bit I[2] C-bus and SMBus I/O port** 

**Rev. 05 — 25 January 2010** 

## **1. General description** 

The PCA9536 is an 8-pin CMOS device that provides 4 bits of General Purpose parallel Input/Output (GPIO) expansion for I[2] C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I[2] C-bus I/O expanders. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc. 

The PCA9536 consists of a 4-bit Configuration register (input or output selection), 4-bit Input Port register, 4-bit Output Port register and a 4-bit Polarity Inversion register (active HIGH or active LOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input Port or Output Port register. The polarity of the read register can be inverted with the Polarity Inversion register. All registers can be read by the system master. 

The power-on reset sets the registers to their default values and initializes the device state machine. 

The I[2] C-bus address is fixed and allows only one device on the same I[2] C-bus/SMBus. 

## **2. Features** 

- 4-bit I[2] C-bus GPIO 

- Operating power supply voltage range of 2.3 V to 5.5 V 

- 5 V tolerant I/Os 

- Polarity Inversion register 

- Low standby current 

- Noise filter on SCL/SDA inputs 

- No glitch on power-up 

- Internal power-on reset 

- 4 I/O pins which default to 4 inputs with 100 kΩ internal pull-up resistor 

- 0 Hz to 400 kHz clock frequency 

- ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 

- Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA 

- Packages offered: SO8, TSSOP8 (MSOP8), HVSON8 

**==> picture [81 x 43] intentionally omitted <==**

**PCA9536** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus I/O port** 

## **3. Ordering information** 

**Table 1. Ordering information** _Tamb =_ − _40_ ° _C to +85_ ° _C_ 

|**Type**<br>**number**|**Topside**<br>**mark**|**Package**|**Package**|**Package**|
|---|---|---|---|---|
|||**Name**|**Description**|**Version**|
|PCA9536D<br>PCA9536||SO8<br>plastic small outline package; 8 leads;<br>body width 3.9 mm<br>SOT96-1|||
|PCA9536DP<br>9536||TSSOP~~8~~[1]<br>plastic thin shrink small outline package;<br>8 leads; body width 3 mm<br>SOT505-1|||
|PCA9536TK<br>9536||HVSON8<br>plastic thermal enhanced very thin small<br>outline package; no leads; 8 terminals;<br>body 3×3×0.85 mm<br>SOT908-1|||



[1] Also known as MSOP8. 

## **4. Block diagram** 

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**----- Start of picture text -----**<br>
PCA9536<br>SCL<br>INPUT IO0<br>FILTER<br>SDA<br>4-bit<br>IO1<br>INPUT/<br>I [2] C-BUS/SMBus<br>OUTPUT<br>CONTROL<br>write pulse PORTS IO2<br>VDD POWER-ON read pulse IO3<br>RESET<br>VSS<br>002aab851<br>All I/Os are set to inputs at reset.<br>**----- End of picture text -----**<br>


**Fig 1. Block diagram of PCA9536** 

© NXP B.V. 2010. All rights reserved. 

PCA9536_5 

**Product data sheet** 

**Rev. 05 — 25 January 2010** 

**2 of 22** 

**PCA9536** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus I/O port** 

## **5. Pinning information** 

## **5.1 Pinning** 

**==> picture [397 x 269] intentionally omitted <==**

**----- Start of picture text -----**<br>
IO0 1 8 VDD<br>IO0 1 8 VDD<br>IO1 2 7 SDA<br>IO1 2 7 SDA<br>PCA9536D PCA9536DP<br>IO2 3 6 SCL IO2 3 6 SCL<br>VSS 4 5 IO3 VSS 4 5 IO3<br>002aab849 002aab850<br>Fig 2. Pin configuration for SO8 Fig 3. Pin configuration for TSSOP8<br>terminal 1<br>index area<br>IO0 1 8 VDD<br>IO1 2 7 SDA<br>PCA9536TK<br>IO2 3 6 SCL<br>VSS 4 5 IO3<br>002aac459<br>Transparent top view<br>**----- End of picture text -----**<br>


**Fig 4. Pin configuration for HVSON8** 

## **5.2 Pin description** 

## **Table 2. Pin description** 

|**Symbol**|**Pin**|**Description**|
|---|---|---|
|IO0|1|input/output 0|
|IO1|2|input/output 1|
|IO2|3|input/output 2|
|VSS|4|supply ground|
|IO3|5|input/output 3|
|SCL|6|serial clock line|
|SDA|7|serial data line|
|VDD|8|supply voltage|



© NXP B.V. 2010. All rights reserved. 

PCA9536_5 

**Product data sheet** 

**Rev. 05 — 25 January 2010** 

**3 of 22** 

**PCA9536** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus I/O port** 

## **6. Functional description** 

“ ” Refer to Figure 1 Block diagram of PCA9536 . 

## **6.1 Registers** 

## **6.1.1 Command byte** 

**Table 3. Command byte** 

|**Command**|**Protocol**|**Function**|
|---|---|---|
|0|read byte|Input Port register|
|1|read/write byte|Output Port register|
|2|read/write byte|Polarity Inversion register|
|3|read/write byte|Configuration register|



The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read. 

## **6.1.2 Register 0 - Input Port register** 

This register is a read-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. 

The default ‘X’ is determined by the externally applied logic level, normally logic 1 when no external signal externally applied because of the internal pull-up resistors. 

**Table 4. Register 0 - Input Port register bit description** _Legend: * default value_ 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|I7|read only|1*|not used|
|6|I6|read only|1*||
|5|I5|read only|1*||
|4|I4|read only|1*||
|3|I3|read only|X|determined by externally applied logic level|
|2|I2|read only|X||
|1|I1|read only|X||
|0|I0|read only|X||



© NXP B.V. 2010. All rights reserved. 

PCA9536_5 **Product data sheet** 

**Rev. 05 — 25 January 2010** 

**4 of 22** 

**PCA9536** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus I/O port** 

## **6.1.3 Register 1 - Output Port register** 

This register reflects the outgoing logic levels of the pins defined as outputs by Register 3. Bit values in this register have no effect on pins defined as inputs. Reads from this register return the value that is in the flip-flop controlling the output selection, **not** the actual pin value. 

‘Not used’ bits can be programmed with either logic 0 or logic 1. 

**Table 5. Register 1 - Output Port register bit description** _Legend: * default value_ 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|O7|R|1*|not used|
|6|O6|R|1*||
|5|O5|R|1*||
|4|O4|R|1*||
|3|O3|R|1*|reflects outgoing logic levels of pins defined as|
|2|O2|R|1*|outputs by Register 3|
|1|O1|R|1*||
|0|O0|R|1*||



## **6.1.4 Register 2 - Polarity Inversion register** 

This register allows the user to invert the polarity of the Input Port register data. If a bit in this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in this register is cleared (written with a ‘0’), the Input Port data polarity is retained. 

‘Not used’ bits can be programmed with either logic 0 or logic 1. 

**Table 6. Register 2 - Polarity Inversion register bit description** _Legend: * default value_ 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|N7|R/W|0*|not used|
|6|N6|R/W|0*||
|5|N5|R/W|0*||
|4|N4|R/W|0*||
|3|N3|R/W|0*|inverts polarity of Input Port register data|
|2|N2|R/W|0*|0 = Input Port register data retained (default|
|1|N1|R/W|0*|value)|
|0|N0|R/W|0*|1 = Input Port register data inverted|



© NXP B.V. 2010. All rights reserved. 

PCA9536_5 **Product data sheet** 

**Rev. 05 — 25 January 2010** 

**5 of 22** 

**PCA9536** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus I/O port** 

## **6.1.5 Register 3 - Configuration register** 

This register configures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are configured as inputs with a weak pull-up to VDD. 

‘Not used’ bits can be programmed with either logic 0 or logic 1. 

**Table 7. Register 3 - Configuration register bit description** _Legend: * default value_ 

|**Bit**|**Symbol**|**Access**|**Value**|**Description**|
|---|---|---|---|---|
|7|C7|R/W|1*|not used|
|6|C6|R/W|1*||
|5|C5|R/W|1*||
|4|C4|R/W|1*||
|3|C3|R/W|1*|configures the directions of the I/O pins|
|2|C2|R/W|1*|0 = corresponding port pin enabled as an output|
|1|C1|R/W|1*|1 = corresponding port pin configured as input|
|0|C0|R/W|1*|(default value)|



## **6.2 Power-on reset** 

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9536 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9536 registers and state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. 

For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the operating voltage. 

## **6.3 I/O port** 

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input with a weak pull-up (100 kΩ typical) to VDD. The input voltage may be raised above VDD to a maximum of 5.5 V. 

If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the state of the Output Port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance paths that exist between the pin and either VDD or VSS. 

© NXP B.V. 2010. All rights reserved. 

PCA9536_5 **Product data sheet** 

**Rev. 05 — 25 January 2010** 

**6 of 22** 

**PCA9536** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus I/O port** 

**==> picture [381 x 320] intentionally omitted <==**

**----- Start of picture text -----**<br>
data from<br>shift register output port<br>register data<br>configuration<br>register VDD<br>data from D Q Q1<br>shift register 100 kΩ<br>FF<br>write configuration D Q<br>CK Q<br>pulse<br>FF<br>IO0 to IO3<br>write pulse CK<br>Q2<br>output port<br>register<br>VSS<br>input port<br>register<br>D Q<br>input port<br>FF register data<br>read pulse CK<br>polarity inversion<br>register<br>data from<br>D Q polarity inversion<br>shift register<br>register data<br>FF<br>write polarity<br>CK<br>pulse<br>002aab852<br>Remark:  At power-on reset, all registers return to default values.<br>**----- End of picture text -----**<br>


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Fig 5. Simplified schematic of IO0 to IO3<br>**----- End of picture text -----**<br>


## **6.4 Device address** 

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slave address<br>1 0 0 0 0 0 1 R/W<br>fixed<br>002aab853<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
Fig 6. PCA9536 device address<br>**----- End of picture text -----**<br>


## **6.5 Bus transactions** 

Data is transmitted to the PCA9536 registers using the Write mode as shown in Figure 7 and Figure 8. Data is read from the PCA9536 registers using the Read mode as shown in Figure 9 and Figure 10. These devices do not implement an auto-increment function, so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent. 

© NXP B.V. 2010. All rights reserved. 

PCA9536_5 **Product data sheet** 

**Rev. 05 — 25 January 2010** 

**7 of 22** 

**PCA9536** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus I/O port** 

**==> picture [440 x 145] intentionally omitted <==**

**----- Start of picture text -----**<br>
SCL 1 2 3 4 5 6 7 8 9<br>slave address command byte data to port<br>SDA S 1 0 0 0 0 0 1 0 A 0 0 0 0 0 0 0 1 A DATA 1 A P<br>START condition R/W acknowledge acknowledge STOP<br>from slave from slave condition<br>acknowledge<br>from slave<br>write to port<br>tv(Q)<br>data out<br>data 1 valid<br>from port<br>002aab854<br>**----- End of picture text -----**<br>


**Fig 7. Write to Output Port register** 

**==> picture [417 x 115] intentionally omitted <==**

**----- Start of picture text -----**<br>
SCL 1 2 3 4 5 6 7 8 9<br>slave address command byte data to register<br>SDA S 1 0 0 0 0 0 1 0 A 0 0 0 0 0 0 0 1/0 A DATA A P<br>START condition R/W acknowledge acknowledge STOP<br>from slave from slave condition<br>acknowledge<br>from slave<br>data to<br>register<br>002aab855<br>**----- End of picture text -----**<br>


**Fig 8. Write to Configuration register or Polarity Inversion register** 

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**----- Start of picture text -----**<br>
slave address<br>SDA S 1 0 0 0 0 0 1 0 A command byte A (cont.)<br>START condition R/W acknowledge<br>from slave<br>acknowledge<br>from slave<br>slave address data from register data from register<br>(cont.) S 1 0 0 0 0 0 1 1 A DATA (first byte) A DATA (last byte) NA P<br>(repeated) R/W acknowledge no acknowledge STOP<br>START condition from master from master condition<br>acknowledge<br>from slave<br>at this moment master-transmitter becomes master-receiver<br>and slave-receiver becomes slave-transmitter<br>002aab856<br>**----- End of picture text -----**<br>


**Fig 9. Read from register** 

© NXP B.V. 2010. All rights reserved. 

PCA9536_5 **Product data sheet** 

**Rev. 05 — 25 January 2010** 

**8 of 22** 

**PCA9536** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus I/O port** 

**==> picture [430 x 180] intentionally omitted <==**

**----- Start of picture text -----**<br>
SCL 1 2 3 4 5 6 7 8 9<br>slave address data from port data from port<br>SDA S 1 0 0 0 0 0 1 1 A DATA 1 A DATA 4 NA P<br>START condition R/W acknowledge no acknowledge STOP<br>from master from master condition<br>acknowledge<br>from slave<br>read from<br>port<br>th(D) tsu(D)<br>data into<br>DATA 2 DATA 3 DATA 4<br>port<br>002aab857<br>This figure assumes the command byte has previously been programmed with 00h.<br>Transfer of data can be stopped at any moment by a STOP condition.<br>**----- End of picture text -----**<br>


**Fig 10. Read Input Port register** 

## **7. Application design-in information** 

**==> picture [380 x 237] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>2 kΩ<br>VDD 10 kΩ 10 kΩ<br>VDD<br>SUBSYSTEM 1<br>SDA SDA IO0 (e.g. temp. sensor)<br>SCL SCL<br>IO1 INT<br>PCA9536<br>MASTER<br>IO2<br>CONTROLLER RESET<br>IO3<br>VSS SUBSYSTEM 2<br>(e.g. counter)<br>VSS A<br>enable controlled switch<br>(e.g. CBT device)<br>B<br>002aab858<br>Device address is 1000 001X; IO0, IO2, IO3 configured as outputs; IO1 configured as input.<br>Fig 11. Typical application<br>**----- End of picture text -----**<br>


© NXP B.V. 2010. All rights reserved. 

PCA9536_5 **Product data sheet** 

**Rev. 05 — 25 January 2010** 

**9 of 22** 

**PCA9536** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus I/O port** 

## **8. Limiting values** 

**Table 8. Limiting values** _In accordance with the Absolute Maximum Rating System (IEC 60134)._ 

|**Symbol**|**Parameter**|**Conditions**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|---|
|VDD|supply voltage||−0.5|+6.0|V|
|II|input current||-|±20|mA|
|VI/O|voltage on an input/output pin||VSS−0.5|5.5|V|
|IO(IOn)|output current on pin IOn||-|±50|mA|
|IDD|supply current||-|85|mA|
|ISS|ground supply current||-|100|mA|
|Ptot|total power dissipation||-|200|mW|
|Tstg|storage temperature||−65|+150|°C|
|Tamb|ambient temperature||−40|+85|°C|
|Tj(max)|maximum junction temperature||-|+125|°C|



© NXP B.V. 2010. All rights reserved. 

PCA9536_5 **Product data sheet** 

**Rev. 05 — 25 January 2010** 

**10 of 22** 

**PCA9536** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus I/O port** 

## **9. Static characteristics** 

**Table 9. Static characteristics** _VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb =_ − _40_ ° _C to +85_ ° _C; unless otherwise specified._ 

|**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**|
|---|---|
|**Supplies**||
|VDD<br>supply voltage|2.3<br>-<br>5.5<br>V|
|IDD<br>supply current|operating mode; VDD= 5.5 V;<br>no load; fSCL= 100 kHz<br>-<br>290<br>400<br>μA|
|Istb<br>standby current|Standby mode; VDD= 5.5 V; no load;<br>VI= VSS; fSCL= 0 kHz; I/O = inputs<br>-<br>225<br>350<br>μA|
||Standby mode; VDD= 5.5 V; no load;<br>VI= VDD; fSCL= 0 kHz; I/O = inputs<br>-<br>0.25<br>1<br>μA|
|VPOR<br>power-on reset voltage|[1]<br>-<br>1.5<br>1.65<br>V|
|**Input SCL; input/output SDA**||
|VIL<br>LOW-level input voltage|−0.5<br>-<br>+0.3VDD<br>V|
|VIH<br>HIGH-level input voltage|0.7VDD<br>-<br>5.5<br>V|
|IOL<br>LOW-level output current|VOL= 0.4 V<br>3<br>6<br>-<br>mA|
|IL<br>leakage current|VI= VDD= VSS<br>−1<br>-<br>+1<br>μA|
|Ci<br>input capacitance|VI= VSS<br>-<br>6<br>10<br>pF|
|**I/Os**||
|VIL<br>LOW-level input voltage|−0.5<br>-<br>+0.8<br>V|
|VIH<br>HIGH-level input voltage|2.0<br>-<br>5.5<br>V|
|IOL<br>LOW-level output current|VOL= 0.5 V; VDD= 2.3 V<br>[2]<br>8<br>10<br>-<br>mA|
||VOL= 0.7 V; VDD= 2.3 V<br>[2]<br>10<br>13<br>-<br>mA|
||VOL= 0.5 V; VDD= 3.0 V<br>[2]<br>8<br>14<br>-<br>mA|
||VOL= 0.7 V; VDD= 3.0 V<br>[2]<br>10<br>19<br>-<br>mA|
||VOL= 0.5 V; VDD= 4.5 V<br>[2]<br>8<br>17<br>-<br>mA|
||VOL= 0.7 V; VDD= 4.5 V<br>[2]<br>10<br>24<br>-<br>mA|
|VOH<br>HIGH-level output voltage|IOH=−8 mA; VDD= 2.3 V<br>[3]<br>1.8<br>-<br>-<br>V|
||IOH=−10 mA; VDD= 2.3 V<br>[3]<br>1.7<br>-<br>-<br>V|
||IOH=−8 mA; VDD= 3.0 V<br>[3]<br>2.6<br>-<br>-<br>V|
||IOH=−10 mA; VDD= 3.0 V<br>[3]<br>2.5<br>-<br>-<br>V|
||IOH=−8 mA; VDD= 4.75 V<br>[3]<br>4.1<br>-<br>-<br>V|
||IOH=−10 mA; VDD= 4.75 V<br>[3]<br>4.0<br>-<br>-<br>V|
|ILIH<br>HIGH-level input leakage<br>current|VDD= 3.6 V; VI= VDD<br>-<br>-<br>1<br>μA|
|ILIL<br>LOW-level input leakage<br>current|VDD= 5.5 V; VI= VSS<br>-<br>-<br>−100<br>μA|
|Ci<br>input capacitance|-<br>3.7<br>5<br>pF|
|Co<br>output capacitance|-<br>3.7<br>5<br>pF|



[1] VDD must be lowered to 0.2 V in order to reset part. 

[2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA. 

[3] The total current sourced by all I/Os must be limited to 85 mA. 

© NXP B.V. 2010. All rights reserved. 

PCA9536_5 

**Product data sheet** 

**Rev. 05 — 25 January 2010** 

**11 of 22** 

**PCA9536** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus I/O port** 

## **10. Dynamic characteristics** 

## **Table 10. Dynamic characteristics** 

|**Symbol**<br>**Parameter**<br>**Conditions**|**Standard-mode**<br>**I2C-bus**|**Standard-mode**<br>**I2C-bus**|**Fast-mode I2C-bus**|**Fast-mode I2C-bus**|**Unit**|
|---|---|---|---|---|---|
||**Min**|**Max**|**Min**|**Max**||
|fSCL<br>SCL clock frequency|0<br>100<br>0<br>400<br>kHz|||||
|tBUF<br>bus free time between a STOP and<br>START condition|4.7<br>-<br>1.3<br>-<br>μs|||||
|tHD;STA<br>hold time (repeated) START condition|4.0<br>-<br>0.6<br>-<br>μs|||||
|tSU;STA<br>set-up time for a repeated START<br>condition|4.7<br>-<br>0.6<br>-<br>μs|||||
|tSU;STO<br>set-up time for STOP condition|4.0<br>-<br>0.6<br>-<br>μs|||||
|tHD;DAT<br>data hold time|0<br>-<br>0<br>-<br>μs|||||
|tVD;ACK<br>data valid acknowledge time<br>[1]|0.3<br>3.45<br>0.1<br>0.9<br>μs|||||
|tVD;DAT<br>data valid time<br>[2]|300<br>-<br>50<br>-<br>ns|||||
|tSU;DAT<br>data set-up time|250<br>-<br>100<br>-<br>ns|||||
|tLOW<br>LOW period of the SCL clock|4.7<br>-<br>1.3<br>-<br>μs|||||
|tHIGH<br>HIGH period of the SCL clock|4.0<br>-<br>0.6<br>-<br>μs|||||
|tr<br>rise time of both SDA and SCL signals|-<br>1000<br>20 + 0.1Cb[3]<br>300<br>ns|||||
|tf<br>fall time of both SDA and SCL signals|-<br>300<br>20 + 0.1Cb[3]<br>300<br>ns|||||
|tSP<br>pulse width of spikes that must be<br>suppressed by the input filter|-<br>50<br>-<br>50<br>ns|||||
|**Port timing**||||||
|tv(Q)<br>data output valid time|-<br>200<br>-<br>200<br>ns|||||
|tsu(D)<br>data input set-up time|100<br>-<br>100<br>-<br>ns|||||
|th(D)<br>data input hold time|1<br>-<br>1<br>-<br>μs|||||



[1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. 

[2] tVD;DAT = minimum time for SDA data output to be valid following SCL LOW. 

- [3] Cb = total capacitance of one bus line in pF. 

**==> picture [395 x 107] intentionally omitted <==**

**----- Start of picture text -----**<br>
SDA<br>tf tLOW tSU;DAT tHD;STA tSP tBUF<br>tr tf tr<br>SCL<br>tHD;STA tHIGH tSU;STA tSU;STO<br>S tHD;DAT Sr P S<br>002aab271<br>**----- End of picture text -----**<br>


**Fig 12. Definition of timing** 

© NXP B.V. 2010. All rights reserved. 

PCA9536_5 **Product data sheet** 

**Rev. 05 — 25 January 2010** 

**12 of 22** 

**PCA9536** 

**NXP Semiconductors** 

## **4-bit I[2] C-bus and SMBus I/O port** 

**==> picture [353 x 179] intentionally omitted <==**

**----- Start of picture text -----**<br>
START bit 7 STOP<br>protocol condition MSB bit 6 bit 0 acknowledge condition<br>(A6) (R/W) (A)<br>(S) (A7) (P)<br>tSU;STA tLOW tHIGH 1/fSCL<br>SCL<br>tBUF tf<br>tr<br>SDA<br>tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO<br>002aab175<br>Rise and fall times refer to VIL and VIH<br>**----- End of picture text -----**<br>


**Fig 13. I[2] C-bus timing diagram** 

## **11. Test information** 

**==> picture [262 x 111] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD<br>open<br>VDD RL VSS<br>500 Ω<br>VI VO<br>PULSE<br>DUT<br>GENERATOR<br>RT CL<br>50 pF<br>002aab880<br>RL = load resistor.<br>**----- End of picture text -----**<br>


CL = load capacitance includes jig and probe capacitance. 

RT = termination resistance should be equal to the output impedance Zo of the pulse generators. 

**Fig 14. Test circuitry for switching times** 

**==> picture [292 x 76] intentionally omitted <==**

**----- Start of picture text -----**<br>
500 Ω S1 2VDD<br>from output open<br>under test VSS<br>CL 500 Ω<br>50 pF<br>002aab881<br>Fig 15. Test circuit<br>**----- End of picture text -----**<br>


**Table 11. Test data** 

|**Test**|**Load**|**Load**|**Switch**|
|---|---|---|---|
||**CL**<br>|**RL**||
|tv(Q)|50 pF<br>500Ω<br>2VDD|||



© NXP B.V. 2010. All rights reserved. 

PCA9536_5 **Product data sheet** 

**Rev. 05 — 25 January 2010** 

**13 of 22** 

**PCA9536** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus I/O port** 

## **12. Package outline** 

## **SO8: plastic small outline package; 8 leads; body width 3.9 mm** 

## **SOT96-1** 

**==> picture [478 x 570] intentionally omitted <==**

**----- Start of picture text -----**<br>
D E A<br>X<br>c<br>y HE v M A<br>Z<br>8 5<br>Q<br>A2 A1 (A  )3 A<br>pin 1 index<br>θ<br>L p<br>1 4 L<br>e w M detail X<br>b p<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (inch dimensions are derived from the original mm dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(2)] e HE L Lp Q v w y Z (1) θ<br>0.25 1.45 0.49 0.25 5.0 4.0 6.2 1.0 0.7 0.7<br>mm 1.75 0.10 1.25 0.25 0.36 0.19 4.8 3.8 1.27 5.8 1.05 0.4 0.6 0.25 0.25 0.1 0.3 8o<br>0.010 0.057 0.019 0.0100 0.20 0.16 0.244 0.039 0.028 0.028 0o<br>inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004<br>0.004 0.049 0.014 0.0075 0.19 0.15 0.228 0.016 0.024 0.012<br>Notes<br>1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.<br>2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.<br>OUTLINE  REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION  IEC  JEDEC  JEITA PROJECTION<br>99-12-27<br> SOT96-1 076E03  MS-012<br>03-02-18<br>**----- End of picture text -----**<br>


**Fig 16. Package outline SOT96-1 (SO8)** 

PCA9536_5 

© NXP B.V. 2010. All rights reserved. 

**Product data sheet** 

**Rev. 05 — 25 January 2010** 

**14 of 22** 

**PCA9536** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus I/O port** 

**TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm** 

**SOT505-1** 

**==> picture [478 x 570] intentionally omitted <==**

**----- Start of picture text -----**<br>
D E A<br>X<br>c<br>y HE v M A<br>Z<br>8 5<br>A2 (A3) A<br>A1<br>pin 1 index<br>θ<br>Lp<br>L<br>1 4<br>detail X<br>e bp w M<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>A<br>UNIT max. A1 A2 A3 bp c D [(1)] E [(2)] e HE L Lp v w y Z [(1)] θ<br>mm 1.1 0.150.05 0.950.80 0.25 0.450.25 0.280.15 3.12.9 3.12.9 0.65 5.14.7 0.94 0.70.4 0.1 0.1 0.1 0.700.35 60°°<br>Notes<br>1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.<br>2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.<br>OUTLINE  REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION  IEC  JEDEC  JEITA PROJECTION<br>99-04-09<br> SOT505-1<br>03-02-18<br>**----- End of picture text -----**<br>


**Fig 17. Package outline SOT505-1 (TSSOP8)** PCA9536_5 

© NXP B.V. 2010. All rights reserved. 

**Product data sheet** 

**Rev. 05 — 25 January 2010** 

**15 of 22** 

**PCA9536** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus I/O port** 

**HVSON8: plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3 x 3 x 0.85 mm** 

**==> picture [43 x 8] intentionally omitted <==**

**----- Start of picture text -----**<br>
SOT908-1<br>**----- End of picture text -----**<br>


**==> picture [482 x 550] intentionally omitted <==**

**----- Start of picture text -----**<br>
0 1 2 mm<br>scale<br>X<br>D B A<br>E A<br>A1<br>c<br>detail X<br>terminal 1<br>index area<br>terminal 1 e1 C<br>v M C A B<br>index area e b<br>1 4 w M C y1 C y<br>L<br>exposed tie bar (4×)<br>Eh<br>exposed tie bar (4×)<br>8 5<br>Dh<br>DIMENSIONS (mm are the original dimensions)<br>A [(1)]<br>UNIT max. A1 b c D [(1)] Dh E [(1)] Eh e e1 L v w y y1<br>0.05 0.3 3.1 2.25 3.1 1.65 0.5<br>mm 1 0.2 0.5 1.5 0.1 0.05 0.05 0.1<br>0.00 0.2 2.9 1.95 2.9 1.35 0.3<br>Note<br>1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.<br>OUTLINE  REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION  IEC  JEDEC JEITA PROJECTION<br>05-09-26<br> SOT908-1 MO-229<br>05-10-05<br>**----- End of picture text -----**<br>


**Fig 18. Package outline SOT908-1 (HVSON8)** 

© NXP B.V. 2010. All rights reserved. 

PCA9536_5 

**Product data sheet** 

**Rev. 05 — 25 January 2010** 

**16 of 22** 

**PCA9536** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus I/O port** 

## **13. Handling information** 

All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in _JESD625-A_ or equivalent standards. 

## **14. Soldering of SMD packages** 

This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note _AN10365 “Surface mount reflow soldering description”_ . 

## **14.1 Introduction to soldering** 

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 

## **14.2 Wave and reflow soldering** 

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: 

- Through-hole components 

- Leaded or leadless SMDs, which are glued to the surface of the printed circuit board 

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. 

The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. 

Key characteristics in both wave and reflow soldering are: 

- Board specifications, including the board finish, solder masks and vias 

- Package footprints, including solder thieves and orientation 

- The moisture sensitivity level of the packages 

- Package placement 

- Inspection and repair 

- Lead-free soldering versus SnPb soldering 

## **14.3 Wave soldering** 

Key characteristics in wave soldering are: 

© NXP B.V. 2010. All rights reserved. 

PCA9536_5 

**Product data sheet** 

**Rev. 05 — 25 January 2010** 

**17 of 22** 

**PCA9536** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus I/O port** 

- Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave 

- Solder bath specifications, including temperature and impurities 

## **14.4 Reflow soldering** 

Key characteristics in reflow soldering are: 

- Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 19) than a SnPb process, thus reducing the process window 

- Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board 

- Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13 

## **Table 12. SnPb eutectic process (from J-STD-020C)** 

|**Package thickness (mm)**|**Package reflow temperature (**°**C)**|**Package reflow temperature (**°**C)**|
|---|---|---|
||**Volume (mm3)**||
||**< 350**|≥**350**|
|< 2.5|235<br>220||
|≥2.5|220<br>220||



## **Table 13. Lead-free process (from J-STD-020C)** 

|**Package thickness (mm)**|**Package reflow temperature (**°**C)**|**Package reflow temperature (**°**C)**|**Package reflow temperature (**°**C)**|
|---|---|---|---|
||**Volume (mm3)**|||
||**< 350**|**350 to 2000**|**> 2000**|
|< 1.6|260<br>260<br>260|||
|1.6 to 2.5|260<br>250<br>245|||
|> 2.5|250<br>245<br>245|||



Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. 

Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 19. 

© NXP B.V. 2010. All rights reserved. 

PCA9536_5 

**Product data sheet** 

**Rev. 05 — 25 January 2010** 

**18 of 22** 

**PCA9536** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus I/O port** 

**==> picture [351 x 222] intentionally omitted <==**

**----- Start of picture text -----**<br>
maximum peak temperature<br>temperature = MSL limit, damage level<br>minimum peak temperature<br>= minimum soldering temperature<br>peak<br> temperature<br>time<br>001aac844<br>MSL: Moisture Sensitivity Level<br>Fig 19. Temperature profiles for large and small components<br>**----- End of picture text -----**<br>


For further information on temperature profiles, refer to Application Note _AN10365 “Surface mount reflow soldering description”_ . 

## **15. Abbreviations** 

## **Table 14. Abbreviations** 

|**Acronym**|**Description**|
|---|---|
|ACPI|Advanced Configuration and Power Interface|
|CDM|Charged Device Model|
|DUT|Device Under Test|
|ESD|ElectroStatic Discharge|
|FET|Field-Effect Transistor|
|GPIO|General Purpose Input/Output|
|HBM|Human Body Model|
|I2C-bus|Inter-Integrated Circuit bus|
|I/O|Input/Output|
|LED|Light-Emitting Diode|
|MM|Machine Model|
|POR|Power-On Reset|
|SMBus|System Management Bus|



© NXP B.V. 2010. All rights reserved. 

PCA9536_5 **Product data sheet** 

**Rev. 05 — 25 January 2010** 

**19 of 22** 

**PCA9536** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus I/O port** 

## **16. Revision history** 

**Table 15. Revision history** 

|**Document ID**|**Release date**|**Release date**|**Data sheet status**|**Change notice**|**Supersedes**|
|---|---|---|---|---|---|
|PCA9536_5|20100125||Product data sheet|-|PCA9536_4|
|Modifications:|**•** Table 9“<br>Static characteristics<br>”<br>,sub-section|||“Supplies”:||
||**–**<br>IDDTypical value changed from “104μA” to “290μA”|||||
||**–**<br>IDDMaximum value changed from “175μA” to “400μA”|||||
||**•** Table 10|“<br>Dynamic characteristics<br>”<br>:Unit for||“tf, fall time of both|SDA and SCL signals”|
||changed||from “μs” to “ns”|||
||**Remark:**The||changes made in this revision are|to correct typographical errors only. There is||
||no change in|the performance of the device.||||
|PCA9536_4|20070911||Product data sheet|-|PCA9536_3|
|PCA9536_3|20061009||Product data sheet|-|PCA9536_2|
|PCA9536_2|20040930||Objective data sheet|-|PCA9536_1|
|(9397 750 14124)||||||
|PCA9536_1|20040820||Objective data sheet|-|-|
|(9397 750 12895)||||||



© NXP B.V. 2010. All rights reserved. 

PCA9536_5 **Product data sheet** 

**Rev. 05 — 25 January 2010** 

**20 of 22** 

**PCA9536** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus I/O port** 

## **17. Legal information** 

## **17.1 Data sheet status** 

|**Document status[1]**<br>**[2]**|**Product statu**~~**s**~~**[3]**|**Definition**|
|---|---|---|
|Objective [short] data sheet|Development|This document contains data from the objective specification for product development.|
|Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.|
|Product [short] data sheet|Production|This document contains the product specification.|



[1] Please consult the most recently issued document before initiating or completing a design. 

[2] The term ‘short data sheet’ is explained in section “Definitions”. 

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 

## **17.2 Definitions** 

**Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 

**Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 

## **17.3 Disclaimers** 

**General —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. 

**Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 

**Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 

damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 

**Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 

**Limiting values —** Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. 

**Terms and conditions of sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. 

**No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 

**Export control —** This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 

## **17.4 Trademarks** 

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. **I[2] C-bus  —** logo is a trademark of NXP B.V. 

## **18. Contact information** 

For more information, please visit: **http://www.nxp.com** 

For sales office addresses, please send an email to: **salesaddresses@nxp.com** 

© NXP B.V. 2010. All rights reserved. 

PCA9536_5 

**Product data sheet** 

**Rev. 05 — 25 January 2010** 

**21 of 22** 

**PCA9536** 

**NXP Semiconductors** 

**4-bit I[2] C-bus and SMBus I/O port** 

## **19. Contents** 

|**1**|**General description . . . . . . . . . . . . . . . . . . . . . .  1**|
|---|---|
|**2**|**Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  1**|
|**3**|**Ordering information. . . . . . . . . . . . . . . . . . . . .  2**|
|**4**|**Block diagram  . . . . . . . . . . . . . . . . . . . . . . . . . .  2**|
|**5**|**Pinning information. . . . . . . . . . . . . . . . . . . . . .  3**|
|5.1|Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3|
|5.2|Pin description  . . . . . . . . . . . . . . . . . . . . . . . . .  3|
|**6**|**Functional description  . . . . . . . . . . . . . . . . . . .  4**|
|6.1|Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4|
|6.1.1|Command byte . . . . . . . . . . . . . . . . . . . . . . . . .  4|
|6.1.2|Register 0 - Input Port register . . . . . . . . . . . . .  4|
|6.1.3|Register 1 - Output Port register. . . . . . . . . . . .  5|
|6.1.4|Register 2 - Polarity Inversion register . . . . . . .  5|
|6.1.5|Register 3 - Configuration register . . . . . . . . . .  6|
|6.2|Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . .  6|
|6.3|I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6|
|6.4|Device address. . . . . . . . . . . . . . . . . . . . . . . . .  7|
|6.5|Bus transactions . . . . . . . . . . . . . . . . . . . . . . . .  7|
|**7**|**Application design-in information . . . . . . . . . .  9**|
|**8**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . .  10**|
|**9**|**Static characteristics. . . . . . . . . . . . . . . . . . . .  11**|
|**10**|**Dynamic characteristics . . . . . . . . . . . . . . . . .  12**|
|**11**|**Test information. . . . . . . . . . . . . . . . . . . . . . . .  13**|
|**12**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . .  14**|
|**13**|**Handling information. . . . . . . . . . . . . . . . . . . .  17**|
|**14**|**Soldering of SMD packages . . . . . . . . . . . . . .  17**|
|14.1|Introduction to soldering . . . . . . . . . . . . . . . . .  17|
|14.2|Wave and reflow soldering . . . . . . . . . . . . . . .  17|
|14.3|Wave soldering. . . . . . . . . . . . . . . . . . . . . . . .  17|
|14.4|Reflow soldering . . . . . . . . . . . . . . . . . . . . . . .  18|
|**15**|**Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . .  19**|
|**16**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . .  20**|
|**17**|**Legal information. . . . . . . . . . . . . . . . . . . . . . .  21**|
|17.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . .  21|
|17.2|Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . .  21|
|17.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .  21|
|17.4|Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . .  21|
|**18**|**Contact information. . . . . . . . . . . . . . . . . . . . .  21**|
|**19**|**Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  22**|



Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 

**==> picture [84 x 52] intentionally omitted <==**

**© NXP B.V. 2010.** 

**All rights reserved.** 

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 25 January 2010 Document identifier: PCA9536_5**