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PCA9535BS,118
I/O Expander, 16bit, 400 kHz, I2C, SMBus, 2.3 V, 5.5 V, HVQFN
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: NXP
- Product type: I/O Expanders
| Delivery and price | |
|---|---|
| Units per pack | 100 |
| Price | 1.77 € |
| Current stock | 1000+ |
| Lead time | 7 days |
Datasheet
**==> picture [35 x 38] intentionally omitted <==** **PCA9535; PCA9535C 16-bit I[2] C-bus and SMBus, low power I/O port with interrupt Rev. 05 — 15 September 2008 Product data sheet** ## **1. General description** The PCA9535 and PCA9535C are 24-pin CMOS devices that provide 16 bits of General Purpose parallel Input/Output (GPIO) expansion for I[2] C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I[2] C-bus I/O expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O configuration, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc. selection), Input, Output and Polarity Inversion (active HIGH or active LOW operation) registers. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity Inversion register. All registers can be read by the system master. Although pin-to-pin and I[2] C-bus address compatible with the PCF8575, software changes are required due to the enhancements and are discussed in Application Note AN469. The PCA9535 is identical to the PCA9555 except for the removal of the internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are held LOW. The PCA9535C is identical to the PCA9535 except that all the I/O pins are high-impedance open-drain outputs. The PCA9535 and PCA9535C open-drain interrupt output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. Three hardware pins (A0, A1, A2) vary the fixed I[2] C-bus address and allow up to eight devices to share the same I[2] C-bus/SMBus. The fixed I[2] C-bus address of the PCA9535 and PCA9535C are the same as the PCA9555 allowing up to eight of these devices in any combination to share the same I[2] C-bus/SMBus. ## **2. Features** I Operating power supply voltage range of 2.3 V to 5.5 V - I 5 V tolerant I/Os - I Polarity Inversion register - I Active LOW interrupt output - I Low standby current - I **==> picture [211 x 101] intentionally omitted <==** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** - I No glitch on power-up - I Internal power-on reset - I 16 I/O pins which default to 16 inputs - I 0 Hz to 400 kHz clock frequency - I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 - I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA - I Offered in four different packages: SO24, TSSOP24, HVQFN24 and HWQFN24 ## **3. Ordering information** **Table 1. Ordering information** |**Type number**|**Package**|**Package**|**Package**| |---|---|---|---| ||**Name**|**Description**|**Version**| |PCA9535D|SO24<br>plastic small outline package; 24 leads;<br>body width 7.5 mm<br>SOT137-1||| |PCA9535PW|TSSOP24<br>plastic thin shrink small outline package; 24 leads; body<br>width 4.4 mm<br>SOT355-1||| |PCA9535BS|HVQFN24<br>plastic thermal enhanced very thin quad fat package;<br>no leads; 24 terminals; body 4×4×0.85 mm<br>SOT616-1||| |PCA9535HF|HWQFN24<br>plastic thermal enhanced very very thin quad fat<br>package; no leads; 24 terminals; body 4×4×0.75 mm<br>SOT994-1||| |PCA9535CD|SO24<br>plastic small outline package; 24 leads;<br>body width 7.5 mm<br>SOT137-1||| |PCA9535CPW|TSSOP24<br>plastic thin shrink small outline package; 24 leads; body<br>width 4.4 mm<br>SOT355-1||| |PCA9535CHF|HWQFN24<br>plastic thermal enhanced very very thin quad fat<br>package; no leads; 24 terminals; body 4×4×0.75 mm<br>SOT994-1||| ## **3.1 Ordering options** **Table 2. Ordering options** |**Type number**|**Topside mark**|**Temperature range**| |---|---|---| |PCA9535D|PCA9535D|Tamb=−40°C to +85°C| |PCA9535PW|PCA9535PW|Tamb=−40°C to +85°C| |PCA9535BS|9535|Tamb=−40°C to +85°C| |PCA9535HF|P35H|Tamb=−40°C to +85°C| |PCA9535CD|PCA9535CD|Tamb=−40°C to +85°C| |PCA9535CPW|PCA9535C|Tamb=−40°C to +85°C| |PCA9535CHF|P35C|Tamb=−40°C to +85°C| © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Product data sheet** **Rev. 05 — 15 September 2008** **2 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** ## **4. Block diagram** **==> picture [371 x 321] intentionally omitted <==** **----- Start of picture text -----**<br> PCA9535<br>IO1_0<br>PCA9535C<br>IO1_1<br>A0 8-bit IO1_2<br>A1 INPUT/ IO1_3<br>OUTPUT<br>A2 PORTS IO1_4<br>write pulse IO1_5<br>IO1_6<br>read pulse<br>IO1_7<br>I [2] C-BUS/SMBus<br>CONTROL<br>SCL INPUT IO0_0<br>FILTER IO0_1<br>SDA<br>8-bit IO0_2<br>INPUT/ IO0_3<br>OUTPUT<br>PORTS IO0_4<br>write pulse IO0_5<br>IO0_6<br>read pulse<br>VDD POWER-ON IO0_7<br>RESET<br>VSS VDD<br>INT<br>002aac217<br>Remark: All I/Os are set to inputs at reset.<br>Fig 1. Block diagram of PCA9535; PCA9535C<br>**----- End of picture text -----**<br> © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Product data sheet** **Rev. 05 — 15 September 2008** **3 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** ## **5. Pinning information** ## **5.1 Pinning** **==> picture [397 x 416] intentionally omitted <==** **----- Start of picture text -----**<br> INT 1 24 VDD INT 1 24 VDD<br>A1 2 23 SDA A1 2 23 SDA<br>A2 3 22 SCL A2 3 22 SCL<br>IO0_0 4 21 A0 IO0_0 4 21 A0<br>IO0_1 5 20 IO1_7 IO0_1 5 20 IO1_7<br>IO0_2 6 PCA9535D 19 IO1_6 IO0_2 6 PCA9535PW 19 IO1_6<br>IO0_3 7 PCA9535CD 18 IO1_5 IO0_3 7 PCA9535CPW 18 IO1_5<br>IO0_4 8 17 IO1_4 IO0_4 8 17 IO1_4<br>IO0_5 9 16 IO1_3 IO0_5 9 16 IO1_3<br>IO0_6 10 15 IO1_2 IO0_6 10 15 IO1_2<br>IO0_7 11 14 IO1_1 IO0_7 11 14 IO1_1<br>VSS 12 13 IO1_0 VSS 12 13 IO1_0<br>002aac214 002aac215<br>Fig 2. Pin configuration for SO24 Fig 3. Pin configuration for TSSOP24<br>PCA9535HF<br>PCA9535BS PCA9535CHF<br>terminal 1 terminal 1<br>index area index area<br>IO0_0 1 18 A0 IO0_0 1 18 A0<br>IO0_1 2 17 IO1_7 IO0_1 2 17 IO1_7<br>IO0_2 3 16 IO1_6 IO0_2 3 16 IO1_6<br>IO0_3 4 15 IO1_5 IO0_3 4 15 IO1_5<br>IO0_4 5 14 IO1_4 IO0_4 5 14 IO1_4<br>IO0_5 6 13 IO1_3 IO0_5 6 13 IO1_3<br>002aac216 002aac880<br>Transparent top view Transparent top view<br>Fig 4. Pin configuration for HVQFN24 Fig 5. Pin configuration for HWQFN24<br>A2 A1 INT VDD SDA SCL A2 A1 INT VDD SDA SCL<br>24 23 22 21 20 19 24 23 22 21 20 19<br>7 8 9 10 11 12 7 8 9 10 11 12<br>VSS VSS<br>IO0_6 IO0_7 IO1_0 IO1_1 IO1_2 IO0_6 IO0_7 IO1_0 IO1_1 IO1_2<br>**----- End of picture text -----**<br> © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Product data sheet** **Rev. 05 — 15 September 2008** **4 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** ## **5.2 Pin description** |**Table 3.**<br>|**Pin description**|**Pin description**|**Pin description**| |---|---|---|---| |**Symbol**|**Pin**||**Description**| ||**SO24, TSSOP24**|**HVQFN24,**<br>**HWQFN24**|| |INT|1<br>22<br>interrupt output (open-drain)||| |A1|2<br>23<br>address input 1||| |A2|3<br>24<br>address input 2||| |IO0_0|4<br>1<br>port 0 input/outpu~~t~~<br>[2]<br>5<br>2<br>6<br>3<br>7<br>4<br>8<br>5<br>9<br>6<br>10<br>7<br>11<br>8||| |IO0_1|||| |IO0_2|||| |IO0_3|||| |IO0_4|||| |IO0_5|||| |IO0_6|||| |IO0_7|||| |VSS|12<br>9<br>[1]<br>supply ground||| |IO1_0|13<br>10<br>port 1 input/outpu~~t~~<br>[2]<br>14<br>11<br>15<br>12<br>16<br>13<br>17<br>14<br>18<br>15<br>19<br>16<br>20<br>17||| |IO1_1|||| |IO1_2|||| |IO1_3|||| |IO1_4|||| |IO1_5|||| |IO1_6|||| |IO1_7|||| |A0|21<br>18<br>address input 0||| |SCL|22<br>19<br>serial clock line||| |SDA|23<br>20<br>serial data line||| |VDD|24<br>21<br>supply voltage||| - [1] HVQFN24 and HWQFN24 package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region. - [2] PCA9535 I/Os are totem pole, whereas the I/Os on PCA9535C are open-drain. © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Product data sheet** **Rev. 05 — 15 September 2008** **5 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** ## **6. Functional description** Refer to Figure 1 “Block diagram of PCA9535; PCA9535C”. ## **6.1 Device address** **==> picture [138 x 56] intentionally omitted <==** **----- Start of picture text -----**<br> slave address<br>0 1 0 0 A2 A1 A0 R/W<br>fixed programmable<br>002aac219<br>**----- End of picture text -----**<br> **Fig 6. PCA9535; PCA9535C device address** ## **6.2 Registers** ## **6.2.1 Command byte** It is used as a pointer to determine which of the following registers will be written or read. **Table 4. Command byte** |**Command**|**Register**| |---|---| |0|Input port 0| |1|Input port 1| |2|Output port 0| |3|Output port 1| |4|Polarity Inversion port 0| |5|Polarity Inversion port 1| |6|Confguration port 0| |7|Confguration port 1| © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Product data sheet** **Rev. 05 — 15 September 2008** **6 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** ## **6.2.2 Registers 0 and 1: Input port registers** regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default value ‘X’ is determined by the externally applied logic level. ## **Table 5. Input port 0 Register** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|I0.7|I0.6|I0.5|I0.4|I0.3|I0.2|I0.1|I0.0| |**Default**|X|X|X|X|X|X|X|X| |**Table 6.**<br>**Input port 1 register**||||||||| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||| |**Symbol**|I1.7|I1.6|I1.5|I1.4|I1.3|I1.2|I1.1|I1.0| |**Default**|X|X|X|X|X|X|X|X| ## **6.2.3 Registers 2 and 3: Output port registers** as outputs by Registers 6 and 7. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, **not** the actual pin value. ## **Table 7. Output port 0 register** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|O0.7|O0.6|O0.5|O0.4|O0.3|O0.2|O0.1|O0.0| |**Default**|1|1|1|1|1|1|1|1| |**Table 8.**<br>**Output port 1 register**||||||||| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||| |**Symbol**|O1.7|O1.6|O1.5|O1.4|O1.3|O1.2|O1.1|O1.0| |**Default**|1|1|1|1|1|1|1|1| ## **6.2.4 Registers 4 and 5: Polarity Inversion registers** This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set (written with ‘1’), the Input port data polarity is inverted. If a bit in this register is cleared (written with a ‘0’), the Input port data polarity is retained. ## **Table 9. Polarity Inversion port 0 register** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|N0.7|N0.6|N0.5|N0.4|N0.3|N0.2|N0.1|N0.0| |**Default**|0|0|0|0|0|0|0|0| |**Table 10.**<br>**Polarity Inversion port 1 register**||||||||| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||| |**Symbol**|N1.7|N1.6|N1.5|N1.4|N1.3|N1.2|N1.1|N1.0| |**Default**|0|0|0|0|0|0|0|0| © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Product data sheet** **Rev. 05 — 15 September 2008** **7 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** ## **6.2.5** with ‘1’), the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin is enabled as an output. At reset, the device's ports are inputs. **Table 11.** |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**|**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**| |---|---|---|---|---|---|---|---|---| |**Symbol**|C0.7|C0.6|C0.5|C0.4|C0.3|C0.2|C0.1|C0.0| |**Default**|1|1|1|1|1|1|1|1| |**Table 12.**<br>**Confguration port 1 register**||||||||| |**Bit**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||| |**Symbol**|C1.7|C1.6|C1.5|C1.4|C1.3|C1.2|C1.1|C1.0| |**Default**|1|1|1|1|1|1|1|1| ## **6.3 Power-on reset** When power is applied to VDD, an internal power-on reset holds the PCA9535/PCA9535C in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9535/PCA9535C registers and SMBus state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the operating voltage. ## **6.4 I/O port** high impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. In the case of PCA9535C, FET Q1 has been removed and the open-drain FET Q2 will function the same as PCA9535. on the state of the Output Port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance path that exists between the pin and either VDD or VSS. © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Product data sheet** **Rev. 05 — 15 September 2008** **8 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** **==> picture [370 x 290] intentionally omitted <==** **----- Start of picture text -----**<br> data from output port<br>shift register register data<br>configuration<br>register (1) VDD<br>data from D Q Q1<br>shift register<br>FF<br>write<br>D Q<br>configuration CK Q<br>pulse FF<br>I/O pin<br>write pulse CK Q2<br>output port input port VSS<br>register register<br>D Q<br>input port<br>FF register data<br>read pulse CK<br>to INT<br>polarity inversion<br>register<br>data from<br>D Q polarity<br>shift register inversion<br>FF register data<br>write polarity<br>CK<br>pulse<br>002aac218<br>At power-on reset, all registers return to default values.<br>**----- End of picture text -----**<br> **==> picture [352 x 18] intentionally omitted <==** **----- Start of picture text -----**<br> (1) PCA9535C I/Os are open-drain only. The portion of the PCA9535 schematic marked inside the<br>dotted line box is not in PCA9535C.<br>**----- End of picture text -----**<br> **==> picture [157 x 14] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 7. Simplified schematic of I/Os<br>**----- End of picture text -----**<br> ## **6.5 Bus transactions** ## **6.5.1 Writing to the port registers** Data is transmitted to the PCA9535/PCA9535C by sending the device address and setting the least significant bit to a logic 0 (see Figure 6 “PCA9535; PCA9535C device address”). The command byte is sent after the address and determines which register will receive the data following the command byte. register pairs. The four pairs are Input Ports, Output Ports, Polarity Inversion Ports, and Configuration Ports. After sending data to one register, the next data byte will be sent to the other register in the pair (see Figure 8 and Figure 9). For example, if the first byte is sent to Output Port 1 (register 3), then the next byte will be stored in Output Port 0 (register 2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register may be updated independently of the other registers. © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Rev. 05 — 15 September 2008** **Product data sheet** **9 of 31** **==> picture [534 x 176] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>slave address command byte data to port 0 data to port 1<br>SDA S 0 1 0 0 A2 A1 A0 0 A 0 0 0 0 0 0 1 0 A 0.7 DATA 0 0.0 A 1.7 DATA 1 1.0 A P<br>START condition R/W acknowledge acknowledge acknowledge STOP<br>from slave from slave from slave condition<br>write to port<br>tv(Q)<br>data out<br>from port 0<br>tv(Q)<br>data out<br>from port 1 DATA VALID<br>002aac220<br>**----- End of picture text -----**<br> **Fig 8. Write to Output Port registers** **==> picture [512 x 90] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>data to register data to register<br>slave address command byte<br>MSB LSB MSB LSB<br>SDA S 0 1 0 0 A2 A1 A0 0 A 0 0 0 0 0 1 1 0 A DATA 0 A DATA 1 A P<br>START condition R/W acknowledge acknowledge acknowledge STOP<br>from slave from slave from slave condition<br>002aac221<br>**----- End of picture text -----**<br> **Fig 9.** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** ## **6.5.2 Reading the port registers** PCA9535/PCA9535C address with the least significant bit set to a logic 0 (see Figure 6 “PCA9535; PCA9535C device address”). The command byte is sent after the address and determines which register will be accessed. After a restart, the device address is sent again, but this time the least significant bit is set to a logic 1. Data from the register defined by the command byte will then be sent by the PCA9535/PCA9535C (see Figure 10, Figure 11 and Figure 12). Data is clocked into the register on the falling edge of the acknowledge clock pulse. After the first byte is read, additional bytes may be read but the data will now reflect the information in the other register in the pair. For example, if you read Input Port 1, then the next byte read would be Input Port 0. There is no limitation on the number of data bytes received in one read transmission but the final byte received, the bus master must not acknowledge the data. **==> picture [433 x 165] intentionally omitted <==** **----- Start of picture text -----**<br> slave address<br>SDA S 0 1 0 0 A2 A1 A0 0 A COMMAND BYTE A (cont.)<br>START condition R/W acknowledge<br>acknowledge from slave<br>from slave<br>data from lower or data from upper or<br>upper byte of register lower byte of register<br>slave address<br>MSB LSB MSB LSB<br>(cont.) S 0 1 0 0 A2 A1 A0 1 A DATA (first byte) A DATA (last byte) NA P<br>(repeated) R/W acknowledge no acknowledge STOP<br>START condition acknowledge from master from master condition<br>from slave<br>at this moment master-transmitter becomes master-receiver<br>and slave-receiver becomes slave-transmitter<br>002aac222<br>**----- End of picture text -----**<br> **Remark:** Transfer can be stopped at any time by a STOP condition. **Fig 10. Read from register** © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Product data sheet** **Rev. 05 — 15 September 2008** **11 of 31** **==> picture [619 x 228] intentionally omitted <==** **----- Start of picture text -----**<br> data into port 0<br>data into port 1<br>INT<br>tv(INT_N) trst(INT_N)<br>SCL 1 2 3 4 5 6 7 8 9<br>R/W STOP condition<br>slave address I0.x I1.x I0.x I1.x<br>SDA S 0 1 0 0 A2 A1 A0 1 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 1 P<br>START condition acknowledge acknowledge acknowledge acknowledge non acknowledge<br>from slave from master from master from master from master<br>read from port 0<br>read from port 1<br>002aac223<br>**----- End of picture text -----**<br> **Remark:** Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to ‘00’ (read Input Port register). **Fig 11. Read Input Port register, scenario 1** **==> picture [619 x 224] intentionally omitted <==** **----- Start of picture text -----**<br> data into port 0 DATA 00 DATA 01 DATA 02 DATA 03<br>th(D) tsu(D)<br>data into port 1 DATA 10 DATA 11 DATA 12<br>th(D) tsu(D)<br>INT<br>tv(INT_N) trst(INT_N)<br>SCL 1 2 3 4 5 6 7 8 9<br>R/W STOP condition<br>slave address I0.x I1.x I0.x I1.x<br>SDA S 0 1 0 0 A2 A1 A0 1 A DATA 00 A DATA 10 A DATA 03 A DATA 12 1 P<br>START condition acknowledge acknowledge acknowledge acknowledge non acknowledge<br>from slave from master from master from master from master<br>read from port 0<br>read from port 1<br>002aac224<br>**----- End of picture text -----**<br> **Remark:** Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to ‘00’ (read Input Port register). **Fig 12. Read Input Port register, scenario 2** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** ## **6.5.3 Interrupt output** The open-drain interrupt output is activated when one of the port pins change state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the Input Port register is read (see Figure 11). A pin configured as an output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt caused by Port 0 will not be cleared by a read of Port 1 or the other way around. **Remark:** Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. ## **7. Characteristics of the I[2] C-bus** The I[2] C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. ## **7.1 Bit transfer** One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 13). **==> picture [313 x 110] intentionally omitted <==** **----- Start of picture text -----**<br> SDA<br>SCL<br>data line change<br>stable; of data<br>data valid allowed mba607<br>Fig 13. Bit transfer<br>**----- End of picture text -----**<br> ## **7.1.1 START and STOP conditions** Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 14). **==> picture [362 x 106] intentionally omitted <==** **----- Start of picture text -----**<br> SDA SDA<br>SCL SCL<br>S P<br>START condition STOP condition<br>mba608<br>Fig 14. Definition of START and STOP conditions<br>**----- End of picture text -----**<br> © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Product data sheet** **Rev. 05 — 15 September 2008** **14 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** ## **7.2** A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 15). **==> picture [433 x 109] intentionally omitted <==** **----- Start of picture text -----**<br> SDA<br>SCL<br>MASTER SLAVE SLAVE MASTER MASTER I [2] C-BUS<br>TRANSMITTER/ RECEIVER TRANSMITTER/ TRANSMITTER TRANSMITTER/ MULTIPLEXER<br>RECEIVER RECEIVER RECEIVER<br>SLAVE<br>002aaa966<br>**----- End of picture text -----**<br> **Fig 15.** ## **7.3 Acknowledge** The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold time must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. **==> picture [297 x 129] intentionally omitted <==** **----- Start of picture text -----**<br> data output<br>by transmitter<br>not acknowledge<br>data output<br>by receiver<br>acknowledge<br>SCL from master<br>1 2 8 9<br>S<br>clock pulse for<br>START acknowledgement<br>condition 002aaa987<br>**----- End of picture text -----**<br> **Fig 16. Acknowledgement on the I[2] C-bus** © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Product data sheet** **Rev. 05 — 15 September 2008** **15 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** ## **8. Application design-in information** **==> picture [439 x 288] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>(5 V) SUB-SYSTEM 1<br>VDD 10 kΩ 10 kΩ 10 kΩ VDD 2 kΩ 100 k(×3) Ω (e.g., temp sensor)<br>INT<br>MASTER PCA9535<br>CONTROLLER<br>SCL SCL IO0_0<br>SUB-SYSTEM 2<br>SDA SDA IO0_1 (e.g., counter)<br>IO0_2 RESET<br>INT INT<br>IO0_3<br>A<br>GND<br>IO0_4 ENABLE controlled<br>switch<br>IO0_5 (e.g., CBT device)<br>B<br>IO0_6<br>IO0_7 SUB-SYSTEM 3<br>IO1_0 (e.g., alarm system)<br>IO1_1 10 DIGIT<br>IO1_2 NUMERIC ALARM<br>IO1_3 KEYPAD<br>IO1_4<br>A2 IO1_5 VDD<br>A1 IO1_6<br>A0 IO1_7<br>VSS<br>002aac225<br>**----- End of picture text -----**<br> IO0_0, IO0_2, IO0_3 configured as outputs. IO0_1, IO0_4, IO0_5 configured as inputs. IO0_6, IO0_7, and IO1_0 to IO1_7 configured as inputs. **Fig 17. Typical application** © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Product data sheet** **Rev. 05 — 15 September 2008** **16 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** ## **8.1 Minimizing IDD when the I/Os are used to control LEDs** When the PCA9535 I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 17. Since the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower than VDD. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 18 shows a high value resistor in parallel with the LED. Figure 19 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VDD and prevents additional supply current consumption when the LED is off. This concern does not occur in the case of PCA9535C because the I/O pins are open-drain. **==> picture [397 x 169] intentionally omitted <==** **----- Start of picture text -----**<br> 3.3 V 5 V<br>VDD<br>VDD LED 100 kΩ VDD LED<br>LEDn LEDn<br>002aac189 002aac190<br>Fig 18. High value resistor in parallel with Fig 19. Device supplied by a lower voltage<br>the LED<br>**----- End of picture text -----**<br> ## **9. Limiting values** ## **Table 13. Limiting values** In accordance with the Absolute Maximum Rating System (IEC 60134). |**Symbol**|**Parameter**|**Conditions**|**Min**|**Max**|**Unit**| |---|---|---|---|---|---| |VDD|supply voltage||−0.5|+6.0|V| |VI/O|voltage on an input/output pin||VSS−0.5|6|V| |IO|output current|on an I/O pin|-|±50|mA| |II|input current||-|±20|mA| |IDD|supply current||-|160|mA| |ISS|ground supply current||-|200|mA| |Ptot|total power dissipation||-|200|mW| |Tstg|storage temperature||−65|+150|°C| |Tamb|ambient temperature|operating|−40|+85|°C| © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Product data sheet** **Rev. 05 — 15 September 2008** **17 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** ## **10. Static characteristics** ## **Table 14. Static characteristics** VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 ° |**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**| |---|---| |**Supplies**|| |VDD<br>supply voltage|2.3<br>-<br>5.5<br>V| |IDD<br>supply current|Operating mode; VDD= 5.5 V;<br>no load; fSCL= 100 kHz; I/O = inputs<br>-<br>135<br>200<br>µA| |Istb<br>standby current|Standby mode; VDD= 5.5 V; no load;<br>VI= VSS; fSCL= 0 kHz; I/O = inputs<br>-<br>0.25<br>1<br>µA| ||Standby mode; VDD= 5.5 V; no load;<br>VI= VDD; fSCL= 0 kHz; I/O = inputs<br>-<br>0.25<br>1<br>µA| |VPOR<br>power-on reset voltage<br>[1]|no load; VI= VDDor VSS<br>-<br>1.5<br>1.65<br>V| |**Input SCL; input/output SDA**|| |VIL<br>LOW-level input voltage|−0.5<br>-<br>+0.3VDD V| |VIH<br>HIGH-level input voltage|0.7VDD<br>-<br>5.5<br>V| |IOL<br>LOW-level output current|VOL= 0.4 V<br>3<br>-<br>-<br>mA| |IL<br>leakage current|VI= VDD= VSS<br>−1<br>-<br>+1<br>µA| |Ci<br>input capacitance|VI= VSS<br>-<br>6<br>10<br>pF| |**I/Os**|| |VIL<br>LOW-level input voltage|−0.5<br>-<br>+0.3VDD V| |VIH<br>HIGH-level input voltage|0.7VDD<br>-<br>5.5<br>V| |IOL<br>LOW-level output current|VDD= 2.3 V to 5.5 V; VOL= 0.5 V<br>[2] 8<br>10<br>-<br>mA| ||VDD= 2.3 V to 5.5 V; VOL= 0.7 V<br>[2] 10<br>14<br>-<br>mA| |VOH<br>HIGH-level output voltage|PCA9535 only| ||IOH=−8 mA; VDD= 2.3 V<br>[3] 1.8<br>-<br>-<br>V| ||IOH=−10 mA; VDD= 2.3 V<br>[3] 1.7<br>-<br>-<br>V| ||IOH=−8 mA; VDD= 3.0 V<br>[3] 2.6<br>-<br>-<br>V| ||IOH=−10 mA; VDD= 3.0 V<br>[3] 2.5<br>-<br>-<br>V| ||IOH=−8 mA; VDD= 4.75 V<br>[3] 4.1<br>-<br>-<br>V| ||IOH=−10 mA; VDD= 4.75 V<br>[3] 4.0<br>-<br>-<br>V| |ILIH<br>HIGH-level input leakage current|VDD= 5.5 V; VI= VDD<br>-<br>-<br>1<br>µA| |ILIL<br>LOW-level input leakage current|VDD= 5.5 V; VI= VSS<br>-<br>-<br>−1<br>µA| |Ci<br>input capacitance|-<br>3.7<br>5<br>pF| |Co<br>output capacitance|-<br>3.7<br>5<br>pF| |**Interrupt**<br>**INT**|| |IOL<br>LOW-level output current|VOL= 0.4 V<br>3<br>-<br>-<br>mA| |**Select inputs A0, A1, A2**|| |VIL<br>LOW-level input voltage|−0.5<br>-<br>+0.3VDD V| |VIH<br>HIGH-level input voltage|0.7VDD<br>-<br>5.5<br>V| |ILI<br>input leakage current|−1<br>-<br>+1<br>µA| [1] VDD must be lowered to 0.2 V for at least 5 µs in order to reset part. © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Rev. 05 — 15 September 2008** **Product data sheet** **18 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** - [2] Each I/O must be externally limited to a maximum of 25 mA and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be limited to a maximum current of 100 mA for a device total of 200 mA. - [3] The total current sourced by all I/Os must be limited to 160 mA. PCA9535C does not source current and does not have the VOH specification. ## **11. Dynamic characteristics** ## **Table 15. Dynamic characteristics** |**Symbol**<br>**Parameter**<br>**Conditions**|**Standard-mode**<br>**I2C-bus**|**Standard-mode**<br>**I2C-bus**|**Fast-mode I2C-bus**|**Fast-mode I2C-bus**|**Unit**| |---|---|---|---|---|---| ||**Min**|**Max**|**Min**|**Max**|| |fSCL<br>SCL clock frequency|0<br>100<br>0<br>400<br>kHz||||| |tBUF<br>bus free time between a STOP and<br>START condition|4.7<br>-<br>1.3<br>-<br>µs||||| |tHD;STA<br>hold time (repeated) START condition|4.0<br>-<br>0.6<br>-<br>µs||||| |tSU;STA<br>set-up time for a repeated START<br>condition|4.7<br>-<br>0.6<br>-<br>µs||||| |tSU;STO<br>set-up time for STOP condition|4.0<br>-<br>0.6<br>-<br>µs||||| |tVD;ACK<br>data valid acknowledge time<br>[1]|0.3<br>3.45<br>0.1<br>0.9<br>µs||||| |tHD;DAT<br>data hold time|0<br>-<br>0<br>-<br>ns||||| |tVD;DAT<br>data valid time<br>[2]|300<br>-<br>50<br>-<br>ns||||| |tSU;DAT<br>data set-up time|250<br>-<br>100<br>-<br>ns||||| |tLOW<br>LOW period of the SCL clock|4.7<br>-<br>1.3<br>-<br>µs||||| |tHIGH<br>HIGH period of the SCL clock|4.0<br>-<br>0.6<br>-<br>µs||||| |tf<br>fall time of both SDA and SCL signals|-<br>300<br>20 + 0.1C~~b~~<br>[3]<br>300<br>ns||||| |tr<br>rise time of both SDA and SCL signals|-<br>1000<br>20 + 0.1C~~b~~<br>[3]<br>300<br>ns||||| |tSP<br>pulse width of spikes that must be<br>suppressed by the input flter|-<br>50<br>-<br>50<br>ns||||| |**Port timing**|||||| |tv(Q)<br>data output valid time<br>[4]|-<br>200<br>-<br>200<br>ns||||| |tsu(D)<br>data input set-up time|150<br>-<br>150<br>-<br>ns||||| |th(D)<br>data input hold time|1<br>-<br>1<br>-<br>µs||||| |**Interrupt timing**|||||| |tv(INT_N)<br>valid time on pin<br>INT|-<br>4<br>-<br>4<br>µs||||| |trst(INT_N)<br>reset time on pin<br>INT|-<br>4<br>-<br>4<br>µs||||| - [1] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW. - [2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. - [3] Cb = total capacitance of one bus line in pF. - [4] tv(Q) measured from 0.7VDD on SCL to 50 % I/O output (PCA9535). For PCA9535C, use load circuit shown in Figure 24 and measure from 0.7VDD on SCL to 30 % I/O output. © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Rev. 05 — 15 September 2008** **Product data sheet** **19 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** **==> picture [450 x 135] intentionally omitted <==** **----- Start of picture text -----**<br> SDA<br>tBUF tr tf tHD;STA tSP<br>tLOW<br>SCL<br>tHD;STA tSU;STA tSU;STO<br>P S tHD;DAT tHIGH tSU;DAT Sr P<br>002aaa986<br>**----- End of picture text -----**<br> **==> picture [182 x 14] intentionally omitted <==** **----- Start of picture text -----**<br> Fig 20. Definition of timing on the I [2] C-bus<br>**----- End of picture text -----**<br> **==> picture [418 x 195] intentionally omitted <==** **----- Start of picture text -----**<br> START bit 7 STOP<br>protocol condition MSB bit 6 bit 0 acknowledge condition<br>(A6) (R/W) (A)<br>(S) (A7) (P)<br>tSU;STA tLOW tHIGH 1/fSCL<br>SCL<br>tBUF tf<br>tr<br>SDA<br>tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO<br>002aab175<br>Rise and fall times refer to VIL and VIH.<br>Fig 21. I [2] C-bus timing diagram<br>**----- End of picture text -----**<br> **==> picture [382 x 116] intentionally omitted <==** **----- Start of picture text -----**<br> SCL SCL<br>tv(Q) tv(Q)<br>IOn IOn<br>002aad327<br>Fig 22. tv(Q) timing<br>**----- End of picture text -----**<br> © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Product data sheet** **Rev. 05 — 15 September 2008** **20 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** ## **12. Test information** **==> picture [213 x 88] intentionally omitted <==** **----- Start of picture text -----**<br> VDD<br>open<br>GND<br>VDD RL<br>500 Ω<br>VI VO<br>PULSE<br>DUT<br>GENERATOR<br>RT CL<br>50 pF<br>002aab284<br>**----- End of picture text -----**<br> **==> picture [64 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> RL = load resistor.<br>**----- End of picture text -----**<br> **==> picture [206 x 9] intentionally omitted <==** **----- Start of picture text -----**<br> CL = load capacitance includes jig and probe capacitance.<br>**----- End of picture text -----**<br> RT = termination resistance should be equal to the output impedance of Zo of the pulse generators. **Fig 23. Test circuitry for switching times** **==> picture [298 x 84] intentionally omitted <==** **----- Start of picture text -----**<br> RL S1 2VDD<br>from output under test open<br>500 Ω GND<br>CL RL<br>50 pF 500 Ω<br>002aac226<br>Fig 24. Load circuit<br>**----- End of picture text -----**<br> © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Product data sheet** **Rev. 05 — 15 September 2008** **21 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** ## **13. Package outline** ## **SO24: plastic small outline package; 24 leads; body width 7.5 mm** ## **SOT137-1** **==> picture [478 x 570] intentionally omitted <==** **----- Start of picture text -----**<br> D E A<br>X<br>c<br>y HE v M A<br>Z<br>24 13<br>Q<br>A2 A<br>A1 (A )3<br>pin 1 index<br>θ<br>L p<br>L<br>1 12 detail X<br>e w M<br>b p<br>0 5 10 mm<br>scale<br>DIMENSIONS (inch dimensions are derived from the original mm dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(1)] e HE L Lp Q v w y Z (1) θ<br>0.3 2.45 0.49 0.32 15.6 7.6 10.65 1.1 1.1 0.9<br>mm 2.65 0.1 2.25 0.25 0.36 0.23 15.2 7.4 1.27 10.00 1.4 0.4 1.0 0.25 0.25 0.1 0.4 8o<br>0.012 0.096 0.019 0.013 0.61 0.30 0.419 0.043 0.043 0.035 0o<br>inches 0.1 0.01 0.05 0.055 0.01 0.01 0.004<br>0.004 0.089 0.014 0.009 0.60 0.29 0.394 0.016 0.039 0.016<br>Note<br>1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>99-12-27<br> SOT137-1 075E05 MS-013<br>03-02-19<br>**----- End of picture text -----**<br> **Fig 25. Package outline SOT137-1 (SO24)** © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Rev. 05 — 15 September 2008** **Product data sheet** **22 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** **SOT355-1** ## **TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm** **==> picture [478 x 570] intentionally omitted <==** **----- Start of picture text -----**<br> D E A<br>X<br>c<br>y HE v M A<br>Z<br>24 13<br>Q<br>A2 (A )3 A<br>pin 1 index A1<br>θ<br>L p<br>L<br>1 12<br>detail X<br>w M<br>e b p<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(2)] e HE L Lp Q v w y Z (1) θ<br>0.15 0.95 0.30 0.2 7.9 4.5 6.6 0.75 0.4 0.5 8o<br>mm 1.1 0.05 0.80 0.25 0.19 0.1 7.7 4.3 0.65 6.2 1 0.50 0.3 0.2 0.13 0.1 0.2 0 o<br>Notes<br>1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.<br>2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>99-12-27<br> SOT355-1 MO-153<br>03-02-19<br>**----- End of picture text -----**<br> © NXP B.V. 2008. All rights reserved. **Fig 26. Package outline SOT355-1 (TSSOP24)** PCA9535_PCA9535C_5 **Product data sheet** **Rev. 05 — 15 September 2008** **23 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** **HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm** **==> picture [43 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> SOT616-1<br>**----- End of picture text -----**<br> **==> picture [478 x 559] intentionally omitted <==** **----- Start of picture text -----**<br> D B A<br>terminal 1<br>index area<br>A<br>A1<br>E c<br>detail X<br>e1 C<br>1/2 e<br>e b v M C A B y1 C y<br>7 12 w M C<br>L<br>13<br>6<br>e<br>Eh e2<br>1/2 e<br>1<br>18<br>terminal 1<br>index area 24 19<br>Dh X<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>A [(1)]<br>UNIT max. A1 b c D [(1)] Dh E [(1)] Eh e e1 e2 L v w y y1<br>0.05 0.30 4.1 2.25 4.1 2.25 0.5<br>mm 1 0.2 0.5 2.5 2.5 0.1 0.05 0.05 0.1<br>0.00 0.18 3.9 1.95 3.9 1.95 0.3<br>Note<br>1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>01-08-08<br> SOT616-1 - - - MO-220 - - -<br>02-10-22<br>**----- End of picture text -----**<br> © NXP B.V. 2008. All rights reserved. **Fig 27. Package outline SOT616-1 (HVQFN24)** PCA9535_PCA9535C_5 **Product data sheet** **Rev. 05 — 15 September 2008** **24 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** **HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.75 mm** **SOT994-1** **==> picture [481 x 555] intentionally omitted <==** **----- Start of picture text -----**<br> D B A<br>terminal 1<br>index area<br>E A<br>A1<br>c<br>detail X<br>e1<br>1/2 e<br>C<br>∅ v M C A B<br>e b<br>∅ w M C y1 C y<br>7 12<br>L<br>13<br>6<br>e<br>Eh e2<br>1/2 e<br>1<br>18<br>terminal 1<br>index area 24 19<br>X<br>Dh<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>A [(1)]<br>UNIT max A1 b c D [(1)] Dh E [(1)] Eh e e1 e2 L v w y y1<br>0.05 0.30 4.1 2.25 4.1 2.25 0.5<br>mm 0.8 0.2 0.5 2.5 2.5 0.1 0.05 0.05 0.1<br>0.00 0.18 3.9 1.95 3.9 1.95 0.3<br>Note<br>1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>07-02-07<br>SOT994-1 - - - MO-220 - - -<br>07-03-03<br>**----- End of picture text -----**<br> **Fig 28. Package outline SOT994-1 (HWQFN24)** © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Rev. 05 — 15 September 2008** **Product data sheet** **25 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** ## **14. Handling information** Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits. ## **15. Soldering of SMD packages** This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. ## **15.1 Introduction to soldering** Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. ## **15.2** Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: - Through-hole components - Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. - - Package footprints, including solder thieves and orientation - The moisture sensitivity level of the packages - Package placement - Inspection and repair - Lead-free soldering versus SnPb soldering ## **15.3 Wave soldering** Key characteristics in wave soldering are: © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Rev. 05 — 15 September 2008** **Product data sheet** **26 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** - transport, the solder wave parameters, and the time during which components are exposed to the wave - ## **15.4** - higher minimum peak temperatures (see Figure 29) than a SnPb process, thus reducing the process window - Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board - heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 16 and 17 ## **Table 16. SnPb eutectic process (from J-STD-020C)** |**Package thickness (mm)**|**Package refow temperature (**°**C)**|**Package refow temperature (**°**C)**| |---|---|---| ||**Volume (mm3)**|| ||**< 350**|≥**350**| |< 2.5|235<br>220|| |≥2.5|220<br>220|| ## **Table 17. Lead-free process (from J-STD-020C)** |**Package thickness (mm)**|**Package refow temperature (**°**C)**|**Package refow temperature (**°**C)**|**Package refow temperature (**°**C)**| |---|---|---|---| ||**Volume (mm3)**||| ||**< 350**|**350 to 2000**|**> 2000**| |< 1.6|260<br>260<br>260||| |1.6 to 2.5|260<br>250<br>245||| |> 2.5|250<br>245<br>245||| Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. soldering, see Figure 29. © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Rev. 05 — 15 September 2008** **Product data sheet** **27 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** ## **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** **==> picture [352 x 225] intentionally omitted <==** **----- Start of picture text -----**<br> maximum peak temperature<br>= MSL limit, damage level<br>temperature<br>minimum peak temperature<br>= minimum soldering temperature<br>peak<br> temperature<br>time<br>001aac844<br>MSL: Moisture Sensitivity Level<br>Fig 29. Temperature profiles for large and small components<br>**----- End of picture text -----**<br> “Surface mount reflow soldering description”. ## **16. Abbreviations** **Table 18. Abbreviations** |**Acronym**|**Description**| |---|---| |ACPI|Advanced Confguration and Power Interface| |CBT|Cross Bar Technology| |CDM|Charged-Device Model| |CMOS|Complementary Metal-Oxide Semiconductor| |DUT|Device Under Test| |ESD|ElectroStatic Discharge| |FET|Field-Effect Transistor| |GPIO|General Purpose Input/Output| |HBM|Human Body Model| |I/O|Input/Output| |I2C-bus|Inter-Integrated Circuit bus| |IC|Integrated Circuit| |LED|Light Emitting Diode| |MM|Machine Model| |PCB|Printed-Circuit Board| |SMBus|System Management Bus| © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Product data sheet** **Rev. 05 — 15 September 2008** **28 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** ## **17. Revision history** **Table 19. Revision history** |**Document ID**|**Release date**|**Release date**|**Release date**|**Data sheet status**|**Change notice**|**Supersedes**| |---|---|---|---|---|---|---| |PCA9535_PCA9535C_5|20080915|||Product data sheet|-|PCA9535_PCA9535C_4| |Modifcations:|**•**<br>T<br>ab<br>le|3|“Pin|descr<br>iption”:<br>T<br>ab<br>le<br>note|[2]re-written; added its reference at port 1 input/output|| |PCA9535_PCA9535C_4|20080731|||Product data sheet|-|PCA9535_PCA9535C_3| |PCA9535_PCA9535C_3|20071004|||Product data sheet|-|PCA9535_2| |PCA9535_2|20040930|||Product data sheet|-|PCA9535_1| |(9397 750 12896)||||||| |PCA9535_1|20030627|||Product data|853-2430 30019 of|-| |(9397 750 11681)|||||11 June 2003|| © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Product data sheet** **Rev. 05 — 15 September 2008** **29 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** ## **18. Legal information** ## **18.1 Data sheet status** |**Document statu**|**s**<br>**[1]**<br>**[2]**<br>**Product status**<br>**[3]**<br>**Defnition**| |---|---| |Objective [short] data sheet<br>Development<br>This document contains data from the objective specifcation for product development.|| |Preliminary [short] data sheet<br>Qualifcation<br>This document contains data from the preliminary specifcation.|| |Product [short] data sheet<br>Production<br>This document contains the product specifcation.|| [1] Please consult the most recently issued document before initiating or completing a design. [2] [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. ## **18.2** **Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. ## **18.3 Disclaimers** **General —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. **Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. **Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. **Limiting values —** the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. **Terms and conditions of sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. **No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. ## **18.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. **I[2] C-bus —** logo is a trademark of NXP B.V. ## **19. Contact information** For more information, please visit: **http://www.nxp.com** **salesaddresses@nxp.com** © NXP B.V. 2008. All rights reserved. PCA9535_PCA9535C_5 **Rev. 05 — 15 September 2008** **Product data sheet** **30 of 31** **PCA9535; PCA9535C** **NXP Semiconductors** **16-bit I[2] C-bus and SMBus, low power I/O port with interrupt** ## **20. Contents** |**1**<br>**2**|**General description . . . . . . . . . . . . . . . . . . . . . . 1**<br>**Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1**|18.1<br>18.2|Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30<br>Defnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 30| |---|---|---|---| |**3**<br>3.1<br>**4**<br>**5**|**Ordering information . . . . . . . . . . . . . . . . . . . . . 2**<br>Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2<br>**Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3**<br>**Pinning information. . . . . . . . . . . . . . . . . . . . . . 4**|18.3<br>18.4<br>**19**<br>**20**|Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 30<br>Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 30<br>**Contact information . . . . . . . . . . . . . . . . . . . . 30**<br>**Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31**| |5.1|Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4||| |5.2|Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5||| |**6**|**Functional description . . . . . . . . . . . . . . . . . . . 6**||| |6.1|Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6||| |6.2|Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6||| |6.2.1|Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 6||| |6.2.2|Registers 0 and 1: Input port registers . . . . . . . 7||| |6.2.3|Registers 2 and 3: Output port registers. . . . . . 7||| |6.2.4<br>6.2.5|Registers 4 and 5: Polarity Inversion registers . 7<br>Registers 6 and 7: Confguration registers . . . . 8||| |6.3|Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8||| |6.4|I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8||| |6.5|Bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 9||| |6.5.1|Writing to the port registers . . . . . . . . . . . . . . . 9||| |6.5.2|Reading the port registers . . . . . . . . . . . . . . . 11||| |6.5.3|Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 14||| |**7**|**Characteristics of the I2C-bus. . . . . . . . . . . . . 14**||| |7.1|Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 14||| |7.1.1|START and STOP conditions . . . . . . . . . . . . . 14||| |7.2|System confguration . . . . . . . . . . . . . . . . . . . 15||| |7.3|Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 15||| |**8**|**Application design-in information . . . . . . . . . 16**||| |8.1|Minimizing IDDwhen the I/Os are used to||| ||control LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . 17||| |**9**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17**||| |**10**|**Static characteristics. . . . . . . . . . . . . . . . . . . . 18**||| |**11**|**Dynamic characteristics . . . . . . . . . . . . . . . . . 19**||| |**12**|**Test information. . . . . . . . . . . . . . . . . . . . . . . . 21**||| |**13**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22**||| |**14**|**Handling information. . . . . . . . . . . . . . . . . . . . 26**||| |**15**|**Soldering of SMD packages . . . . . . . . . . . . . . 26**||| |15.1<br>15.2|Introduction to soldering . . . . . . . . . . . . . . . . . 26<br>Wave and refow soldering . . . . . . . . . . . . . . . 26||| |15.3<br>15.4|Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 26<br>Refow soldering . . . . . . . . . . . . . . . . . . . . . . . 27||| |**16**|**Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 28**||| |**17**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . . 29**||| |**18**|**Legal information. . . . . . . . . . . . . . . . . . . . . . . 30**||| **==> picture [151 x 121] intentionally omitted <==** Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. **© NXP B.V. 2008.** **All rights reserved.** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 15 September 2008 Document identifier: PCA9535_PCA9535C_5**
Updated at February 9, 2023
NXP Semiconductors is a global leader in secure connectivity solutions, driving innovation across the automotive, industrial, IoT, mobile, and communications infrastructure markets. By developing advanced, purpose-built technologies, NXP enables devices to sense, think, connect, and act intelligently, delivering rigorously tested components that make the connected world safer and more efficient. Within the semiconductor space, NXP is highly regarded for its extensive range of high-performance integrated circuits and discrete devices. The brand's portfolio excels in drivers and interfaces, featuring a comprehensive selection of I/O expanders designed to streamline complex system architectures. For demanding high-frequency and wireless applications, NXP provides industry-leading RF FETs and RF/PIN diodes engineered to deliver exceptional signal integrity, efficiency, and reliability. The NXP product lineup further extends to essential discrete components, including versatile bipolar transistors, JFETs, and small signal diodes optimized for precision switching and amplification. Additionally, the portfolio supports advanced automation and smart applications with precision IC sensors, such as MEMS accelerometers, alongside specialized power management solutions like AC/DC LED driver ICs and single MOSFETs for cutting-edge electronics design.
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