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PCA9534BS,118
I/O Expander, 8bit, 400 kHz, I2C, SMBus, 2.3 V, 5.5 V, HVQFN
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- Manufacturer: NXP
- Product type: I/O Expanders
- No. of Pins: 16Pins
- No. of I/O's: 8I/O's
- Bus Frequency: 400kHz
- IC Interface Type: I2C, SMBus
- Chip Configuration: 8bit
- Supply Voltage Max: 5.5V
- Supply Voltage Min: 2.3V
- Interface Case Style: HVQFN
| Delivery and price | |
|---|---|
| Units per pack | 100 |
| Price | 1.5 € |
| Current stock | 1000+ |
| Lead time | 7 days |
Datasheet
**==> picture [35 x 38] intentionally omitted <==** ## **PCA9534** ## **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** **Rev. 03 — 6 November 2006 Product data sheet** ## **1. General description** The PCA9534 is a 16-pin CMOS device that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion for I[2] C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I[2] C-bus I/O expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc. Input register, 8-bit Output register and an 8-bit Polarity Inversion register (active HIGH or active LOW operation). The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system master. Although pin-to-pin and I[2] C-bus address compatible with the PCF8574 series, software changes are required due to the enhancements and are discussed in Application Note AN469. The PCA9534 is identical to the PCA9554 except for the removal of the internal I/O pull-up resistor which greatly reduces power consumption when the I/Os are held LOW. The PCA9534 open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. Three hardware pins (A0, A1, A2) vary the fixed I[2] C-bus address and allow up to eight devices to share the same I[2] C-bus/SMBus. ## **2. Features** I 8-bit I[2] C-bus GPIO - I Operating power supply voltage range of 2.3 V to 5.5 V - I 5 V tolerant I/Os - I Polarity Inversion register - I Active LOW interrupt output - I Low standby current - I - I No glitch on power-up - I Internal power-on reset **==> picture [211 x 101] intentionally omitted <==** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** - I 8 I/O pins which default to 8 inputs - I 0 Hz to 400 kHz clock frequency - I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 - I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA - I Offered in four different packages: SO16, TSSOP16, and HVQFN16 (4 × 4 × 0.85 mm and 3 × 3 × 0.85 mm versions) ## **3. Ordering information** **Table 1. Ordering information** Tamb = −40 °C to +85 °C. |**Type number**|**Topside**<br>**mark**|**Package**|**Package**|**Package**| |---|---|---|---|---| |||**Name**|**Description**|**Version**| |PCA9534D<br>PCA9534D||SO16<br>plastic small outline package; 16 leads; body width 7.5 mm<br>SOT162-1||| |PCA9534PW<br>PCA9534||TSSOP16<br>plastic thin shrink small outline package; 16 leads;<br>body width 4.4 mm<br>SOT403-1||| |PCA9534BS<br>9534||HVQFN16<br>plastic thermal enhanced very thin quad fat package;<br>no leads; 16 terminals; body 4×4×0.85 mm<br>SOT629-1||| |PCA9534BS3<br>P34||HVQFN16<br>plastic thermal enhanced very thin quad fat package;<br>no leads; 16 terminals; body 3×3×0.85 mm<br>SOT758-1||| ## **4. Block diagram** **==> picture [369 x 227] intentionally omitted <==** **----- Start of picture text -----**<br> PCA9534<br>A0<br>IO0<br>A1<br>A2 IO1<br>8-bit IO2<br>SDASCL FILTERINPUT I [2] C-BUS/SMBus OUTPUTINPUT/ IO3<br>CONTROL PORTS IO4<br>write pulse IO5<br>read pulse IO6<br>VDD POWER-ON IO7<br>RESET<br>VSS VDD<br>LP INT<br>FILTER<br>002aac469<br>All I/Os are set to inputs at reset.<br>Fig 1. Block diagram of PCA9534<br>**----- End of picture text -----**<br> © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **2 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** ## **5. Pinning information** ## **5.1 Pinning** **==> picture [397 x 353] intentionally omitted <==** **----- Start of picture text -----**<br> A0 1 16 VDD A0 1 16 VDD<br>A1 2 15 SDA A1 2 15 SDA<br>A2 3 14 SCL A2 3 14 SCL<br>IO0 4 13 INT IO0 4 13 INT<br>PCA9534D PCA9534PW<br>IO1 5 12 IO7 IO1 5 12 IO7<br>IO2 6 11 IO6 IO2 6 11 IO6<br>IO3 7 10 IO5 IO3 7 10 IO5<br>VSS 8 9 IO4 VSS 8 9 IO4<br>002aac465 002aac466<br>Fig 2. Pin configuration for SO16 Fig 3. Pin configuration for TSSOP16<br>terminal 1 terminal 1<br>index area index area<br>A2 1 12 SCL A2 1 12 SCL<br>IO0 2 11 INT IO0 2 11 INT<br>PCA9534BS PCA9534BS3<br>IO1 3 10 IO7 IO1 3 10 IO7<br>IO2 4 9 IO6 IO2 4 9 IO6<br>002aac467 002aac468<br>Transparent top view Transparent top view<br>Fig 4. Pin configuration for HVQFN16 Fig 5. Pin configuration for HVQFN16<br>(SOT629-1; 4 × 4 × 0.85 mm) (SOT758-1; 3 × 3 × 0.85 mm)<br>A1 A0 VDD SDA A1 A0 VDD SDA<br>16 15 14 13 16 15 14 13<br>5 6 7 8 5 6 7 8<br>IO3 VSS IO4 IO5 IO3 VSS IO4 IO5<br>**----- End of picture text -----**<br> ## **5.2 Pin description** ## **Table 2. Pin description** |**Symbol**|**Pin**|**Pin**|**Description**| |---|---|---|---| ||**SO16, TSSOP16**<br>|**HVQFN16**|| |A0|1<br>15<br>address input 0||| |A1|2<br>16<br>address input 1||| |A2|3<br>1<br>address input 2||| |IO0|4<br>2<br>input/output 0||| |IO1|5<br>3<br>input/output 1||| |IO2|6<br>4<br>input/output 2||| |IO3|7<br>5<br>input/output 3||| |VSS|8<br>~~6~~<br>[1]<br>ground supply voltage||| |IO4|9<br>7<br>input/output 4||| |IO5|10<br>8<br>input/output 5||| © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **3 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** **Table 2. Pin description** …continued |**Symbol**|**Pin**|**Pin**|**Description**| |---|---|---|---| ||**SO16, TSSOP16**|**HVQFN16**|| |IO6|11<br>9<br>input/output 6||| |IO7|12<br>10<br>input/output 7||| |INT|13<br>11<br>interrupt output (open-drain)||| |SCL|14<br>12<br>serial clock line||| |SDA|15<br>13<br>serial data line||| |VDD|16<br>14<br>supply voltage||| - [1] HVQFN package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region. ## **6. Functional description** Refer to Figure 1 “Block diagram of PCA9534”. ## **6.1 Registers** ## **6.1.1 Command byte** ## **Table 3. Command byte** |**Command**|**Protocol**|**Function**| |---|---|---| |0|read byte|Input Port register| |1|read/write byte|Output Port register| |2|read/write byte|Polarity Inversion register| |3|read/write byte|Confguration register| It is used as a pointer to determine which of the following registers will be written or read. ## **6.1.2 Register 0 - Input Port register** of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default ‘X’ is determined by the externally applied logic level. © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **4 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** **Table 4. Register 0 - Input Port register bit description** |**Bit**|**Symbol**|**Access**|**Value**|**Description**| |---|---|---|---|---| |7|I7|read only|X|determined by externally applied logic level| |6|I6|read only|X|| |5|I5|read only|X|| |4|I4|read only|X|| |3|I3|read only|X|| |2|I2|read only|X|| |1|I1|read only|X|| |0|I0|read only|X|| ## **6.1.3 Register 1 - Output Port register** Bit values in this register have no effect on pins defined as inputs. Reads from this register return the value that is in the flip-flop controlling the output selection, **not** the actual pin value. **Table 5. Register 1 - Output Port register bit description** Legend: * default value. |**Bit**|**Symbol**|**Access**|**Value**|**Description**| |---|---|---|---|---| |7|O7|R|1*|refects outgoing logic levels of pins defned as| |6|O6|R|1*|outputs by Register 3| |5|O5|R|1*|| |4|O4|R|1*|| |3|O3|R|1*|| |2|O2|R|1*|| |1|O1|R|1*|| |0|O0|R|1*|| ## **6.1.4 Register 2 - Polarity Inversion register** This register allows the user to invert the polarity of the Input Port register data. If a bit in this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in this register is cleared (written with a ‘0’), the Input Port data polarity is retained. **Table 6. Register 2 - Polarity Inversion register bit description** Legend: * default value. |**Bit**|**Symbol**|**Access**|**Value**|**Description**| |---|---|---|---|---| |7|N7|R/W|0*|inverts polarity of Input Port register data| |6|N6|R/W|0*|0 = Input Port register data retained (default value)| |5|N5|R/W|0*|1 = Input Port register data inverted| |4|N4|R/W|0*|| |3|N3|R/W|0*|| |2|N2|R/W|0*|| |1|N1|R/W|0*|| |0|N0|R/W|0*|| © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **5 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** ## **6.1.5** corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are configured as inputs. **Table 7.** Legend: * default value. |**Bit**|**Symbol**|**Access**|**Value**|**Description**| |---|---|---|---|---| |7|C7|R/W|1*|confgures the directions of the I/O pins| |6|C6|R/W|1*|0 = corresponding port pin enabled as an output<br>| |5|C5|R/W|1*|1 = corresponding port pin confgured as input| |4|C4|R/W|1*|(default value)| |3|C3|R/W|1*|| |2|C2|R/W|1*|| |1|C1|R/W|1*|| |0|C0|R/W|1*|| ## **6.2 Power-on reset** When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9534 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9534 registers and state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the operating voltage. ## **6.3 Interrupt output** The open-drain interrupt output is activated when one of the port pins change state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the Input Port register is read. Note that changing an I/O from and output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register. ## **6.4 I/O port** high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V. state of the Output Port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance paths that exist between the pin and either VDD or VSS. © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **6 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** **==> picture [403 x 298] intentionally omitted <==** **----- Start of picture text -----**<br> data from<br>shift register output port<br>register data<br>configuration<br>register VDD<br>data from<br>D Q Q1<br>shift register<br>FF<br>write configuration D Q<br>CK Q<br>pulse<br>FF<br>IO0 to IO7<br>write pulse CK<br>Q2<br>output port<br>register<br>VSS<br>input port<br>register<br>D Q<br>input port<br>FF register data<br>read pulse CK to INT<br>polarity inversion<br>register<br>data from<br>D Q polarity inversion<br>shift register<br>register data<br>FF<br>write polarity<br>CK<br>pulse<br>002aac470<br>**----- End of picture text -----**<br> **==> picture [229 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> Remark: At power-on reset, all registers return to default values.<br>**----- End of picture text -----**<br> **Fig 6.** ## **6.5 Device address** **==> picture [260 x 86] intentionally omitted <==** **----- Start of picture text -----**<br> slave address<br>0 1 0 0 A2 A1 A0 R/W<br>fixed hardware<br>selectable<br>002aac471<br>Fig 7. PCA9534 device address<br>**----- End of picture text -----**<br> ## **6.6 Bus transactions** Data is transmitted to the PCA9534 registers using the Write mode as shown in Figure 8 and Figure 9. Data is read from the PCA9534 registers using the Read mode as shown in Figure 10 and Figure 11. These devices do not implement an auto-increment function, so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent. © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **7 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** **==> picture [440 x 137] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>slave address command byte data to port<br>SDA S 0 1 0 0 A2 A1 A0 0 A 0 0 0 0 0 0 0 1 A DATA 1 A P<br>START condition R/W acknowledge acknowledge STOP<br>from slave from slave condition<br>acknowledge<br>from slave<br>write to port<br>tv(Q)<br>data out<br>data 1 valid<br>from port<br>002aac472<br>**----- End of picture text -----**<br> **Fig 8. Write to Output Port register** **==> picture [417 x 107] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>slave address command byte data to register<br>SDA S 0 1 0 0 A2 A1 A0 0 A 0 0 0 0 0 0 1 1/0 A DATA A P<br>START condition R/W acknowledge acknowledge STOP<br>from slave from slave condition<br>acknowledge<br>from slave<br>data to<br>register<br>002aac473<br>**----- End of picture text -----**<br> **Fig 9.** **==> picture [437 x 155] intentionally omitted <==** **----- Start of picture text -----**<br> slave address<br>SDA S 0 1 0 0 A2 A1 A0 0 A command byte A (cont.)<br>START condition R/W acknowledge<br>from slave<br>acknowledge<br>from slave<br>slave address data from register data from register<br>(cont.) S 0 1 0 0 A2 A1 A0 1 A DATA (first byte) A DATA (last byte) NA P<br>(repeated) R/W acknowledge no acknowledge STOP<br>START condition from master from master condition<br>acknowledge<br>from slave<br>at this moment master-transmitter becomes master-receiver<br>and slave-receiver becomes slave-transmitter<br>002aac474<br>**----- End of picture text -----**<br> **Fig 10. Read from register** © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **8 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** **==> picture [430 x 163] intentionally omitted <==** **----- Start of picture text -----**<br> SCL 1 2 3 4 5 6 7 8 9<br>slave address data from port data from port<br>SDA S 0 1 0 0 A2 A1 A0 1 A DATA 1 A DATA 4 NA P<br>START condition R/W acknowledge no acknowledge STOP<br>from master from master condition<br>acknowledge<br>from slave<br>read from<br>port<br>th(D) tsu(D)<br>data into<br>DATA 2 DATA 3 DATA 4<br>port<br>tv(INT_N) trst(INT_N)<br>INT<br>002aac475<br>**----- End of picture text -----**<br> Transfer of data can be stopped at any moment by a STOP condition. **Fig 11. Read Input Port register** © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **9 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** ## **7. Application design-in information** **==> picture [470 x 274] intentionally omitted <==** **----- Start of picture text -----**<br> 5 V<br>VDD (5 V)<br>100 kΩ<br>10 kΩ 10 kΩ 10 kΩ 10 kΩ 2 kΩ<br>(× 3)<br>VDD VDD<br>MASTER<br>PCA9534<br>CONTROLLER SUBSYSTEM 1<br>SCL SCL IO0 (e.g., temp. sensor)<br>SDA SDA IO1 INT<br>IO2<br>RESET<br>INT INT IO3<br>SUBSYSTEM 2<br>IO4<br>(e.g., counter)<br>VSS IO5<br>IO6 A<br>IO7<br>enable controlled switch<br>A2 (e.g., CBT device)<br>A1<br>A0 B<br>VSS ALARM<br>SUBSYSTEM 3<br>(e.g., alarm system)<br>VDD<br>002aac476<br>**----- End of picture text -----**<br> IO0, IO1, IO2 configured as outputs. IO3, IO4, IO5 configured as inputs. IO6, IO7 are not used and must be configured as outputs. **Fig 12. Typical application** ## **7.1 Minimizing IDD when the I/O us used to control LEDs** When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 12. Since the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower than VDD. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the IOn pins greater than or equal to VDD when the LED is off. Figure 13 shows a high value resistor in parallel with the LED. Figure 14 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VDD and prevents additional supply current consumption when the LED is off. © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **10 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** **==> picture [397 x 168] intentionally omitted <==** **----- Start of picture text -----**<br> 3.3 V 5 V<br>VDD<br>VDD LED 100 kΩ VDD LED<br>IOn IOn<br>002aac660 002aac661<br>Fig 13. High value resistor in parallel with Fig 14. Device supplied by a lower voltage<br>the LED<br>**----- End of picture text -----**<br> ## **8. Limiting values** ## **Table 8. Limiting values** In accordance with the Absolute Maximum Rating System (IEC 60134). |**Symbol**|**Parameter**|**Conditions**|**Min**|**Max**|**Unit**| |---|---|---|---|---|---| |VDD|supply voltage||−0.5|+6.0|V| |II|input current||-|±20|mA| |VI/O|voltage on an input/output pin||VSS−0.5|5.5|V| |IO(IOn)|output current on pin IOn||-|±50|mA| |IDD|supply current||-|85|mA| |ISS|ground supply current||-|100|mA| |Ptot|total power dissipation||-|200|mW| |Tstg|storage temperature||−65|+150|°C| |Tamb|ambient temperature||−40|+85|°C| © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **11 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** ## **9. Static characteristics** **Table 9. Static characteristics** VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. |**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**| |---|---| |**Supplies**|| |VDD<br>supply voltage|2.3<br>-<br>5.5<br>V| |IDD<br>supply current|operating mode; VDD= 5.5 V;<br>no load; fSCL= 100 kHz<br>-<br>104<br>175<br>µA| |Istb<br>standby current|Standby mode; VDD= 5.5 V; no load;<br>fSCL= 0 kHz; I/O = inputs| ||VI= VSS<br>-<br>0.25<br>1<br>µA| ||VI= VDD<br>-<br>0.25<br>1<br>µA| |VPOR<br>power-on reset voltage|no load; VI= VDDor VSS<br>[1] -<br>1.5<br>1.65<br>V| |**Input SCL; input/output SDA**|| |VIL<br>LOW-level input voltage|−0.5<br>-<br>+0.3VDD<br>V| |VIH<br>HIGH-level input voltage|0.7VDD<br>-<br>5.5<br>V| |IOL<br>LOW-level output current|VOL= 0.4 V<br>3<br>6<br>-<br>mA| |IL<br>leakage current|VI= VDD= VSS<br>−1<br>-<br>+1<br>µA| |Ci<br>input capacitance|VI= VSS<br>-<br>5<br>10<br>pF| |**I/Os**|| |VIL<br>LOW-level input voltage|−0.5<br>-<br>+0.8<br>V| |VIH<br>HIGH-level input voltage|2.0<br>-<br>5.5<br>V| |IOL<br>LOW-level output current|VOL= 0.5 V; VDD= 2.3 V<br>[2] 8<br>10<br>-<br>mA| ||VOL= 0.7 V; VDD= 2.3 V<br>[2] 10<br>13<br>-<br>mA| ||VOL= 0.5 V; VDD= 3.0 V<br>[2] 8<br>14<br>-<br>mA| ||VOL= 0.7 V; VDD= 3.0 V<br>[2] 10<br>19<br>-<br>mA| ||VOL= 0.5 V; VDD= 4.5 V<br>[2] 8<br>17<br>-<br>mA| ||VOL= 0.7 V; VDD= 4.5 V<br>[2] 10<br>24<br>-<br>mA| |VOH<br>HIGH-level output voltage|IOH=−8 mA; VDD= 2.3 V<br>[3] 1.8<br>-<br>-<br>V| ||IOH=−10 mA; VDD= 2.3 V<br>[3] 1.7<br>-<br>-<br>V| ||IOH=−8 mA; VDD= 3.0 V<br>[3] 2.6<br>-<br>-<br>V| ||IOH=−10 mA; VDD= 3.0 V<br>[3] 2.5<br>-<br>-<br>V| ||IOH=−8 mA; VDD= 4.75 V<br>[3] 4.1<br>-<br>-<br>V| ||IOH=−10 mA; VDD= 4.75 V<br>[3] 4.0<br>-<br>-<br>V| |ILI<br>input leakage current|VI= VDD= VSS<br>−1<br>-<br>+1<br>µA| |Ci<br>input capacitance|-<br>5<br>10<br>pF| |**Interrupt**<br>**INT**|| |IOL<br>LOW-level output current|VOL= 0.4 V<br>3<br>-<br>-<br>mA| |**Select inputs A0, A1, A2**|| |VIL<br>LOW-level input voltage|−0.5<br>-<br>0.8<br>V| |VIH<br>HIGH-level input voltage|2.0<br>-<br>5.5<br>V| |ILI<br>input leakage current|−1<br>-<br>1<br>µA| © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **12 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** - [1] VDD must be lowered to 0.2 V in order to reset part. - [2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA. - [3] The total current sourced by all I/Os must be limited to 85 mA. ## **10. Dynamic characteristics** |**10. Dynamic characteristics**|||||| |---|---|---|---|---|---| |**Table 10.**<br>**Dynamic characteristics**|||||| |**Symbol**<br>**Parameter**<br>**Conditions**|**Standard-mode**<br>**I2C-bus**||**Fast-mode I2C-bus**||**Unit**| ||**Min**|**Max**|**Min**|**Max**|| |fSCL<br>SCL clock frequency|0<br>100<br>0<br>400<br>kHz||||| |tBUF<br>bus free time between a STOP and<br>START condition|4.7<br>-<br>1.3<br>-<br>µs||||| |tHD;STA<br>hold time (repeated) START condition|4.0<br>-<br>0.6<br>-<br>µs||||| |tSU;STA<br>set-up time for a repeated START<br>condition|4.7<br>-<br>0.6<br>-<br>µs||||| |tSU;STO<br>set-up time for STOP condition|4.0<br>-<br>0.6<br>-<br>µs||||| |tHD;DAT<br>data hold time|0<br>-<br>0<br>-<br>µs||||| |tVD:ACK<br>data valid acknowledge time<br>[1]|0.3<br>3.45<br>0.1<br>0.9<br>µs||||| |tVD;DAT<br>data valid time<br>[2]|300<br>-<br>50<br>-<br>ns||||| |tSU;DAT<br>data set-up time|250<br>-<br>100<br>-<br>ns||||| |tLOW<br>LOW period of the SCL clock|4.7<br>-<br>1.3<br>-<br>µs||||| |tHIGH<br>HIGH period of the SCL clock|4.0<br>-<br>0.6<br>-<br>µs||||| |tr<br>rise time of both SDA and SCL signals|-<br>1000<br>20 + 0.1C~~b~~<br>[3]<br>300<br>ns||||| |tf<br>fall time of both SDA and SCL signals|-<br>300<br>20 + 0.1C~~b~~<br>[3]<br>300<br>µs||||| |tSP<br>pulse width of spikes that must be<br>suppressed by the input flter|-<br>50<br>-<br>50<br>ns||||| |**Port timing**|||||| |tv(Q)<br>data output valid time|-<br>200<br>-<br>200<br>ns||||| |tsu(D)<br>data input setup time|100<br>-<br>100<br>-<br>ns||||| |th(D)<br>data input hold time|1<br>-<br>1<br>-<br>µs||||| |**Interrupt timing**|||||| |tv(INT_N)<br>valid time on pin<br>INT|-<br>4<br>-<br>4<br>µs||||| |trst(INT_N)<br>reset time on pin<br>INT|-<br>4<br>-<br>4<br>µs||||| [1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. [2] tVD;DAT = minimum time for SDA data output to be valid following SCL LOW. [3] Cb = total capacitance of one bus line in pF. © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **13 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** **==> picture [497 x 389] intentionally omitted <==** **----- Start of picture text -----**<br> SDA<br>tBUF tr tf tHD;STA tSP<br>tLOW<br>SCL<br>tHD;STA tSU;STA tSU;STO<br>P S tHD;DAT tHIGH tSU;DAT Sr P<br>002aaa986<br>Fig 15. Definition of timing<br>START bit 7 STOP<br>protocol condition MSB bit 6 bit 0 acknowledge condition<br>(A6) (R/W) (A)<br>(S) (A7) (P)<br>tSU;STA tLOW tHIGH 1/fSCL<br>SCL<br>tBUF tf<br>tr<br>SDA<br>tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO<br>002aab175<br>Rise and fall times refer to VIL and VIH.<br>Fig 16. I [2] C-bus timing diagram<br>**----- End of picture text -----**<br> © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **14 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** ## **11. Test information** **==> picture [298 x 146] intentionally omitted <==** **----- Start of picture text -----**<br> 6.0 V<br>open<br>VDD RL VSS<br>500 Ω<br>VI VO<br>PULSE<br>D.U.T.<br>GENERATOR<br>RT 50 pFCL<br>002aab393<br>RL = load resistor.<br>CL = load capacitance includes jig and probe capacitance.<br>RT = termination resistance should be equal to the output impedance Zo of the pulse<br>generators.<br>**----- End of picture text -----**<br> ## **Fig 17. Test circuitry for switching times** **==> picture [292 x 76] intentionally omitted <==** **----- Start of picture text -----**<br> 500 Ω S1 2VDD<br>from output open<br>under test VSS<br>CL 500 Ω<br>50 pF<br>002aab881<br>Fig 18. Test circuit<br>**----- End of picture text -----**<br> ## **Table 11. Test data** |**Test**|**Load**|**Load**|**Switch**| |---|---|---|---| ||**CL**|**RL**|| |tv(Q)|50 pF<br>500Ω<br>2VDD||| © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **15 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** ## **12. Package outline** ## **SO16: plastic small outline package; 16 leads; body width 7.5 mm** ## **SOT162-1** **==> picture [478 x 570] intentionally omitted <==** **----- Start of picture text -----**<br> D E A<br>X<br>c<br>y HE v M A<br>Z<br>16 9<br>Q<br>A2 A<br>A1 (A )3<br>pin 1 index<br>θ<br>L p<br>L<br>1 8 detail X<br>e w M<br>b p<br>0 5 10 mm<br>scale<br>DIMENSIONS (inch dimensions are derived from the original mm dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(1)] e HE L Lp Q v w y Z (1) θ<br>0.3 2.45 0.49 0.32 10.5 7.6 10.65 1.1 1.1 0.9<br>mm 2.65 0.1 2.25 0.25 0.36 0.23 10.1 7.4 1.27 10.00 1.4 0.4 1.0 0.25 0.25 0.1 0.4 8o<br>0.012 0.096 0.019 0.013 0.41 0.30 0.419 0.043 0.043 0.035 0o<br>inches 0.1 0.01 0.05 0.055 0.01 0.01 0.004<br>0.004 0.089 0.014 0.009 0.40 0.29 0.394 0.016 0.039 0.016<br>Note<br>1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>99-12-27<br> SOT162-1 075E03 MS-013<br>03-02-19<br>**----- End of picture text -----**<br> **Fig 19. Package outline SOT162-1 (SO16)** © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **16 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** ## **TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm** **SOT403-1** **==> picture [478 x 570] intentionally omitted <==** **----- Start of picture text -----**<br> D E A<br>X<br>c<br>y HE v M A<br>Z<br>16 9<br>Q<br>A2 (A )3 A<br>pin 1 index A1<br>θ<br>L p<br>L<br>1 8<br>detail X<br>w M<br>e b p<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT max.A A1 A2 A3 bp c D [(1)] E [(2)] e HE L Lp Q v w y Z (1) θ<br>mm 1.1 0.150.05 0.950.80 0.25 0.300.19 0.20.1 5.14.9 4.54.3 0.65 6.66.2 1 0.750.50 0.40.3 0.2 0.13 0.1 0.400.06 80oo<br>Notes<br>1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.<br>2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>99-12-27<br> SOT403-1 MO-153<br>03-02-18<br>**----- End of picture text -----**<br> **Fig 20. Package outline SOT403-1 (TSSOP16)** © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **17 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** **HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm** **SOT629-1** **==> picture [478 x 559] intentionally omitted <==** **----- Start of picture text -----**<br> D B A<br>terminal 1<br>index area A<br>A1<br>E c<br>detail X<br>e1<br>C<br>1/2 e<br>e b v M C A B y1 C y<br>5 8 w M C<br>L<br>9<br>4<br>e<br>Eh e2<br>1/2 e<br>1<br>12<br>terminal 1<br>index area 16 13<br>Dh X<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>A [(1)]<br>UNIT max. A1 b c D [(1)] Dh E [(1)] Eh e e1 e2 L v w y y1<br>0.05 0.38 4.1 2.25 4.1 2.25 0.75<br>mm 1 0.2 0.65 1.95 1.95 0.1 0.05 0.05 0.1<br>0.00 0.23 3.9 1.95 3.9 1.95 0.50<br>Note<br>1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>01-08-08<br> SOT629-1 - - - MO-220 - - -<br>02-10-22<br>**----- End of picture text -----**<br> **Fig 21. Package outline SOT629-1 (HVQFN16)** © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **18 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** **HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 x 3 x 0.85 mm** **SOT758-1** **==> picture [478 x 559] intentionally omitted <==** **----- Start of picture text -----**<br> D B A<br>terminal 1<br>index area<br>E A<br>A1<br>c<br>detail X<br>e1 C<br>1/2 e<br>v M C A B y1 C y<br>e b<br>w M C<br>5 8<br>L<br>4 9<br>e<br>Eh e2<br>1/2 e<br>1 12<br>terminal 1 16 13<br>index area Dh<br>X<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>A [(1)]<br>UNIT max. A1 b c D [(1)] Dh E [(1)] Eh e e1 e2 L v w y y1<br>0.05 0.30 3.1 1.75 3.1 1.75 0.5<br>mm 1 0.2 0.5 1.5 1.5 0.1 0.05 0.05 0.1<br>0.00 0.18 2.9 1.45 2.9 1.45 0.3<br>Note<br>1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>02-03-25<br> SOT758-1 - - - MO-220 - - -<br>02-10-21<br>**----- End of picture text -----**<br> **Fig 22. Package outline SOT758-1 (HVQFN16)** © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **19 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** ## **13. Handling information** Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits. ## **14. Soldering** This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. ## **14.1 Introduction to soldering** Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. ## **14.2** Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: - Through-hole components - Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. - - Package footprints, including solder thieves and orientation - The moisture sensitivity level of the packages - Package placement - Inspection and repair - Lead-free soldering versus PbSn soldering ## **14.3 Wave soldering** Key characteristics in wave soldering are: © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **20 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** - transport, the solder wave parameters, and the time during which components are exposed to the wave - ## **14.4** - higher minimum peak temperatures (see Figure 23) than a PbSn process, thus reducing the process window - Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board - heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13 ## **Table 12. SnPb eutectic process (from J-STD-020C)** |**Package thickness (mm)**|**Package refow temperature (**°**C)**|**Package refow temperature (**°**C)**| |---|---|---| ||**Volume (mm3)**|| ||**< 350**|≥**350**| |< 2.5|235<br>220|| |≥2.5|220<br>220|| ## **Table 13. Lead-free process (from J-STD-020C)** |**Package thickness (mm)**|**Package refow temperature (**°**C)**|**Package refow temperature (**°**C)**|**Package refow temperature (**°**C)**| |---|---|---|---| ||**Volume (mm3)**||| ||**< 350**|**350 to 2000**|**> 2000**| |< 1.6|260<br>260<br>260||| |1.6 to 2.5|260<br>250<br>245||| |> 2.5|250<br>245<br>245||| Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. soldering, see Figure 23. © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **21 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** **==> picture [320 x 208] intentionally omitted <==** **----- Start of picture text -----**<br> maximum peak temperature<br>= MSL limit, damage level<br>temperature<br>minimum peak temperature<br>= minimum soldering temperature<br>peak<br> temperature<br>time<br>001aac844<br>MSL: Moisture Sensitivity Level<br>**----- End of picture text -----**<br> **Fig 23.** “Surface mount reflow soldering description”. ## **15. Abbreviations** **Table 14. Abbreviations** |**Acronym**|**Description**| |---|---| |ACPI|Advanced Confguration and Power Interface| |CDM|Charged Device Model| |DUT|Device Under Test| |ESD|ElectroStatic Discharge| |FET|Field-Effect Transistor| |GPIO|General Purpose Input/Output| |HBM|Human Body Model| |I2C-bus|Inter-Integrated Circuit bus| |I/O|Input/Output| |LED|Light-Emitting Diode| |MM|Machine Model| |POR|Power-On Reset| |SMBus|System Management Bus| © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **22 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** ## **16. Revision history** **Table 15. Revision history** |**Document ID**|**Release date**<br>**Data sheet status**|**Release date**<br>**Data sheet status**|**Change notice**|**Supersedes**| |---|---|---|---|---| |PCA9534_3|20061106<br>Product data sheet||-|PCA9534_2| |Modifcations:|**•**|The format of this data sheet has been redesigned to comply with the new identity guidelines of||| |||NXP Semiconductors.||| ||**•**|Legal texts have been adapted to the new company name where appropriate.||| ||**•**|pin names I/O0 through I/O7 changed to IO0 through IO7||| ||**•**|added HVQFN16 (SOT758-1) package||| ||**•**|symbol (tpvand tPV) changed to tv(Q)||| ||**•**|symbol (tphand tPH) changed to th(D)||| ||**•**|symbol (tpsand tPS) changed to tsu(D)||| ||**•**|symbol (tivand tIV) changed to tv(INT_N)||| ||**•**|symbol (tirand tIR) changed to trst(INT_N)||| ||**•**|Figure 6“Simplif<br>ed schematic of IO0 toIO7”: removed ESD diodes||| ||**•**|T<br>ab<br>le 8“Limitingv<br>alues”: symbol “II/O, DC output current on an I/O” changed to “IO(IOn), output||| |||current on pin IOn”||| ||**•**|T<br>ab<br>le 9“Static char<br>acter<br>istics”, sub-section “I/Os”: symbol IILchanged to ILI||| ||**•**|added<br>Section 15“Ab<br>bre<br>viations”||| |PCA9534_2|20040930<br>Product data sheet||-|PCA9534_1| |(9397 750 13506)||||| |PCA9534_1|20031202<br>Product data||ECN 853-2319 01-A14517|-| |(9397 750 12454)|||of 14 Nov 2003|| © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **23 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** ## **17. Legal information** ## **17.1 Data sheet status** |**Document statu**|**s**<br>**[1]**<br>**[2]**<br>**Product status**<br>**[3]**<br>**Defnition**| |---|---| |Objective [short] data sheet<br>Development<br>This document contains data from the objective specifcation for product development.|| |Preliminary [short] data sheet<br>Qualifcation<br>This document contains data from the preliminary specifcation.|| |Product [short] data sheet<br>Production<br>This document contains the product specifcation.|| [1] Please consult the most recently issued document before initiating or completing a design. [2] [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. ## **17.2** **Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. ## **17.3 Disclaimers** **General —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. **Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. **Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. **Limiting values —** the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. **Terms and conditions of sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. **No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. ## **17.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. **I[2] C-bus —** logo is a trademark of NXP B.V. ## **18. Contact information** For additional information, please visit: **http://www.nxp.com** **salesaddresses@nxp.com** © NXP B.V. 2006. All rights reserved. PCA9534_3 **Product data sheet** **Rev. 03 — 6 November 2006** **24 of 25** **PCA9534** **NXP Semiconductors** **8-bit I[2] C-bus and SMBus low power I/O port with interrupt** ## **19. Contents** |**1**|**General description . . . . . . . . . . . . . . . . . . . . . . 1**| |---|---| |**2**|**Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1**| |**3**|**Ordering information . . . . . . . . . . . . . . . . . . . . . 2**| |**4**|**Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2**| |**5**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . 3**| |5.1|Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3| |5.2|Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3| |**6**|**Functional description . . . . . . . . . . . . . . . . . . . 4**| |6.1|Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4| |6.1.1|Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 4| |6.1.2|Register 0 - Input Port register . . . . . . . . . . . . . 4| |6.1.3|Register 1 - Output Port register. . . . . . . . . . . . 5| |6.1.4<br>6.1.5|Register 2 - Polarity Inversion register . . . . . . . 5<br>Register 3 - Confguration register . . . . . . . . . . 6| |6.2|Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6| |6.3|Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 6| |6.4|I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6| |6.5|Device address . . . . . . . . . . . . . . . . . . . . . . . . . 7| |6.6|Bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 7| |**7**|**Application design-in information . . . . . . . . . 10**| |7.1|Minimizing IDDwhen the I/O us used to| ||control LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . 10| |**8**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11**| |**9**|**Static characteristics. . . . . . . . . . . . . . . . . . . . 12**| |**10**|**Dynamic characteristics . . . . . . . . . . . . . . . . . 13**| |**11**|**Test information. . . . . . . . . . . . . . . . . . . . . . . . 15**| |**12**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16**| |**13**|**Handling information. . . . . . . . . . . . . . . . . . . . 20**| |**14**|**Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20**| |14.1<br>14.2|Introduction to soldering . . . . . . . . . . . . . . . . . 20<br>Wave and refow soldering . . . . . . . . . . . . . . . 20| |14.3<br>14.4|Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 20<br>Refow soldering . . . . . . . . . . . . . . . . . . . . . . . 21| |**15**|**Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 22**| |**16**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . . 23**| |**17**|**Legal information. . . . . . . . . . . . . . . . . . . . . . . 24**| |17.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24| |17.2|Defnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24| |17.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24| |17.4|Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24| |**18**|**Contact information. . . . . . . . . . . . . . . . . . . . . 24**| |**19**|**Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25**| **==> picture [151 x 121] intentionally omitted <==** Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. **© NXP B.V. 2006.** **All rights reserved.** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 6 November 2006 Document identifier: PCA9534_3**
Updated at February 9, 2023
NXP Semiconductors is a global leader in secure connectivity solutions, driving innovation across the automotive, industrial, IoT, mobile, and communications infrastructure markets. By developing advanced, purpose-built technologies, NXP enables devices to sense, think, connect, and act intelligently, delivering rigorously tested components that make the connected world safer and more efficient. Within the semiconductor space, NXP is highly regarded for its extensive range of high-performance integrated circuits and discrete devices. The brand's portfolio excels in drivers and interfaces, featuring a comprehensive selection of I/O expanders designed to streamline complex system architectures. For demanding high-frequency and wireless applications, NXP provides industry-leading RF FETs and RF/PIN diodes engineered to deliver exceptional signal integrity, efficiency, and reliability. The NXP product lineup further extends to essential discrete components, including versatile bipolar transistors, JFETs, and small signal diodes optimized for precision switching and amplification. Additionally, the portfolio supports advanced automation and smart applications with precision IC sensors, such as MEMS accelerometers, alongside specialized power management solutions like AC/DC LED driver ICs and single MOSFETs for cutting-edge electronics design.
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